Changeset 10779


Ignore:
Timestamp:
May 23, 2011, 3:00:19 PM (8 years ago)
Author:
weitzel
Message:
some changes in FTM Timing_counter
Location:
firmware/FTM
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/FTM_central_control.vhd

    r10760 r10779  
    8383    trigger_stop : out std_logic := '1';
    8484    enable_ID_sending : out std_logic := '0';
    85     reset_timer : out std_logic := '0'
     85    reset_timer : out std_logic := '0';
     86    crate_res_0 : out std_logic := '1';
     87    crate_res_1 : out std_logic := '1';
     88    crate_res_2 : out std_logic := '1';
     89    crate_res_3 : out std_logic := '1'
    8690  );
    8791end FTM_central_control;
     
    99103  signal new_period_ack_sig    : std_logic := '0';
    100104  signal prescaling_FTU01_sig  : std_logic_vector(7 downto 0) := "00100111";
     105  signal reset_cnt_sig         : integer range 0 to RESET_TIME := 0;
    101106 
    102107  type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER,
     
    108113                                   CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01,
    109114                                   CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01,
    110                                    CP_SEND_START, CP_SEND_END);
     115                                   CP_SEND_START, CP_SEND_END,
     116                                   CP_CRATE_RESET, CP_CRATE_RESET_ACK);
    111117  signal state_central_proc : state_central_proc_type := CP_INIT;
    112118
     
    124130        when CP_INIT =>  -- wait for DCMs to lock
    125131          current_cc_state <= X"FFFF";
    126           --cc_state_test <= X"00";
    127132          cc_state_test <= X"01";
    128133          if (clk_ready = '1') then
     
    250255          if (new_config = '1') then
    251256            config_started <= '1';
    252             start_run_ack <= '1';
     257            start_run_ack <= '1';  --remove this line???
    253258            state_central_proc <= CP_CONFIG_START;
    254259          elsif (ping_ftu_start = '1') then
     
    274279              state_central_proc <= CP_RUNNING;
    275280            end if;
     281          elsif (crate_reset = '1') then
     282            crate_reset_ack <= '1';
     283            state_central_proc <= CP_CRATE_RESET;
    276284          end if;
    277285
     
    317325            enable_Id_sending <= '0';
    318326            state_central_proc <= CP_RUNNING_02;
     327          elsif (crate_reset = '1') then
     328            crate_reset_ack <= '1';
     329            state_central_proc <= CP_CRATE_RESET_ACK;
    319330          end if;
    320331
     
    329340         
    330341        when CP_CONFIG_ACK =>
    331           current_cc_state <= FTM_STATE_CFG;
    332342          cc_state_test <= X"11";
    333343          if (config_started_ack = '1') then
     
    335345            state_central_proc <= CP_RUNNING_01;
    336346          end if;
    337          
     347
    338348        when CP_PING =>
    339349          cc_state_test <= X"12";
     
    392402          end if;
    393403
     404        when CP_CRATE_RESET_ACK =>
     405          cc_state_test <= X"18";
     406          if (crate_reset = '0') then
     407            crate_reset_ack <= '0';
     408            state_central_proc <= CP_RUNNING_01;
     409          end if;
     410
     411        when CP_CRATE_RESET =>
     412          cc_state_test <= X"19";
     413          if (crate_reset = '0') then
     414            crate_reset_ack <= '0';
     415            state_central_proc <= CP_IDLE;
     416          end if;
     417         
    394418        when others =>
    395           cc_state_test <= X"18";
     419          cc_state_test <= X"1A";
    396420         
    397421      end case;
  • firmware/FTM/FTM_top.vhd

    r10760 r10779  
    406406  signal enable_ID_sending_sig : std_logic;
    407407  signal reset_timer_sig : std_logic;  -- initialized in FTM_central_control
    408  
     408
     409  signal crate_res0_sig : std_logic;  -- initialized in FTM_central_control
     410  signal crate_res1_sig : std_logic;  -- initialized in FTM_central_control
     411  signal crate_res2_sig : std_logic;  -- initialized in FTM_central_control
     412  signal crate_res3_sig : std_logic;  -- initialized in FTM_central_control
     413
    409414--  component FTM_clk_gen
    410415--    port(
     
    570575      trigger_stop : out std_logic;
    571576      enable_ID_sending : out std_logic;
    572       reset_timer : out std_logic
     577      reset_timer : out std_logic;
     578      crate_res_0 : out std_logic;
     579      crate_res_1 : out std_logic;
     580      crate_res_2 : out std_logic;
     581      crate_res_3 : out std_logic
    573582    );
    574583  end component;
     
    967976      trigger_stop  => trigger_stop_sig,
    968977      enable_ID_sending => enable_ID_sending_sig,
    969       reset_timer => reset_timer_sig
     978      reset_timer => reset_timer_sig,
     979      crate_res_0 => crate_res0_sig,
     980      crate_res_1 => crate_res1_sig,
     981      crate_res_2 => crate_res2_sig,
     982      crate_res_3 => crate_res3_sig
    970983    );
    971984 
     
    10341047      rx_d_3            => Bus2_RxD_3,
    10351048      tx_d_3            => Bus2_TxD_3,
    1036       --enable_ID_sending => trigger_start_sig,
    10371049      enable_ID_sending => enable_ID_sending_sig,
    1038       --enable_ID_sending => '1',
    10391050      TIM_source        => general_settings_sig(0),
    10401051      LP_settings       => "0000",
     
    11971208  TP( 7 downto 0) <= cc_state_test_sig;
    11981209
    1199   Crate_Res0 <= '1';
    1200   Crate_Res1 <= '1';
    1201   Crate_Res2 <= '1';
    1202   Crate_Res3 <= '1';
     1210  Crate_Res0 <= crate_res0_sig;
     1211  Crate_Res1 <= crate_res1_sig;
     1212  Crate_Res2 <= crate_res2_sig;
     1213  Crate_Res3 <= crate_res3_sig;
    12031214 
    12041215end Behavioral;
  • firmware/FTM/Timing_counters/Timing_counter.vhd

    r10760 r10779  
    2323--
    2424-- May 18 2011 by Patrick Vogler
     25--
     26-- May 20, 2011, by Q. Weitzel
     27-- counting was wrong by one clock cycle (1 us)
     28--
     29-- May 23, 2011, by Q. Weitzel
     30-- counter reset changed from async to sync reset
     31-- reset, enable and read_counter removed from sensitity lists
     32--
    2533----------------------------------------------------------------------------------
    2634
     
    4048USE ftm_definitions.ftm_array_types.all;
    4149USE ftm_definitions.ftm_constants.all;
    42 
    4350
    4451
     
    6471
    6572
    66 
    6773architecture Behavioral of Timing_counter is
    6874
     
    7884--  counting
    7985-------------------------------------------------------------------------------
    80   count :  process (clk, reset, enable)
    81   begin
    82     if reset = '1' then
    83          counting    <= (others => '0');
    84          precounting <= (others => '0');
    85                  
    86        elsif rising_edge(clk) then
    87            if enable = '1' then
    88               precounting <= precounting + 1;
    89               if (precounting = (PRECOUNT_DIVIDER - 1)) then         
    90                 counting <= counting + 1;
    91                 precounting <= (others => '0'); 
    92               end if;         
    93        end if;       
    94     end if;   
     86  count :  process (clk)
     87  begin
     88     
     89    if rising_edge(clk) then
     90      if (reset = '1') then
     91        counting    <= (others => '0');
     92        precounting <= (others => '0');       
     93      elsif enable = '1' then
     94        precounting <= precounting + 1;
     95        if (precounting = (PRECOUNT_DIVIDER - 1)) then         
     96          counting <= counting + 1;
     97          precounting <= (others => '0');       
     98        end if;         
     99      end if;       
     100    end if;
     101   
    95102  end process count;
    96 
    97103
    98104-- read counter
    99105-------------------------------------------------------------------------------
    100   readout_counter : process (clk, read_counter)
     106  readout_counter : process (clk)
    101107  begin
    102108    if rising_edge(clk) then
     
    131137
    132138end Behavioral;
    133 
    134 
  • firmware/FTM/ftm_definitions.vhd

    r10742 r10779  
    234234  -- crate reset
    235235  constant CMD_CRESET         : std_logic_vector := X"0020";
    236 
     236  constant RESET_TIME         : integer := 1000;
     237 
    237238  -- start and end of package
    238239  constant FTM_PACKAGE_START  : std_logic_vector := X"FB01";
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