- Timestamp:
- 05/24/11 18:08:46 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/FTM_central_control.vhd
r10779 r10803 70 70 dna_ready : in std_logic; 71 71 crate_reset : IN std_logic; 72 crate_reset_ack : OUT std_logic := ' 1';72 crate_reset_ack : OUT std_logic := '0'; 73 73 crate_reset_param : IN std_logic_vector (15 DOWNTO 0); 74 74 start_run : IN std_logic; … … 104 104 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 105 105 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0; 106 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0) := (others => '0'); 106 107 107 108 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER, … … 114 115 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, 115 116 CP_SEND_START, CP_SEND_END, 116 CP_CRATE_RESET, CP_CRATE_RESET_ ACK);117 CP_CRATE_RESET, CP_CRATE_RESET_01, CP_CRATE_RESET_ACK); 117 118 signal state_central_proc : state_central_proc_type := CP_INIT; 118 119 … … 177 178 --state_central_proc <= CP_CONFIG_SCALER; 178 179 --state_central_proc <= CP_IDLE; 180 --state_central_proc <= CP_CRATE_RESET; 179 181 end if; 180 182 … … 280 282 end if; 281 283 elsif (crate_reset = '1') then 284 crate_reset_param_sig <= crate_reset_param; 282 285 crate_reset_ack <= '1'; 283 286 state_central_proc <= CP_CRATE_RESET; … … 413 416 if (crate_reset = '0') then 414 417 crate_reset_ack <= '0'; 418 state_central_proc <= CP_CRATE_RESET_01; 419 end if; 420 421 when CP_CRATE_RESET_01 => 422 cc_state_test <= X"1A"; 423 if (reset_cnt_sig < RESET_TIME) then 424 reset_cnt_sig <= reset_cnt_sig + 1; 425 if (crate_reset_param_sig = "0000000000000001") then 426 crate_res_0 <= '0'; 427 elsif (crate_reset_param_sig = "0000000000000010") then 428 crate_res_1 <= '0'; 429 elsif (crate_reset_param_sig = "0000000000000100") then 430 crate_res_2 <= '0'; 431 elsif (crate_reset_param_sig = "0000000000001000") then 432 crate_res_3 <= '0'; 433 end if; 434 else 435 reset_cnt_sig <= 0; 436 crate_res_0 <= '1'; 437 crate_res_1 <= '1'; 438 crate_res_2 <= '1'; 439 crate_res_3 <= '1'; 415 440 state_central_proc <= CP_IDLE; 416 441 end if; 417 442 418 443 when others => 419 cc_state_test <= X"1 A";444 cc_state_test <= X"1B"; 420 445 421 446 end case; -
firmware/FTM/ethernet/w5300_modul.vhd
r10740 r10803 18 18 -- 19 19 ---------------------------------------------------------------------------------- 20 20 21 LIBRARY IEEE; 21 22 USE IEEE.STD_LOGIC_1164.all; … … 109 110 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 110 111 ); 111 112 112 END w5300_modul ; 113 113 … … 606 606 if (dd_write_general_ready = '1') then 607 607 data_package_type <= FTM_PACKAGE_TYPE_DD; 608 data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end608 data_package_length <= X"0" & (DD_BLOCK_SIZE + 1); -- +1 := package end 609 609 read_addr_state <= READ_FROM_DD_ADDR; 610 610 local_sd_addr <= X"000"; -- start at address 0x000 … … 640 640 next_state <= SEND_FTU_ERROR; 641 641 data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR; 642 data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end642 data_package_length <= X"0" & (FTU_ERROR_LENGTH + 1); -- +1 := package end 643 643 read_addr_state <= READ_FTU_ERROR; 644 644 local_sd_addr <= X"000"; … … 851 851 state_read_data <= RD_5; 852 852 data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST; 853 data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end853 data_package_length <= X"0" & (FL_BLOCK_SIZE + 1); -- +1 := package end 854 854 read_addr_state <= READ_FROM_FL_ADDR; 855 855 local_sd_addr <= X"000"; --start at address 0x000 … … 863 863 when RD_READ_SD_BLOCK => 864 864 data_package_type <= FTM_PACKAGE_TYPE_SD; 865 data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end865 data_package_length <= X"0" & (SD_BLOCK_SIZE + 1); -- +1 := package end 866 866 state_read_data <= RD_5; 867 867 read_addr_state <= READ_FROM_SD_ADDR; … … 875 875 when RD_READ_SD_ADDR => 876 876 data_package_type <= FTM_PACKAGE_TYPE_SD_WORD; 877 data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end877 data_package_length <= X"0" & (SD_SINGLE_WORD_SIZE + 1); -- +1 := package end 878 878 state_read_data <= RD_5; 879 879 read_addr_state <= READ_FROM_SD_ADDR; -
firmware/FTM/ftm_definitions.vhd
r10779 r10803 234 234 -- crate reset 235 235 constant CMD_CRESET : std_logic_vector := X"0020"; 236 constant RESET_TIME : integer := 1000;236 constant RESET_TIME : integer := 50; -- hold reset line for 1us (@ 50MHz clk) 237 237 238 238 -- start and end of package
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