- Timestamp:
- 06/01/11 16:52:22 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 2 added
- 7 edited
-
clock_generator_var_ps_struct.vhd (modified) (2 diffs)
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fad_board_struct.vhd (modified) (2 diffs)
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fad_board_with_5300_2_struct.vhd (added)
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fad_definitions.vhd (modified) (1 diff)
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fad_main_struct.vhd (modified) (2 diffs)
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fad_main_with_w53002_struct.vhd (added)
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spi_interface_struct.vhd (modified) (2 diffs)
-
w5300_interface.vhd (modified) (1 diff)
-
w5300_modul2.vhd (modified) (23 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10225 r10900 2 2 -- 3 3 -- Created: 4 -- by - d aqct3.UNKNOWN (IHP110)5 -- at - 1 7:35:41 03.03.20114 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 13:20:47 01.06.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 8 8 -- 9 9 LIBRARY ieee; … … 33 33 -- 34 34 -- Created: 35 -- by - d aqct3.UNKNOWN (IHP110)36 -- at - 1 7:35:41 03.03.201135 -- by - dneise.UNKNOWN (E5B-LABOR6) 36 -- at - 13:20:48 01.06.2011 37 37 -- 38 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)38 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 39 39 -- 40 40 LIBRARY ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10883 r10900 2 2 -- 3 3 -- Created: 4 -- by - d aqct3.UNKNOWN (IHP110)5 -- at - 1 1:58:57 27.05.20116 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 15:10:43 01.06.2011 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 8 8 -- 9 9 LIBRARY ieee; … … 74 74 -- 75 75 -- Created: 76 -- by - d aqct3.UNKNOWN (IHP110)77 -- at - 1 1:58:58 27.05.201178 -- 79 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)76 -- by - dneise.UNKNOWN (E5B-LABOR6) 77 -- at - 15:10:44 01.06.2011 78 -- 79 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 80 80 -- 81 81 LIBRARY ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10892 r10900 193 193 194 194 -- for W5300 modul2 195 constant W5300_RAM_ADDR_WIDTH : integer := 1 4;195 constant W5300_RAM_ADDR_WIDTH : integer := 17; 196 196 197 197 -- not needed -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10883 r10900 2 2 -- 3 3 -- Created: 4 -- by - d aqct3.UNKNOWN (IHP110)5 -- at - 1 1:58:56 27.05.20114 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 13:22:03 01.06.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 8 8 -- 9 9 LIBRARY ieee; … … 82 82 -- 83 83 -- Created: 84 -- by - d aqct3.UNKNOWN (IHP110)85 -- at - 1 1:58:57 27.05.201184 -- by - dneise.UNKNOWN (E5B-LABOR6) 85 -- at - 13:22:04 01.06.2011 86 86 -- 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 88 88 -- 89 89 library ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10744 r10900 2 2 -- 3 3 -- Created: 4 -- by - d aqct3.UNKNOWN (IHP110)5 -- at - 08:31:16 18.05.20114 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 13:20:48 01.06.2011 6 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 8 8 -- 9 9 LIBRARY ieee; … … 38 38 -- 39 39 -- Created: 40 -- by - d aqct3.UNKNOWN (IHP110)41 -- at - 08:31:16 18.05.201140 -- by - dneise.UNKNOWN (E5B-LABOR6) 41 -- at - 13:20:48 01.06.2011 42 42 -- 43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009. 1 (Build 12)43 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 44 44 -- 45 45 LIBRARY ieee; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd
r10888 r10900 53 53 signal RST_TIME : integer range 0 to 500000 := 500000; 54 54 55 signal reset_counter : integer range 0 to RST_TIME:= 0;55 signal reset_counter : integer range 0 to 500000 := 0; 56 56 signal ready : std_logic := '0'; 57 57 begin -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd
r10891 r10900 41 41 42 42 43 -- to be removed: 44 led : out std_logic_vector (7 downto 0) := X"00"; 45 socket_tx_free_out : out std_logic_vector (16 downto 0) := '0' & X"0000"; 43 46 44 47 -- FAD configuration signals: … … 105 108 type state_init_type is ( 106 109 INTERRUPT, RESET, WAIT_FOR_RESET, 107 WRITE_REG, READ_REG, 108 WRITE_DATA, 109 INIT, LOCATE, IM, MT, 110 STX0, STX1, STX2, STX3, 111 SRX0, SRX1, SRX2, SRX3, 112 MAC0, MAC1, MAC2, 113 GW0, GW1, 114 SNM0, SNM1, 115 IP0, IP1, 116 --TIMEOUT, 117 RETRY, 118 SI_MR, SI_IMR, SI_PORTOR, SI_PORT, SI_SSR, SI_CR_OPEN, SI_IS_OPEN, SI_CR_LISTEN, 119 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 110 INIT, 111 LOCATE, IM, MT, 112 STX0, STX1, STX2, STX3, 113 SRX0, SRX1, SRX2, SRX3, 114 MAC0, MAC1, MAC2, 115 GW0, GW1, 116 SNM0, SNM1, 117 IP0, IP1, 118 -- Socket initialisiation 119 SI_MR, SI_IMR, SI_PORTOR, SI_PORT, SI_SSR, SI_CR_OPEN, SI_IS_OPEN, SI_CR_LISTEN, 120 ESTABLISH, EST1, 120 121 121 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, 122 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 123 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, 124 CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY, 122 MAIN, 123 CONFIG, 124 WAIT_100NS, WAIT_UNTIL_DG_IDLE, 125 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 126 CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY, 127 MAIN1, 128 READ_DATA, 129 MAIN2, MAIN3, 130 WRITE_DATA 125 131 126 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA 132 -- these states do not exist anymore. 133 -- WRITE_REG, READ_REG, 134 -- --TIMEOUT, 135 -- RETRY, 136 -- CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, 137 -- CHK_RECEIVED, 127 138 ); 128 139 129 140 type state_write_type is ( 130 WR_START, 131 WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, 132 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 133 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 134 WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 135 WR_STRANGE_WAIT, 136 WR_ACK, WR_WAIT_FOR_ACK, 137 WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, 138 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 139 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2 141 WR_START, 142 WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, 143 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 144 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 145 WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, 146 WR_ADC, WR_ADC1, WR_ADC2, 147 WR_STRANGE_WAIT, 148 WR_ENDFLAG_WAIT, WR_ENDFLAG, 149 WR_ENDFLAG2_WAIT, WR_ENDFLAG2, 150 WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 151 WR_MESSAGE_LEN_HIGH_WORD, WR_MESSAGE_LEN_LOW_WORD, WR_SEND_COMMAND, 152 WR_ACK, WR_WAIT_FOR_ACK 140 153 ); 141 154 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); … … 181 194 signal drs_cnt : integer range 0 to 3 := 0; 182 195 signal channel_cnt : integer range 0 to 9 :=0; 183 signal socket_cnt : integer range 0 to 7 := 0; 196 signal socket_cnt : std_logic_vector (2 downto 0 ) := "000"; 197 -- should be integer range 0 to 7 := 0; , but I didn't manage to get it working... 184 198 signal roi_max : std_logic_vector (10 downto 0) := (others => '0'); 185 199 … … 417 431 when IR1_03 => 418 432 state_init <= INTERRUPT; 419 socket_cnt <= 0;433 socket_cnt <= "000"; 420 434 int_flag <= '0'; 421 435 interrupt_ignore <= '1'; … … 444 458 when IR2_CHECK_WHICH_SN_IRQ => 445 459 if (ready_wi = '1') then 446 if (data_read( socket_cnt) = '1') then -- Sx Interrupt460 if (data_read(conv_integer(socket_cnt)) = '1') then -- Sx Interrupt 447 461 state_interrupt_2 <= IR2_GET_SN_IR; 448 462 else … … 483 497 484 498 if (socket_cnt = 7) then 485 socket_cnt = 0;486 state_interrupt_2 <= IR2_WAIT_ UNTIL_SOCKS_CLOSED;499 socket_cnt <= "000"; 500 state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; 487 501 else 488 502 state_interrupt_2 <= IR2_GET_IR; … … 493 507 if (ready_wi = '1') then 494 508 wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 495 read_wi = '1';509 read_wi <= '1'; 496 510 state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; 497 511 end if; … … 501 515 if (data_read = X"0000") then --closed 502 516 if (socket_cnt = 7) then 503 socket_cnt <= 0;517 socket_cnt <= "000"; 504 518 state_interrupt_2 <= IR2_GOTO_RESET; 505 519 else … … 516 530 state_interrupt_1 <= IR1_01; 517 531 state_interrupt_2 <= IR2_GET_IR; 518 socket_cnt <= 0;532 socket_cnt <= "000"; 519 533 state_init <= RESET; 520 when others =>521 null;534 --when others => 535 --null; 522 536 end case; 523 537 … … 530 544 socks_waiting <= '0'; 531 545 socks_connected <= '0'; 532 socket_cnt <= 0;546 socket_cnt <= "000"; 533 547 interrupt_ignore <= '0'; 534 548 … … 799 813 when SI_PORT => 800 814 wiz_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; 801 wiz_data <= conv_std_logic_vector(FIRST_PORT + socket_cnt, 16);815 wiz_data <= conv_std_logic_vector(FIRST_PORT + unsigned(socket_cnt), 16); 802 816 if (ready_wi = '1') then 803 817 write_wi <= '1'; … … 832 846 socket_cnt <= socket_cnt + 1; 833 847 if (socket_cnt = 7) then 834 socket_cnt <= 0;848 socket_cnt <= "000"; 835 849 state_init <= ESTABLISH; 836 850 else … … 857 871 when X"17" => -- established 858 872 if (socket_cnt = 7) then 859 socket_cnt <= 0;873 socket_cnt <= "000"; 860 874 busy <= '0'; 861 875 state_init <= MAIN; … … 1188 1202 end if; 1189 1203 1190 when others =>1191 state_sig <= X"3F";1204 --when others => 1205 --state_sig <= X"3F"; 1192 1206 end case; -- state_data_read 1193 1207 … … 1265 1279 state_write <= WR_CHECK_FOR_FIFO_SPACE_03; 1266 1280 read_wi <= '1'; 1267 end if 1281 end if; 1268 1282 1269 1283 when WR_CHECK_FOR_FIFO_SPACE_03 => … … 1282 1296 else 1283 1297 if (local_write_header_flag = '1') then 1284 state_write <= WR_HEADER_FETCH _1ST;1298 state_write <= WR_HEADER_FETCH; 1285 1299 else 1286 1300 state_write <= WR_ADC; … … 1302 1316 state_sig <= X"4A"; 1303 1317 ram_addr <= local_ram_start_addr + local_ram_addr; 1304 state_write <= WR_HEADER_WAIT _1ST;1318 state_write <= WR_HEADER_WAIT; 1305 1319 1306 1320 when WR_HEADER_WAIT => … … 1380 1394 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1381 1395 wiz_data <= ram_data; 1382 write_wi = '1';1396 write_wi <= '1'; 1383 1397 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1384 1398 data_cnt <= data_cnt + 1; … … 1422 1436 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1423 1437 wiz_data <= ram_data; 1424 write_wi = '1';1438 write_wi <= '1'; 1425 1439 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1426 1440 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; … … 1434 1448 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1435 1449 wiz_data <= ram_data; 1436 write_wi = '1';1450 write_wi <= '1'; 1437 1451 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1438 1452 state_write <= WR_STRANGE_WAIT; … … 1455 1469 1456 1470 when WR_MESSAGE_LEN_HIGH_WORD => 1457 if (ready_ i = '1') then1471 if (ready_wi = '1') then 1458 1472 wiz_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; 1459 1473 wiz_data <= (0 => write_length_bytes (16), others => '0'); … … 1476 1490 wiz_data <= X"0020"; -- Send 1477 1491 write_wi <= '1'; 1478 end if 1492 end if; 1479 1493 state_write <= WR_ACK; 1480 1494 … … 1494 1508 1495 1509 1496 when others =>1497 null;1510 --when others => 1511 --null; 1498 1512 end case; 1499 1513 -- End WRITE_DATA 1500 1514 1501 1515 1502 when others =>1503 null;1516 --when others => 1517 --null; 1504 1518 end case; 1505 1519 end if; -- int_flag = '0'
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