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Changeset 10988 for firmware/FAD/FACT_FAD_20MHz_VAR_PS

Timestamp:

06/10/11 16:59:58 (14 years ago)

Author:

neise

Message:

Location:

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib

Files:

: 1 added
: 6 edited

. (modified) (1 prop)
hds/.cache.dat (modified) ( previous)
hds/@f@a@d_@board/struct.bd (modified) (273 diffs)
hds/@f@a@d_@board/struct.bd.bak (modified) (1 diff)
hds/@f@a@d_main/struct.bd (modified) (152 diffs)
hds/@f@a@d_main/struct.bd.bak (modified) (986 diffs)
ise (added)

Legend:

: Unmodified
: Added
: Removed

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib ¶

Property svn:ignore

TabularUnified

old	new
4	4	*.sig
5	5	iMPACT
6		~~ise~~
7	6	work

TabularUnified firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd ¶

-              r10958
+              r10988
 uid 19500,0
+)
+(Instance
+name "I4"
+duLibraryName "moduleware"
+duName "assignment"
+elements [
+]
+mwi 1
+uid 20188,0
+)
+]
 embeddedInstances [
 …
 (vvPair
 variable "date"
 value "09.06.2011"
+value "10.06.2011"
+)
 (vvPair
 variable "day"
 value "Do"
+value "Fr"
+)
 (vvPair
 variable "day_long"
 value "Donnerstag"
+value "Freitag"
+)
 (vvPair
 variable "dd"
 value "09"
+value "10"
+)
 (vvPair
 …
 (vvPair
 variable "time"
 value "16:56:32"
+value "10:56:46"
+)
 (vvPair
 …
+)
 xt "39000,52800,70500,53600"
+st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
+st "SIGNAL board_id              : std_logic_vector(3 downto 0)
+"
+)
+)
 …
+)
 xt "39000,54400,70500,55200"
+st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
+st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
+"
+)
+)
 …
+)
 xt "39000,50400,66000,51200"
+st "SIGNAL adc_data_array        : adc_data_array_type"
+st "SIGNAL adc_data_array        : adc_data_array_type
+"
+)
+)
 …
+)
 xt "39000,35000,71500,35800"
+st "RSRLOAD               : std_logic                      := '0'"
+st "RSRLOAD               : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,20600,57000,21400"
+st "DAC_CS                : std_logic"
+st "DAC_CS                : std_logic
+"
+)
+)
 …
+)
 xt "39000,16600,57000,17400"
+st "X_50M                 : STD_LOGIC"
+st "X_50M                 : STD_LOGIC
+"
+)
+)
 …
+)
 xt "39000,15000,57000,15800"
+st "TRG                   : STD_LOGIC"
+st "TRG                   : STD_LOGIC
+"
+)
+)
 …
+)
 xt "39000,19800,67000,20600"
+st "A_CLK                 : std_logic_vector(3 downto 0)"
+st "A_CLK                 : std_logic_vector(3 downto 0)
+"
+)
+)
 …
+)
 xt "39000,28600,57000,29400"
+st "OE_ADC                : STD_LOGIC"
+st "OE_ADC                : STD_LOGIC
+"
+)
+)
 …
+)
 xt "39000,7000,67000,7800"
+st "A_OTR                 : std_logic_vector(3 DOWNTO 0)"
+st "A_OTR                 : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,3800,67500,4600"
+st "A0_D                  : std_logic_vector(11 DOWNTO 0)"
+st "A0_D                  : std_logic_vector(11 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,4600,67500,5400"
+st "A1_D                  : std_logic_vector(11 DOWNTO 0)"
+st "A1_D                  : std_logic_vector(11 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,5400,67500,6200"
+st "A2_D                  : std_logic_vector(11 DOWNTO 0)"
+st "A2_D                  : std_logic_vector(11 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,6200,67500,7000"
+st "A3_D                  : std_logic_vector(11 DOWNTO 0)"
+st "A3_D                  : std_logic_vector(11 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,7800,57000,8600"
+st "D0_SROUT              : std_logic"
+st "D0_SROUT              : std_logic
+"
+)
+)
 …
+)
 xt "39000,8600,57000,9400"
+st "D1_SROUT              : std_logic"
+st "D1_SROUT              : std_logic
+"
+)
+)
 …
+)
 xt "39000,9400,57000,10200"
+st "D2_SROUT              : std_logic"
+st "D2_SROUT              : std_logic
+"
+)
+)
 …
+)
 xt "39000,10200,57000,11000"
+st "D3_SROUT              : std_logic"
+st "D3_SROUT              : std_logic
+"
+)
+)
 …
+)
 xt "39000,23800,77500,24600"
+st "D_A                   : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
+st "D_A                   : std_logic_vector(3 DOWNTO 0)   := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,23000,71500,23800"
+st "DWRITE                : std_logic                      := '0'"
+st "DWRITE                : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,36600,57000,37400"
+st "S_CLK                 : std_logic"
+st "S_CLK                 : std_logic
+"
+)
+)
 …
+)
 xt "39000,39000,67000,39800"
+st "W_A                   : std_logic_vector(9 DOWNTO 0)"
+st "W_A                   : std_logic_vector(9 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,44600,67500,45400"
+st "W_D                   : std_logic_vector(15 DOWNTO 0)"
+st "W_D                   : std_logic_vector(15 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,41400,71500,42200"
+st "W_RES                 : std_logic                      := '1'"
+st "W_RES                 : std_logic                      := '1'
+"
+)
+)
 …
+)
 xt "39000,40600,71500,41400"
+st "W_RD                  : std_logic                      := '1'"
+st "W_RD                  : std_logic                      := '1'
+"
+)
+)
 …
+)
 xt "39000,43000,71500,43800"
+st "W_WR                  : std_logic                      := '1'"
+st "W_WR                  : std_logic                      := '1'
+"
+)
+)
 …
+)
 xt "39000,15800,57000,16600"
+st "W_INT                 : std_logic"
+st "W_INT                 : std_logic
+"
+)
+)
 …
+)
 xt "39000,39800,71500,40600"
+st "W_CS                  : std_logic                      := '1'"
+st "W_CS                  : std_logic                      := '1'
+"
+)
+)
 …
+)
 xt "39000,27800,71500,28600"
+st "MOSI                  : std_logic                      := '0'"
+st "MOSI                  : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,43800,57000,44600"
+st "MISO                  : std_logic"
+st "MISO                  : std_logic
+"
+)
+)
 …
+)
 xt "39000,31800,57000,32600"
+st "RS485_C_RE            : std_logic"
+st "RS485_C_RE            : std_logic
+"
+)
+)
 …
+)
 xt "39000,30200,57000,31000"
+st "RS485_C_DE            : std_logic"
+st "RS485_C_DE            : std_logic
+"
+)
+)
 …
+)
 xt "39000,34200,57000,35000"
+st "RS485_E_RE            : std_logic"
+st "RS485_E_RE            : std_logic
+"
+)
+)
 …
+)
 xt "39000,32600,57000,33400"
+st "RS485_E_DE            : std_logic"
+st "RS485_E_DE            : std_logic
+"
+)
+)
 …
+)
 xt "39000,21400,71500,22200"
+st "DENABLE               : std_logic                      := '0'"
+st "DENABLE               : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,26200,57000,27000"
+st "EE_CS                 : std_logic"
+st "EE_CS                 : std_logic
+"
+)
+)
 …
+)
 xt "39000,24600,77500,25400"
+st "D_T                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
+st "D_T                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
+"
+)
+)
 …
+)
 xt "39000,25400,77500,26200"
+st "D_T2                  : std_logic_vector(1 DOWNTO 0)   := (others => '0')"
+st "D_T2                  : std_logic_vector(1 DOWNTO 0)   := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,18200,77500,19000"
+st "A1_T                  : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
+st "A1_T                  : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
+"
+)
+)
 …
+)
 xt "39000,47200,61000,48000"
+st "SIGNAL CLK_50                : std_logic"
+st "SIGNAL CLK_50                : std_logic
+"
+)
+)
 …
+)
 xt "39000,17400,77500,18200"
+st "A0_T                  : std_logic_vector(7 DOWNTO 0)   := (others => '0')"
+st "A0_T                  : std_logic_vector(7 DOWNTO 0)   := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,31000,57000,31800"
+st "RS485_C_DO            : std_logic"
+st "RS485_C_DO            : std_logic
+"
+)
+)
 …
+)
 xt "39000,14200,57000,15000"
+st "RS485_E_DI            : std_logic"
+st "RS485_E_DI            : std_logic
+"
+)
+)
 …
+)
 xt "39000,33400,57000,34200"
+st "RS485_E_DO            : std_logic"
+st "RS485_E_DO            : std_logic
+"
+)
+)
 …
+)
 xt "39000,35800,71500,36600"
+st "SRIN                  : std_logic                      := '0'"
+st "SRIN                  : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,19000,57000,19800"
+st "AMBER_LED             : std_logic"
+st "AMBER_LED             : std_logic
+"
+)
+)
 …
+)
 xt "39000,27000,57000,27800"
+st "GREEN_LED             : std_logic"
+st "GREEN_LED             : std_logic
+"
+)
+)
 …
+)
 xt "39000,29400,57000,30200"
+st "RED_LED               : std_logic"
+st "RED_LED               : std_logic
+"
+)
+)
 …
+)
 xt "39000,12600,68000,13400"
+st "LINE                  : std_logic_vector( 5 DOWNTO 0 )"
+st "LINE                  : std_logic_vector( 5 DOWNTO 0 )
+"
+)
+)
 …
+)
 xt "39000,13400,57000,14200"
+st "REFCLK                : std_logic"
+st "REFCLK                : std_logic
+"
+)
+)
 …
+)
 xt "39000,11800,67000,12600"
+st "D_T_in                : std_logic_vector(1 DOWNTO 0)"
+st "D_T_in                : std_logic_vector(1 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,57600,81000,58400"
+st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
+st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
+"
+)
+)
 …
+)
 xt "39000,11000,67000,11800"
+st "D_PLLLCK              : std_logic_vector(3 DOWNTO 0)"
+st "D_PLLLCK              : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,37400,67000,38200"
+st "TCS                   : std_logic_vector(3 DOWNTO 0)"
+st "TCS                   : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,22200,77500,23000"
+st "DSRCLK                : std_logic_vector(3 DOWNTO 0)   := (others => '0')"
+st "DSRCLK                : std_logic_vector(3 DOWNTO 0)   := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,49600,75000,50400"
+st "SIGNAL SRCLK                 : std_logic                      := '0'"
+st "SIGNAL SRCLK                 : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,51200,75000,52000"
+st "SIGNAL alarm_refclk_too_high : std_logic                      := '0'"
+st "SIGNAL alarm_refclk_too_high : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,52000,75000,52800"
+st "SIGNAL alarm_refclk_too_low  : std_logic                      := '0'"
+st "SIGNAL alarm_refclk_too_low  : std_logic                      := '0'
+"
+)
+)
 …
+)
 xt "39000,53600,81000,54400"
+st "SIGNAL counter_result        : std_logic_vector(11 downto 0)  := (others => '0')"
+st "SIGNAL counter_result        : std_logic_vector(11 downto 0)  := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,46400,61000,47200"
+st "SIGNAL ADC_CLK               : std_logic"
+st "SIGNAL ADC_CLK               : std_logic
+"
+)
+)
 …
 sl 0
 ro 270
 xt "87500,143625,89000,144375"
+xt "112500,143625,114000,144375"
+)
 (Line
 …
 sl 0
 ro 270
 xt "87000,144000,87500,144000"
 pts [
 "87000,144000"
 "87500,144000"
+xt "112000,144000,112500,144000"
+pts [
+"112000,144000"
+"112500,144000"
+]
+)
 …
 va (VaSet
+)
 xt "90000,143500,92900,144500"
+xt "115000,143500,117900,144500"
 st "TRG_V"
 blo "90000,144300"
+blo "115000,144300"
 tm "WireNameMgr"
+)
 …
+)
 xt "39000,38200,71500,39000"
+st "TRG_V                 : std_logic                      := '0'"
+st "TRG_V                 : std_logic                      := '0'
+"
+)
+)
 …
 font "Courier New,8,0"
+)
+xt "39000,62400,96000,63200"
+st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
+xt "39000,63200,96000,64000"
+st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
+"
+)
+)
 …
+)
 xt "39000,56000,61000,56800"
+st "SIGNAL debug_data_ram_empty  : std_logic"
+st "SIGNAL debug_data_ram_empty  : std_logic
+"
+)
+)
 …
+)
 xt "39000,56800,61000,57600"
+st "SIGNAL debug_data_valid      : std_logic"
+st "SIGNAL debug_data_valid      : std_logic
+"
+)
+)
 …
+)
 xt "39000,58400,96000,59200"
+st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
+st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
+"
+)
+)
 …
 xt "39000,48000,70500,49600"
 st "-- for debugging
+SIGNAL DG_state              : std_logic_vector(7 downto 0)"
+SIGNAL DG_state              : std_logic_vector(7 downto 0)
+"
+)
+)
 …
+)
 xt "39000,61600,86000,62400"
+st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
+st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true
+"
+)
+)
 …
+)
 xt "39000,42200,77500,43000"
+st "W_T                   : std_logic_vector( 3 DOWNTO 0 ) := (others => '0')"
+st "W_T                   : std_logic_vector( 3 DOWNTO 0 ) := (others => '0')
+"
+)
+)
 …
+)
 xt "39000,55200,61000,56000"
+st "SIGNAL dac_cs1               : std_logic"
+st "SIGNAL dac_cs1               : std_logic
+"
+)
+)
 …
+)
 xt "39000,60800,70500,61600"
+st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
+st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
 …
+)
 xt "39000,60000,61000,60800"
+st "SIGNAL sclk                  : std_logic"
+st "SIGNAL sclk                  : std_logic
+"
+)
+)
 …
+)
 xt "39000,59200,61000,60000"
+st "SIGNAL mosi1                 : std_logic"
+)
+)
+*265 (Wire
+st "SIGNAL mosi1                 : std_logic
+"
+)
+)
+*265 (MWC
+uid 20188,0
+optionalChildren [
+*266 (CptPort
+uid 20197,0
+optionalChildren [
+*267 (Line
+uid 20202,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+)
+xt "105000,137000,105000,137000"
+pts [
+"105000,137000"
+"105000,137000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 20198,0
+ro 90
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "104250,136625,105000,137375"
+)
+tg (CPTG
+uid 20199,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 20200,0
+sl 0
+va (VaSet
+isHidden 1
+font "arial,8,0"
+)
+xt "498200,98500,499000,99500"
+st "s"
+blo "498200,99300"
+)
+s (Text
+uid 20201,0
+sl 0
+va (VaSet
+font "arial,8,0"
+)
+xt "498200,99500,498200,99500"
+blo "498200,99500"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "s"
+t "std_logic"
+o 73
+i "'1'"
+)
+)
+)
+*268 (CptPort
+uid 20203,0
+optionalChildren [
+*269 (Line
+uid 20208,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+)
+xt "108000,137000,108000,137000"
+pts [
+"108000,137000"
+"108000,137000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 20204,0
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TabularUnified firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak ¶

r10958	r10988
299	299	(vvPair
300	300	variable "time"
301		value "16:56:31"
	301	value "16:56:32"
302	302	)
303	303	(vvPair

TabularUnified firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd ¶

r10958	r10988
348	348	)
349	349	(Instance
350		name "~~U_7~~"
	350	name "Inst_rs485_receiver"
351	351	duLibraryName "FACT_FAD_lib"
352	352	duName "FAD_rs485_receiver"
…	…
470	470	(vvPair
471	471	variable "date"
472		value "09.06.2011"
	472	value "10.06.2011"
473	473	)
474	474	(vvPair
475	475	variable "day"
476		value "Do"
	476	value "Fr"
477	477	)
478	478	(vvPair
479	479	variable "day_long"
480		value "~~Donners~~tag"
	480	value "Freitag"
481	481	)
482	482	(vvPair
483	483	variable "dd"
484		value "09"
	484	value "10"
485	485	)
486	486	(vvPair
…	…
622	622	(vvPair
623	623	variable "time"
624		value "1~~6:55:25~~"
	624	value "10:56:40"
625	625	)
626	626	(vvPair
…	…
714	714	)
715	715	xt "-172000,127600,-125500,128400"
716		st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"
717		"
	716	st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\""
718	717	)
719	718	)
…	…
733	732	)
734	733	xt "-172000,60400,-129000,61200"
735		st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
736		"
	734	st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
737	735	)
738	736	)
…	…
752	750	)
753	751	xt "-172000,65200,-136500,66000"
754		st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)
755		"
	752	st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)"
756	753	)
757	754	)
…	…
771	768	)
772	769	xt "-172000,95600,-129000,96400"
773		st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
774		"
	770	st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
775	771	)
776	772	)
…	…
790	786	)
791	787	xt "-172000,96400,-136500,97200"
792		st "SIGNAL ram_data : std_logic_vector(15 downto 0)
793		"
	788	st "SIGNAL ram_data : std_logic_vector(15 downto 0)"
794	789	)
795	790	)
…	…
809	804	)
810	805	xt "-172000,43200,-129000,44000"
811		st "wiz_reset : std_logic := '1'
812		"
	806	st "wiz_reset : std_logic := '1'"
813	807	)
814	808	)
…	…
828	822	)
829	823	xt "-172000,40800,-140500,41600"
830		st "wiz_addr : std_logic_vector(9 DOWNTO 0)
831		"
	824	st "wiz_addr : std_logic_vector(9 DOWNTO 0)"
832	825	)
833	826	)
…	…
847	840	)
848	841	xt "-172000,45600,-140000,46400"
849		st "wiz_data : std_logic_vector(15 DOWNTO 0)
850		"
	842	st "wiz_data : std_logic_vector(15 DOWNTO 0)"
851	843	)
852	844	)
…	…
866	858	)
867	859	xt "-172000,41600,-129000,42400"
868		st "wiz_cs : std_logic := '1'
869		"
	860	st "wiz_cs : std_logic := '1'"
870	861	)
871	862	)
…	…
885	876	)
886	877	xt "-172000,44000,-129000,44800"
887		st "wiz_wr : std_logic := '1'
888		"
	878	st "wiz_wr : std_logic := '1'"
889	879	)
890	880	)
…	…
904	894	)
905	895	xt "-172000,42400,-129000,43200"
906		st "wiz_rd : std_logic := '1'
907		"
	896	st "wiz_rd : std_logic := '1'"
908	897	)
909	898	)
…	…
922	911	)
923	912	xt "-172000,14400,-150000,15200"
924		st "wiz_int : std_logic
925		"
	913	st "wiz_int : std_logic"
926	914	)
927	915	)
…	…
3398	3386	)
3399	3387	xt "-172000,10400,-140500,11200"
3400		st "board_id : std_logic_vector(3 DOWNTO 0)
3401		"
	3388	st "board_id : std_logic_vector(3 DOWNTO 0)"
3402	3389	)
3403	3390	)
…	…
3418	3405	)
3419	3406	xt "-172000,13600,-150000,14400"
3420		st "trigger : std_logic
3421		"
	3407	st "trigger : std_logic"
3422	3408	)
3423	3409	)
…	…
5464	5450	)
5465	5451	xt "-172000,11200,-140500,12000"
5466		st "crate_id : std_logic_vector(1 DOWNTO 0)
5467		"
	5452	st "crate_id : std_logic_vector(1 DOWNTO 0)"
5468	5453	)
5469	5454	)
…	…
5723	5708	)
5724	5709	xt "-172000,97200,-129000,98000"
5725		st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
5726		"
	5710	st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
5727	5711	)
5728	5712	)
…	…
5743	5727	)
5744	5728	xt "-172000,124400,-125500,125200"
5745		st "SIGNAL wiz_write_ea : std_logic := '0'
5746		"
	5729	st "SIGNAL wiz_write_ea : std_logic := '0'"
5747	5730	)
5748	5731	)
…	…
5764	5747	)
5765	5748	xt "-172000,126800,-119500,127600"
5766		st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')
5767		"
	5749	st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')"
5768	5750	)
5769	5751	)
…	…
5786	5768	)
5787	5769	xt "-172000,123600,-119500,124400"
5788		st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
5789		"
	5770	st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
5790	5771	)
5791	5772	)
…	…
5807	5788	)
5808	5789	xt "-172000,122800,-119500,123600"
5809		st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')
5810		"
	5790	st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')"
5811	5791	)
5812	5792	)
…	…
5827	5807	)
5828	5808	xt "-172000,125200,-125500,126000"
5829		st "SIGNAL wiz_write_end : std_logic := '0'
5830		"
	5809	st "SIGNAL wiz_write_end : std_logic := '0'"
5831	5810	)
5832	5811	)
…	…
5847	5826	)
5848	5827	xt "-172000,126000,-125500,126800"
5849		st "SIGNAL wiz_write_header : std_logic := '0'
5850		"
	5828	st "SIGNAL wiz_write_header : std_logic := '0'"
5851	5829	)
5852	5830	)
…	…
5865	5843	)
5866	5844	xt "-172000,98000,-146500,98800"
5867		st "SIGNAL ram_write_ea : std_logic
5868		"
	5845	st "SIGNAL ram_write_ea : std_logic"
5869	5846	)
5870	5847	)
…	…
5884	5861	)
5885	5862	xt "-172000,98800,-125500,99600"
5886		st "SIGNAL ram_write_ready : std_logic := '0'
5887		"
	5863	st "SIGNAL ram_write_ready : std_logic := '0'"
5888	5864	)
5889	5865	)
…	…
5902	5878	)
5903	5879	xt "-172000,102800,-145000,103600"
5904		st "SIGNAL roi_max : roi_max_type
5905		"
	5880	st "SIGNAL roi_max : roi_max_type"
5906	5881	)
5907	5882	)
…	…
5921	5896	)
5922	5897	xt "-172000,92400,-136500,93200"
5923		st "SIGNAL package_length : std_logic_vector(15 downto 0)
5924		"
	5898	st "SIGNAL package_length : std_logic_vector(15 downto 0)"
5925	5899	)
5926	5900	)
…	…
5940	5914	)
5941	5915	xt "-172000,24000,-129000,24800"
5942		st "adc_oeb : std_logic := '1'
5943		"
	5916	st "adc_oeb : std_logic := '1'"
5944	5917	)
5945	5918	)
…	…
6145	6118	bg "0,0,32768"
6146	6119	)
6147		xt "85200,178000,96000,179000"
	6120	xt "85200,178000,95900,179000"
6148	6121	st "
6149	6122	by %user on %dd %month %year
…	…
6464	6437	)
6465	6438	xt "-172000,16000,-150000,16800"
6466		st "CLK_25_PS : std_logic
6467		"
	6439	st "CLK_25_PS : std_logic"
6468	6440	)
6469	6441	)
…	…
6528	6500	)
6529	6501	xt "-172000,16800,-150000,17600"
6530		st "CLK_50 : std_logic
6531		"
	6502	st "CLK_50 : std_logic"
6532	6503	)
6533	6504	)
…	…
6548	6519	)
6549	6520	xt "-172000,48400,-146500,49200"
6550		st "SIGNAL CLK_25 : std_logic
6551		"
	6521	st "SIGNAL CLK_25 : std_logic"
6552	6522	)
6553	6523	)
…	…
6610	6580	)
6611	6581	xt "-172000,3200,-150000,4000"
6612		st "CLK : std_logic
6613		"
	6582	st "CLK : std_logic"
6614	6583	)
6615	6584	)
…	…
6629	6598	)
6630	6599	xt "-172000,9600,-140500,10400"
6631		st "adc_otr_array : std_logic_vector(3 DOWNTO 0)
6632		"
	6600	st "adc_otr_array : std_logic_vector(3 DOWNTO 0)"
6633	6601	)
6634	6602	)
…	…
6647	6615	)
6648	6616	xt "-172000,8800,-145000,9600"
6649		st "adc_data_array : adc_data_array_type
6650		"
	6617	st "adc_data_array : adc_data_array_type"
6651	6618	)
6652	6619	)
…	…
6711	6678	)
6712	6679	xt "-172000,78000,-125500,78800"
6713		st "SIGNAL drs_clk_en : std_logic := '0'
6714		"
	6680	st "SIGNAL drs_clk_en : std_logic := '0'"
6715	6681	)
6716	6682	)
…	…
6729	6695	)
6730	6696	xt "-172000,84400,-140500,85200"
6731		st "SIGNAL drs_s_cell_array : drs_s_cell_array_type
6732		"
	6697	st "SIGNAL drs_s_cell_array : drs_s_cell_array_type"
6733	6698	)
6734	6699	)
…	…
6748	6713	)
6749	6714	xt "-172000,78800,-125500,79600"
6750		st "SIGNAL drs_read_s_cell : std_logic := '0'
6751		"
	6715	st "SIGNAL drs_read_s_cell : std_logic := '0'"
6752	6716	)
6753	6717	)
…	…
6768	6732	)
6769	6733	xt "-172000,31200,-123000,32000"
6770		st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')
6771		"
	6734	st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')"
6772	6735	)
6773	6736	)
…	…
6787	6750	)
6788	6751	xt "-172000,32000,-129000,32800"
6789		st "drs_dwrite : std_logic := '1'
6790		"
	6752	st "drs_dwrite : std_logic := '1'"
6791	6753	)
6792	6754	)
…	…
6895	6857	)
6896	6858	xt "-172000,5600,-150000,6400"
6897		st "SROUT_in_0 : std_logic
6898		"
	6859	st "SROUT_in_0 : std_logic"
6899	6860	)
6900	6861	)
…	…
6913	6874	)
6914	6875	xt "-172000,6400,-150000,7200"
6915		st "SROUT_in_1 : std_logic
6916		"
	6876	st "SROUT_in_1 : std_logic"
6917	6877	)
6918	6878	)
…	…
6931	6891	)
6932	6892	xt "-172000,7200,-150000,8000"
6933		st "SROUT_in_2 : std_logic
6934		"
	6893	st "SROUT_in_2 : std_logic"
6935	6894	)
6936	6895	)
…	…
6949	6908	)
6950	6909	xt "-172000,8000,-150000,8800"
6951		st "SROUT_in_3 : std_logic
6952		"
	6910	st "SROUT_in_3 : std_logic"
6953	6911	)
6954	6912	)
…	…
7147	7105	)
7148	7106	xt "-172000,79600,-146500,80400"
7149		st "SIGNAL drs_read_s_cell_ready : std_logic
7150		"
	7107	st "SIGNAL drs_read_s_cell_ready : std_logic"
7151	7108	)
7152	7109	)
…	…
7803	7760	)
7804	7761	xt "-172000,21600,-129000,22400"
7805		st "RSRLOAD : std_logic := '0'
7806		"
	7762	st "RSRLOAD : std_logic := '0'"
7807	7763	)
7808	7764	)
…	…
7867	7823	)
7868	7824	xt "-172000,22400,-129000,23200"
7869		st "SRCLK : std_logic := '0'
7870		"
	7825	st "SRCLK : std_logic := '0'"
7871	7826	)
7872	7827	)
…	…
7933	7888	)
7934	7889	xt "-172000,33600,-123000,34400"
7935		st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
7936		"
	7890	st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
7937	7891	)
7938	7892	)
…	…
7951	7905	)
7952	7906	xt "-172000,110000,-146500,110800"
7953		st "SIGNAL sensor_ready : std_logic
7954		"
	7907	st "SIGNAL sensor_ready : std_logic"
7955	7908	)
7956	7909	)
…	…
7969	7922	)
7970	7923	xt "-172000,109200,-142500,110000"
7971		st "SIGNAL sensor_array : sensor_array_type
7972		"
	7924	st "SIGNAL sensor_array : sensor_array_type"
7973	7925	)
7974	7926	)
…	…
7989	7941	)
7990	7942	xt "-172000,59600,-137000,60400"
7991		st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)
7992		"
	7943	st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)"
7993	7944	)
7994	7945	)
…	…
8007	7958	)
8008	7959	xt "-172000,58800,-141500,59600"
8009		st "SIGNAL adc_data_array_int : adc_data_array_type
8010		"
	7960	st "SIGNAL adc_data_array_int : adc_data_array_type"
8011	7961	)
8012	7962	)
…	…
8848	8798	)
8849	8799	xt "-172000,36800,-150000,37600"
8850		st "sclk : std_logic
8851		"
	8800	st "sclk : std_logic"
8852	8801	)
8853	8802	)
…	…
8868	8817	)
8869	8818	xt "-172000,44800,-150000,45600"
8870		st "sio : std_logic
8871		"
	8819	st "sio : std_logic"
8872	8820	)
8873	8821	)
…	…
8886	8834	)
8887	8835	xt "-172000,28000,-150000,28800"
8888		st "dac_cs : std_logic
8889		"
	8836	st "dac_cs : std_logic"
8890	8837	)
8891	8838	)
…	…
8905	8852	)
8906	8853	xt "-172000,37600,-140500,38400"
8907		st "sensor_cs : std_logic_vector(3 DOWNTO 0)
8908		"
	8854	st "sensor_cs : std_logic_vector(3 DOWNTO 0)"
8909	8855	)
8910	8856	)
…	…
9104	9050	)
9105	9051	xt "-172000,35200,-129000,36000"
9106		st "mosi : std_logic := '0'
9107		"
	9052	st "mosi : std_logic := '0'"
9108	9053	)
9109	9054	)
…	…
9170	9115	)
9171	9116	xt "-172000,30400,-115500,31200"
9172		st "denable : std_logic := '0' -- default domino wave off
9173		"
	9117	st "denable : std_logic := '0' -- default domino wave off"
9174	9118	)
9175	9119	)
…	…
9957	9901	)
9958	9902	xt "-172000,108400,-146500,109200"
9959		st "SIGNAL sclk_enable : std_logic
9960		"
	9903	st "SIGNAL sclk_enable : std_logic"
9961	9904	)
9962	9905	)
…	…
9976	9919	)
9977	9920	xt "-172000,58000,-146500,58800"
9978		st "SIGNAL adc_clk_en : std_logic
9979		"
	9921	st "SIGNAL adc_clk_en : std_logic"
9980	9922	)
9981	9923	)
…	…
10449	10391	)
10450	10392	xt "-172000,93200,-110000,94000"
10451		st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards
10452		"
	10393	st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards"
10453	10394	)
10454	10395	)
…	…
10471	10412	)
10472	10413	xt "-172000,94000,-109000,94800"
10473		st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once
10474		"
	10414	st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once"
10475	10415	)
10476	10416	)
…	…
10492	10432	)
10493	10433	xt "-172000,94800,-101500,95600"
10494		st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift
10495		"
	10434	st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift"
10496	10435	)
10497	10436	)
…	…
10511	10450	)
10512	10451	xt "-172000,114800,-125500,115600"
10513		st "SIGNAL srclk_enable : std_logic := '0'
10514		"
	10452	st "SIGNAL srclk_enable : std_logic := '0'"
10515	10453	)
10516	10454	)
…	…
10896	10834	)
10897	10835	xt "-172000,57200,-125500,58000"
10898		st "SIGNAL SRCLK1 : std_logic := '0'
10899		"
	10836	st "SIGNAL SRCLK1 : std_logic := '0'"
10900	10837	)
10901	10838	)
…	…
10914	10851	)
10915	10852	xt "-172000,106800,-146500,107600"
10916		st "SIGNAL s_trigger : std_logic
10917		"
	10853	st "SIGNAL s_trigger : std_logic"
10918	10854	)
10919	10855	)
…	…
10932	10868	)
10933	10869	xt "-172000,117200,-146500,118000"
10934		st "SIGNAL start_srin_write_8b : std_logic
10935		"
	10870	st "SIGNAL start_srin_write_8b : std_logic"
10936	10871	)
10937	10872	)
…	…
10951	10886	)
10952	10887	xt "-172000,115600,-125500,116400"
10953		st "SIGNAL srin_write_ack : std_logic := '0'
10954		"
	10888	st "SIGNAL srin_write_ack : std_logic := '0'"
10955	10889	)
10956	10890	)
…	…
10970	10904	)
10971	10905	xt "-172000,116400,-125500,117200"
10972		st "SIGNAL srin_write_ready : std_logic := '0'
10973		"
	10906	st "SIGNAL srin_write_ready : std_logic := '0'"
10974	10907	)
10975	10908	)
…	…
10990	10923	)
10991	10924	xt "-172000,85200,-119500,86000"
10992		st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')
10993		"
	10925	st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')"
10994	10926	)
10995	10927	)
…	…
11009	10941	)
11010	10942	xt "-172000,23200,-129000,24000"
11011		st "SRIN_out : std_logic := '0'
11012		"
	10943	st "SRIN_out : std_logic := '0'"
11013	10944	)
11014	10945	)
…	…
11526	11457	)
11527	11458	xt "-172000,110800,-146500,111600"
11528		st "SIGNAL socks_connected : std_logic
11529		"
	11459	st "SIGNAL socks_connected : std_logic"
11530	11460	)
11531	11461	)
…	…
11544	11474	)
11545	11475	xt "-172000,111600,-146500,112400"
11546		st "SIGNAL socks_waiting : std_logic
11547		"
	11476	st "SIGNAL socks_waiting : std_logic"
11548	11477	)
11549	11478	)
…	…
11562	11491	)
11563	11492	xt "-172000,32800,-150000,33600"
11564		st "green : std_logic
11565		"
	11493	st "green : std_logic"
11566	11494	)
11567	11495	)
…	…
11624	11552	)
11625	11553	xt "-172000,26400,-150000,27200"
11626		st "amber : std_logic
11627		"
	11554	st "amber : std_logic"
11628	11555	)
11629	11556	)
…	…
11686	11613	)
11687	11614	xt "-172000,36000,-150000,36800"
11688		st "red : std_logic
11689		"
	11615	st "red : std_logic"
11690	11616	)
11691	11617	)
…	…
12185	12111	)
12186	12112	xt "-172000,83600,-146500,84400"
12187		st "SIGNAL drs_readout_started : std_logic
12188		"
	12113	st "SIGNAL drs_readout_started : std_logic"
12189	12114	)
12190	12115	)
…	…
12203	12128	)
12204	12129	xt "-172000,118800,-146500,119600"
12205		st "SIGNAL trigger_enable : std_logic
12206		"
	12130	st "SIGNAL trigger_enable : std_logic"
12207	12131	)
12208	12132	)
…	…
12891	12815	st "-- --
12892	12816	-- drs_dwrite : out std_logic := '1';
12893		SIGNAL drs_readout_ready : std_logic := '0'
12894		"
	12817	SIGNAL drs_readout_ready : std_logic := '0'"
12895	12818	)
12896	12819	)
…	…
12909	12832	)
12910	12833	xt "-172000,82800,-146500,83600"
12911		st "SIGNAL drs_readout_ready_ack : std_logic
12912		"
	12834	st "SIGNAL drs_readout_ready_ack : std_logic"
12913	12835	)
12914	12836	)
…	…
13164	13086	)
13165	13087	xt "-172000,61200,-125500,62000"
13166		st "SIGNAL c_trigger_enable : std_logic := '0'
13167		"
	13088	st "SIGNAL c_trigger_enable : std_logic := '0'"
13168	13089	)
13169	13090	)
…	…
13679	13600	)
13680	13601	xt "-172000,4000,-140500,4800"
13681		st "D_T_in : std_logic_vector(1 DOWNTO 0)
13682		"
	13602	st "D_T_in : std_logic_vector(1 DOWNTO 0)"
13683	13603	)
13684	13604	)
…	…
13743	13663	)
13744	13664	xt "-172000,12000,-118500,12800"
13745		st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
13746		"
	13665	st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
13747	13666	)
13748	13667	)
…	…
13808	13727	)
13809	13728	xt "-172000,12800,-111000,13600"
13810		st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
13811		"
	13729	st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
13812	13730	)
13813	13731	)
…	…
14089	14007	)
14090	14008	xt "-172000,24800,-150000,25600"
14091		st "alarm_refclk_too_high : std_logic
14092		"
	14009	st "alarm_refclk_too_high : std_logic"
14093	14010	)
14094	14011	)
…	…
14152	14069	)
14153	14070	xt "-172000,25600,-150000,26400"
14154		st "alarm_refclk_too_low : std_logic
14155		"
	14071	st "alarm_refclk_too_low : std_logic"
14156	14072	)
14157	14073	)
…	…
14215	14131	)
14216	14132	xt "-172000,27200,-140000,28000"
14217		st "counter_result : std_logic_vector(11 DOWNTO 0)
14218		"
	14133	st "counter_result : std_logic_vector(11 DOWNTO 0)"
14219	14134	)
14220	14135	)
…	…
14904	14819	)
14905	14820	xt "-172000,67600,-112000,68400"
14906		st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off
14907		"
	14821	st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off"
14908	14822	)
14909	14823	)
…	…
14925	14839	)
14926	14840	xt "-172000,70800,-112000,71600"
14927		st "SIGNAL din1 : std_logic := '0' -- default domino wave off
14928		"
	14841	st "SIGNAL din1 : std_logic := '0' -- default domino wave off"
14929	14842	)
14930	14843	)
…	…
14943	14856	)
14944	14857	xt "-172000,121200,-146500,122000"
14945		st "SIGNAL trigger_out : std_logic
14946		"
	14858	st "SIGNAL trigger_out : std_logic"
14947	14859	)
14948	14860	)
…	…
14965	14877	)
14966	14878	xt "-172000,119600,-136500,120400"
14967		st "SIGNAL trigger_id : std_logic_vector(31 downto 0)
14968		"
	14879	st "SIGNAL trigger_id : std_logic_vector(31 downto 0)"
14969	14880	)
14970	14881	)
…	…
14987	14898	)
14988	14899	xt "-172000,49200,-119500,50000"
14989		st "SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
14990		"
	14900	st "SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
14991	14901	)
14992	14902	)
…	…
15211	15121	)
15212	15122	xt "-172000,71600,-119500,72400"
15213		st "SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0')
15214		"
	15123	st "SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0')"
15215	15124	)
15216	15125	)
…	…
15232	15141	)
15233	15142	xt "-172000,99600,-125500,100400"
15234		st "SIGNAL ready : STD_LOGIC := '0'
15235		"
	15143	st "SIGNAL ready : STD_LOGIC := '0'"
15236	15144	)
15237	15145	)
…	…
15766	15674	)
15767	15675	xt "-172000,88400,-146500,89200"
15768		st "SIGNAL enable_i : std_logic
15769		"
	15676	st "SIGNAL enable_i : std_logic"
15770	15677	)
15771	15678	)
…	…
15977	15884	)
15978	15885	xt "-172000,101200,-146500,102000"
15979		st "SIGNAL reset_synch_i : std_logic
15980		"
	15886	st "SIGNAL reset_synch_i : std_logic"
15981	15887	)
15982	15888	)
…	…
15996	15902	)
15997	15903	xt "-172000,118000,-136500,118800"
15998		st "SIGNAL time : std_logic_vector(31 DOWNTO 0)
15999		"
	15904	st "SIGNAL time : std_logic_vector(31 DOWNTO 0)"
16000	15905	)
16001	15906	)
…	…
16017	15922	)
16018	15923	xt "-172000,104400,-132000,105200"
16019		st "SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0) --7 byte
16020		"
	15924	st "SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0) --7 byte"
16021	15925	)
16022	15926	)
…	…
16046	15950	-- during EVT header wrinting, this field is left out ... and only written into event header,
16047	15951	-- when the DRS chip were read out already.
16048		SIGNAL FTM_RS485_ready : std_logic
16049		"
	15952	SIGNAL FTM_RS485_ready : std_logic"
16050	15953	)
16051	15954	)
…	…
16066	15969	)
16067	15970	xt "-172000,62000,-136500,62800"
16068		st "SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0)
16069		"
	15971	st "SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0)"
16070	15972	)
16071	15973	)
…	…
16085	15987	)
16086	15988	xt "-172000,66000,-146500,66800"
16087		st "SIGNAL data_ram_empty : std_logic
16088		"
	15989	st "SIGNAL data_ram_empty : std_logic"
16089	15990	)
16090	15991	)
…	…
16149	16050	)
16150	16051	xt "-172000,15200,-150000,16000"
16151		st "ADC_CLK : std_logic
16152		"
	16052	st "ADC_CLK : std_logic"
16153	16053	)
16154	16054	)
…	…
16543	16443	)
16544	16444	xt "-172000,63600,-120000,64400"
16545		st "SIGNAL current_dac_array : dac_array_type := ( others => 0)
16546		"
	16445	st "SIGNAL current_dac_array : dac_array_type := ( others => 0)"
16547	16446	)
16548	16447	)
…	…
16563	16462	)
16564	16463	xt "-172000,120400,-146500,121200"
16565		st "SIGNAL trigger_or_s_trigger : std_logic
16566		"
	16464	st "SIGNAL trigger_or_s_trigger : std_logic"
16567	16465	)
16568	16466	)
…	…
16583	16481	)
16584	16482	xt "-172000,89200,-146500,90000"
16585		st "SIGNAL enabled_trigger_or_s_trigger : std_logic
16586		"
	16483	st "SIGNAL enabled_trigger_or_s_trigger : std_logic"
16587	16484	)
16588	16485	)
…	…
16601	16498	)
16602	16499	xt "-172000,62800,-146500,63600"
16603		st "SIGNAL cont_trigger : std_logic
16604		"
	16500	st "SIGNAL cont_trigger : std_logic"
16605	16501	)
16606	16502	)
…	…
16619	16515	)
16620	16516	xt "-172000,107600,-146500,108400"
16621		st "SIGNAL s_trigger_or_cont_trigger : std_logic
16622		"
	16517	st "SIGNAL s_trigger_or_cont_trigger : std_logic"
16623	16518	)
16624	16519	)
…	…
16640	16535	)
16641	16536	xt "-172000,64400,-98500,65200"
16642		st "SIGNAL dac_setting : dac_array_type := DEFAULT_DAC --<<-- default defined in fad_definitions.vhd
16643		"
	16537	st "SIGNAL dac_setting : dac_array_type := DEFAULT_DAC --<<-- default defined in fad_definitions.vhd"
16644	16538	)
16645	16539	)
…	…
16658	16552	)
16659	16553	xt "-172000,103600,-144000,104400"
16660		st "SIGNAL roi_setting : roi_array_type
16661		"
	16554	st "SIGNAL roi_setting : roi_array_type"
16662	16555	)
16663	16556	)
…	…
16677	16570	)
16678	16571	xt "-172000,90800,-125500,91600"
16679		st "SIGNAL memory_manager_config_start : std_logic := '0'
16680		"
	16572	st "SIGNAL memory_manager_config_start : std_logic := '0'"
16681	16573	)
16682	16574	)
…	…
16695	16587	)
16696	16588	xt "-172000,91600,-146500,92400"
16697		st "SIGNAL memory_manager_config_valid : std_logic
16698		"
	16589	st "SIGNAL memory_manager_config_valid : std_logic"
16699	16590	)
16700	16591	)
…	…
16714	16605	)
16715	16606	xt "-172000,113200,-125500,114000"
16716		st "SIGNAL spi_interface_config_start : std_logic := '0'
16717		"
	16607	st "SIGNAL spi_interface_config_start : std_logic := '0'"
16718	16608	)
16719	16609	)
…	…
16732	16622	)
16733	16623	xt "-172000,114000,-146500,114800"
16734		st "SIGNAL spi_interface_config_valid : std_logic
16735		"
	16624	st "SIGNAL spi_interface_config_valid : std_logic"
16736	16625	)
16737	16626	)
…	…
17683	17572	)
17684	17573	xt "-172000,73200,-146500,74000"
17685		st "SIGNAL dout0 : STD_LOGIC
17686		"
	17574	st "SIGNAL dout0 : STD_LOGIC"
17687	17575	)
17688	17576	)
…	…
17701	17589	)
17702	17590	xt "-172000,74000,-146500,74800"
17703		st "SIGNAL dout1 : STD_LOGIC
17704		"
	17591	st "SIGNAL dout1 : STD_LOGIC"
17705	17592	)
17706	17593	)
…	…
17719	17606	)
17720	17607	xt "-172000,74800,-146500,75600"
17721		st "SIGNAL dout2 : STD_LOGIC
17722		"
	17608	st "SIGNAL dout2 : STD_LOGIC"
17723	17609	)
17724	17610	)
…	…
17737	17623	)
17738	17624	xt "-172000,75600,-146500,76400"
17739		st "SIGNAL dout3 : STD_LOGIC
17740		"
	17625	st "SIGNAL dout3 : STD_LOGIC"
17741	17626	)
17742	17627	)
…	…
18203	18088	)
18204	18089	xt "-172000,72400,-146500,73200"
18205		st "SIGNAL dout : STD_LOGIC
18206		"
	18090	st "SIGNAL dout : STD_LOGIC"
18207	18091	)
18208	18092	)
…	…
18221	18105	)
18222	18106	xt "-172000,56400,-146500,57200"
18223		st "SIGNAL I_really_want_dwrite : STD_LOGIC
18224		"
	18107	st "SIGNAL I_really_want_dwrite : STD_LOGIC"
18225	18108	)
18226	18109	)
…	…
18240	18123	)
18241	18124	xt "-172000,86000,-125500,86800"
18242		st "SIGNAL dwrite_enable_w5300 : std_logic := '1'
18243		"
	18125	st "SIGNAL dwrite_enable_w5300 : std_logic := '1'"
18244	18126	)
18245	18127	)
…	…
18259	18141	)
18260	18142	xt "-172000,86800,-125500,87600"
18261		st "SIGNAL dwrite_global_enable : std_logic := '1'
18262		"
	18143	st "SIGNAL dwrite_global_enable : std_logic := '1'"
18263	18144	)
18264	18145	)
…	…
18644	18525	)
18645	18526	xt "-172000,76400,-146500,77200"
18646		st "SIGNAL dout4 : STD_LOGIC
18647		"
	18527	st "SIGNAL dout4 : STD_LOGIC"
18648	18528	)
18649	18529	)
…	…
18663	18543	)
18664	18544	xt "-172000,87600,-125500,88400"
18665		st "SIGNAL dwrite_trigger_manager : std_logic := '1'
18666		"
	18545	st "SIGNAL dwrite_trigger_manager : std_logic := '1'"
18667	18546	)
18668	18547	)
…	…
19224	19103	)
19225	19104	xt "-172000,68400,-112000,69200"
19226		st "SIGNAL denable_sig : std_logic := '0' -- default domino wave off
19227		"
	19105	st "SIGNAL denable_sig : std_logic := '0' -- default domino wave off"
19228	19106	)
19229	19107	)
…	…
19242	19120	)
19243	19121	xt "-172000,50000,-146500,50800"
19244		st "SIGNAL DCM_locked_status : std_logic
19245		"
	19122	st "SIGNAL DCM_locked_status : std_logic"
19246	19123	)
19247	19124	)
…	…
19260	19137	)
19261	19138	xt "-172000,50800,-146500,51600"
19262		st "SIGNAL DCM_ready_status : std_logic
19263		"
	19139	st "SIGNAL DCM_ready_status : std_logic"
19264	19140	)
19265	19141	)
…	…
19279	19155	)
19280	19156	xt "-172000,39200,-129000,40000"
19281		st "trigger_veto : std_logic := '1'
19282		"
	19157	st "trigger_veto : std_logic := '1'"
19283	19158	)
19284	19159	)
…	…
19687	19562	font "Arial,8,1"
19688	19563	)
19689		xt "-15000,159000,-13200,160000"
19690		st "~~U_7~~"
	19564	xt "-15000,159000,-7200,160000"
	19565	st "Inst_rs485_receiver"
19691	19566	blo "-15000,159800"
19692	19567	tm "InstanceNameMgr"
…	…
19933	19808	)
19934	19809	xt "-172000,4800,-150000,5600"
19935		st "FTM_RS485_rx_d : std_logic
19936		"
	19810	st "FTM_RS485_rx_d : std_logic"
19937	19811	)
19938	19812	)
…	…
19951	19825	)
19952	19826	xt "-172000,20000,-150000,20800"
19953		st "FTM_RS485_tx_d : std_logic
19954		"
	19827	st "FTM_RS485_tx_d : std_logic"
19955	19828	)
19956	19829	)
…	…
19969	19842	)
19970	19843	xt "-172000,19200,-150000,20000"
19971		st "FTM_RS485_rx_en : std_logic
19972		"
	19844	st "FTM_RS485_rx_en : std_logic"
19973	19845	)
19974	19846	)
…	…
19987	19859	)
19988	19860	xt "-172000,20800,-150000,21600"
19989		st "FTM_RS485_tx_en : std_logic
19990		"
	19861	st "FTM_RS485_tx_en : std_logic"
19991	19862	)
19992	19863	)
…	…
20006	19877	)
20007	19878	xt "-172000,100400,-125500,101200"
20008		st "SIGNAL rec_timeout_occured : std_logic := '0'
20009		"
	19879	st "SIGNAL rec_timeout_occured : std_logic := '0'"
20010	19880	)
20011	19881	)
…	…
20025	19895	)
20026	19896	xt "-172000,102000,-125500,102800"
20027		st "SIGNAL reset_trigger_id : std_logic := '0'
20028		"
	19897	st "SIGNAL reset_trigger_id : std_logic := '0'"
20029	19898	)
20030	19899	)
…	…
20090	19959	)
20091	19960	xt "-172000,40000,-115000,40800"
20092		st "w5300_state : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
20093		"
	19961	st "w5300_state : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
20094	19962	)
20095	19963	)
…	…
20108	19976	)
20109	19977	xt "-172000,28800,-150000,29600"
20110		st "debug_data_ram_empty : std_logic
20111		"
	19978	st "debug_data_ram_empty : std_logic"
20112	19979	)
20113	19980	)
…	…
20170	20037	)
20171	20038	xt "-172000,29600,-150000,30400"
20172		st "debug_data_valid : std_logic
20173		"
	20039	st "debug_data_valid : std_logic"
20174	20040	)
20175	20041	)
…	…
20425	20291	)
20426	20292	xt "-172000,112400,-146500,113200"
20427		st "SIGNAL software_trigger_in : std_logic
20428		"
	20293	st "SIGNAL software_trigger_in : std_logic"
20429	20294	)
20430	20295	)
…	…
20491	20356	)
20492	20357	xt "-172000,34400,-115000,35200"
20493		st "mem_manager_state : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
20494		"
	20358	st "mem_manager_state : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
20495	20359	)
20496	20360	)
…	…
20509	20373	)
20510	20374	xt "-172000,90000,-146500,90800"
20511		st "SIGNAL is_idle : std_logic
20512		"
	20375	st "SIGNAL is_idle : std_logic"
20513	20376	)
20514	20377	)
…	…
20575	20438	xt "-172000,17600,-140500,19200"
20576	20439	st "-- for debugging
20577		DG_state : std_logic_vector(7 downto 0)
20578		"
	20440	DG_state : std_logic_vector(7 downto 0)"
20579	20441	)
20580	20442	)
…	…
21396	21258	)
21397	21259	xt "-172000,66800,-125500,67600"
21398		st "SIGNAL data_valid_ack : std_logic := '0'
21399		"
	21260	st "SIGNAL data_valid_ack : std_logic := '0'"
21400	21261	)
21401	21262	)
…	…
21415	21276	)
21416	21277	xt "-172000,70000,-125500,70800"
21417		st "SIGNAL dg_start_config : std_logic := '0'
21418		"
	21278	st "SIGNAL dg_start_config : std_logic := '0'"
21419	21279	)
21420	21280	)
…	…
21433	21293	)
21434	21294	xt "-172000,69200,-146500,70000"
21435		st "SIGNAL dg_config_done : std_logic
21436		"
	21295	st "SIGNAL dg_config_done : std_logic"
21437	21296	)
21438	21297	)
…	…
21456	21315	xt "-172000,105200,-136500,106800"
21457	21316	st "-- EVT HEADER - part 6
21458		SIGNAL runnumber : std_logic_vector(31 downto 0)
21459		"
	21317	SIGNAL runnumber : std_logic_vector(31 downto 0)"
21460	21318	)
21461	21319	)
…	…
21477	21335	)
21478	21336	xt "-172000,38400,-125000,39200"
21479		st "socket_tx_free_out : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true
21480		"
	21337	st "socket_tx_free_out : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
21481	21338	)
21482	21339	)
…	…
22241	22098	)
22242	22099	xt "-172000,77200,-146500,78000"
22243		st "SIGNAL dout5 : std_logic
22244		"
	22100	st "SIGNAL dout5 : std_logic"
22245	22101	)
22246	22102	)
…	…
22260	22116	)
22261	22117	xt "-172000,122000,-125500,122800"
22262		st "SIGNAL trigger_veto1 : std_logic := '1'
22263		"
	22118	st "SIGNAL trigger_veto1 : std_logic := '1'"
22264	22119	)
22265	22120	)
…	…
30230	30085	)
30231	30086	windowSize "0,22,1681,1050"
30232		viewArea "-~~59900,89700,36592,148176~~"
	30087	viewArea "-40628,107718,55864,168042"
30233	30088	cachedDiagramExtent "-174000,-16000,261100,353300"
30234	30089	pageSetupInfo (PageSetupInfo
…	…
30256	30111	hasePageBreakOrigin 1
30257	30112	pageBreakOrigin "-73000,0"
30258		lastUid 30~~018~~,0
	30113	lastUid 30231,0
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TabularUnified firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak ¶

-              r10958
+              r10988
+)
 (Instance
 name "U_7"
+name "Inst_rs485_receiver"
 duLibraryName "FACT_FAD_lib"
 duName "FAD_rs485_receiver"
 …
 (vvPair
 variable "date"
 value "09.06.2011"
+value "10.06.2011"
+)
 (vvPair
 variable "day"
 value "Do"
+value "Fr"
+)
 (vvPair
 variable "day_long"
 value "Donnerstag"
+value "Freitag"
+)
 (vvPair
 variable "dd"
 value "09"
+value "10"
+)
 (vvPair
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 (vvPair
 variable "time"
 value "16:33:39"
+value "10:56:40"
+)
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 font "Courier New,8,0"
+)
 xt "-172000,128400,-125500,129200"
+xt "-172000,127600,-125500,128400"
 st "SIGNAL write_ea                     : std_logic_vector(0 downto 0)                 := \"0\""
+)
 …
 font "Courier New,8,0"
+)
 xt "-172000,61200,-129000,62000"
+xt "-172000,60400,-129000,61200"
 st "SIGNAL addr_out                     : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
+)
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 font "Courier New,8,0"
+)
 xt "-172000,66000,-136500,66800"
+xt "-172000,65200,-136500,66000"
 st "SIGNAL data_out                     : std_logic_vector(63 DOWNTO 0)"
+)
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 font "Courier New,8,0"
+)
 xt "-172000,96400,-129000,97200"
+xt "-172000,95600,-129000,96400"
 st "SIGNAL ram_addr                     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
+)
 …
 font "Courier New,8,0"
+)
 xt "-172000,97200,-136500,98000"
+xt "-172000,96400,-136500,97200"
 st "SIGNAL ram_data                     : std_logic_vector(15 downto 0)"
+)
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 font "Courier New,8,0"
+)
 xt "-172000,44000,-129000,44800"
+xt "-172000,43200,-129000,44000"
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+)
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+)
 xt "-172000,41600,-140500,42400"
+xt "-172000,40800,-140500,41600"
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+)
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 xt "-172000,46400,-140000,47200"
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+)
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 font "Courier New,8,0"
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 xt "-172000,42400,-129000,43200"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,44800,-129000,45600"
+xt "-172000,44000,-129000,44800"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,43200,-129000,44000"
+xt "-172000,42400,-129000,43200"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,98000,-129000,98800"
+xt "-172000,97200,-129000,98000"
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+)
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+)
 xt "-172000,125200,-125500,126000"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,127600,-119500,128400"
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+)
 …
 font "Courier New,8,0"
+)
 xt "-172000,124400,-119500,125200"
+xt "-172000,123600,-119500,124400"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,123600,-119500,124400"
+xt "-172000,122800,-119500,123600"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,126000,-125500,126800"
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+)
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+)
 xt "-172000,126800,-125500,127600"
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+)
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+)
 xt "-172000,98800,-146500,99600"
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+)
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 xt "-172000,99600,-125500,100400"
+xt "-172000,98800,-125500,99600"
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+)
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 font "Courier New,8,0"
+)
 xt "-172000,103600,-145000,104400"
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+)
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+)
 xt "-172000,93200,-136500,94000"
+xt "-172000,92400,-136500,93200"
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+)
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 xt "-172000,49200,-146500,50000"
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 xt "-172000,78800,-125500,79600"
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+)
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+)
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 xt "-172000,79600,-125500,80400"
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+)
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+)
 xt "-172000,80400,-146500,81200"
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+)
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 xt "-172000,110800,-146500,111600"
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+)
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+)
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+)
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 …
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 sat 16
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 …
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 …
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 eat 32
 …
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 …
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 eat 16
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 …
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 …
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 eat 32
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 …
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 …
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 …
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 …
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 …
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 eat 32
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 …
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 eat 32
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+)
+)
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 eat 32
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 …
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 …
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 …
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+)
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+)
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+)
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+)
+)
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+)
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 eat 32
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+)
+)
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+)
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+"-2250,128000"
+"9000,128000"
+]
+)
+start &252
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+sat 32
+eat 32
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+f (Text
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+va (VaSet
+isHidden 1
+)
+xt "-1000,127000,6100,128000"
+st "spi_debug_16bit"
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+)
+)
+on &808
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+)
+]
 …
 color "26368,26368,26368"
+)
 packageList *1024 (PackageList
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 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
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 uid 42,0
 va (VaSet
 …
 blo "-163000,-15200"
+)
 *1026 (MLText
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 va (VaSet
 …
 blo "20000,800"
+)
 *1028 (Text
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 va (VaSet
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 blo "20000,1800"
+)
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 va (VaSet
 …
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+)
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 va (VaSet
 …
 blo "20000,4800"
+)
 *1031 (MLText
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 va (VaSet
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 tm "BdCompilerDirectivesTextMgr"
+)
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 va (VaSet
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 blo "20000,5800"
+)
 *1033 (MLText
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 va (VaSet
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+)
 windowSize "0,22,1681,1050"
 viewArea "-59900,89700,36592,148176"
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 cachedDiagramExtent "-174000,-16000,261100,353300"
 pageSetupInfo (PageSetupInfo
 …
 hasePageBreakOrigin 1
 pageBreakOrigin "-73000,0"
 lastUid 29805,0
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 defaultCommentText (CommentText
 shape (Rectangle
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *1035 (Text
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 tm "BlkNameMgr"
+)
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 …
 stg "VerticalLayoutStrategy"
 textVec [
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 blo "550,4300"
+)
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 …
 blo "550,5300"
+)
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 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 font "Arial,8,1"
 …
 tm "BdLibraryNameMgr"
+)
 *1041 (Text
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 va (VaSet
 font "Arial,8,1"
 …
 tm "CptNameMgr"
+)
 *1042 (Text
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 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
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 …
 blo "500,4300"
+)
 *1044 (Text
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 …
 blo "500,5300"
+)
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 …
 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
 font "Arial,8,1"
 …
 blo "50,4300"
+)
 *1047 (Text
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 …
 blo "50,5300"
+)
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 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 font "Arial,8,1"
 …
 tm "HdlTextNameMgr"
+)
 *1050 (Text
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 va (VaSet
 font "Arial,8,1"
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 va (VaSet
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 …
 blo "14100,20800"
+)
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 va (VaSet
+)
 …
 stg "VerticalLayoutStrategy"
 textVec [
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 …
 blo "14100,20800"
+)
 *1054 (MLText
+*1050 (MLText
 va (VaSet
+)
 …
 font "Arial,8,1"
+)
 xt "-174000,47200,-170200,48200"
+xt "-174000,46400,-170200,47400"
 st "Pre User:"
 blo "-174000,48000"
+blo "-174000,47200"
+)
 preUserText (MLText
 …
 font "Arial,8,1"
+)
 xt "-174000,48200,-166900,49200"
+xt "-174000,47400,-166900,48400"
 st "Diagram Signals:"
 blo "-174000,49000"
+blo "-174000,48200"
+)
 postUserLabel (Text
 …
 font "Arial,8,1"
+)
 xt "-174000,129200,-169300,130200"
+xt "-174000,128400,-169300,129400"
 st "Post User:"
 blo "-174000,130000"
+blo "-174000,129200"
+)
 postUserText (MLText
 …
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 usingSuid 1
 emptyRow *1055 (LEmptyRow
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+)
 uid 54,0
 optionalChildren [
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+)
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+)
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+*1053 (TitleRowHdr
+)
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 tm "RefLabelColHdrMgr"
+)
 *1060 (RowExpandColHdr
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+)
 *1061 (GroupColHdr
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 tm "GroupColHdrMgr"
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 *1064 (TypeColHdr
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 *1065 (BoundsColHdr
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 *1066 (InitColHdr
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 *1067 (EolColHdr
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 o 128
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 uid 10026,0
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