Changeset 11173
- Timestamp:
- 06/24/11 14:15:51 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r11155 r11173 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 3:24:39 23.06.20115 -- at - 15:01:19 24.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 3:24:39 23.06.201178 -- at - 15:01:20 24.06.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r11155 r11173 48 48 constant MAC_LIST : mac_list_type := (MAC_FAD0,MAC_FAD1,MAC_FAD2); 49 49 50 constant FIRST_PORT : integer := 5000;50 constant FIRST_PORT : integer := 31919; 51 51 constant CAM_IP_PREFIX : ip_type := (10, 0, 0, 0); 52 52 constant IP_offset : integer := 128; … … 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 5";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"06"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 97 97 constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; 98 98 constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; 99 constant W5300_S0_PORTOR: std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A"; -- HIGH byte is S0_KPALVTR register99 constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A"; -- HIGH byte is S0_KPALVTR register 100 100 constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; 101 101 constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; … … 171 171 constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"31"; 172 172 constant CMD_TRIGGER : std_logic_vector := X"A0"; 173 constant CMD_TRIGGER_C : std_logic_vector := X" B0"; -- should be 1F in next revision .. T.B. wants it.173 constant CMD_TRIGGER_C : std_logic_vector := X"1F"; -- should be 1F in next revision .. T.B. wants it. 174 174 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 175 175 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r11155 r11173 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 3:24:37 23.06.20115 -- at - 15:01:18 24.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 83 83 -- Created: 84 84 -- by - daqct3.UNKNOWN (IHP110) 85 -- at - 1 3:24:38 23.06.201185 -- at - 15:01:19 24.06.2011 86 86 -- 87 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 190 190 SIGNAL sensor_array : sensor_array_type; 191 191 SIGNAL sensor_ready : std_logic; 192 SIGNAL socket_send_mode : std_logic; 192 193 SIGNAL socks_connected : std_logic; 193 194 SIGNAL socks_waiting : std_logic; … … 328 329 denable_enable_in : IN std_logic ; 329 330 busy_enable_in : IN std_logic ; 331 trigger_enable_in : IN std_logic ; 332 cont_trigger_en_in : IN std_logic ; 333 socket_send_mode_in : IN std_logic ; 330 334 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 331 335 -- during EVT header wrinting, this field is left out ... and only written into event header, … … 561 565 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 562 566 busy_enable : OUT std_logic := '1'; 567 socket_send_mode_out : OUT std_logic ; 563 568 ------------------------------------------------------------------------------ 564 569 … … 772 777 denable_enable_in => denable_sig, 773 778 busy_enable_in => busy_enable, 779 trigger_enable_in => trigger_enable, 780 cont_trigger_en_in => c_trigger_enable, 781 socket_send_mode_in => socket_send_mode, 774 782 FTM_RS485_ready => FTM_RS485_ready, 775 783 FTM_trigger_info => rs465_data, … … 975 983 srclk_enable => srclk_enable, 976 984 busy_enable => busy_enable, 985 socket_send_mode_out => socket_send_mode, 977 986 ps_direction => ps_direction, 978 987 ps_do_phase_shift => ps_do_phase_shift, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r11155 r11173 108 108 type state_init_type is ( 109 109 INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, 110 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, 110 INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, 111 TIMEOUT, 112 --RETRY, 111 113 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 112 114 … … 290 292 signal wait_for_sockets_closed_counter_enable : std_logic := '0'; 291 293 signal wfscc_1 : integer range 0 to 50000 := 0; 292 signal wfscc_2 : integer range 0 to 2000 := 0;294 signal wfscc_2 : integer range 0 to 20000 := 0; 293 295 294 296 … … 714 716 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 715 717 state_init <= WRITE_REG; 718 --next_state <= SI; 719 next_state <= TIMEOUT; 720 when TIMEOUT => 721 par_addr <= W5300_RTR; 722 --par_data <= X"07D0"; -- 0x07D0 = 200ms 723 par_data <= X"07D0"; -- unit is 100us, so 0x000A = 10 stnads for 1ms. 724 state_init <= WRITE_REG; 716 725 next_state <= SI; 717 -- when TIMEOUT =>718 -- par_addr <= W5300_RTR;719 -- par_data <= X"07D0"; -- 0x07D0 = 200ms720 -- state_init <= WRITE_REG;721 -- next_state <= RETRY;722 726 -- when RETRY => 723 727 -- par_addr <= W5300_RCR; … … 741 745 next_state <= SI1b; 742 746 when SI1b => 743 par_addr <= W5300_S0_ PORTOR + socket_cnt * W5300_S_INC;744 par_data <= X"0 606"; -- send automatic KEEP ALIVE every 30s.747 par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC; 748 par_data <= X"0200"; -- send automatic KEEP ALIVE every 10s. 745 749 state_init <= WRITE_REG; 746 750 next_state <= SI2; … … 1023 1027 denable <= '0'; 1024 1028 state_read_data <= RD_5; 1029 1030 when CMD_BUSY_ON => 1031 busy_enable <= '1'; 1032 state_read_data <= RD_5; 1033 when CMD_BUSY_OFF => 1034 busy_enable <= '0'; 1035 state_read_data <= RD_5; 1036 1037 1025 1038 when CMD_TRIGGER_C => 1026 1039 c_trigger_enable <= '1'; … … 1531 1544 wait_for_sockets_closed_counter_overflow <= '0'; 1532 1545 if (wfscc_1 = 50000) then 1533 if (wfscc_2 = 2000 ) then1546 if (wfscc_2 = 20000) then 1534 1547 wait_for_sockets_closed_counter_overflow <= '1'; 1535 wfscc_2 <= 2000 ;1548 wfscc_2 <= 20000; 1536 1549 wfscc_1 <= 50000; 1537 1550 else
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