Changeset 11648
- Timestamp:
- 07/27/11 11:55:25 (13 years ago)
- Location:
- firmware/FTM/Clock_cond_interface
- Files:
-
- 3 edited
-
Clock_cond_interface.vhd (modified) (6 diffs)
-
Clock_cond_interface_tb.vhd (modified) (6 diffs)
-
microwire_controller.vhd (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10740 r11648 21 21 -- March 23 2011 by Patrick Vogler 22 22 -- May 03 2011 by Patrick Vogler and Quirin Weitzel 23 -- July 19 2011 by Patrick Vogler 23 24 ---------------------------------------------------------------------------------- 24 25 … … 76 77 -- FPGA intern control signals 77 78 ------------------------------------------------------------------------------- 78 start_config : in STD_LOGIC;-- load new configuration into the clock79 start_config : in STD_LOGIC; -- load new configuration into the clock 79 80 -- conditioner 80 81 81 config_started : out STD_LOGIC;-- indicates that the new configuration82 config_started : out STD_LOGIC; -- indicates that the new configuration 82 83 -- is currently loaded into the clock conditioner 83 84 84 config_done : out STD_LOGIC; -- indicates that the configuration has 85 -- been loaded and the clock conditioners 86 -- PLL is locked 87 85 config_done : out STD_LOGIC; -- indicates that the configuration has 86 -- been loaded 87 88 -- locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked 89 88 90 timemarker_select: in STD_LOGIC -- selects time marker source 89 91 -- … … 96 98 ); 97 99 end Clock_cond_interface; 100 98 101 99 102 … … 118 121 signal config_ready_sig : STD_LOGIC; 119 122 signal config_started_sig : STD_LOGIC; 120 121 signal clk_cond_array_sig : clk_cond_array_type; 122 123 signal cc_R0_sig : std_logic_vector (31 downto 0); 124 signal cc_R1_sig : std_logic_vector (31 downto 0); 125 126 signal cc_R2_sig : std_logic_vector (31 downto 0); 127 signal cc_R3_sig : std_logic_vector (31 downto 0); 128 signal cc_R4_sig : std_logic_vector (31 downto 0); 129 signal cc_R5_sig : std_logic_vector (31 downto 0); 130 signal cc_R6_sig : std_logic_vector (31 downto 0); 131 signal cc_R7_sig : std_logic_vector (31 downto 0); 132 133 signal cc_R8_sig : std_logic_vector (31 downto 0); 134 signal cc_R9_sig : std_logic_vector (31 downto 0); 135 signal cc_R11_sig : std_logic_vector (31 downto 0); 136 signal cc_R13_sig : std_logic_vector (31 downto 0); 137 signal cc_R14_sig : std_logic_vector (31 downto 0); 138 signal cc_R15_sig : std_logic_vector (31 downto 0); 139 123 124 125 signal clk_cond_array_sig : clk_cond_array_type; 126 127 128 -- signal cc_R0_sig : std_logic_vector (31 downto 0); 129 -- signal cc_R1_sig : std_logic_vector (31 downto 0); 130 131 -- signal cc_R2_sig : std_logic_vector (31 downto 0); 132 -- signal cc_R3_sig : std_logic_vector (31 downto 0); 133 -- signal cc_R4_sig : std_logic_vector (31 downto 0); 134 -- signal cc_R5_sig : std_logic_vector (31 downto 0); 135 -- signal cc_R6_sig : std_logic_vector (31 downto 0); 136 -- signal cc_R7_sig : std_logic_vector (31 downto 0); 137 138 -- signal cc_R8_sig : std_logic_vector (31 downto 0); 139 -- signal cc_R9_sig : std_logic_vector (31 downto 0); 140 -- signal cc_R11_sig : std_logic_vector (31 downto 0); 141 -- signal cc_R13_sig : std_logic_vector (31 downto 0); 142 -- signal cc_R14_sig : std_logic_vector (31 downto 0); 143 -- signal cc_R15_sig : std_logic_vector (31 downto 0); 144 145 146 147 140 148 signal timemarker_select_sig : std_logic := '0'; 141 149 … … 166 174 end process sync_ld_proc; 167 175 168 --config_done <= config_ready_sig; -- indicates that the configuration 169 -- has been loaded 170 171 --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 172 -- has been loaded and 173 -- the PLL has locked 174 175 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); 176 -- config_done <= config_ready_sig; -- indicates that the configuration 177 -- has been loaded 178 179 -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration 180 -- has been loaded and 181 -- the PLL has locked 182 183 config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); 184 185 -- config_done <= config_ready_sig; 186 -- locked <= load_detect_sr(1) and load_detect_sr(0); 187 188 189 176 190 177 191 TIM_Sel <= timemarker_select_sig; … … 201 215 config_started <= config_started_sig; 202 216 203 cc_R0_sig <= cc_R0; 204 cc_R1_sig <= cc_R1; 205 cc_R2_sig <= cc_R2_const; 206 cc_R3_sig <= cc_R3_const; 207 cc_R4_sig <= cc_R4_const; 208 cc_R5_sig <= cc_R5_const; 209 cc_R6_sig <= cc_R6_const; 210 cc_R7_sig <= cc_R7_const; 211 cc_R8_sig <= cc_R8; 212 cc_R9_sig <= cc_R9; 213 cc_R11_sig <= cc_R11; 214 cc_R13_sig <= cc_R13; 215 cc_R14_sig <= cc_R14; 216 cc_R15_sig <= cc_R15; 217 217 218 -- ----------------------------------------------------------------------------- 219 220 -- cc_R0_sig <= cc_R0; 221 -- cc_R1_sig <= cc_R1; 222 223 -- cc_R2_sig <= cc_R2_const; 224 -- cc_R3_sig <= cc_R3_const; 225 -- cc_R4_sig <= cc_R4_const; 226 -- cc_R5_sig <= cc_R5_const; 227 -- cc_R6_sig <= cc_R6_const; 228 -- cc_R7_sig <= cc_R7_const; 229 230 -- cc_R8_sig <= cc_R8; 231 -- cc_R9_sig <= cc_R9; 232 -- cc_R11_sig <= cc_R11; 233 -- cc_R13_sig <= cc_R13; 234 -- cc_R14_sig <= cc_R14; 235 -- cc_R15_sig <= cc_R15; 236 237 238 239 240 241 242 243 -- clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting 244 -- -- bit 31 of register 0 245 -- clk_cond_array_sig(1) <= cc_R0_sig; 246 -- clk_cond_array_sig(2) <= cc_R1_sig; 247 248 -- clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels 249 -- clk_cond_array_sig(4) <= cc_R3_sig; 250 -- clk_cond_array_sig(5) <= cc_R4_sig; 251 -- clk_cond_array_sig(6) <= cc_R5_sig; 252 -- clk_cond_array_sig(7) <= cc_R6_sig; 253 -- clk_cond_array_sig(8) <= cc_R7_sig; -- unused channels 254 255 -- clk_cond_array_sig(9) <= cc_R8_sig; 256 -- clk_cond_array_sig(10) <= cc_R9_sig; 257 -- clk_cond_array_sig(11) <= cc_R11_sig; 258 -- clk_cond_array_sig(12) <= cc_R13_sig; 259 -- clk_cond_array_sig(13) <= cc_R14_sig; 260 -- clk_cond_array_sig(14) <= cc_R15_sig; 261 262 -- ----------------------------------------------------------------------------- 263 264 218 265 clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting 219 266 -- bit 31 of register 0 220 clk_cond_array_sig(1) <= cc_R0_sig; 221 clk_cond_array_sig(2) <= cc_R1_sig; 222 223 clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels 224 clk_cond_array_sig(4) <= cc_R3_sig; 225 clk_cond_array_sig(5) <= cc_R4_sig; 226 clk_cond_array_sig(6) <= cc_R5_sig; 227 clk_cond_array_sig(7) <= cc_R6_sig; 228 clk_cond_array_sig(8) <= cc_R7_sig; 229 230 clk_cond_array_sig(9) <= cc_R8_sig; 231 clk_cond_array_sig(10) <= cc_R9_sig; 232 clk_cond_array_sig(11) <= cc_R11_sig; 233 clk_cond_array_sig(12) <= cc_R13_sig; 234 clk_cond_array_sig(13) <= cc_R14_sig; 235 clk_cond_array_sig(14) <= cc_R15_sig; 267 clk_cond_array_sig(1) <= cc_R0; 268 clk_cond_array_sig(2) <= cc_R1; 269 270 clk_cond_array_sig(3) <= cc_R2_const; -- unused channels 271 clk_cond_array_sig(4) <= cc_R3_const; 272 clk_cond_array_sig(5) <= cc_R4_const; 273 clk_cond_array_sig(6) <= cc_R5_const; 274 clk_cond_array_sig(7) <= cc_R6_const; 275 clk_cond_array_sig(8) <= cc_R7_const; -- unused channels 276 277 clk_cond_array_sig(9) <= cc_R8; 278 clk_cond_array_sig(10) <= cc_R9; 279 clk_cond_array_sig(11) <= cc_R11; 280 clk_cond_array_sig(12) <= cc_R13; 281 clk_cond_array_sig(13) <= cc_R14; 282 clk_cond_array_sig(14) <= cc_R15; 283 236 284 237 285 end Behavioral; -
firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd
r11513 r11648 53 53 LD_Clk_Cond : IN std_logic; 54 54 TIM_Sel : OUT std_logic; 55 -- locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked 55 56 cc_R0 : IN std_logic_vector(31 downto 0); 56 57 cc_R1 : IN std_logic_vector(31 downto 0); … … 83 84 signal cc_R13 : std_logic_vector(31 downto 0) := x"020A000D"; 84 85 signal cc_R14 : std_logic_vector(31 downto 0) := x"0830280E"; 85 signal cc_R15 : std_logic_vector(31 downto 0) := 86 signal cc_R15 : std_logic_vector(31 downto 0) := x"1400FA0F"; 86 87 87 88 … … 101 102 signal config_started : std_logic; 102 103 signal config_done : std_logic; 103 104 -- signal locked : STD_LOGIC; -- PLL in the Clock Conditioner locked 104 105 105 106 … … 121 122 LD_Clk_Cond => LD_Clk_Cond, 122 123 TIM_Sel => TIM_Sel, 124 -- locked => locked, 123 125 cc_R0 => cc_R0, 124 126 cc_R1 => cc_R1, … … 147 149 end process; 148 150 149 -- CLK_Clk_Cond_process :process 150 -- begin 151 -- CLK_Clk_Cond <= '0'; 152 -- wait for CLK_Clk_Cond_period/2; 153 -- CLK_Clk_Cond <= '1'; 154 -- wait for CLK_Clk_Cond_period/2; 155 -- end process; 156 151 157 152 158 153 … … 174 169 start_config <= '0'; 175 170 176 wait for 180 us;171 wait for 300 us; 177 172 LD_Clk_Cond <= '1'; 178 173 174 175 wait for 300 us; 176 LD_Clk_Cond <= '0'; 177 start_config <= '1'; 178 wait for clk_period*100; 179 start_config <= '0'; 180 wait for 300 us; 181 LD_Clk_Cond <= '1'; 182 183 184 185 186 187 -- programm new settings 188 189 cc_R0 <= x"00038027"; 190 cc_R1 <= x"00010101"; 191 cc_R8 <= x"10000963"; 192 cc_R9 <= x"A0032A09"; 193 cc_R11 <= x"0082000B"; 194 cc_R13 <= x"020A000D"; 195 cc_R14 <= x"0830280E"; 196 cc_R15 <= x"1400FA0F"; 197 198 wait for 300 us; 199 LD_Clk_Cond <= '0'; 200 start_config <= '1'; 201 wait for clk_period*100; 202 start_config <= '0'; 203 wait for 300 us; 204 LD_Clk_Cond <= '1'; 205 206 207 179 208 wait; 180 209 end process; -
firmware/FTM/Clock_cond_interface/microwire_controller.vhd
r10231 r11648 18 18 -- modified to be used as a Microwire interface to control the clock 19 19 -- conditioner LMK03000 on the FTM board 20 -- 21 -- modified July 19 2011 by Patrick Vogler 22 -- 20 23 ------------------------------------------------------------------------------- 21 24 … … 40 43 clk_cond_array : IN clk_cond_array_type; -- data to be loaded 41 44 -- into the clock conditioner 45 42 46 config_start : IN std_logic; 43 47 config_ready : OUT std_logic := '0'; … … 54 58 signal bit_count : integer range 0 to LMK03000_REGISTER_WIDTH := 0; 55 59 signal shift_reg : std_logic_vector (LMK03000_REGISTER_WIDTH - 1 downto 0) := (others => '0'); 56 60 61 signal clk_cond_array_update : clk_cond_array_type := (others => (others => '0')); 62 63 64 57 65 58 66 … … 80 88 end if; 81 89 90 91 ------------------------------------------------------------------------------- 92 -- send new data only when settings changed 82 93 83 94 when LOAD_SHIFT_REG => 84 bit_count <= 0; 85 config_started <= '1'; 86 shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0); 87 register_count <= register_count + 1; 88 -- le_uwire <= '0'; 89 uwire_state <= SHIFT; 90 95 96 if (clk_cond_array_update = clk_cond_array) then -- compare old and new settings 97 config_started <= '1'; 98 uwire_state <= IDLE; -- do nothing if settings didn't change 99 100 else -- program new (changed !!) settings to clock conditioner 101 bit_count <= 0; 102 config_started <= '1'; 103 shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0); 104 register_count <= register_count + 1; 105 uwire_state <= SHIFT; 106 107 end if; 108 ------------------------------------------------------------------------------- 109 91 110 92 111 when SHIFT => 93 94 112 data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1); 113 le_uwire <= '0'; 95 114 shift_reg <= shift_reg(LMK03000_REGISTER_WIDTH - 2 downto 0) & shift_reg(LMK03000_REGISTER_WIDTH - 1); 96 115 bit_count <= bit_count + 1; 97 116 if ((bit_count = LMK03000_REGISTER_WIDTH)AND(register_count = LMK03000_REGISTER_COUNT)) then 98 le_uwire <= '1'; 117 le_uwire <= '1'; 118 clk_cond_array_update <= clk_cond_array; -- get a copy of the date for comparison lateron 99 119 uwire_state <= IDLE; 100 120 elsif ((bit_count =LMK03000_REGISTER_WIDTH )AND(NOT(register_count = LMK03000_REGISTER_COUNT))) then 101 121 le_uwire <= '1'; 102 122 uwire_state <= LOAD_SHIFT_REG; 103 123 else
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