Changeset 11653 for firmware


Ignore:
Timestamp:
Jul 27, 2011, 3:43:05 PM (8 years ago)
Author:
vogler
Message:
clock cond interface with PLL lock seperate
File:
1 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

    r11648 r11653  
    2222--                 May      03  2011 by Patrick Vogler and Quirin Weitzel
    2323--                 July     19  2011 by Patrick Vogler
     24--                 July     27  2011 by Patrick Vogler
    2425----------------------------------------------------------------------------------
    2526
     
    8687                                       -- been loaded
    8788
    88  -- locked           : out STD_LOGIC;  -- PLL in the Clock Conditioner locked
     89   locked           : out STD_LOGIC;  -- PLL in the Clock Conditioner locked
    8990   
    9091    timemarker_select: in STD_LOGIC    -- selects time marker source
     
    122123  signal config_started_sig : STD_LOGIC;
    123124
    124 
    125125  signal clk_cond_array_sig    : clk_cond_array_type;
    126126
    127 
    128 --  signal cc_R0_sig             : std_logic_vector (31 downto 0);
    129 --  signal cc_R1_sig             : std_logic_vector (31 downto 0);
    130 
    131 --  signal cc_R2_sig             : std_logic_vector (31 downto 0);       
    132 --  signal cc_R3_sig             : std_logic_vector (31 downto 0);
    133 --  signal cc_R4_sig             : std_logic_vector (31 downto 0);
    134 --  signal cc_R5_sig             : std_logic_vector (31 downto 0);
    135 --  signal cc_R6_sig             : std_logic_vector (31 downto 0);
    136 --  signal cc_R7_sig             : std_logic_vector (31 downto 0);
    137 
    138 --  signal cc_R8_sig             : std_logic_vector (31 downto 0);
    139 --  signal cc_R9_sig             : std_logic_vector (31 downto 0);
    140 --  signal cc_R11_sig            : std_logic_vector (31 downto 0);
    141 --  signal cc_R13_sig            : std_logic_vector (31 downto 0);
    142 --  signal cc_R14_sig            : std_logic_vector (31 downto 0);
    143 --  signal cc_R15_sig            : std_logic_vector (31 downto 0);
    144 
    145 
    146 
    147  
    148127  signal timemarker_select_sig : std_logic := '0';
    149128
     
    174153  end process sync_ld_proc;
    175154 
    176  -- config_done <= config_ready_sig;  -- indicates that the configuration
    177                                       -- has been loaded
    178 
    179  -- config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration
    180                                                         -- has been loaded and
    181                                                         -- the PLL has locked
    182  
    183  config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
    184 
    185 --  config_done <= config_ready_sig;
    186 --  locked      <= load_detect_sr(1) and load_detect_sr(0);
     155-- config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
     156
     157  config_done <= config_ready_sig;
     158  locked      <= load_detect_sr(1) and load_detect_sr(0);
    187159 
    188160 
     
    214186 
    215187  config_started <= config_started_sig;
    216 
    217 
    218 --  -----------------------------------------------------------------------------
    219    
    220 --  cc_R0_sig  <= cc_R0;             
    221 --  cc_R1_sig  <= cc_R1;
    222  
    223 --  cc_R2_sig  <= cc_R2_const;                 
    224 --  cc_R3_sig  <= cc_R3_const;   
    225 --  cc_R4_sig  <= cc_R4_const;           
    226 --  cc_R5_sig  <= cc_R5_const;   
    227 --  cc_R6_sig  <= cc_R6_const;       
    228 --  cc_R7_sig  <= cc_R7_const;
    229  
    230 --  cc_R8_sig  <= cc_R8;
    231 --  cc_R9_sig  <= cc_R9;     
    232 --  cc_R11_sig <= cc_R11;       
    233 --  cc_R13_sig <= cc_R13;         
    234 --  cc_R14_sig <= cc_R14;           
    235 --  cc_R15_sig <= cc_R15;
    236 
    237 
    238 
    239 
    240 
    241 
    242  
    243 --  clk_cond_array_sig(0) <= LMK03000_Reset;      -- reset LKM03000 by setting
    244 --                                                -- bit 31 of register 0
    245 --  clk_cond_array_sig(1) <= cc_R0_sig;
    246 --  clk_cond_array_sig(2) <= cc_R1_sig;
    247  
    248 --  clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
    249 --  clk_cond_array_sig(4) <= cc_R3_sig;
    250 --  clk_cond_array_sig(5) <= cc_R4_sig;
    251 --  clk_cond_array_sig(6) <= cc_R5_sig;
    252 --  clk_cond_array_sig(7) <= cc_R6_sig;
    253 --  clk_cond_array_sig(8) <= cc_R7_sig; -- unused channels
    254  
    255 --  clk_cond_array_sig(9)  <= cc_R8_sig;
    256 --  clk_cond_array_sig(10) <= cc_R9_sig;
    257 --  clk_cond_array_sig(11) <= cc_R11_sig;
    258 --  clk_cond_array_sig(12) <= cc_R13_sig;
    259 --  clk_cond_array_sig(13) <= cc_R14_sig;
    260 --  clk_cond_array_sig(14) <= cc_R15_sig;
    261 
    262 -- -----------------------------------------------------------------------------
    263  
    264  
     188     
    265189  clk_cond_array_sig(0) <= LMK03000_Reset;      -- reset LKM03000 by setting
    266190                                                -- bit 31 of register 0
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