Changeset 11653 for firmware

Timestamp:

07/27/11 15:43:05 (13 years ago)

Author:

vogler

Message:

clock cond interface with PLL lock seperate

File:

• firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (modified) (5 diffs)

firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

@@ -22 +22 @@
 --                 May      03  2011 by Patrick Vogler and Quirin Weitzel
 --                 July     19  2011 by Patrick Vogler
+--                 July     27  2011 by Patrick Vogler
 ----------------------------------------------------------------------------------
 
@@ -86 +87 @@
                                        -- been loaded 
 
- -- locked           : out STD_LOGIC;  -- PLL in the Clock Conditioner locked
+    locked           : out STD_LOGIC;  -- PLL in the Clock Conditioner locked
     
     timemarker_select: in STD_LOGIC    -- selects time marker source
@@ -122 +123 @@
   signal config_started_sig : STD_LOGIC;
 
-
   signal clk_cond_array_sig    : clk_cond_array_type;
 
-
---  signal cc_R0_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R1_sig             : std_logic_vector (31 downto 0);
-
---  signal cc_R2_sig             : std_logic_vector (31 downto 0);        
---  signal cc_R3_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R4_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R5_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R6_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R7_sig             : std_logic_vector (31 downto 0);
-
---  signal cc_R8_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R9_sig             : std_logic_vector (31 downto 0); 
---  signal cc_R11_sig            : std_logic_vector (31 downto 0); 
---  signal cc_R13_sig            : std_logic_vector (31 downto 0); 
---  signal cc_R14_sig            : std_logic_vector (31 downto 0); 
---  signal cc_R15_sig            : std_logic_vector (31 downto 0); 
-
-
-
-  
   signal timemarker_select_sig : std_logic := '0';
 
@@ -174 +153 @@
   end process sync_ld_proc;
   
- -- config_done <= config_ready_sig;  -- indicates that the configuration 
-                                      -- has been loaded 
-
- -- config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration 
-                                                        -- has been loaded and
-                                                        -- the PLL has locked
-  
- config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
-
---  config_done <= config_ready_sig;
---  locked      <= load_detect_sr(1) and load_detect_sr(0);
+-- config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
+
+  config_done <= config_ready_sig;
+  locked      <= load_detect_sr(1) and load_detect_sr(0);
   
   
@@ -214 +186 @@
   
   config_started <= config_started_sig;
-
-
---  -----------------------------------------------------------------------------
-    
---  cc_R0_sig  <= cc_R0;             
---  cc_R1_sig  <= cc_R1;
-  
---  cc_R2_sig  <= cc_R2_const;                 
---  cc_R3_sig  <= cc_R3_const;   
---  cc_R4_sig  <= cc_R4_const;           
---  cc_R5_sig  <= cc_R5_const;    
---  cc_R6_sig  <= cc_R6_const;       
---  cc_R7_sig  <= cc_R7_const;
-  
---  cc_R8_sig  <= cc_R8;
---  cc_R9_sig  <= cc_R9;      
---  cc_R11_sig <= cc_R11;       
---  cc_R13_sig <= cc_R13;          
---  cc_R14_sig <= cc_R14;           
---  cc_R15_sig <= cc_R15;
-
-
-
-
-
-
-  
---  clk_cond_array_sig(0) <= LMK03000_Reset;      -- reset LKM03000 by setting
---                                                -- bit 31 of register 0
---  clk_cond_array_sig(1) <= cc_R0_sig;
---  clk_cond_array_sig(2) <= cc_R1_sig;
-  
---  clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels
---  clk_cond_array_sig(4) <= cc_R3_sig; 
---  clk_cond_array_sig(5) <= cc_R4_sig; 
---  clk_cond_array_sig(6) <= cc_R5_sig; 
---  clk_cond_array_sig(7) <= cc_R6_sig; 
---  clk_cond_array_sig(8) <= cc_R7_sig; -- unused channels
-  
---  clk_cond_array_sig(9)  <= cc_R8_sig; 
---  clk_cond_array_sig(10) <= cc_R9_sig; 
---  clk_cond_array_sig(11) <= cc_R11_sig;
---  clk_cond_array_sig(12) <= cc_R13_sig;
---  clk_cond_array_sig(13) <= cc_R14_sig;
---  clk_cond_array_sig(14) <= cc_R15_sig;
-
--- -----------------------------------------------------------------------------
- 
-  
+     
   clk_cond_array_sig(0) <= LMK03000_Reset;      -- reset LKM03000 by setting
                                                 -- bit 31 of register 0