Changeset 11801 for firmware/FAD/FACT_FAD_lib/hdl
- Timestamp:
- 08/05/11 18:44:23 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_lib/hdl
- Files:
-
- 4 edited
-
fad_board_struct.vhd (modified) (2 diffs)
-
fad_definitions.vhd (modified) (3 diffs)
-
fad_main_struct.vhd (modified) (3 diffs)
-
w5300_modul.vhd (modified) (15 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd
r11757 r11801 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 9:03:20 03.08.20115 -- at - 17:22:06 05.08.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 9:03:20 03.08.201178 -- at - 17:22:07 05.08.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_lib/hdl/fad_definitions.vhd
r11757 r11801 55 55 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 56 56 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; 57 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"1 3";57 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"14"; 58 58 constant PACKAGE_HEADER_LENGTH : integer := 36; 59 59 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 107 107 108 108 -- 109 constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes 109 --constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes 110 constant W5300_TX_FIFO_SIZE_8B : integer := 61440; -- Socket TX FIFO-Size in Bytes 110 111 constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words 111 112 … … 177 178 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 178 179 179 constant CMD_BUSY_ ON: std_logic_vector := X"24";180 constant CMD_BUSY_ OFF: std_logic_vector := X"25";180 constant CMD_BUSY_FIX_OFF_TRUE : std_logic_vector := X"24"; 181 constant CMD_BUSY_FIX_OFF_FALSE : std_logic_vector := X"25"; 181 182 182 183 constant CMD_STATUS : std_logic_vector := X"FF"; -
firmware/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
r11757 r11801 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 9:03:18 03.08.20115 -- at - 17:22:05 05.08.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 83 83 -- Created: 84 84 -- by - daqct3.UNKNOWN (IHP110) 85 -- at - 1 9:03:19 03.08.201185 -- at - 17:22:06 05.08.2011 86 86 -- 87 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 571 571 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 572 572 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 573 busy_enable : OUT std_logic := ' 0';573 busy_enable : OUT std_logic := '1'; 574 574 socket_send_mode_out : OUT std_logic ; 575 575 busy_manual : OUT std_logic := '0'; -
firmware/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd
r11757 r11801 81 81 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH. 82 82 srclk_enable : out std_logic := '1'; -- default SRCLK on. 83 busy_enable : out std_logic := ' 0';83 busy_enable : out std_logic := '1'; 84 84 socket_send_mode_out : out std_logic; 85 85 busy_manual : out std_logic := '0'; … … 450 450 else 451 451 socket_cnt <= socket_cnt + 1; 452 if (socket_cnt = 7) then452 if (socket_cnt = 1) then 453 453 state_interrupt_2 <= IR2_05; 454 454 else … … 483 483 next_state <= INTERRUPT; 484 484 socket_cnt <= socket_cnt + 1; 485 if (socket_cnt = 7) then485 if (socket_cnt = 1) then 486 486 socket_cnt <= "000"; 487 487 --state_interrupt_2 <= IR2_06; … … 506 506 else 507 507 if ( data_read(7 downto 0) = SOCKET_CLOSED ) then 508 if ( socket_cnt = 7) then508 if ( socket_cnt = 1 ) then 509 509 socket_cnt <= "000"; 510 510 state_interrupt_2 <= IR2_06; … … 546 546 c_trigger_enable <= '0'; 547 547 trigger_enable_sig <= '0'; 548 busy_enable <= ' 0';548 busy_enable <= '1'; 549 549 busy_manual <= '0'; 550 550 socket_send_mode <= '0'; … … 674 674 -- Socket TX Memory Size 675 675 when STX => 676 par_data <= X"0F0F"; -- 15K TX 677 678 par_addr <= W5300_TMS01R; 679 state_init <=WRITE_REG; 680 next_state <= STX1; 681 when STX1 => 682 par_addr <= W5300_TMS23R; 683 state_init <=WRITE_REG; 684 next_state <= STX2; 685 when STX2 => 686 par_addr <= W5300_TMS45R; 687 state_init <=WRITE_REG; 688 next_state <= STX3; 689 when STX3 => 690 par_addr <= W5300_TMS67R; 691 state_init <=WRITE_REG; 692 next_state <= SRX; 676 par_data <= X"3C3C"; -- 60K TX 677 par_addr <= W5300_TMS01R; 678 state_init <=WRITE_REG; 679 next_state <= STX1; 680 when STX1 => 681 par_data <= X"0000"; --- nothing 682 par_addr <= W5300_TMS23R; 683 state_init <=WRITE_REG; 684 next_state <= STX2; 685 when STX2 => 686 par_data <= X"0000"; --- nothing 687 par_addr <= W5300_TMS45R; 688 state_init <=WRITE_REG; 689 next_state <= STX3; 690 when STX3 => 691 par_data <= X"0000"; --- nothing 692 par_addr <= W5300_TMS67R; 693 state_init <=WRITE_REG; 694 next_state <= SRX; 693 695 694 -- Socket RX Memory Size 695 when SRX => 696 par_data <= X"0101"; -- 1K RX 697 698 par_addr <= W5300_RMS01R; 699 state_init <=WRITE_REG; 700 next_state <= SRX1; 701 when SRX1 => 702 par_addr <= W5300_RMS23R; 703 state_init <=WRITE_REG; 704 next_state <= SRX2; 705 when SRX2 => 706 par_addr <= W5300_RMS45R; 707 state_init <=WRITE_REG; 708 next_state <= SRX3; 709 when SRX3 => 710 par_addr <= W5300_RMS67R; 711 state_init <=WRITE_REG; 712 next_state <= MAC; 696 -- Socket RX Memory Size 697 when SRX => 698 par_data <= X"0404"; -- 4K RX 699 par_addr <= W5300_RMS01R; 700 state_init <=WRITE_REG; 701 next_state <= SRX1; 702 when SRX1 => 703 par_data <= X"0000"; --- nothing 704 par_addr <= W5300_RMS23R; 705 state_init <=WRITE_REG; 706 next_state <= SRX2; 707 when SRX2 => 708 par_data <= X"0000"; --- nothing 709 par_addr <= W5300_RMS45R; 710 state_init <=WRITE_REG; 711 next_state <= SRX3; 712 when SRX3 => 713 par_data <= X"0000"; --- nothing 714 par_addr <= W5300_RMS67R; 715 state_init <=WRITE_REG; 716 next_state <= MAC; 713 717 714 718 -- MAC … … 826 830 state_init <= WRITE_REG; 827 831 socket_cnt <= socket_cnt + 1; 828 if (socket_cnt = 7) then832 if (socket_cnt = 1) then 829 833 socket_cnt <= "000"; 830 834 next_state <= ESTABLISH; -- All Sockets open … … 845 849 case data_read (7 downto 0) is 846 850 when X"17" => -- established 847 if (socket_cnt = 7) then851 if (socket_cnt = 1) then 848 852 socket_cnt <= "000"; 849 853 busy <= '0'; … … 875 879 state_init <= WRITE_REG; 876 880 socket_cnt <= socket_cnt + 1; 877 if (socket_cnt = 7) then881 if (socket_cnt = 1) then 878 882 socket_cnt <= "000"; 879 883 next_state <= SET_Sn_KPALVTR; … … 887 891 888 892 socket_cnt <= socket_cnt + 1; 889 if (socket_cnt = 7) then893 if (socket_cnt = 1) then 890 894 socket_cnt <= "000"; 891 895 next_state <= MAIN; … … 905 909 initial_message_counter <= 0; 906 910 socket_cnt <= socket_cnt + 1; 907 if (socket_cnt = 7) then911 if (socket_cnt = 1) then 908 912 socket_cnt <= "000"; 909 913 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE; … … 918 922 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_HIGH_BYTE; 919 923 socket_cnt <= socket_cnt + 1; 920 if (socket_cnt = 7) then924 if (socket_cnt = 1) then 921 925 socket_cnt <= "000"; 922 926 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE; … … 930 934 next_state <= INITIAL_CONNECTION_MESSAGE_SET_SIZE_LOW_BYTE; 931 935 socket_cnt <= socket_cnt + 1; 932 if (socket_cnt = 7) then936 if (socket_cnt = 1) then 933 937 socket_cnt <= "000"; 934 938 next_state <= INITIAL_CONNECTION_MESSAGE_SEND; … … 942 946 next_state <= INITIAL_CONNECTION_MESSAGE_SEND; 943 947 socket_cnt <= socket_cnt + 1; 944 if (socket_cnt = 7) then948 if (socket_cnt = 1) then 945 949 socket_cnt <= "000"; 946 950 next_state <= MAIN; … … 1197 1201 state_read_data <= RD_5; 1198 1202 1199 when CMD_BUSY_ ON=>1203 when CMD_BUSY_FIX_OFF_TRUE => 1200 1204 busy_enable <= '1'; 1201 1205 state_read_data <= RD_5; 1202 when CMD_BUSY_ OFF=>1206 when CMD_BUSY_FIX_OFF_FALSE => 1203 1207 busy_enable <= '0'; 1204 1208 state_read_data <= RD_5;
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