- Timestamp:
- 07/06/10 16:46:25 (14 years ago)
- File:
-
- 1 edited
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FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd
r236 r242 19 19 mosi : OUT std_logic := '0'; 20 20 dac_id : IN std_logic_vector (2 DOWNTO 0); 21 data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 21 --data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 22 data : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 22 23 dac_cs : OUT std_logic := '1'; 23 24 dac_start : IN std_logic; … … 43 44 miso <= 'Z'; 44 45 mosi <= '0'; 45 data <= (others => 'Z');46 --data <= (others => 'Z'); 46 47 case spi_state is 47 48 when SPI_IDLE =>
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