Changeset 243
- Timestamp:
- 07/07/10 16:30:13 (14 years ago)
- Location:
- FPGA/FTU/test_firmware/FTU_test2
- Files:
-
- 4 edited
-
FTU_test2.vhd (modified) (1 diff)
-
FTU_test2_dac_control.vhd (modified) (6 diffs)
-
FTU_test2_spi_controller.vhd (modified) (2 diffs)
-
FTU_test2_spi_distributor.vhd (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
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FPGA/FTU/test_firmware/FTU_test2/FTU_test2.vhd
r241 r243 3 3 -- Engineer: P. Vogler, Q. Weitzel 4 4 -- 5 -- Create Date: 05/ 17/20105 -- Create Date: 05/07/2010 6 6 -- Design Name: 7 7 -- Module Name: FTU_test2 - Behavioral -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r241 r243 3 3 -- Engineer: P. Vogler, Q. Weitzel 4 4 -- 5 -- Create Date: 05/ 17/20105 -- Create Date: 05/07/2010 6 6 -- Design Name: 7 7 -- Module Name: FTU_test2_dac_control - Behavioral … … 60 60 end component; 61 61 62 --component FTU_test2_upcnt1663 -- port(64 -- full : out STD_LOGIC;65 -- clr : in STD_LOGIC;66 -- reset : in STD_Logic;67 -- clk : in STD_LOGIC68 -- );69 --end component;70 71 62 signal clk_sig : std_logic; 72 63 signal reset_sig : std_logic; … … 81 72 signal config_started_sig : std_logic := '0'; 82 73 signal dac_array_sig : dac_array_type := (100,200,300,400,500); 83 84 --signal full_sig : std_logic; 85 --signal clr_wcnt_sig : std_logic; 86 74 87 75 -- Build an enumerated type for the state machine 88 76 type state_type is (START, WAITING, STOP); 89 77 90 78 -- Register to hold the current state 91 signal state, next_state : state_type;79 signal state, next_state : state_type; 92 80 93 81 begin 94 82 95 --to be checked96 83 reset_sig <= reset; 97 84 clk_sig <= clk; … … 122 109 next_state <= WAITING; 123 110 when WAITING => 111 config_start_sig <= '1'; 124 112 enable1 <= '0'; 125 113 enable2 <= '1'; … … 134 122 enable2 <= '0'; 135 123 enable3 <= '1'; 136 config_start_sig <= '0'; 124 config_start_sig <= '0'; 137 125 end case; 138 126 end process; … … 151 139 ); 152 140 153 --Inst_FTU_test2_upcnt16: FTU_test2_upcnt16154 -- port map(155 -- full => full_sig,156 -- clr => clr_wcnt_sig,157 -- reset => reset_sig,158 -- clk => serial_clock_sig159 -- );160 161 141 end Behavioral; 162 142 -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_controller.vhd
r242 r243 7 7 -- 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) 9 -- 10 -- modified by Q. Weitzel 9 11 -- 10 12 LIBRARY ieee; … … 55 57 spi_cycle_cnt <= 0; 56 58 if (dac_start = '1') then 57 shift_reg <= "0011" & '0' & dac_id & data ;59 shift_reg <= "0011" & '0' & dac_id & data(11 downto 0) & "0000"; 58 60 spi_state <= SPI_LOAD_DAC; 59 61 end if; -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd
r242 r243 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) 9 9 -- 10 10 -- modified by Q. Weitzel 11 -- 11 12 LIBRARY ieee; 12 13 USE ieee.std_logic_1164.all; … … 37 38 signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; 38 39 signal dac_id_cnt : integer range 0 to 4 := 0; 39 signal wait_cnt : integer range 0 to 3 := 0;40 40 41 41 BEGIN … … 51 51 --data <= (others => 'Z'); 52 52 data <= (others => '0'); 53 if wait_cnt < 3 then 54 wait_cnt <= wait_cnt + 1; 55 spi_distr_state <= INIT; 56 else 57 spi_distr_state <= IDLE; 58 end if; 53 spi_distr_state <= IDLE; 59 54 when IDLE => 60 55 --data <= (others => 'Z');
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