- Timestamp:
- 07/12/10 12:19:49 (14 years ago)
- Location:
- FPGA/FTU
- Files:
-
- 2 copied
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FTU/FTU_top.vhd
r250 r251 15 15 -- Revision: 16 16 -- Revision 0.01 - File Created 17 -- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel 17 18 -- Additional Comments: 18 19 -- … … 75 76 architecture Behavioral of FTU_top is 76 77 77 component FTU_dac_dcm78 port(79 CLKIN_IN : IN STD_LOGIC;80 RST_IN : IN STD_LOGIC;81 CLKFX_OUT : OUT STD_LOGIC;82 CLKIN_IBUFG_OUT : OUT STD_LOGIC;83 LOCKED_OUT : OUT STD_LOGIC84 );85 end component;86 87 component FTU_dac_control88 port(89 clk : IN STD_LOGIC;90 reset : IN STD_LOGIC;91 miso : IN STD_LOGIC;92 clr : OUT STD_LOGIC;93 mosi : OUT STD_LOGIC;94 sck : OUT STD_LOGIC;95 cs_ld : OUT STD_LOGIC96 );97 end component;98 99 78 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up 100 79 signal clk_5M_sig : STD_LOGIC; … … 104 83 105 84 begin 106 107 Inst_FTU_dac_dcm : FTU_dac_dcm108 port map(109 CLKIN_IN => ext_clk,110 RST_IN => reset_sig,111 CLKFX_OUT => clk_5M_sig,112 CLKIN_IBUFG_OUT => open,113 LOCKED_OUT => open114 );115 116 Inst_FTU_dac_control : FTU_dac_control117 port map(118 clk => clk_5M_sig,119 reset => reset_sig,120 miso => '0',121 clr => clr,122 mosi => mosi,123 sck => sck,124 cs_ld => cs_ld125 );126 85 127 86 --FTU main state machine (two-process implementation) … … 149 108 150 109 end Behavioral; 151 152 --What is missing?153 --UART154 --registers (enables, DAC values etc.)155 --rate counters156 --main state machine for FTU: talks to DAC, reads counters, listens to UART157
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