Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd

Timestamp:

07/16/10 16:25:44 (14 years ago)

Author:

dneise

Message:

DRS addresses may not be set via
sa 44 0 .. 31

File:

• FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd (modified) (6 diffs)

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd

@@ -36 +36 @@
       ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
       dac_array         : OUT    dac_array_type;
-      roi_array         : OUT    roi_array_type
+      roi_array         : OUT    roi_array_type;
+      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
+      drs_address_mode  : OUT    std_logic
    );
 
@@ -53 +55 @@
   signal int_dac_array : dac_array_type := DEFAULT_DAC;
   signal int_roi_array : roi_array_type := DEFAULT_ROI;
+  signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR;
+  signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE;
 
 BEGIN
@@ -66 +70 @@
         
         when CTRL_INIT =>
+          -- WRITES DEFAULT VALUES IN config ram
           addr_cntr <= addr_cntr + 1;
           ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
@@ -76 +81 @@
           elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
             ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16);
+          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
+            ram_data_in <=  "0000" & "0000" 
+                            & "000" & conv_std_logic_vector(int_drs_address_mode, 1)
+                            & int_drs_address;
           else
             ram_write_en <= "0"; 
@@ -82 +91 @@
       
         when CTRL_IDLE =>
+          -- 
           addr_cntr <= 0;
           ram_write_en <= "0";
@@ -119 +129 @@
             dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out);
             ctrl_state <= CTRL_LOAD_ADDR;
-          else
+          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
+             drs_address <= ram_data_out(3 downto 0);
+             drs_address_mode <= ram_data_out(4);
+             ctrl_state <= CTRL_LOAD_ADDR;
+          else 
             addr_cntr <= 0;
             config_started <= '0';