Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd

Timestamp:

07/16/10 16:25:44 (14 years ago)

Author:

dneise

Message:

DRS addresses may not be set via
sa 44 0 .. 31

File:

• FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd (modified) (9 diffs)

FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd

@@ -2 +2 @@
 --
 -- Created:
---          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
---          at - 12:42:19 02.07.2010
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 15:25:14 14.07.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -27 +27 @@
       W_INT      : IN     std_logic;
       X_50M      : IN     STD_LOGIC;
-      A1_T       : OUT    std_logic_vector (3 DOWNTO 0);
+      A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0');
       A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
       D0_SRCLK   : OUT    STD_LOGIC;
@@ -72 +72 @@
 --
 -- Created:
---          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
---          at - 12:42:20 02.07.2010
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 15:25:14 14.07.2010
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
@@ -95 +95 @@
    SIGNAL CLK_25_PS      : std_logic;
    SIGNAL CLK_50         : std_logic;
-   SIGNAL SRCLK          : std_logic := '0';
+   SIGNAL SRCLK          : std_logic                    := '0';
    SIGNAL TRG_OR         : std_logic;
    SIGNAL adc_data_array : adc_data_array_type;
    SIGNAL board_id       : std_logic_vector(3 DOWNTO 0);
    SIGNAL crate_id       : std_logic_vector(1 DOWNTO 0);
+   SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
    SIGNAL dummy          : std_logic;
-   SIGNAL not_TEST_TRG   : STD_LOGIC;
    SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0);
-   SIGNAL trigger_out    : STD_LOGIC := '0';
-
-   -- Implicit buffer signal declarations
-   SIGNAL RSRLOAD_internal : std_logic;
 
 
@@ -148 +144 @@
    );
    END COMPONENT;
-   COMPONENT debouncer
-   GENERIC (
-      WIDTH : INTEGER := 17
-   );
-   PORT (
-      clk         : IN     STD_LOGIC ;
-      --           rst : in  STD_LOGIC;
-      trigger_in  : IN     STD_LOGIC ;
-      trigger_out : OUT    STD_LOGIC  := '0'
-   );
-   END COMPONENT;
 
    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
-   FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer;
    -- pragma synthesis_on
 
@@ -228 +212 @@
    -- HDL Embedded Text Block 8 eb2
    -- eb2 8                                        
-   A1_T(0) <= dummy;
-   A1_T(1) <= RSRLOAD_internal;
-   A1_T(2) <= D0_SROUT;
-   A1_T(3) <= D1_SROUT;
+   A1_T(3 downto 0) <= drs_channel_id;
+   D_A <= drs_channel_id;
+   A1_T(4)  <= TRG_OR;
 
 
@@ -237 +220 @@
    DAC_CS <= dummy;
 
-   -- ModuleWare code(v1.9) for instance 'I1' of 'inv'
-   not_TEST_TRG <= NOT(TEST_TRG);
-
    -- ModuleWare code(v1.9) for instance 'I2' of 'or'
-   TRG_OR <= TRG OR trigger_out;
+   TRG_OR <= TRG OR TEST_TRG;
 
    -- Instance port mappings.
@@ -262 +242 @@
          CLK_25_PS      => CLK_25_PS,
          CLK_50         => CLK_50,
-         RSRLOAD        => RSRLOAD_internal,
+         RSRLOAD        => RSRLOAD,
          SRCLK          => SRCLK,
          adc_oeb        => OE_ADC,
          dac_cs         => dummy,
          denable        => DENABLE,
-         drs_channel_id => D_A,
+         drs_channel_id => drs_channel_id,
          drs_dwrite     => DWRITE,
          led            => D_T,
@@ -281 +261 @@
          wiz_data       => W_D
       );
-   I_debouncer : debouncer
-      GENERIC MAP (
-         WIDTH => 17
-      )
-      PORT MAP (
-         clk         => CLK_50,
-         trigger_in  => not_TEST_TRG,
-         trigger_out => trigger_out
-      );
-
-   -- Implicit buffered output assignments
-   RSRLOAD <= RSRLOAD_internal;
 
 END struct;