- Timestamp:
- 07/22/10 10:33:08 (14 years ago)
- File:
-
- 1 edited
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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r252 r260 105 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0";107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; 108 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 109 … … 124 124 constant CMD_DWRITE_RUN : std_logic_vector := X"08"; 125 125 constant CMD_DWRITE_STOP : std_logic_vector := X"09"; 126 constant CMD_SCLK_ON : std_logic_vector := X"10"; 127 constant CMD_SCLK_ON : std_logic_vector := X"11"; 128 129 126 130 -- Declare functions and procedure 127 131
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