- Timestamp:
- 07/22/10 10:33:08 (14 years ago)
- File:
-
- 1 edited
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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
r252 r260 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 4:46:38 12.07.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 11:40:17 21.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 59 59 -- 60 60 -- Created: 61 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)62 -- at - 1 4:46:38 12.07.201061 -- by - dneise.UNKNOWN (E5B-LABOR6) 62 -- at - 11:40:18 21.07.2010 63 63 -- 64 64 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 125 125 SIGNAL roi_max : roi_max_type; 126 126 SIGNAL s_trigger : std_logic := '0'; 127 SIGNAL sclk1 : std_logic; 128 SIGNAL sclk_enable : std_logic; 127 129 SIGNAL sensor_array : sensor_array_type; 128 130 SIGNAL sensor_ready : std_logic; … … 332 334 config_busy : IN std_logic ; 333 335 denable : OUT std_logic := '0'; -- default domino wave off 334 dwrite_enable : OUT std_logic := '0' -- default DWRITE low. 336 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 337 sclk_enable : OUT std_logic := '1' -- default DWRITE HIGH. 335 338 ); 336 339 END COMPONENT; … … 355 358 -- ModuleWare code(v1.9) for instance 'I5' of 'and' 356 359 drs_dwrite <= dwrite AND dwrite_enable; 360 361 -- ModuleWare code(v1.9) for instance 'U_1' of 'and' 362 sclk <= sclk_enable AND sclk1; 357 363 358 364 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' … … 502 508 dac_cs => dac_cs, 503 509 mosi => mosi, 504 sclk => sclk ,510 sclk => sclk1, 505 511 sensor_array => sensor_array, 506 512 sensor_cs => sensor_cs, … … 547 553 config_busy => config_busy, 548 554 denable => denable, 549 dwrite_enable => dwrite_enable 555 dwrite_enable => dwrite_enable, 556 sclk_enable => sclk_enable 550 557 ); 551 558
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