Changeset 9879 for firmware/FTM


Ignore:
Timestamp:
08/18/10 13:42:10 (14 years ago)
Author:
vogler
Message:
FTM pin location ucf file updated and test 1 & 2 checked in
File:
1 edited

Legend:

Unmodified
Added
Removed

  • firmware/FTM/ftm_board.ucf

    r9844 r9879  
    66#
    77# by Patrick Vogler
    8 # 02 July 2010
     8# 18 August 2010
    99########################################################
    1010
    … …  
    1212#Clock
    1313#######################################################
    14 NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK
     14NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
    1515
    1616
    1717# Ethernet Interface
    18 # connection to the WIZnet W5300 ethernet controller
     18# connection to the WIZnet W5300 ethernet controller (U37)
    1919# on IO-Bank 1
    2020#######################################################
    … …  
    5757NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
    5858
    59 # W5300
     59# W5300 buffer ready indicator
    6060NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
    6161NET W_BRDY<1>   LOC  = AC26  | IOSTANDARD=LVCMOS33; #
    … …  
    6363NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
    6464
    65 # W5300
     65# W5300 associated testpoints
    6666NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
    6767NET W_T<1>   LOC  = M21  | IOSTANDARD=LVCMOS33; #
    6868NET W_T<2>   LOC  = K21  | IOSTANDARD=LVCMOS33; #
     69NET W_T<3>   LOC  = R19  | IOSTANDARD=LVCMOS33; #
    6970
    7071
    … …  
    8384# temperature sensors
    8485NET SIO        LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
    85 NET TS_CS_<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
    86 NET TS_CS_<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
    87 NET TS_CS_<2>  LOC  = C25  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select2
    88 NET TS_CS_<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
     86NET TS_CS<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
     87NET TS_CS<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
     88NET TS_CS<2>  LOC  = C25  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select2
     89NET TS_CS<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
    8990
    9091
    … …  
    9293# on IO-Bank 2
    9394#######################################################
    94 # crate 0
    95 NET Trig-Prim_0_<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; #       
    96 NET Trig-Prim_0_<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; #
    97 NET Trig-Prim_0_<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; #
    98 NET Trig-Prim_0_<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; #
    99 NET Trig-Prim_0_<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; #
    100 NET Trig-Prim_0_<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; #
    101 NET Trig-Prim_0_<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; #
    102 NET Trig-Prim_0_<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; #
    103 NET Trig-Prim_0_<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; #
    104 NET Trig-Prim_0_<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; #
     95# crate 0
     96# crate A
     97NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>       
     98NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
     99NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
     100NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
     101NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
     102NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
     103NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
     104NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
     105NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
     106NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
    105107
    106108# crate 1
    107 NET Trig-Prim_1_<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; #       
    108 NET Trig-Prim_1_<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; #
    109 NET Trig-Prim_1_<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; #
    110 NET Trig-Prim_1_<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; #
    111 NET Trig-Prim_1_<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; #
    112 NET Trig-Prim_1_<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; #
    113 NET Trig-Prim_1_<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; #
    114 NET Trig-Prim_1_<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; #
    115 NET Trig-Prim_1_<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; #
    116 NET Trig-Prim_1_<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; #
     109# crate B
     110NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>       
     111NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
     112NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
     113NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
     114NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
     115NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
     116NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
     117NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
     118NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
     119NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
    117120
    118121# crate 2
    119 NET Trig-Prim_2_<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; #       
    120 NET Trig-Prim_2_<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; #
    121 NET Trig-Prim_2_<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; #
    122 NET Trig-Prim_2_<3>  LOC  = AD21 | IOSTANDARD=LVCMOS33; #
    123 NET Trig-Prim_2_<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; #
    124 NET Trig-Prim_2_<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; #
    125 NET Trig-Prim_2_<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; #
    126 NET Trig-Prim_2_<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; #
    127 NET Trig-Prim_2_<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; #
    128 NET Trig-Prim_2_<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; #
     122# crate C
     123NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>       
     124NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
     125NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
     126NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
     127NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
     128NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
     129NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
     130NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
     131NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
     132NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
    129133
    130134# crate 3
    131 NET Trig-Prim_3_<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; #       
    132 NET Trig-Prim_3_<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; #
    133 NET Trig-Prim_3_<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; #
    134 NET Trig-Prim_3_<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; #
    135 NET Trig-Prim_3_<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; #
    136 NET Trig-Prim_3_<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; #
    137 NET Trig-Prim_3_<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; #
    138 NET Trig-Prim_3_<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; #
    139 NET Trig-Prim_3_<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; #
    140 NET Trig-Prim_3_<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; #
     135# crate D
     136NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>       
     137NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
     138NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
     139NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
     140NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
     141NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
     142NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
     143NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
     144NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
     145NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
    141146
    142147
    … …  
    144149#######################################################
    145150# on IO-Bank 3
    146 NET ext_Trig_<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
    147 NET ext_Trig_<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
     151NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
     152NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
    148153NET Veto          LOC  = E4  | IOSTANDARD=LVCMOS33; #
    149154NET NIM_In<0>     LOC  = D3  | IOSTANDARD=LVCMOS33; #
    … …  
    152157
    153158# on IO-Bank 0
    154 NET NIM_In3/GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33; # input with global clock buffer
     159NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33; # input with global clock buffer
    155160                                                     # available
    156161
    … …  
    159164# on IO-Banks 0 and 3
    160165#######################################################
    161 ###                                                 ###
    162 #          OPEN COLLECTOR OUTPUTS FOR THE LEDs        #
    163 ###                                                 ###
    164166# red
    165 NET LED_red_<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
    166 NET LED_red_<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
    167 NET LED_red_<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3 
    168 NET LED_red_<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3 
     167NET LED_red<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
     168NET LED_red<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
     169NET LED_red<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
     170NET LED_red<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
    169171
    170172# yellow
    171 NET LED_ye_<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
    172 NET LED_ye_<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
     173NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
     174NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    173175
    174176# green
    175 NET LED_gn_<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
    176 NET LED_gn_<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
     177NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
     178NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    177179
    178180
    … …  
    180182# on IO-Bank 3
    181183#######################################################
    182 NET CLK_Clk-Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    183 NET LE_Clk-Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    184 NET LD_Clk-Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    185 NET DATA_Clk-Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    186 NET SYNC_Clk-Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
     184NET CLK_Clk_Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
     185NET LE_Clk_Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
     186NET LD_Clk_Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
     187NET DATA_Clk_Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
     188NET SYNC_Clk_Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    187189
    188190
    … …  
    191193#######################################################
    192194# Bus 1: FTU slow control
    193 NET Bus1_Tx-En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    194 NET Bus1_Rx-En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     195NET Bus1_Tx_En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     196NET Bus1_Rx_En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    195197
    196198# crate 0
    … …  
    212214
    213215# Bus 2: Trigger-ID to FAD boards
    214 NET Bus2_Tx-En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    215 NET Bus2_Rx-En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     216NET Bus2_Tx_En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     217NET Bus2_Rx_En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    216218
    217219# crate 0
    … …  
    233235
    234236# auxiliary access
    235 NET Aux_Rx-D     LOC  = W3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    236 NET Aux_Tx-D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    237 NET Aux_Rx-En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
    238 NET Aux_Tx-En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
     237NET Aux_Rx_D     LOC  = W3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     238NET Aux_Tx_D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     239NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
     240NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
    239241                                                                  # Trigger-ID
    240242
    241243# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
    242 NET TrID_Rx-D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    243 NET TrID_Tx-D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     244NET TrID_Rx_D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     245NET TrID_Tx_D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    244246
    245247
    … …  
    247249# on IO-Bank 3
    248250#######################################################
    249 NET Crate-Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    250 NET Crate-Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    251 NET Crate-Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    252 NET Crate-Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     251NET Crate_Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     252NET Crate_Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     253NET Crate_Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
     254NET Crate_Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    253255
    254256
    … …  
    268270#######################################################
    269271# calibration
    270 NET Cal_NIM1+   LOC  = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
    271 NET Cal_NIM1-   LOC  = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
    272 NET Cal_NIM2+   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
    273 NET Cal_NIM2-   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
     272NET Cal_NIM1_p   LOC  = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM1+
     273NET Cal_NIM1_n   LOC  = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM1-
     274NET Cal_NIM2_p   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2+
     275NET Cal_NIM2_n   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2-
    274276
    275277# auxiliarry / spare NIM outputs
    276 NET NIM_Out0+  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
    277 NET NIM_Out0-  LOC  = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
    278 NET NIM_Out1+  LOC  = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #
    279 NET NIM_Out1-  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #
     278NET NIM_Out0_p  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #  NIM_Out0+
     279NET NIM_Out0_n  LOC  = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-
     280NET NIM_Out1_p  LOC  = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  NIM_Out1+
     281NET NIM_Out1_n  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
    280282
    281283
    … …  
    284286# conversion stage
    285287#######################################################
    286 NET RES+       LOC  = D16  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # Reset
    287 NET RES-       LOC  = C15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # IO-Bank 0
    288 
    289 NET TRG+       LOC  = B15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; # Trigger
    290 NET TRG-       LOC  = A15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; # IO-Bank 0
    291 
    292 NET TIM_Run+   LOC  = AF25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # Time Marker
    293 NET TIM_Run-   LOC  = AE25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # IO-Bank 2
    294 NET TIM-Sel    LOC  = AD22 | IOSTANDARD=LVCMOS33;   # Time Marker selector
     288NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES+   Reset
     289NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES-   IO-Bank 0
     290
     291NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; #   TRG+  Trigger
     292NET TRG_n      LOC  = A15  | IOSTANDARD=LVDS_33   | DIFF_TERM="False";  #   TRG- IO-Bank 0
     293
     294NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  TIM_Run+ Time Marker
     295NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  TIM_Run-
     296                                                                        #  on IO-Bank2
     297NET TIM_Sel    LOC  = AD22 | IOSTANDARD=LVCMOS33;   # Time Marker selector
    295298                                                    # IO-Bank 2
    296299NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
    … …  
    301304#######################################################
    302305# to connector J13
    303 NET Cal_0+   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    304 NET Cal_0-   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    305 NET Cal_1+   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    306 NET Cal_1-   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    307 NET Cal_2+   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    308 NET Cal_2-   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    309 NET Cal_3+   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    310 NET Cal_3-   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
     306NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
     307NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
     308NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
     309NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
     310NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
     311NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
     312NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
     313NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
    311314
    312315# to connector J12
    313 NET Cal_4+   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    314 NET Cal_4-   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    315 NET Cal_5+   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    316 NET Cal_5-   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    317 NET Cal_6+   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    318 NET Cal_6-   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    319 NET Cal_7+   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; #
    320 NET Cal_7-   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # 
     316NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ 
     317NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- 
     318NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ 
     319NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- 
     320NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ 
     321NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- 
     322NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ 
     323NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-   
    321324
    322325
    … …  
    384387# on Connector T15
    385388NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
    386 NET TP<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
    387 NET TP<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
     389NET TP_in<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
     390NET TP_in<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
    388391
    389392
Note: See TracChangeset for help on using the changeset viewer.