source: firmware/FTM/FTM_top.vhd@ 10454

Last change on this file since 10454 was 10441, checked in by weitzel, 14 years ago
new FTM firmware featuring e.g. start/stop run commands and new header
File size: 49.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 08 December 2010
6-- Design Name:
7-- Module Name: FTM_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity for FTM firmware
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftm_definitions;
28USE ftm_definitions.ftm_array_types.all;
29USE ftm_definitions.ftm_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36
37entity FTM_top is
38 port(
39
40 -- Clock
41 clk : IN STD_LOGIC; -- external clock from oscillator U47
42
43 -- connection to the WIZnet W5300 ethernet controller
44 -- on IO-Bank 1
45 -------------------------------------------------------------------------------
46 -- W5300 data bus
47 W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
48
49 -- W5300 address bus
50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because
51 -- the W5300 is operated in the
52 -- 16-bit mode
53 -- -> W_A<0> assigned to unconnected pin
54
55 -- W5300 control signals
56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
57 -- W_CS is also routed to testpoint JP7
58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select
59 W_INT : IN STD_LOGIC; -- interrupt
60 W_RD : out STD_LOGIC := '1'; -- read
61 W_WR : out STD_LOGIC := '1'; -- write
62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip
63
64 -- W5300 buffer ready indicator
65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
66
67 -- testpoints (T18) associated with the W5300 on IO-bank 1
68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
69
70
71 -- SPI Interface
72 -- connection to the EEPROM U36 (AL25L016M) and
73 -- temperature sensors U45, U46, U48 and U49 (all MAX6662)
74 -- on IO-Bank 1
75 -------------------------------------------------------------------------------
76 -- S_CLK : out STD_LOGIC; -- SPI clock
77
78 -- EEPROM
79 -- MOSI : out STD_LOGIC; -- master out slave in
80 -- MISO : in STD_LOGIC; -- master in slave out
81 -- EE_CS : out STD_LOGIC; -- EEPROM chip select
82
83 -- temperature sensors U45, U46, U48 and U49
84 -- SIO : inout STD_LOGIC; -- serial IO
85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
86
87
88 -- Trigger primitives inputs
89 -- on IO-Bank 2
90 -------------------------------------------------------------------------------
91 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
92 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
93 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
94 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
95
96
97 -- NIM inputs
98 ------------------------------------------------------------------------------
99 -- on IO-Bank 3
100 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
101 Veto : in STD_LOGIC; -- trigger veto input
102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
103
104 -- on IO-Bank 0
105 -- alternative external clock input for FPGA
106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
107
108
109 -- LEDs on IO-Banks 0 and 3
110 -------------------------------------------------------------------------------
111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
114
115
116 -- Clock conditioner LMK03000
117 -- on IO-Bank 3
118 -------------------------------------------------------------------------------
119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock
120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable
121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data
122
123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization
124 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for
125
126
127 -- various RS-485 Interfaces
128 -- on IO-Bank 3
129 -------------------------------------------------------------------------------
130 -- Bus 1: FTU slow control
131 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
132 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
133
134 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
135 Bus1_TxD_0 : out STD_LOGIC;
136
137 Bus1_RxD_1 : in STD_LOGIC; -- crate 1
138 Bus1_TxD_1 : out STD_LOGIC;
139
140 Bus1_RxD_2 : in STD_LOGIC; -- crate 2
141 Bus1_TxD_2 : out STD_LOGIC;
142
143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3
144 Bus1_TxD_3 : out STD_LOGIC;
145
146
147 -- Bus 2: Trigger-ID to FAD boards
148 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
149 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
150
151 Bus2_RxD_0 : in STD_LOGIC; -- crate 0
152 Bus2_TxD_0 : out STD_LOGIC;
153
154 Bus2_RxD_1 : in STD_LOGIC; -- crate 1
155 Bus2_TxD_1 : out STD_LOGIC;
156
157 Bus2_RxD_2 : in STD_LOGIC; -- crate 2
158 Bus2_TxD_2 : out STD_LOGIC;
159
160 Bus2_RxD_3 : in STD_LOGIC; -- crate 3
161 Bus2_TxD_3 : out STD_LOGIC;
162
163
164 -- auxiliary access
165 -- Aux_Rx_D : in STD_LOGIC;
166 -- Aux_Tx_D : out STD_LOGIC;
167 -- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
168 -- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
169
170
171 -- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
172 -- TrID_Rx_D : in STD_LOGIC;
173 -- TrID_Tx_D : out STD_LOGIC;
174
175
176 -- Crate-Resets
177 -- on IO-Bank 3
178 -------------------------------------------------------------------------------
179 -- Crate_Res0 : out STD_LOGIC;
180 -- Crate_Res1 : out STD_LOGIC;
181 -- Crate_Res2 : out STD_LOGIC;
182 -- Crate_Res3 : out STD_LOGIC;
183
184
185 -- Busy signals from the FAD boards
186 -- on IO-Bank 3
187 -------------------------------------------------------------------------------
188 Busy0 : in STD_LOGIC;
189 Busy1 : in STD_LOGIC;
190 Busy2 : in STD_LOGIC;
191 Busy3 : in STD_LOGIC;
192
193
194 -- NIM outputs
195 -- on IO-Bank 0
196 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
197 -------------------------------------------------------------------------------
198 -- calibration
199 -- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
200 -- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
201 -- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
202 -- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
203
204 -- auxiliarry / spare NIM outputs
205 -- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
206 -- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
207 -- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
208 -- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
209
210
211 -- fast control signal outputs
212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
213 -------------------------------------------------------------------------------
214 -- RES_p : out STD_LOGIC; -- RES+ Reset
215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
216
217 TRG_p : out STD_LOGIC; -- TRG+ Trigger
218 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
219
220 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
221 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
222 TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2
223
224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227 -- LVDS calibration outputs
228 -- on IO-Bank 0
229 -------------------------------------------------------------------------------
230 -- to connector J13
231 -- for light pulsar in the mirror dish
232 -- Cal_0_p : out STD_LOGIC;
233 -- Cal_0_n : out STD_LOGIC;
234 -- Cal_1_p : out STD_LOGIC;
235 -- Cal_1_n : out STD_LOGIC;
236 -- Cal_2_p : out STD_LOGIC;
237 -- Cal_2_n : out STD_LOGIC;
238 -- Cal_3_p : out STD_LOGIC;
239 -- Cal_3_n : out STD_LOGIC;
240
241 -- to connector J12
242 -- for light pulsar inside shutter
243 -- Cal_4_p : out STD_LOGIC;
244 -- Cal_4_n : out STD_LOGIC;
245 -- Cal_5_p : out STD_LOGIC;
246 -- Cal_5_n : out STD_LOGIC;
247 -- Cal_6_p : out STD_LOGIC;
248 -- Cal_6_n : out STD_LOGIC;
249 -- Cal_7_p : out STD_LOGIC;
250 -- Cal_7_n : out STD_LOGIC
251
252
253 -- Testpoints
254 -------------------------------------------------------------------------------
255 -- TP : inout STD_LOGIC_VECTOR(32 downto 0);
256 -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
257
258 -- Board ID - inputs
259 -- local board-ID "solder programmable"
260 -- all on 'input only' pins
261 -------------------------------------------------------------------------------
262 -- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
263
264 );
265end FTM_top;
266
267architecture Behavioral of FTM_top is
268
269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0);
270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0);
271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0);
272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0);
273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0);
274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0);
275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0);
276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0);
277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0);
278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0);
279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0);
280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0);
281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0);
282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0);
283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0);
284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0);
285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0);
286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0);
287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0);
288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0);
289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0);
290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0);
291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0);
292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0);
293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0);
294 signal sd_busy_sig : std_logic;
295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
296 signal sd_read_ftu_sig : std_logic;
297 signal sd_ready_sig : std_logic;
298 signal sd_started_ftu_sig : std_logic := '0';
299 signal new_config_sig : std_logic := '0';
300 signal config_started_sig : std_logic := '0';
301 signal config_start_eth_sig : std_logic := '0';
302 signal config_started_eth_sig : std_logic := '0';
303 signal config_ready_eth_sig : std_logic := '0';
304 signal config_started_ack_sig : std_logic := '0';
305 signal ping_ftu_start_sig : std_logic := '0';
306 signal ping_ftu_started_sig : std_logic := '0';
307 signal ping_ftu_ready_sig : std_logic := '0';
308 signal config_start_ftu_sig : std_logic := '0';
309 signal config_started_ftu_sig : std_logic := '0';
310 signal config_ready_ftu_sig : std_logic := '0';
311 signal rates_ftu_start_sig : std_logic := '0';
312 signal rates_ftu_started_sig : std_logic := '0';
313 signal rates_ftu_ready_sig : std_logic := '0';
314 signal fl_busy_sig : std_logic;
315 signal fl_ready_sig : std_logic;
316 signal fl_write_sig : std_logic := '0';
317 signal fl_started_ftu_sig : std_logic := '0';
318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
320 signal ping_ftu_start_ftu_sig : std_logic := '0';
321 signal ping_ftu_started1_sig : std_logic := '0';
322 signal ping_ftu_ready1_sig : std_logic := '0';
323 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
324 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
325 --new or changed stuff
326 signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0');
327 signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0');
328 signal dd_block_start_ftu_sig : std_logic := '0';
329 signal dd_block_start_ack_ftu_sig : std_logic := '0';
330 signal dd_block_ready_ftu_sig : std_logic := '0';
331 signal dd_busy_sig : std_logic;
332 signal dd_write_sig : std_logic := '0';
333 signal dd_started_ftu_sig : std_logic := '0';
334 signal dd_ready_sig : std_logic;
335 signal dd_send_sig : std_logic := '1';
336 signal dd_send_ack_sig : std_logic := '1';
337 signal dd_send_ready_sig : std_logic := '1';
338 --very new stuff
339 SIGNAL ftu_error_send_ack_sig : std_logic := '1';
340 SIGNAL ftu_error_send_ready_sig : std_logic := '1';
341 SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000";
342 SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0');
343 SIGNAL ftu_error_send_sig : std_logic := '0';
344 signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0);
345 signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0);
346 signal trigger_counter_read_sig : std_logic;
347 signal trigger_counter_valid_sig : std_logic;
348
349 signal config_start_cc_sig : std_logic := '0';
350 signal config_started_cc_sig : std_logic := '0';
351 signal config_ready_cc_sig : std_logic := '0';
352
353 signal config_trigger_sig : std_logic;
354 signal config_trigger_done_sig : std_logic;
355
356 signal clk_buf_sig : std_logic;
357 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
358 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
359 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM
360 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM
361 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked
362
363 signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager
364 signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager
365 signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast
366
367 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up
368
369 signal trigger_signal_sig : std_logic := '0';
370 signal TIM_signal_sig : std_logic := '0';
371
372 --signals for FPGA DNA identifier
373 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen
374 signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control
375 signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen
376
377 signal led_sig : std_logic_vector(7 downto 0) := (others => '0');
378
379 signal get_ot_counter_sig : std_logic;
380 signal get_ot_counter_started_sig : std_logic;
381 signal get_ot_counter_ready_sig : std_logic;
382 signal on_time_counter_sig : std_logic_vector(47 downto 0);
383
384 signal get_ts_counter_sig : std_logic;
385 signal get_ts_counter_started_sig : std_logic;
386 signal get_ts_counter_ready_sig : std_logic;
387 signal timestamp_counter_sig : std_logic_vector(47 downto 0);
388
389 signal crate_reset_sig : std_logic;
390 signal crate_reset_ack_sig : std_logic;
391 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0);
392 signal start_run_sig : std_logic;
393 signal start_run_ack_sig : std_logic;
394 signal stop_run_sig : std_logic;
395 signal stop_run_ack_sig : std_logic;
396 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0);
397 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0);
398 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0);
399
400 signal trigger_start_sig : std_logic;
401 signal trigger_stop_sig : std_logic;
402
403-- component FTM_clk_gen
404-- port(
405-- clk : IN STD_LOGIC;
406-- rst : IN STD_LOGIC;
407-- clk_1 : OUT STD_LOGIC;
408-- clk_50 : OUT STD_LOGIC;
409-- clk_250 : OUT STD_LOGIC;
410-- clk_250_ps : OUT STD_LOGIC;
411-- ready : OUT STD_LOGIC
412-- );
413-- end component;
414
415 component FTM_clk_gen_2
416 port(
417 clk : IN STD_LOGIC;
418 rst : IN STD_LOGIC;
419 clk_1 : OUT STD_LOGIC;
420 clk_50 : OUT STD_LOGIC;
421 clk_250 : OUT STD_LOGIC;
422 clk_250_ps : OUT STD_LOGIC;
423 ready : OUT STD_LOGIC
424 );
425 end component;
426
427 component FTM_dna_gen
428 port(
429 clk : IN STD_LOGIC;
430 start : IN STD_LOGIC;
431 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
432 ready : OUT STD_LOGIC
433 );
434 end component;
435
436 component trigger_manager
437 port(
438 --clocks
439 clk_50MHz : in std_logic;
440 clk_250MHz : in std_logic;
441 clk_250MHz_180 : in std_logic;
442 --trigger primitives from FTUs
443 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
444 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
445 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
446 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
447 --external signals
448 ext_trig_1 : in std_logic;
449 ext_trig_2 : in std_logic;
450 ext_veto : in std_logic;
451 FAD_busy_0 : in std_logic; --crate 0
452 FAD_busy_1 : in std_logic; --crate 1
453 FAD_busy_2 : in std_logic; --crate 2
454 FAD_busy_3 : in std_logic; --crate 3
455 --control signals from e.g. main control
456 start_run : in std_logic; --enable trigger output
457 stop_run : in std_logic; --disable trigger output
458 new_config : in std_logic;
459 --settings register (see FTM Firmware Specifications)
460 general_settings : in std_logic_vector(15 downto 0);
461 LP_and_PED_freq : in std_logic_vector(15 downto 0);
462 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
463 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
464 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
465 trigger_delay : in std_logic_vector(15 downto 0);
466 TIM_delay : in std_logic_vector(15 downto 0);
467 dead_time : in std_logic_vector(15 downto 0);
468 coinc_window_phys : in std_logic_vector(15 downto 0);
469 coinc_window_calib : in std_logic_vector(15 downto 0);
470 active_FTU_list_0 : in std_logic_vector(15 downto 0);
471 active_FTU_list_1 : in std_logic_vector(15 downto 0);
472 active_FTU_list_2 : in std_logic_vector(15 downto 0);
473 active_FTU_list_3 : in std_logic_vector(15 downto 0);
474 --control signals or information for other entities
475 trigger_ID_read : in std_logic;
476 trig_cnt_copy_read : in std_logic;
477 trigger_ID_ready : out std_logic;
478 trigger_ID : out std_logic_vector(55 downto 0);
479 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
480 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
481 trigger_active : out std_logic; --phys triggers are enabled/active
482 config_done : out std_logic;
483 LP1_pulse : out std_logic; --send start signal to light pulser 1
484 LP2_pulse : out std_logic; --send start signal to light pulser 2
485 --trigger and time marker output signals to FADs
486 trigger_signal : out std_logic;
487 TIM_signal : out std_logic
488 );
489 end component;
490
491 component Clock_cond_interface is
492 port(
493 clk : IN STD_LOGIC;
494 CLK_Clk_Cond : out STD_LOGIC;
495 LE_Clk_Cond : out STD_LOGIC;
496 DATA_Clk_Cond : out STD_LOGIC;
497 SYNC_Clk_Cond : out STD_LOGIC;
498 LD_Clk_Cond : in STD_LOGIC;
499 TIM_Sel : out STD_LOGIC;
500 cc_R0 : in std_logic_vector (31 downto 0) := (others => '0');
501 cc_R1 : in std_logic_vector (31 downto 0) := (others => '0');
502 cc_R8 : in std_logic_vector (31 downto 0) := (others => '0');
503 cc_R9 : in std_logic_vector (31 downto 0) := (others => '0');
504 cc_R11 : in std_logic_vector (31 downto 0) := (others => '0');
505 cc_R13 : in std_logic_vector (31 downto 0) := (others => '0');
506 cc_R14 : in std_logic_vector (31 downto 0) := (others => '0');
507 cc_R15 : in std_logic_vector (31 downto 0) := (others => '0');
508 start_config : in STD_LOGIC;
509 config_started : out STD_LOGIC;
510 config_done : out STD_LOGIC;
511 timemarker_select: in STD_LOGIC
512 );
513 end component;
514
515 component FTM_central_control
516 port(
517 clk : IN std_logic;
518 clk_ready : in std_logic;
519 clk_scaler : IN std_logic;
520 new_config : IN std_logic;
521 config_started : OUT std_logic := '0';
522 config_started_ack : IN std_logic;
523 config_start_eth : OUT std_logic := '0';
524 config_started_eth : IN std_logic;
525 config_ready_eth : IN std_logic;
526 config_start_ftu : OUT std_logic := '0';
527 config_started_ftu : IN std_logic;
528 config_ready_ftu : IN std_logic;
529 ping_ftu_start : IN std_logic;
530 ping_ftu_started : OUT std_logic := '0';
531 ping_ftu_ready : OUT std_logic := '0';
532 ping_ftu_start_ftu : OUT std_logic := '0';
533 ping_ftu_started_ftu : IN std_logic;
534 ping_ftu_ready_ftu : IN std_logic;
535 rates_ftu : OUT std_logic := '0';
536 rates_started_ftu : IN std_logic;
537 rates_ready_ftu : IN std_logic;
538 prescaling_FTU01 : IN std_logic_vector(7 downto 0);
539 dd_send : OUT std_logic := '0';
540 dd_send_ack : IN std_logic;
541 dd_send_ready : IN std_logic;
542 dd_block_ready_ftu : out std_logic := '0';
543 dd_block_start_ack_ftu : in std_logic;
544 dd_block_start_ftu : out std_logic := '0';
545 config_start_cc : out std_logic := '0';
546 config_started_cc : in std_logic;
547 config_ready_cc : in std_logic;
548 config_trigger : out std_logic;
549 config_trigger_done : in std_logic;
550 dna_start : out std_logic;
551 dna_ready : in std_logic;
552 crate_reset : IN std_logic;
553 crate_reset_ack : OUT std_logic;
554 crate_reset_param : IN std_logic_vector (15 DOWNTO 0);
555 start_run : IN std_logic;
556 start_run_ack : OUT std_logic;
557 stop_run : IN std_logic;
558 stop_run_ack : OUT std_logic;
559 current_cc_state : OUT std_logic_vector (15 DOWNTO 0);
560 start_run_param : IN std_logic_vector (15 DOWNTO 0);
561 start_run_num_events : IN std_logic_vector (31 DOWNTO 0);
562 trigger_start : out std_logic;
563 trigger_stop : out std_logic
564 );
565 end component;
566
567 component FTM_ftu_control
568 port(
569 clk_50MHz : in std_logic;
570 rx_en : out STD_LOGIC;
571 tx_en : out STD_LOGIC;
572 rx_d_0 : in STD_LOGIC;
573 tx_d_0 : out STD_LOGIC;
574 rx_d_1 : in STD_LOGIC;
575 tx_d_1 : out STD_LOGIC;
576 rx_d_2 : in STD_LOGIC;
577 tx_d_2 : out STD_LOGIC;
578 rx_d_3 : in STD_LOGIC;
579 tx_d_3 : out STD_LOGIC;
580 new_config : in std_logic;
581 ping_all : in std_logic;
582 read_rates : in std_logic;
583 read_rates_started : out std_logic := '0';
584 read_rates_done : out std_logic := '0';
585 new_config_started : out std_logic := '0';
586 new_config_done : out std_logic := '0';
587 ping_all_started : out std_logic := '0';
588 ping_all_done : out std_logic := '0';
589 ftu_active_cr0 : in std_logic_vector (15 downto 0);
590 ftu_active_cr1 : in std_logic_vector (15 downto 0);
591 ftu_active_cr2 : in std_logic_vector (15 downto 0);
592 ftu_active_cr3 : in std_logic_vector (15 downto 0);
593 ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0');
594 ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
595 ftu_error_send : out std_logic := '0';
596 ftu_error_send_ack : in std_logic;
597 ftu_error_send_ready : in std_logic;
598 static_RAM_busy : in std_logic;
599 static_RAM_started : in std_logic;
600 static_RAM_ready : in std_logic;
601 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0');
602 read_static_RAM : out std_logic := '0';
603 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0');
604 dynamic_RAM_busy : in std_logic;
605 dynamic_RAM_started : in std_logic;
606 dynamic_RAM_ready : in std_logic;
607 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0');
608 write_dynamic_RAM : out std_logic := '0';
609 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0');
610 FTUlist_RAM_busy : in std_logic;
611 FTUlist_RAM_started : in std_logic;
612 FTUlist_RAM_ready : in std_logic;
613 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0');
614 write_FTUlist_RAM : out std_logic := '0';
615 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0')
616 );
617 end component;
618
619 component FTM_fad_broadcast
620 port(
621 clk_50MHz : in std_logic;
622 rx_en : out STD_LOGIC;
623 tx_en : out STD_LOGIC;
624 rx_d_0 : in STD_LOGIC;
625 tx_d_0 : out STD_LOGIC;
626 rx_d_1 : in STD_LOGIC;
627 tx_d_1 : out STD_LOGIC;
628 rx_d_2 : in STD_LOGIC;
629 tx_d_2 : out STD_LOGIC;
630 rx_d_3 : in STD_LOGIC;
631 tx_d_3 : out STD_LOGIC;
632 enable_ID_sending : in std_logic;
633 TIM_source : in std_logic;
634 LP_settings : in std_logic_vector(3 downto 0);
635 trigger_ID_ready : in std_logic;
636 trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0);
637 trigger_ID_read : out std_logic
638 );
639 end component;
640
641 component ethernet_modul
642 port(
643 wiz_reset : OUT std_logic := '1';
644 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
645 wiz_data : INOUT std_logic_vector (15 DOWNTO 0);
646 wiz_cs : OUT std_logic := '1';
647 wiz_wr : OUT std_logic := '1';
648 wiz_rd : OUT std_logic := '1';
649 wiz_int : IN std_logic ;
650 clk : IN std_logic ;
651 sd_ready : OUT std_logic ;
652 sd_busy : OUT std_logic ;
653 led : OUT std_logic_vector (7 DOWNTO 0);
654 sd_read_ftu : IN std_logic ;
655 sd_started_ftu : OUT std_logic := '0';
656 cc_R0 : OUT std_logic_vector (31 DOWNTO 0);
657 cc_R1 : OUT std_logic_vector (31 DOWNTO 0);
658 cc_R11 : OUT std_logic_vector (31 DOWNTO 0);
659 cc_R13 : OUT std_logic_vector (31 DOWNTO 0);
660 cc_R14 : OUT std_logic_vector (31 DOWNTO 0);
661 cc_R15 : OUT std_logic_vector (31 DOWNTO 0);
662 cc_R8 : OUT std_logic_vector (31 DOWNTO 0);
663 cc_R9 : OUT std_logic_vector (31 DOWNTO 0);
664 coin_n_c : OUT std_logic_vector (15 DOWNTO 0);
665 coin_n_p : OUT std_logic_vector (15 DOWNTO 0);
666 dead_time : OUT std_logic_vector (15 DOWNTO 0);
667 general_settings : OUT std_logic_vector (15 DOWNTO 0);
668 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0);
669 lp1_delay : OUT std_logic_vector (15 DOWNTO 0);
670 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0);
671 lp2_delay : OUT std_logic_vector (15 DOWNTO 0);
672 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0);
673 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0);
674 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0);
675 trigger_delay : OUT std_logic_vector (15 DOWNTO 0);
676 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
677 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
678 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0);
679 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0);
680 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0);
681 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0);
682 new_config : OUT std_logic := '0';
683 config_started : IN std_logic ;
684 config_start_eth : IN std_logic ;
685 config_started_eth : OUT std_logic := '0';
686 config_ready_eth : OUT std_logic := '0';
687 config_started_ack : OUT std_logic := '0';
688 fl_busy : OUT std_logic ;
689 fl_ready : OUT std_logic ;
690 fl_write_ftu : IN std_logic ;
691 fl_started_ftu : OUT std_logic := '0';
692 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
693 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0');
694 ping_ftu_start : OUT std_logic := '0';
695 ping_ftu_started : IN std_logic ;
696 ping_ftu_ready : IN std_logic ;
697 dd_write_ftu : IN std_logic ;
698 dd_started_ftu : OUT std_logic := '0';
699 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0);
700 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0);
701 dd_busy : OUT std_logic ;
702 dd_ready : OUT std_logic ;
703 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
704 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
705 --new stuff
706 dd_block_ready_ftu : IN std_logic;
707 dd_block_start_ack_ftu : OUT std_logic := '0';
708 dd_block_start_ftu : IN std_logic;
709 dd_send : IN std_logic;
710 dd_send_ack : OUT std_logic := '1';
711 dd_send_ready : OUT std_logic := '1';
712 --very new stuff
713 ftu_error_calls : IN std_logic_vector (15 DOWNTO 0);
714 ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1
715 ftu_error_send : IN std_logic;
716 ftu_error_send_ack : OUT std_logic := '1';
717 ftu_error_send_ready : OUT std_logic := '1';
718 prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
719 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0');
720 trigger_counter_read : OUT std_logic := '0';
721 trigger_counter_valid : IN std_logic;
722 --newest stuff
723 board_id : IN std_logic_vector (63 DOWNTO 0);
724 get_ts_counter : OUT std_logic := '0';
725 get_ts_counter_ready : IN std_logic;
726 get_ts_counter_started : IN std_logic;
727 timestamp_counter : IN std_logic_vector (47 DOWNTO 0);
728 get_ot_counter : OUT std_logic := '0';
729 get_ot_counter_ready : IN std_logic;
730 get_ot_counter_started : IN std_logic;
731 on_time_counter : IN std_logic_vector (47 DOWNTO 0);
732 temp_sensor_array : IN sensor_array_type;
733 temp_sensor_ready : IN std_logic;
734 crate_reset : OUT std_logic := '0';
735 crate_reset_ack : IN std_logic;
736 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
737 start_run : OUT std_logic := '0';
738 start_run_ack : IN std_logic;
739 stop_run : OUT std_logic := '0';
740 stop_run_ack : IN std_logic;
741 current_cc_state : IN std_logic_vector (15 DOWNTO 0);
742 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
743 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0')
744 );
745 end component;
746
747 component counter_dummy IS
748 PORT(
749 clk : IN std_logic;
750 get_counter : IN std_logic;
751 get_counter_started : OUT std_logic := '0';
752 get_counter_ready : OUT std_logic := '0';
753 counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0')
754 );
755 end component;
756
757begin
758
759-- -- IBUFG: Single-ended global clock input buffer
760-- -- Spartan-3A
761-- -- Xilinx HDL Language Template, version 11.4
762
763-- IBUFG_inst : IBUFG
764-- generic map (
765-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
766-- -- "0"-"16"
767-- IOSTANDARD => "DEFAULT")
768-- port map (
769-- O => clk_buf_sig, -- Clock buffer output
770-- I => clk -- Clock buffer input (connect directly to top-level port)
771-- );
772
773-- Inst_FTM_clk_gen : FTM_clk_gen
774-- port map(
775-- clk => clk_buf_sig,
776-- rst => reset_sig,
777-- clk_1 => clk_1M_sig,
778-- clk_50 => clk_50M_sig,
779-- clk_250 => clk_250M_sig,
780-- clk_250_ps => clk_250M_ps_sig,
781-- ready => clk_ready_sig
782-- );
783
784 Inst_FTM_clk_gen_2 : FTM_clk_gen_2
785 port map(
786 clk => clk,
787 rst => reset_sig,
788 clk_1 => clk_1M_sig,
789 clk_50 => clk_50M_sig,
790 clk_250 => clk_250M_sig,
791 clk_250_ps => clk_250M_ps_sig,
792 ready => clk_ready_sig
793 );
794
795 Inst_FTM_dna_gen : FTM_dna_gen
796 port map(
797 clk => clk_50M_sig,
798 start => dna_start_sig,
799 dna => dna_sig,
800 ready => dna_ready_sig
801 );
802
803 --differential output buffer for trigger signal
804 OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
805 port map(
806 O => TRG_p,
807 OB => TRG_n,
808 I => trigger_signal_sig
809 );
810
811 --differential output buffer for trigger signal
812 OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
813 port map(
814 O => TIM_Run_p,
815 OB => TIM_Run_n,
816 I => TIM_signal_sig
817 );
818
819 Inst_trigger_manager : trigger_manager
820 port map(
821 --clocks
822 clk_50MHz => clk_50M_sig,
823 clk_250MHz => clk_250M_sig,
824 clk_250MHz_180 => clk_250M_ps_sig,
825 --trigger primitives from FTUs
826 trig_prim_0 => Trig_Prim_A, --crate 0
827 trig_prim_1 => Trig_Prim_B, --crate 1
828 trig_prim_2 => Trig_Prim_C, --crate 2
829 trig_prim_3 => Trig_Prim_D, --crate 3
830 --external signals
831 ext_trig_1 => ext_Trig(1),
832 ext_trig_2 => ext_Trig(2),
833 ext_veto => Veto,
834 FAD_busy_0 => Busy0, --crate 0
835 FAD_busy_1 => Busy1, --crate 1
836 FAD_busy_2 => Busy2, --crate 2
837 FAD_busy_3 => Busy3, --crate 3
838 --control signals from e.g. main control
839 start_run => trigger_start_sig, --enable trigger output
840 stop_run => trigger_stop_sig, --disable trigger output
841 new_config => config_trigger_sig,
842 --settings register (see FTM Firmware Specifications)
843 general_settings => general_settings_sig,
844 LP_and_PED_freq => lp_pt_freq_sig,
845 LP1_LP2_PED_ratio => lp_pt_ratio_sig,
846 maj_coinc_n_phys => coin_n_p_sig,
847 maj_coinc_n_calib => coin_n_c_sig,
848 trigger_delay => trigger_delay_sig,
849 TIM_delay => timemarker_delay_sig,
850 dead_time => dead_time_sig,
851 coinc_window_phys => coin_win_p_sig,
852 coinc_window_calib => coin_win_c_sig,
853 active_FTU_list_0 => ftu_active_cr0_sig,
854 active_FTU_list_1 => ftu_active_cr1_sig,
855 active_FTU_list_2 => ftu_active_cr2_sig,
856 active_FTU_list_3 => ftu_active_cr3_sig,
857 --control signals or information for other entities
858 trigger_ID_read => trigger_ID_read_sig,
859 trig_cnt_copy_read => trigger_counter_read_sig,
860 trigger_ID_ready => trigger_ID_ready_sig,
861 trigger_ID => trigger_ID_sig,
862 trig_cnt_copy => trigger_counter_sig, --counter reading
863 trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid
864 trigger_active => open, --phys triggers are enabled/active
865 config_done => config_trigger_done_sig,
866 LP1_pulse => open, --send start signal to light pulser 1
867 LP2_pulse => open, --send start signal to light pulser 2
868 --trigger and time marker output signals to FADs
869 trigger_signal => trigger_signal_sig,
870 TIM_signal => TIM_signal_sig
871 );
872
873 Inst_Clock_cond_interface : Clock_cond_interface
874 port map(
875 clk => clk_50M_sig,
876 CLK_Clk_Cond => CLK_Clk_Cond,
877 LE_Clk_Cond => LE_Clk_Cond,
878 DATA_Clk_Cond => DATA_Clk_Cond,
879 SYNC_Clk_Cond => SYNC_Clk_Cond,
880 LD_Clk_Cond => LD_Clk_Cond,
881 TIM_Sel => TIM_Sel,
882 cc_R0 => cc_R0_sig,
883 cc_R1 => cc_R1_sig,
884 cc_R8 => cc_R8_sig,
885 cc_R9 => cc_R9_sig,
886 cc_R11 => cc_R11_sig,
887 cc_R13 => cc_R13_sig,
888 cc_R14 => cc_R14_sig,
889 cc_R15 => cc_R15_sig,
890 start_config => config_start_cc_sig,
891 config_started => config_started_cc_sig,
892 config_done => config_ready_cc_sig,
893 timemarker_select => general_settings_sig(0)
894 );
895
896 Inst_FTM_central_control : FTM_central_control
897 port map(
898 clk => clk_50M_sig,
899 clk_ready => clk_ready_sig,
900 clk_scaler => clk_1M_sig,
901 new_config => new_config_sig,
902 config_started => config_started_sig,
903 config_started_ack => config_started_ack_sig,
904 config_start_eth => config_start_eth_sig,
905 config_started_eth => config_started_eth_sig,
906 config_ready_eth => config_ready_eth_sig,
907 config_start_ftu => config_start_ftu_sig,
908 config_started_ftu => config_started_ftu_sig,
909 config_ready_ftu => config_ready_ftu_sig,
910 ping_ftu_start => ping_ftu_start_sig,
911 ping_ftu_started => ping_ftu_started_sig,
912 ping_ftu_ready => ping_ftu_ready_sig,
913 ping_ftu_start_ftu => ping_ftu_start_ftu_sig,
914 ping_ftu_started_ftu => ping_ftu_started1_sig,
915 ping_ftu_ready_ftu => ping_ftu_ready1_sig,
916 rates_ftu => rates_ftu_start_sig,
917 rates_started_ftu => rates_ftu_started_sig,
918 rates_ready_ftu => rates_ftu_ready_sig,
919 prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0),
920 dd_send => dd_send_sig,
921 dd_send_ack => dd_send_ack_sig,
922 dd_send_ready => dd_send_ready_sig,
923 dd_block_ready_ftu => dd_block_ready_ftu_sig,
924 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
925 dd_block_start_ftu => dd_block_start_ftu_sig,
926 config_start_cc => config_start_cc_sig,
927 config_started_cc => config_started_cc_sig,
928 config_ready_cc => config_ready_cc_sig,
929 config_trigger => config_trigger_sig,
930 config_trigger_done => config_trigger_done_sig,
931 dna_start => dna_start_sig,
932 dna_ready => dna_ready_sig,
933 crate_reset => crate_reset_sig,
934 crate_reset_ack => crate_reset_ack_sig,
935 crate_reset_param => crate_reset_param_sig,
936 start_run => start_run_sig,
937 start_run_ack => start_run_ack_sig,
938 stop_run => stop_run_sig,
939 stop_run_ack => stop_run_ack_sig,
940 current_cc_state => current_cc_state_sig,
941 start_run_param => start_run_param_sig,
942 start_run_num_events => start_run_num_events_sig,
943 trigger_start => trigger_start_sig,
944 trigger_stop => trigger_stop_sig
945 );
946
947 Inst_FTM_ftu_control : FTM_ftu_control
948 port map(
949 clk_50MHz => clk_50M_sig,
950 rx_en => Bus1_Rx_En,
951 tx_en => Bus1_Tx_En,
952 rx_d_0 => Bus1_RxD_0,
953 tx_d_0 => Bus1_TxD_0,
954 rx_d_1 => Bus1_RxD_1,
955 tx_d_1 => Bus1_TxD_1,
956 rx_d_2 => Bus1_RxD_2,
957 tx_d_2 => Bus1_TxD_2,
958 rx_d_3 => Bus1_RxD_3,
959 tx_d_3 => Bus1_TxD_3,
960 new_config => config_start_ftu_sig,
961 ping_all => ping_ftu_start_ftu_sig,
962 read_rates => rates_ftu_start_sig,
963 read_rates_started => rates_ftu_started_sig,
964 read_rates_done => rates_ftu_ready_sig,
965 new_config_started => config_started_ftu_sig,
966 new_config_done => config_ready_ftu_sig,
967 ping_all_started => ping_ftu_started1_sig,
968 ping_all_done => ping_ftu_ready1_sig,
969 ftu_active_cr0 => ftu_active_cr0_sig,
970 ftu_active_cr1 => ftu_active_cr1_sig,
971 ftu_active_cr2 => ftu_active_cr2_sig,
972 ftu_active_cr3 => ftu_active_cr3_sig,
973 ftu_error_calls => ftu_error_calls_sig,
974 ftu_error_data => ftu_error_data_sig,
975 ftu_error_send => ftu_error_send_sig,
976 ftu_error_send_ack => ftu_error_send_ack_sig,
977 ftu_error_send_ready=> ftu_error_send_ready_sig,
978 static_RAM_busy => sd_busy_sig,
979 static_RAM_started => sd_started_ftu_sig,
980 static_RAM_ready => sd_ready_sig,
981 data_static_RAM => sd_data_out_ftu_sig,
982 read_static_RAM => sd_read_ftu_sig,
983 addr_static_RAM => sd_addr_ftu_sig,
984 dynamic_RAM_busy => dd_busy_sig,
985 dynamic_RAM_started => dd_started_ftu_sig,
986 dynamic_RAM_ready => dd_ready_sig,
987 data_dynamic_RAM => dd_data_sig,
988 write_dynamic_RAM => dd_write_sig,
989 addr_dynamic_RAM => dd_addr_sig,
990 FTUlist_RAM_busy => fl_busy_sig,
991 FTUlist_RAM_started => fl_started_ftu_sig,
992 FTUlist_RAM_ready => fl_ready_sig,
993 data_FTUlist_RAM => fl_data_sig,
994 write_FTUlist_RAM => fl_write_sig,
995 addr_FTUlist_RAM => fl_addr_sig
996 );
997
998 Inst_FTM_fad_broadcast : FTM_fad_broadcast
999 port map(
1000 clk_50MHz => clk_50M_sig,
1001 rx_en => Bus2_Rx_En,
1002 tx_en => Bus2_Tx_En,
1003 rx_d_0 => Bus2_RxD_0,
1004 tx_d_0 => Bus2_TxD_0,
1005 rx_d_1 => Bus2_RxD_1,
1006 tx_d_1 => Bus2_TxD_1,
1007 rx_d_2 => Bus2_RxD_2,
1008 tx_d_2 => Bus2_TxD_2,
1009 rx_d_3 => Bus2_RxD_3,
1010 tx_d_3 => Bus2_TxD_3,
1011 enable_ID_sending => '1',
1012 TIM_source => general_settings_sig(0),
1013 LP_settings => "0000",
1014 trigger_ID_ready => trigger_ID_ready_sig,
1015 trigger_ID => trigger_ID_sig,
1016 trigger_ID_read => trigger_ID_read_sig
1017 );
1018
1019 Inst_ethernet_modul : ethernet_modul
1020 port map(
1021 wiz_reset => W_RES,
1022 wiz_addr => W_A,
1023 wiz_data => W_D,
1024 wiz_cs => W_CS,
1025 wiz_wr => W_WR,
1026 wiz_rd => W_RD,
1027 wiz_int => W_INT,
1028 clk => clk_50M_sig,
1029 sd_ready => sd_ready_sig,
1030 sd_busy => sd_busy_sig,
1031 led => led_sig,
1032 sd_read_ftu => sd_read_ftu_sig,
1033 sd_started_ftu => sd_started_ftu_sig,
1034 cc_R0 => cc_R0_sig,
1035 cc_R1 => cc_R1_sig,
1036 cc_R11 => cc_R11_sig,
1037 cc_R13 => cc_R13_sig,
1038 cc_R14 => cc_R14_sig,
1039 cc_R15 => cc_R15_sig,
1040 cc_R8 => cc_R8_sig,
1041 cc_R9 => cc_R9_sig,
1042 coin_n_c => coin_n_c_sig,
1043 coin_n_p => coin_n_p_sig,
1044 dead_time => dead_time_sig,
1045 general_settings => general_settings_sig,
1046 lp1_amplitude => lp1_amplitude_sig,
1047 lp1_delay => lp1_delay_sig,
1048 lp2_amplitude => lp2_amplitude_sig,
1049 lp2_delay => lp2_delay_sig,
1050 lp_pt_freq => lp_pt_freq_sig,
1051 lp_pt_ratio => lp_pt_ratio_sig,
1052 timemarker_delay => timemarker_delay_sig,
1053 trigger_delay => trigger_delay_sig,
1054 sd_addr_ftu => sd_addr_ftu_sig,
1055 sd_data_out_ftu => sd_data_out_ftu_sig,
1056 ftu_active_cr0 => ftu_active_cr0_sig,
1057 ftu_active_cr1 => ftu_active_cr1_sig,
1058 ftu_active_cr2 => ftu_active_cr2_sig,
1059 ftu_active_cr3 => ftu_active_cr3_sig,
1060 new_config => new_config_sig,
1061 config_started => config_started_sig,
1062 config_start_eth => config_start_eth_sig,
1063 config_started_eth => config_started_eth_sig,
1064 config_ready_eth => config_ready_eth_sig,
1065 config_started_ack => config_started_ack_sig,
1066 fl_busy => fl_busy_sig,
1067 fl_ready => fl_ready_sig,
1068 fl_write_ftu => fl_write_sig,
1069 fl_started_ftu => fl_started_ftu_sig,
1070 fl_addr_ftu => fl_addr_sig,
1071 fl_data_in_ftu => fl_data_sig,
1072 ping_ftu_start => ping_ftu_start_sig,
1073 ping_ftu_started => ping_ftu_started_sig,
1074 ping_ftu_ready => ping_ftu_ready_sig,
1075 dd_write_ftu => dd_write_sig,
1076 dd_started_ftu => dd_started_ftu_sig,
1077 dd_data_in_ftu => dd_data_sig,
1078 dd_addr_ftu => dd_addr_sig,
1079 dd_busy => dd_busy_sig,
1080 dd_ready => dd_ready_sig,
1081 coin_win_c => coin_win_c_sig,
1082 coin_win_p => coin_win_p_sig,
1083 --new stuff
1084 dd_block_ready_ftu => dd_block_ready_ftu_sig,
1085 dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig,
1086 dd_block_start_ftu => dd_block_start_ftu_sig,
1087 dd_send => dd_send_sig,
1088 dd_send_ack => dd_send_ack_sig,
1089 dd_send_ready => dd_send_ready_sig,
1090 --very new stuff
1091 ftu_error_calls => ftu_error_calls_sig,
1092 ftu_error_data => ftu_error_data_sig,
1093 ftu_error_send => ftu_error_send_sig,
1094 ftu_error_send_ack => ftu_error_send_ack_sig,
1095 ftu_error_send_ready => ftu_error_send_ready_sig,
1096 prescaling_FTU01 => prescaling_FTU01_sig,
1097 trigger_counter => trigger_counter_sig,
1098 trigger_counter_read => trigger_counter_read_sig,
1099 trigger_counter_valid => trigger_counter_valid_sig,
1100 --newest stuff
1101 board_id => dna_sig,
1102 get_ts_counter => get_ts_counter_sig,
1103 get_ts_counter_ready => get_ts_counter_ready_sig,
1104 get_ts_counter_started => get_ts_counter_started_sig,
1105 timestamp_counter => timestamp_counter_sig,
1106 get_ot_counter => get_ot_counter_sig,
1107 get_ot_counter_ready => get_ot_counter_ready_sig,
1108 get_ot_counter_started => get_ot_counter_started_sig,
1109 on_time_counter => on_time_counter_sig,
1110 temp_sensor_array => (35, 45, 55, 65),
1111 temp_sensor_ready => '1',
1112 crate_reset => crate_reset_sig,
1113 crate_reset_ack => crate_reset_ack_sig,
1114 crate_reset_param => crate_reset_param_sig,
1115 start_run => start_run_sig,
1116 start_run_ack => start_run_ack_sig,
1117 stop_run => stop_run_sig,
1118 stop_run_ack => stop_run_ack_sig,
1119 current_cc_state => current_cc_state_sig,
1120 start_run_param => start_run_param_sig,
1121 start_run_num_events => start_run_num_events_sig
1122 );
1123
1124 Inst_counter_dummy_ts : counter_dummy
1125 port map(
1126 clk => clk_50M_sig,
1127 get_counter => get_ts_counter_sig,
1128 get_counter_started => get_ts_counter_started_sig,
1129 get_counter_ready => get_ts_counter_ready_sig,
1130 counter => timestamp_counter_sig
1131 );
1132
1133 Inst_counter_dummy_ot : counter_dummy
1134 port map(
1135 clk => clk_50M_sig,
1136 get_counter => get_ot_counter_sig,
1137 get_counter_started => get_ot_counter_started_sig,
1138 get_counter_ready => get_ot_counter_ready_sig,
1139 counter => on_time_counter_sig
1140 );
1141
1142 LED_red <= led_sig(3 downto 0);
1143 LED_ye <= led_sig(5 downto 4);
1144 LED_gn <= led_sig(7 downto 6);
1145
1146end Behavioral;
1147
1148
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