Changeset 10441 for firmware/FTM/FTM_top.vhd
- Timestamp:
- 04/21/11 11:17:11 (13 years ago)
- File:
-
- 1 edited
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firmware/FTM/FTM_top.vhd
r10418 r10441 376 376 377 377 signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); 378 379 signal get_ot_counter_sig : std_logic; 380 signal get_ot_counter_started_sig : std_logic; 381 signal get_ot_counter_ready_sig : std_logic; 382 signal on_time_counter_sig : std_logic_vector(47 downto 0); 383 384 signal get_ts_counter_sig : std_logic; 385 signal get_ts_counter_started_sig : std_logic; 386 signal get_ts_counter_ready_sig : std_logic; 387 signal timestamp_counter_sig : std_logic_vector(47 downto 0); 388 389 signal crate_reset_sig : std_logic; 390 signal crate_reset_ack_sig : std_logic; 391 signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0); 392 signal start_run_sig : std_logic; 393 signal start_run_ack_sig : std_logic; 394 signal stop_run_sig : std_logic; 395 signal stop_run_ack_sig : std_logic; 396 signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0); 397 signal start_run_param_sig : std_logic_vector (15 DOWNTO 0); 398 signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0); 399 400 signal trigger_start_sig : std_logic; 401 signal trigger_stop_sig : std_logic; 378 402 379 403 -- component FTM_clk_gen … … 525 549 config_trigger_done : in std_logic; 526 550 dna_start : out std_logic; 527 dna_ready : in std_logic 551 dna_ready : in std_logic; 552 crate_reset : IN std_logic; 553 crate_reset_ack : OUT std_logic; 554 crate_reset_param : IN std_logic_vector (15 DOWNTO 0); 555 start_run : IN std_logic; 556 start_run_ack : OUT std_logic; 557 stop_run : IN std_logic; 558 stop_run_ack : OUT std_logic; 559 current_cc_state : OUT std_logic_vector (15 DOWNTO 0); 560 start_run_param : IN std_logic_vector (15 DOWNTO 0); 561 start_run_num_events : IN std_logic_vector (31 DOWNTO 0); 562 trigger_start : out std_logic; 563 trigger_stop : out std_logic 528 564 ); 529 565 end component; … … 683 719 trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); 684 720 trigger_counter_read : OUT std_logic := '0'; 685 trigger_counter_valid : IN std_logic 721 trigger_counter_valid : IN std_logic; 722 --newest stuff 723 board_id : IN std_logic_vector (63 DOWNTO 0); 724 get_ts_counter : OUT std_logic := '0'; 725 get_ts_counter_ready : IN std_logic; 726 get_ts_counter_started : IN std_logic; 727 timestamp_counter : IN std_logic_vector (47 DOWNTO 0); 728 get_ot_counter : OUT std_logic := '0'; 729 get_ot_counter_ready : IN std_logic; 730 get_ot_counter_started : IN std_logic; 731 on_time_counter : IN std_logic_vector (47 DOWNTO 0); 732 temp_sensor_array : IN sensor_array_type; 733 temp_sensor_ready : IN std_logic; 734 crate_reset : OUT std_logic := '0'; 735 crate_reset_ack : IN std_logic; 736 crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 737 start_run : OUT std_logic := '0'; 738 start_run_ack : IN std_logic; 739 stop_run : OUT std_logic := '0'; 740 stop_run_ack : IN std_logic; 741 current_cc_state : IN std_logic_vector (15 DOWNTO 0); 742 start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 743 start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0') 686 744 ); 687 745 end component; 688 746 747 component counter_dummy IS 748 PORT( 749 clk : IN std_logic; 750 get_counter : IN std_logic; 751 get_counter_started : OUT std_logic := '0'; 752 get_counter_ready : OUT std_logic := '0'; 753 counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') 754 ); 755 end component; 756 689 757 begin 690 758 … … 769 837 FAD_busy_3 => Busy3, --crate 3 770 838 --control signals from e.g. main control 771 start_run => '1', --enable trigger output772 stop_run => '0', --disable trigger output839 start_run => trigger_start_sig, --enable trigger output 840 stop_run => trigger_stop_sig, --disable trigger output 773 841 new_config => config_trigger_sig, 774 842 --settings register (see FTM Firmware Specifications) … … 862 930 config_trigger_done => config_trigger_done_sig, 863 931 dna_start => dna_start_sig, 864 dna_ready => dna_ready_sig 932 dna_ready => dna_ready_sig, 933 crate_reset => crate_reset_sig, 934 crate_reset_ack => crate_reset_ack_sig, 935 crate_reset_param => crate_reset_param_sig, 936 start_run => start_run_sig, 937 start_run_ack => start_run_ack_sig, 938 stop_run => stop_run_sig, 939 stop_run_ack => stop_run_ack_sig, 940 current_cc_state => current_cc_state_sig, 941 start_run_param => start_run_param_sig, 942 start_run_num_events => start_run_num_events_sig, 943 trigger_start => trigger_start_sig, 944 trigger_stop => trigger_stop_sig 865 945 ); 866 946 … … 1017 1097 trigger_counter => trigger_counter_sig, 1018 1098 trigger_counter_read => trigger_counter_read_sig, 1019 trigger_counter_valid => trigger_counter_valid_sig 1020 ); 1021 1099 trigger_counter_valid => trigger_counter_valid_sig, 1100 --newest stuff 1101 board_id => dna_sig, 1102 get_ts_counter => get_ts_counter_sig, 1103 get_ts_counter_ready => get_ts_counter_ready_sig, 1104 get_ts_counter_started => get_ts_counter_started_sig, 1105 timestamp_counter => timestamp_counter_sig, 1106 get_ot_counter => get_ot_counter_sig, 1107 get_ot_counter_ready => get_ot_counter_ready_sig, 1108 get_ot_counter_started => get_ot_counter_started_sig, 1109 on_time_counter => on_time_counter_sig, 1110 temp_sensor_array => (35, 45, 55, 65), 1111 temp_sensor_ready => '1', 1112 crate_reset => crate_reset_sig, 1113 crate_reset_ack => crate_reset_ack_sig, 1114 crate_reset_param => crate_reset_param_sig, 1115 start_run => start_run_sig, 1116 start_run_ack => start_run_ack_sig, 1117 stop_run => stop_run_sig, 1118 stop_run_ack => stop_run_ack_sig, 1119 current_cc_state => current_cc_state_sig, 1120 start_run_param => start_run_param_sig, 1121 start_run_num_events => start_run_num_events_sig 1122 ); 1123 1124 Inst_counter_dummy_ts : counter_dummy 1125 port map( 1126 clk => clk_50M_sig, 1127 get_counter => get_ts_counter_sig, 1128 get_counter_started => get_ts_counter_started_sig, 1129 get_counter_ready => get_ts_counter_ready_sig, 1130 counter => timestamp_counter_sig 1131 ); 1132 1133 Inst_counter_dummy_ot : counter_dummy 1134 port map( 1135 clk => clk_50M_sig, 1136 get_counter => get_ot_counter_sig, 1137 get_counter_started => get_ot_counter_started_sig, 1138 get_counter_ready => get_ot_counter_ready_sig, 1139 counter => on_time_counter_sig 1140 ); 1141 1022 1142 LED_red <= led_sig(3 downto 0); 1023 1143 LED_ye <= led_sig(5 downto 4);
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