Changeset 10037 for firmware/FTU
- Timestamp:
- 10/25/10 15:29:13 (14 years ago)
- Location:
- firmware/FTU
- Files:
-
- 19 added
- 10 edited
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FTU_control.vhd (modified) (21 diffs)
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FTU_top.vhd (modified) (18 diffs)
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FTU_top_tb.vhd (modified) (3 diffs)
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clock/FTU_clk_gen.vhd (modified) (3 diffs)
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counter/FTU_rate_counter.vhd (modified) (7 diffs)
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ftu_board.ucf (modified) (1 diff)
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ftu_definitions.vhd (modified) (3 diffs)
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ram64 (added)
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ram64/FTU_dual_port_ram64.asy (added)
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ram64/FTU_dual_port_ram64.gise (added)
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ram64/FTU_dual_port_ram64.ise (added)
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ram64/FTU_dual_port_ram64.ngc (added)
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ram64/FTU_dual_port_ram64.sym (added)
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ram64/FTU_dual_port_ram64.v (added)
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ram64/FTU_dual_port_ram64.veo (added)
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ram64/FTU_dual_port_ram64.vhd (added)
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ram64/FTU_dual_port_ram64.vho (added)
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ram64/FTU_dual_port_ram64.xco (added)
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ram64/FTU_dual_port_ram64.xise (added)
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ram64/FTU_dual_port_ram64_flist.txt (added)
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ram64/FTU_dual_port_ram64_readme.txt (added)
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ram64/FTU_dual_port_ram64_xdb (added)
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ram64/FTU_dual_port_ram64_xdb/tmp (added)
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ram64/FTU_dual_port_ram64_xmdf.tcl (added)
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ram64/_xmsgs (added)
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ram64/blk_mem_gen_ds512.pdf (added)
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rs485/FTU_rs485_control.vhd (modified) (12 diffs)
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rs485/FTU_rs485_interface.vhd (modified) (2 diffs)
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rs485/FTU_rs485_interpreter.vhd (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTU/FTU_control.vhd
r10009 r10037 15 15 -- Revision: 16 16 -- Revision 0.01 - File Created 17 -- Revision 0.02 - change-over to 64 byte RAM, 19.10.2010, Q. Weitzel 17 18 -- Additional Comments: 18 19 -- … … 62 63 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 63 64 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 64 ram_ada : OUT STD_LOGIC_VECTOR( 4downto 0);65 ram_adb : OUT STD_LOGIC_VECTOR( 3downto 0);65 ram_ada : OUT STD_LOGIC_VECTOR(5 downto 0); 66 ram_adb : OUT STD_LOGIC_VECTOR(4 downto 0); 66 67 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 67 68 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); 68 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); 69 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; 69 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module 70 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module 70 71 rates_ready : OUT std_logic := '0'; -- to RS485 module 71 72 DACs_ready : OUT std_logic := '0'; -- to RS485 module … … 83 84 architecture Behavioral of FTU_control is 84 85 86 signal new_rates_sr : std_logic_vector(1 downto 0) := (others => '0'); 87 85 88 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up 86 89 … … 103 106 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A 104 107 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B 105 signal ram_ada_sig : STD_LOGIC_VECTOR( 4downto 0) := (others => '0'); --RAM port A address106 signal ram_adb_sig : STD_LOGIC_VECTOR( 3downto 0) := (others => '0'); --RAM port B address108 signal ram_ada_sig : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); --RAM port A address 109 signal ram_adb_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port B address 107 110 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A 108 111 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B … … 112 115 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0; 113 116 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0; 114 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0; --includes overflow register117 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER*RAM_CEF + 2) := 0; --includes overflow register 115 118 116 119 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0; … … 123 126 signal new_prescaling_in_RAM : STD_LOGIC := '0'; 124 127 128 signal ram_buffer_sig : STD_LOGIC_VECTOR(29 downto 0) := (others => '0'); 129 125 130 type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING, 126 131 CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER, … … 172 177 end if; 173 178 FTU_control_State <= INIT_RAM; 174 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO )) then -- default counter values179 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) then -- default counter values 175 180 ram_dia_sig <= (others => '0'); 176 181 FTU_control_State <= INIT_RAM; 177 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs178 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then182 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs 183 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then 179 184 if (ram_ada_cntr mod 2 = 0) then 180 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO )) / 2),16)(7 downto 0);185 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(7 downto 0); 181 186 else 182 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO )) / 2),16)(15 downto 8);187 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(15 downto 8); 183 188 end if; 184 189 else 185 190 if (ram_ada_cntr mod 2 = 0) then 186 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO )) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);191 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0); 187 192 else 188 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO )) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);193 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8); 189 194 end if; 190 195 end if; 191 196 FTU_control_State <= INIT_RAM; 192 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling197 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling 193 198 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8); 194 199 FTU_control_State <= INIT_RAM; 195 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register200 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register 196 201 ram_dia_sig <= (others => '0'); 197 202 FTU_control_State <= INIT_RAM; 198 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum203 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default CRC errors 199 204 ram_dia_sig <= (others => '0'); 200 205 FTU_control_State <= INIT_RAM; 201 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell206 elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then -- empty RAM cells 202 207 ram_dia_sig <= (others => '0'); 203 208 FTU_control_State <= INIT_RAM; … … 224 229 if (new_DACs_in_RAM = '1') then 225 230 ram_enb_sig <= '1'; 226 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER ), RAM_ADDR_WIDTH_B);231 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF), RAM_ADDR_WIDTH_B); 227 232 FTU_control_State <= CONFIG_DAC; 228 233 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then … … 232 237 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then 233 238 ram_ena_sig <= '1'; 234 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);239 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 235 240 FTU_control_State <= CONFIG_COUNTER; 236 241 else -- nothing to be updated, check new commands from RS485 … … 249 254 read_rates = '0' and read_DACs = '1') then 250 255 ram_enb_sig <= '1'; 251 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER , RAM_ADDR_WIDTH_B);256 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF, RAM_ADDR_WIDTH_B); 252 257 FTU_control_State <= READOUT_DAC; 253 258 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and … … 259 264 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then 260 265 ram_ena_sig <= '1'; 261 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);266 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 262 267 FTU_control_State <= READOUT_PRESCALING; 263 268 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and … … 317 322 ram_dac_cntr <= ram_dac_cntr + 1; 318 323 if (ram_dac_cntr = 0) then 319 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);324 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 320 325 FTU_control_State <= CONFIG_DAC; 321 326 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 322 327 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 323 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);328 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 324 329 FTU_control_State <= CONFIG_DAC; 325 330 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then 331 dac_array_sig(4) <= 0; 332 dac_array_sig(5) <= 0; 333 dac_array_sig(6) <= 0; 326 334 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); 327 335 ram_adb_sig <= (others => '0'); … … 357 365 new_rates_busy <= '1'; 358 366 ram_counter_cntr <= ram_counter_cntr + 1; 359 if (ram_counter_cntr < NO_OF_COUNTER ) then367 if (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then 360 368 ram_enb_sig <= '1'; 361 369 ram_web_sig <= "1"; 362 370 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B); 363 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16); 371 if (ram_counter_cntr mod 2 = 0) then 372 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(15 downto 0); 373 else 374 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(31 downto 16); 375 end if; 364 376 FTU_control_State <= WRITE_RATES; 365 elsif (ram_counter_cntr = NO_Of_COUNTER ) then377 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then 366 378 ram_dib_sig <= (others => '0'); 367 379 ram_adb_sig <= (others => '0'); … … 369 381 ram_web_sig <= "0"; 370 382 ram_ena_sig <= '1'; 371 ram_wea_sig <= "1"; 372 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);383 ram_wea_sig <= "1"; 384 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A); 373 385 ram_dia_sig <= overflow_array; 374 386 FTU_control_State <= WRITE_RATES; … … 386 398 ram_enb_sig <= '1'; 387 399 ram_web_sig <= "1"; 388 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);400 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B); 389 401 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16); 390 402 FTU_control_State <= WRITE_DAC; … … 392 404 ram_enb_sig <= '1'; 393 405 ram_web_sig <= "1"; 394 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);406 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B); 395 407 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16); 396 408 FTU_control_State <= WRITE_DAC; … … 427 439 ram_ena_sig <= '1'; 428 440 ram_wea_sig <= "1"; 429 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);441 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 430 442 ram_dia_sig <= prescaling_rs485_out; 431 443 else … … 445 457 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); 446 458 FTU_control_State <= READOUT_RATES; 447 elsif (ram_counter_cntr < NO_OF_COUNTER) then459 elsif (ram_counter_cntr < 3) then 448 460 ram_ena_sig <= '1'; 449 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);461 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 450 462 ram_enb_sig <= '1'; 451 463 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); 452 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); 464 if (ram_counter_cntr = 1) then 465 ram_buffer_sig(15 downto 0) <= ram_dob; 466 else 467 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0); 468 end if; 453 469 FTU_control_State <= READOUT_RATES; 454 elsif (ram_counter_cntr = NO_Of_COUNTER) then 455 ram_enb_sig <= '0'; 456 ram_adb_sig <= (others => '0'); 457 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob)); 470 elsif (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then 458 471 ram_ena_sig <= '1'; 459 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 472 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 473 ram_enb_sig <= '1'; 474 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B); 475 if (ram_counter_cntr mod 2 = 1) then 476 ram_buffer_sig(15 downto 0) <= ram_dob; 477 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig)); 478 else 479 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0); 480 end if; 460 481 FTU_control_State <= READOUT_RATES; 461 elsif (ram_counter_cntr = NO_Of_COUNTER + 1) then 482 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then 483 ram_enb_sig <= '0'; 484 ram_adb_sig <= (others => '0'); 485 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0); 486 ram_ena_sig <= '1'; 487 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A); 488 FTU_control_State <= READOUT_RATES; 489 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF + 1) then 490 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig)); 491 ram_buffer_sig <= (others => '0'); 462 492 ram_enb_sig <= '0'; 463 493 ram_adb_sig <= (others => '0'); … … 481 511 if (ram_dac_cntr = 0) then 482 512 ram_enb_sig <= '1'; 483 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);513 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 484 514 FTU_control_State <= READOUT_DAC; 485 515 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 486 516 ram_enb_sig <= '1'; 487 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);517 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 488 518 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 489 519 FTU_control_State <= READOUT_DAC; … … 531 561 if (wait_cntr = 0) then 532 562 ram_ena_sig <= '1'; 533 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A);563 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A); 534 564 FTU_control_State <= READOUT_PRESCALING; 535 565 elsif (wait_cntr = 1) then … … 567 597 end process FTU_control_FSM; 568 598 569 detect_new_rates: process(new_rates, new_rates_busy) 599 --detect_new_rates: process(new_rates, new_rates_busy) 600 --begin 601 --if(new_rates_busy = '1') then 602 --new_rates_sig <= '0'; 603 --elsif rising_edge(new_rates) then 604 --new_rates_sig <= '1'; 605 --end if; 606 --end process detect_new_rates; 607 608 detect_new_rates: process(clk_50MHz) 570 609 begin 571 if(new_rates_busy = '1') then 572 new_rates_sig <= '0'; 573 elsif rising_edge(new_rates) then 574 new_rates_sig <= '1'; 610 if rising_edge(clk_50MHz) then 611 new_rates_sr <= new_rates_sr(new_rates_sr'left - 1 downto 0) & new_rates; 612 if(new_rates_busy = '1') then 613 new_rates_sig <= '0'; 614 else 615 if (new_rates_sr(1 downto 0) = "01") then 616 new_rates_sig <= '1'; 617 end if; 618 end if; 575 619 end if; 576 620 end process detect_new_rates; 577 621 578 622 reset <= reset_sig; 579 623 -
firmware/FTU/FTU_top.vhd
r10009 r10037 16 16 -- Revision 0.01 - File Created 17 17 -- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel 18 -- Revision 0.03 - counters changed from 16 to 30 bit, 19.10.2010, Q. Weitzel 18 19 -- Additional Comments: 19 20 -- … … 87 88 signal patch_D_sig : STD_LOGIC := '0'; 88 89 signal trigger_sig : STD_LOGIC := '0'; 89 90 90 91 --DAC/SPI interface 91 92 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control … … 107 108 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter 108 109 signal new_rates_sig : STD_LOGIC := '0'; 110 111 --attribute clock_signal : string; 112 --attribute clock_signal of new_rates_sig : signal is "no"; 109 113 110 114 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM 115 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider 111 116 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked 112 117 … … 116 121 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0); 117 122 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0); 118 signal ram_ada_sig : STD_LOGIC_VECTOR( 4downto 0);119 signal ram_adb_sig : STD_LOGIC_VECTOR( 3downto 0);123 signal ram_ada_sig : STD_LOGIC_VECTOR(5 downto 0); 124 signal ram_adb_sig : STD_LOGIC_VECTOR(4 downto 0); 120 125 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0); 121 126 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0); … … 135 140 signal enable_array_rs485_out_sig : enable_array_type; 136 141 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0); 137 142 138 143 --signals to RS485 module, all initialized in FTU_control 139 144 signal rates_ready_sig : std_logic; … … 155 160 rst : IN STD_LOGIC; 156 161 clk_50 : OUT STD_LOGIC; 162 clk_1 : OUT STD_LOGIC; 157 163 ready : OUT STD_LOGIC 158 164 ); … … 165 171 trigger : in std_logic; 166 172 prescaling : in std_logic_vector(7 downto 0); 167 counts : out integer range 0 to 2** 16- 1;173 counts : out integer range 0 to 2**30 - 1; 168 174 overflow : out std_logic; 169 175 new_rate : out std_logic … … 200 206 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0); 201 207 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0); 202 ram_ada : OUT STD_LOGIC_VECTOR( 4downto 0);203 ram_adb : OUT STD_LOGIC_VECTOR( 3downto 0);208 ram_ada : OUT STD_LOGIC_VECTOR(5 downto 0); 209 ram_adb : OUT STD_LOGIC_VECTOR(4 downto 0); 204 210 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0); 205 211 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0); … … 274 280 end component; 275 281 276 component FTU_dual_port_ram 282 component FTU_dual_port_ram64 277 283 port( 278 284 clka : IN std_logic; 279 285 ena : IN std_logic; 280 286 wea : IN std_logic_VECTOR(0 downto 0); 281 addra : IN std_logic_VECTOR( 4downto 0);287 addra : IN std_logic_VECTOR(5 downto 0); 282 288 dina : IN std_logic_VECTOR(7 downto 0); 283 289 douta : OUT std_logic_VECTOR(7 downto 0); … … 285 291 enb : IN std_logic; 286 292 web : IN std_logic_VECTOR(0 downto 0); 287 addrb : IN std_logic_VECTOR( 3downto 0);293 addrb : IN std_logic_VECTOR(4 downto 0); 288 294 dinb : IN std_logic_VECTOR(15 downto 0); 289 295 doutb : OUT std_logic_VECTOR(15 downto 0) … … 293 299 -- Synplicity black box declaration 294 300 attribute syn_black_box : boolean; 295 attribute syn_black_box of FTU_dual_port_ram : component is true;301 attribute syn_black_box of FTU_dual_port_ram64: component is true; 296 302 -- avoid "black box" warning during synthesis 297 303 attribute box_type : string; 298 attribute box_type of FTU_dual_port_ram : component is "black_box";304 attribute box_type of FTU_dual_port_ram64: component is "black_box"; 299 305 300 306 begin … … 360 366 rst => reset_sig, 361 367 clk_50 => clk_50M_sig, 368 clk_1 => clk_1M_sig, 362 369 ready => clk_ready_sig 363 370 ); … … 365 372 Inst_FTU_rate_counter_A : FTU_rate_counter 366 373 port map( 367 clk => clk_ 50M_sig,374 clk => clk_1M_sig, 368 375 cntr_reset => cntr_reset_sig, 369 376 trigger => patch_A_sig, … … 376 383 Inst_FTU_rate_counter_B : FTU_rate_counter 377 384 port map( 378 clk => clk_ 50M_sig,385 clk => clk_1M_sig, 379 386 cntr_reset => cntr_reset_sig, 380 387 trigger => patch_B_sig, … … 387 394 Inst_FTU_rate_counter_C : FTU_rate_counter 388 395 port map( 389 clk => clk_ 50M_sig,396 clk => clk_1M_sig, 390 397 cntr_reset => cntr_reset_sig, 391 398 trigger => patch_C_sig, … … 398 405 Inst_FTU_rate_counter_D : FTU_rate_counter 399 406 port map( 400 clk => clk_ 50M_sig,407 clk => clk_1M_sig, 401 408 cntr_reset => cntr_reset_sig, 402 409 trigger => patch_D_sig, … … 409 416 Inst_FTU_rate_counter_t : FTU_rate_counter 410 417 port map( 411 clk => clk_ 50M_sig,418 clk => clk_1M_sig, 412 419 cntr_reset => cntr_reset_sig, 413 420 trigger => trigger_sig, … … 517 524 ); 518 525 519 Inst_FTU_dual_port_ram : FTU_dual_port_ram526 Inst_FTU_dual_port_ram64 : FTU_dual_port_ram64 520 527 port map( 521 528 clka => clk_50M_sig, -
firmware/FTU/FTU_top_tb.vhd
r10009 r10037 282 282 wait for 150us; 283 283 --------------------------------------------------------------------------- 284 -- test one RS485 command ( 16byte)284 -- test one RS485 command (28 byte) 285 285 --------------------------------------------------------------------------- 286 286 assign_rs485("01000000"); --start delimiter … … 290 290 assign_rs485("11000000"); --FTM address 291 291 wait for 0ns; 292 assign_rs485("00000001"); --FTM firmware ID 293 wait for 0ns; 294 assign_rs485("00000010"); --instruction 295 wait for 0us; 296 assign_rs485("00000001"); --data byte 01 297 wait for 0ns; 298 assign_rs485("00000000"); --data byte 02 299 wait for 0ns; 300 assign_rs485("00000010"); --data byte 03 301 wait for 0ns; 302 assign_rs485("00000000"); --data byte 04 303 wait for 0ns; 304 assign_rs485("00000100"); --data byte 05 305 wait for 0ns; 306 assign_rs485("00000000"); --data byte 06 307 wait for 0ns; 308 assign_rs485("00001000"); --data byte 07 309 wait for 0ns; 310 assign_rs485("00000000"); --data byte 08 311 wait for 0ns; 312 assign_rs485("00010000"); --data byte 09 313 wait for 0ns; 314 assign_rs485("00000000"); --data byte 10 315 wait for 0ns; 316 assign_rs485("00000000"); --data byte 11 317 wait for 0ns; 318 assign_rs485("00000000"); --data byte 12 319 wait for 0ns; 320 assign_rs485("00000001"); --data byte 13 321 wait for 0ns; 322 assign_rs485("00000000"); --data byte 14 323 wait for 0ns; 324 assign_rs485("00000010"); --data byte 15 325 wait for 0ns; 326 assign_rs485("00000000"); --data byte 16 327 wait for 0ns; 328 assign_rs485("00000100"); --data byte 17 329 wait for 0ns; 330 assign_rs485("00000000"); --data byte 18 331 wait for 0ns; 332 assign_rs485("00001000"); --data byte 19 333 wait for 0ns; 334 assign_rs485("00000000"); --data byte 20 335 wait for 0ns; 336 assign_rs485("00010000"); --data byte 21 337 wait for 0ns; 338 assign_rs485("00000000"); --CRC error counter (not used) 339 wait for 0ns; 340 assign_rs485("00000000"); --check sum 341 --------------------------------------------------------------------------- 342 -- wait enough time and send another command 343 --------------------------------------------------------------------------- 344 wait for 1500us; 345 assign_rs485("01000000"); --start delimiter 346 wait for 0us; 347 assign_rs485("00000000"); --FTU address 348 wait for 0ns; 349 assign_rs485("11000000"); --FTM address 350 wait for 0ns; 351 assign_rs485("00000001"); --FTM firmware ID 352 wait for 0ns; 292 353 assign_rs485("00000101"); --instruction 293 354 wait for 0us; … … 314 375 assign_rs485("00000000"); --data byte 11 315 376 wait for 0ns; 316 assign_rs485("00000000"); --check sum 317 --------------------------------------------------------------------------- 318 -- wait enough time and send another command 319 --------------------------------------------------------------------------- 320 wait for 1ms; 321 assign_rs485("01000000"); --start delimiter 322 wait for 0us; 323 assign_rs485("00000000"); --FTU address 324 wait for 0ns; 325 assign_rs485("11000000"); --FTM address 326 wait for 0ns; 327 assign_rs485("00000101"); --instruction 328 wait for 0us; 329 assign_rs485("00000001"); --data byte 01 330 wait for 0ns; 331 assign_rs485("00000000"); --data byte 02 332 wait for 0ns; 333 assign_rs485("00000010"); --data byte 03 334 wait for 0ns; 335 assign_rs485("00000000"); --data byte 04 336 wait for 0ns; 337 assign_rs485("00000100"); --data byte 05 338 wait for 0ns; 339 assign_rs485("00000000"); --data byte 06 340 wait for 0ns; 341 assign_rs485("00001000"); --data byte 07 342 wait for 0ns; 343 assign_rs485("00000000"); --data byte 08 344 wait for 0ns; 345 assign_rs485("00010000"); --data byte 09 346 wait for 0ns; 347 assign_rs485("00000000"); --data byte 10 348 wait for 0ns; 349 assign_rs485("00000000"); --data byte 11 377 assign_rs485("00000000"); --data byte 12 378 wait for 0ns; 379 assign_rs485("00000001"); --data byte 13 380 wait for 0ns; 381 assign_rs485("00000000"); --data byte 14 382 wait for 0ns; 383 assign_rs485("00000010"); --data byte 15 384 wait for 0ns; 385 assign_rs485("00000000"); --data byte 16 386 wait for 0ns; 387 assign_rs485("00000100"); --data byte 17 388 wait for 0ns; 389 assign_rs485("00000000"); --data byte 18 390 wait for 0ns; 391 assign_rs485("00001000"); --data byte 19 392 wait for 0ns; 393 assign_rs485("00000000"); --data byte 20 394 wait for 0ns; 395 assign_rs485("00010000"); --data byte 21 396 wait for 0ns; 397 assign_rs485("00000000"); --CRC error counter (not used) 350 398 wait for 0ns; 351 399 assign_rs485("00000000"); --check sum -
firmware/FTU/clock/FTU_clk_gen.vhd
r9880 r10037 34 34 rst : IN STD_LOGIC; 35 35 clk_50 : OUT STD_LOGIC; 36 clk_1 : OUT STD_LOGIC; 36 37 ready : OUT STD_LOGIC 37 38 ); … … 48 49 LOCKED_OUT : out std_logic); 49 50 end component; 51 52 component Clock_Divider 53 port( 54 clock_in : IN STD_LOGIC; 55 clock_out : OUT STD_LOGIC 56 ); 57 end component; 58 59 signal clk_1M_sig : std_logic; 60 signal clk_50M_sig : std_logic; 50 61 51 62 begin … … 55 66 CLKIN_IN => clk, 56 67 RST_IN => rst, 57 CLKFX_OUT => clk_50 ,68 CLKFX_OUT => clk_50M_sig, 58 69 CLKIN_IBUFG_OUT => open, 59 70 LOCKED_OUT => ready 60 71 ); 72 73 Inst_Clock_Divider : Clock_Divider 74 port map ( 75 clock_in => clk_50M_sig, 76 clock_out => clk_1M_sig 77 ); 78 79 clk_50 <= clk_50M_sig; 80 clk_1 <= clk_1M_sig; 61 81 62 82 end Behavioral; 83 84 ---------------------------------------------------------------------------------- 85 86 library IEEE; 87 use IEEE.STD_LOGIC_1164.ALL; 88 use IEEE.STD_LOGIC_ARITH.ALL; 89 use IEEE.STD_LOGIC_UNSIGNED.ALL; 90 91 library ftu_definitions; 92 USE ftu_definitions.ftu_array_types.all; 93 USE ftu_definitions.ftu_constants.all; 94 95 entity Clock_Divider is 96 generic( 97 divider : integer := INT_CLK_FREQUENCY / COUNTER_FREQUENCY 98 ); 99 port( 100 clock_in : in std_logic; 101 clock_out : out std_logic := '0' 102 ); 103 end entity Clock_Divider; 104 105 architecture RTL of Clock_Divider is 106 107 begin 108 109 process (clock_in) 110 variable Z: integer range 0 to divider - 1; 111 begin 112 if rising_edge(clock_in) then 113 if (Z < divider - 1) then 114 Z := Z + 1; 115 else 116 Z := 0; 117 end if; 118 if (Z = 0) then 119 clock_out <= '1'; 120 end if; 121 if (Z = divider / 2) then 122 clock_out <= '0'; 123 end if; 124 end if; 125 end process; 126 127 end architecture RTL; -
firmware/FTU/counter/FTU_rate_counter.vhd
r9939 r10037 15 15 -- Revision: 16 16 -- Revision 0.01 - File Created 17 -- Revision 0.02 - counter range changed from 16 to 30 bit, 19.10.2010, Q. Weitzel 18 -- Revision 0.03 - no local clock division anymore, 20.10.2010, Q. Weitzel 17 19 -- Additional Comments: 18 20 -- … … 39 41 trigger : in std_logic; 40 42 prescaling : in std_logic_vector(7 downto 0); 41 counts : out integer range 0 to 2** 16- 1 := 0;43 counts : out integer range 0 to 2**30 - 1 := 0; 42 44 overflow : out std_logic := '0'; 43 45 new_rate : out std_logic … … 49 51 signal counting_period : integer range 0 to 128*COUNTER_FREQUENCY := 128*COUNTER_FREQUENCY; 50 52 signal period_finished : std_logic := '0'; 51 signal trigger_counts : integer range 0 to 2**16 - 1 := 0; 52 signal clk_1M_sig : std_logic; 53 signal trigger_counts : integer range 0 to 2**30 - 1 := 0; 53 54 signal overflow_sig : std_logic := '0'; 54 55 signal new_rate_sig : std_logic := '0'; 55 56 component Clock_Divider 57 port( 58 clock_in : IN STD_LOGIC; 59 clock_out : OUT STD_LOGIC 60 ); 61 end component; 62 56 63 57 begin 64 58 65 Inst_Clock_Divider : Clock_Divider 66 port map ( 67 clock_in => clk, 68 clock_out => clk_1M_sig 69 ); 70 71 process(cntr_reset, clk_1M_sig) 59 process(cntr_reset, clk) 72 60 73 61 variable clk_cntr : integer range 0 to 128*COUNTER_FREQUENCY := 0; … … 83 71 overflow <= '0'; 84 72 85 elsif rising_edge(clk _1M_sig) then73 elsif rising_edge(clk) then 86 74 87 75 if (clk_cntr < counting_period - 1) then … … 106 94 else 107 95 if rising_edge(trigger) then 108 if (trigger_counts < 2** 16- 1) then96 if (trigger_counts < 2**30 - 1) then 109 97 trigger_counts <= trigger_counts + 1; 110 98 else … … 121 109 --calculate counting period from prescaling value 122 110 --default is 0.5s - 128s if CNTR_FREQ_DIVIDER = 1 123 if (prescaling = "00000000") then 124 counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 125 elsif (prescaling = "11111111") then 126 counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 111 --if (prescaling = "00000000") then 112 --counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER); 113 --elsif (prescaling = "11111111") then 114 --counting_period <= 128 * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 115 --else 116 --counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 117 --end if; 118 if ((conv_integer(unsigned(prescaling))) mod 2 = 0) then 119 counting_period <= ((((conv_integer(unsigned(prescaling)) / 2)) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER)) + (COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER))); 127 120 else 128 counting_period <= (( conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);121 counting_period <= (((conv_integer(unsigned(prescaling)) - 1) / 2) + 1) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER); 129 122 end if; 130 123 end if; … … 134 127 135 128 end Behavioral; 136 137 ----------------------------------------------------------------------------------138 139 library IEEE;140 use IEEE.STD_LOGIC_1164.ALL;141 use IEEE.STD_LOGIC_ARITH.ALL;142 use IEEE.STD_LOGIC_UNSIGNED.ALL;143 144 library ftu_definitions;145 USE ftu_definitions.ftu_array_types.all;146 USE ftu_definitions.ftu_constants.all;147 148 entity Clock_Divider is149 generic(150 divider : integer := INT_CLK_FREQUENCY / COUNTER_FREQUENCY151 );152 port(153 clock_in : in std_logic;154 clock_out : out std_logic := '0'155 );156 end entity Clock_Divider;157 158 architecture RTL of Clock_Divider is159 160 begin161 162 process (clock_in)163 variable Z: integer range 0 to divider - 1;164 begin165 if rising_edge(clock_in) then166 if (Z < divider - 1) then167 Z := Z + 1;168 else169 Z := 0;170 end if;171 if (Z = 0) then172 clock_out <= '1';173 end if;174 if (Z = divider / 2) then175 clock_out <= '0';176 end if;177 end if;178 end process;179 180 end architecture RTL; -
firmware/FTU/ftu_board.ucf
r10009 r10037 79 79 ###################################################### 80 80 # logic signal from first trigger patch 81 NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_P 82 NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_N 81 NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS0_P 82 NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS0_N 83 #NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_P 84 #NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_N 83 85 84 86 # logic signal from second trigger patch 85 NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_P 86 NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_N 87 NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS1_P 88 NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS1_N 89 #NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_P 90 #NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_N 87 91 88 92 # logic signal from third trigger patch 89 NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_P 90 NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_N 93 NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS2_P 94 NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS2_N 95 #NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_P 96 #NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_N 91 97 92 98 # logic signal from fourth trigger patch 93 NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_P 94 NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_N 99 NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS3_P 100 NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS3_N 101 #NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_P 102 #NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_N 95 103 96 104 #The Trigger Primitive: logic signal from n-out-of-4 circuit 97 NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P+ 98 NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P- 99 105 NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # TRG_P+ 106 NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # TRG_P- 107 #NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P+ 108 #NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P- 100 109 101 110 # Enables -
firmware/FTU/ftu_definitions.vhd
r10009 r10037 42 42 43 43 --array to hold current values of rate counters (as integers) 44 type rate_array_type is array (0 to 4) of integer range 0 to 2** 16- 1;44 type rate_array_type is array (0 to 4) of integer range 0 to 2**30 - 1; 45 45 46 46 end ftu_array_types; … … 58 58 constant INT_CLK_FREQUENCY : integer := 50000000; -- 50MHz 59 59 constant COUNTER_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY 60 constant CNTR_FREQ_DIVIDER : integer := 50000; -- for simulation, should normally be 160 constant CNTR_FREQ_DIVIDER : integer := 25000; -- for simulation, should normally be 1 61 61 62 62 --32byte dual-port RAM, port A: 8byte, port B: 16byte 63 constant RAM_ADDR_WIDTH_A : integer := 5;64 constant RAM_ADDR_WIDTH_B : integer := 4;63 constant RAM_ADDR_WIDTH_A : integer := 6; 64 constant RAM_ADDR_WIDTH_B : integer := 5; 65 65 constant RAM_ADDR_RATIO : integer := 2; 66 66 67 --counter extension factor (for RAM) 68 constant RAM_CEF : integer := 2; 69 67 70 --normalization time for trigger counters 68 71 constant DEFAULT_PRESCALING : integer := 59; --30s integration time … … 75 78 --communication with FTM 76 79 constant RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case 77 constant RS485_BLOCK_WIDTH : integer := 128; -- 16byte protocol80 constant RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol 78 81 constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter 79 82 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 83 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version 84 85 --DNA identifier for simulation 86 constant DNA_FOR_SIM : bit_vector := X"01710000E0000501"; 80 87 81 --DNA identifier for simulation82 constant DNA_FOR_SIM : bit_vector := X"01710000E0000500";83 84 88 end ftu_constants; -
firmware/FTU/rs485/FTU_rs485_control.vhd
r10009 r10037 74 74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface 75 75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface 76 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface76 --signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface 77 77 78 78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver … … 88 88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter 89 89 90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 161-byte frames90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames 91 91 92 92 component FTU_rs485_receiver … … 131 131 -- FPGA 132 132 rx_data : OUT std_logic_vector (7 DOWNTO 0); 133 rx_busy : OUT std_logic := '0';133 --rx_busy : OUT std_logic := '0'; 134 134 rx_valid : OUT std_logic := '0'; 135 135 tx_data : IN std_logic_vector (7 DOWNTO 0); … … 187 187 -- FPGA 188 188 rx_data => rx_data_sig, 189 rx_busy => rx_busy_sig,189 --rx_busy => rx_busy_sig, 190 190 rx_valid => rx_valid_sig, 191 191 tx_data => tx_data_sig, … … 390 390 tx_start_sig <= '1'; 391 391 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 392 elsif txcnt = 3 then -- mirrored command 392 elsif txcnt = 3 then -- firmware ID 393 txcnt <= txcnt + 1; 394 tx_data_sig <= FIRMWARE_ID; 395 tx_start_sig <= '1'; 396 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 397 elsif txcnt = 4 then -- mirrored command 393 398 txcnt <= txcnt + 1; 394 399 tx_data_sig <= "00000000"; 395 400 tx_start_sig <= '1'; 396 401 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 397 elsif txcnt = 4then -- data: DAC A low402 elsif txcnt = 5 then -- data: DAC A low 398 403 txcnt <= txcnt + 1; 399 404 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); 400 405 tx_start_sig <= '1'; 401 406 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 402 elsif txcnt = 5then -- data: DAC A high407 elsif txcnt = 6 then -- data: DAC A high 403 408 txcnt <= txcnt + 1; 404 409 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); 405 410 tx_start_sig <= '1'; 406 411 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 407 elsif txcnt = 6then -- data: DAC B low412 elsif txcnt = 7 then -- data: DAC B low 408 413 txcnt <= txcnt + 1; 409 414 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); 410 415 tx_start_sig <= '1'; 411 416 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 412 elsif txcnt = 7then -- data: DAC B high417 elsif txcnt = 8 then -- data: DAC B high 413 418 txcnt <= txcnt + 1; 414 419 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); 415 420 tx_start_sig <= '1'; 416 421 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 417 elsif txcnt = 8then -- data: DAC C low422 elsif txcnt = 9 then -- data: DAC C low 418 423 txcnt <= txcnt + 1; 419 424 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); 420 425 tx_start_sig <= '1'; 421 426 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 422 elsif txcnt = 9then -- data: DAC C high427 elsif txcnt = 10 then -- data: DAC C high 423 428 txcnt <= txcnt + 1; 424 429 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); 425 430 tx_start_sig <= '1'; 426 431 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 427 elsif txcnt = 1 0then -- data: DAC D low432 elsif txcnt = 11 then -- data: DAC D low 428 433 txcnt <= txcnt + 1; 429 434 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); 430 435 tx_start_sig <= '1'; 431 436 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 432 elsif txcnt = 1 1then -- data: DAC D high437 elsif txcnt = 12 then -- data: DAC D high 433 438 txcnt <= txcnt + 1; 434 439 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); 435 440 tx_start_sig <= '1'; 436 441 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 437 elsif txcnt = 1 2then -- data: DAC E low442 elsif txcnt = 13 then -- data: DAC E low 438 443 txcnt <= txcnt + 1; 439 444 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); 440 445 tx_start_sig <= '1'; 441 446 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 442 elsif txcnt = 1 3then -- data: DAC E high447 elsif txcnt = 14 then -- data: DAC E high 443 448 txcnt <= txcnt + 1; 444 449 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); 445 450 tx_start_sig <= '1'; 446 451 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 447 elsif txcnt < 15then -- data: not used452 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 448 453 txcnt <= txcnt + 1; 449 454 tx_data_sig <= "00000000"; 450 455 tx_start_sig <= '1'; 451 456 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 452 elsif txcnt = 15 then -- check sum 457 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 458 txcnt <= txcnt + 1; 459 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 460 tx_start_sig <= '1'; 461 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 462 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 453 463 txcnt <= txcnt + 1; 454 464 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 481 491 tx_start_sig <= '1'; 482 492 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 483 elsif txcnt = 3 then -- mirrored command 493 elsif txcnt = 3 then -- firmware ID 494 txcnt <= txcnt + 1; 495 tx_data_sig <= FIRMWARE_ID; 496 tx_start_sig <= '1'; 497 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 498 elsif txcnt = 4 then -- mirrored command 484 499 txcnt <= txcnt + 1; 485 500 tx_data_sig <= "00000011"; 486 501 tx_start_sig <= '1'; 487 502 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 488 elsif txcnt = 4then -- data: enable pattern A7-0503 elsif txcnt = 5 then -- data: enable pattern A7-0 489 504 txcnt <= txcnt + 1; 490 505 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); 491 506 tx_start_sig <= '1'; 492 507 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 493 elsif txcnt = 5then -- data: enable pattern A8508 elsif txcnt = 6 then -- data: enable pattern A8 494 509 txcnt <= txcnt + 1; 495 510 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); 496 511 tx_start_sig <= '1'; 497 512 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 498 elsif txcnt = 6then -- data: enable pattern B7-0513 elsif txcnt = 7 then -- data: enable pattern B7-0 499 514 txcnt <= txcnt + 1; 500 515 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); 501 516 tx_start_sig <= '1'; 502 517 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 503 elsif txcnt = 7then -- data: enable pattern B8518 elsif txcnt = 8 then -- data: enable pattern B8 504 519 txcnt <= txcnt + 1; 505 520 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); 506 521 tx_start_sig <= '1'; 507 522 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 508 elsif txcnt = 8then -- data: enable pattern C7-0523 elsif txcnt = 9 then -- data: enable pattern C7-0 509 524 txcnt <= txcnt + 1; 510 525 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); 511 526 tx_start_sig <= '1'; 512 527 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 513 elsif txcnt = 9then -- data: enable pattern C8528 elsif txcnt = 10 then -- data: enable pattern C8 514 529 txcnt <= txcnt + 1; 515 530 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); 516 531 tx_start_sig <= '1'; 517 532 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 518 elsif txcnt = 1 0then -- data: enable pattern D7-0533 elsif txcnt = 11 then -- data: enable pattern D7-0 519 534 txcnt <= txcnt + 1; 520 535 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); 521 536 tx_start_sig <= '1'; 522 537 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 523 elsif txcnt = 1 1then -- data: enable pattern D8538 elsif txcnt = 12 then -- data: enable pattern D8 524 539 txcnt <= txcnt + 1; 525 540 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); 526 541 tx_start_sig <= '1'; 527 542 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 528 elsif txcnt < 15then -- data: not used543 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 529 544 txcnt <= txcnt + 1; 530 545 tx_data_sig <= "00000000"; 531 546 tx_start_sig <= '1'; 532 547 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 533 elsif txcnt = 15 then -- check sum 548 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 549 txcnt <= txcnt + 1; 550 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 551 tx_start_sig <= '1'; 552 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 553 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 534 554 txcnt <= txcnt + 1; 535 555 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 562 582 tx_start_sig <= '1'; 563 583 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 564 elsif txcnt = 3 then -- mirrored command 584 elsif txcnt = 3 then -- firmware ID 585 txcnt <= txcnt + 1; 586 tx_data_sig <= FIRMWARE_ID; 587 tx_start_sig <= '1'; 588 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 589 elsif txcnt = 4 then -- mirrored command 565 590 txcnt <= txcnt + 1; 566 591 tx_data_sig <= "00000110"; 567 592 tx_start_sig <= '1'; 568 593 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 569 elsif txcnt = 4then -- data: prescaling594 elsif txcnt = 5 then -- data: prescaling 570 595 txcnt <= txcnt + 1; 571 596 tx_data_sig <= prescaling_rs485_in; 572 597 tx_start_sig <= '1'; 573 598 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 574 elsif txcnt < 15then -- data: not used599 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 575 600 txcnt <= txcnt + 1; 576 601 tx_data_sig <= "00000000"; 577 602 tx_start_sig <= '1'; 578 603 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 579 elsif txcnt = 15 then -- check sum 604 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 605 txcnt <= txcnt + 1; 606 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 607 tx_start_sig <= '1'; 608 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 609 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 580 610 txcnt <= txcnt + 1; 581 611 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 608 638 tx_start_sig <= '1'; 609 639 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 610 elsif txcnt = 3 then -- mirrored command 640 elsif txcnt = 3 then -- firmware ID 641 txcnt <= txcnt + 1; 642 tx_data_sig <= FIRMWARE_ID; 643 tx_start_sig <= '1'; 644 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 645 elsif txcnt = 4 then -- mirrored command 611 646 txcnt <= txcnt + 1; 612 647 tx_data_sig <= "00000010"; 613 648 tx_start_sig <= '1'; 614 649 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 615 elsif txcnt = 4 then -- data: counter A low 616 txcnt <= txcnt + 1; 617 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0); 618 tx_start_sig <= '1'; 619 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 620 elsif txcnt = 5 then -- data: counter A high 621 txcnt <= txcnt + 1; 622 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8); 623 tx_start_sig <= '1'; 624 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 625 elsif txcnt = 6 then -- data: counter B low 626 txcnt <= txcnt + 1; 627 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0); 628 tx_start_sig <= '1'; 629 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 630 elsif txcnt = 7 then -- data: counter B high 631 txcnt <= txcnt + 1; 632 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8); 633 tx_start_sig <= '1'; 634 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 635 elsif txcnt = 8 then -- data: counter C low 636 txcnt <= txcnt + 1; 637 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0); 638 tx_start_sig <= '1'; 639 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 640 elsif txcnt = 9 then -- data: counter C high 641 txcnt <= txcnt + 1; 642 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8); 643 tx_start_sig <= '1'; 644 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 645 elsif txcnt = 10 then -- data: counter D low 646 txcnt <= txcnt + 1; 647 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0); 648 tx_start_sig <= '1'; 649 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 650 elsif txcnt = 11 then -- data: counter D high 651 txcnt <= txcnt + 1; 652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8); 653 tx_start_sig <= '1'; 654 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 655 elsif txcnt = 12 then -- data: trigger counter low 656 txcnt <= txcnt + 1; 657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0); 658 tx_start_sig <= '1'; 659 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 660 elsif txcnt = 13 then -- data: trigger counter high 661 txcnt <= txcnt + 1; 662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8); 663 tx_start_sig <= '1'; 664 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 665 elsif txcnt = 14 then -- data: overflow register 650 elsif txcnt = 5 then -- data: counter A 7...0 651 txcnt <= txcnt + 1; 652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0); 653 tx_start_sig <= '1'; 654 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 655 elsif txcnt = 6 then -- data: counter A 15...8 656 txcnt <= txcnt + 1; 657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8); 658 tx_start_sig <= '1'; 659 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 660 elsif txcnt = 7 then -- data: counter A 23...16 661 txcnt <= txcnt + 1; 662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16); 663 tx_start_sig <= '1'; 664 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 665 elsif txcnt = 8 then -- data: counter A 31...24 666 txcnt <= txcnt + 1; 667 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24); 668 tx_start_sig <= '1'; 669 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 670 elsif txcnt = 9 then -- data: counter B 7...0 671 txcnt <= txcnt + 1; 672 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0); 673 tx_start_sig <= '1'; 674 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 675 elsif txcnt = 10 then -- data: counter B 15...8 676 txcnt <= txcnt + 1; 677 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8); 678 tx_start_sig <= '1'; 679 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 680 elsif txcnt = 11 then -- data: counter B 23...16 681 txcnt <= txcnt + 1; 682 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16); 683 tx_start_sig <= '1'; 684 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 685 elsif txcnt = 12 then -- data: counter B 31...24 686 txcnt <= txcnt + 1; 687 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24); 688 tx_start_sig <= '1'; 689 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 690 elsif txcnt = 13 then -- data: counter C 7...0 691 txcnt <= txcnt + 1; 692 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0); 693 tx_start_sig <= '1'; 694 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 695 elsif txcnt = 14 then -- data: counter C 15...8 696 txcnt <= txcnt + 1; 697 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8); 698 tx_start_sig <= '1'; 699 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 700 elsif txcnt = 15 then -- data: counter C 23...16 701 txcnt <= txcnt + 1; 702 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16); 703 tx_start_sig <= '1'; 704 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 705 elsif txcnt = 16 then -- data: counter C 31...24 706 txcnt <= txcnt + 1; 707 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24); 708 tx_start_sig <= '1'; 709 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 710 elsif txcnt = 17 then -- data: counter D 7...0 711 txcnt <= txcnt + 1; 712 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0); 713 tx_start_sig <= '1'; 714 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 715 elsif txcnt = 18 then -- data: counter D 15...8 716 txcnt <= txcnt + 1; 717 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8); 718 tx_start_sig <= '1'; 719 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 720 elsif txcnt = 19 then -- data: counter D 23...16 721 txcnt <= txcnt + 1; 722 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16); 723 tx_start_sig <= '1'; 724 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 725 elsif txcnt = 20 then -- data: counter D 31...24 726 txcnt <= txcnt + 1; 727 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24); 728 tx_start_sig <= '1'; 729 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 730 elsif txcnt = 21 then -- data: trigger counter 7...0 731 txcnt <= txcnt + 1; 732 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0); 733 tx_start_sig <= '1'; 734 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 735 elsif txcnt = 22 then -- data: trigger counter 15...8 736 txcnt <= txcnt + 1; 737 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8); 738 tx_start_sig <= '1'; 739 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 740 elsif txcnt = 23 then -- data: trigger counter 23...16 741 txcnt <= txcnt + 1; 742 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16); 743 tx_start_sig <= '1'; 744 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 745 elsif txcnt = 24 then -- data: trigger counter 31...24 746 txcnt <= txcnt + 1; 747 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24); 748 tx_start_sig <= '1'; 749 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 750 elsif txcnt = 25 then -- data: overflow register 666 751 txcnt <= txcnt + 1; 667 752 tx_data_sig <= overflow_array_rs485_in; 668 753 tx_start_sig <= '1'; 669 754 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 670 elsif txcnt = 15 then -- check sum 755 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 756 txcnt <= txcnt + 1; 757 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 758 tx_start_sig <= '1'; 759 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 760 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 671 761 txcnt <= txcnt + 1; 672 762 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 699 789 tx_start_sig <= '1'; 700 790 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 701 elsif txcnt = 3 then -- mirrored command 791 elsif txcnt = 3 then -- firmware ID 792 txcnt <= txcnt + 1; 793 tx_data_sig <= FIRMWARE_ID; 794 tx_start_sig <= '1'; 795 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 796 elsif txcnt = 4 then -- mirrored command 702 797 txcnt <= txcnt + 1; 703 798 tx_data_sig <= "00000001"; 704 799 tx_start_sig <= '1'; 705 800 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 706 elsif txcnt = 4then -- data: DAC A low801 elsif txcnt = 5 then -- data: DAC A low 707 802 txcnt <= txcnt + 1; 708 803 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); 709 804 tx_start_sig <= '1'; 710 805 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 711 elsif txcnt = 5then -- data: DAC A high806 elsif txcnt = 6 then -- data: DAC A high 712 807 txcnt <= txcnt + 1; 713 808 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); 714 809 tx_start_sig <= '1'; 715 810 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 716 elsif txcnt = 6then -- data: DAC B low811 elsif txcnt = 7 then -- data: DAC B low 717 812 txcnt <= txcnt + 1; 718 813 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); 719 814 tx_start_sig <= '1'; 720 815 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 721 elsif txcnt = 7then -- data: DAC B high816 elsif txcnt = 8 then -- data: DAC B high 722 817 txcnt <= txcnt + 1; 723 818 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); 724 819 tx_start_sig <= '1'; 725 820 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 726 elsif txcnt = 8then -- data: DAC C low821 elsif txcnt = 9 then -- data: DAC C low 727 822 txcnt <= txcnt + 1; 728 823 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); 729 824 tx_start_sig <= '1'; 730 825 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 731 elsif txcnt = 9then -- data: DAC C high826 elsif txcnt = 10 then -- data: DAC C high 732 827 txcnt <= txcnt + 1; 733 828 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); 734 829 tx_start_sig <= '1'; 735 830 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 736 elsif txcnt = 1 0then -- data: DAC D low831 elsif txcnt = 11 then -- data: DAC D low 737 832 txcnt <= txcnt + 1; 738 833 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); 739 834 tx_start_sig <= '1'; 740 835 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 741 elsif txcnt = 1 1then -- data: DAC D high836 elsif txcnt = 12 then -- data: DAC D high 742 837 txcnt <= txcnt + 1; 743 838 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); 744 839 tx_start_sig <= '1'; 745 840 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 746 elsif txcnt = 1 2then -- data: DAC E low841 elsif txcnt = 13 then -- data: DAC E low 747 842 txcnt <= txcnt + 1; 748 843 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); 749 844 tx_start_sig <= '1'; 750 845 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 751 elsif txcnt = 1 3then -- data: DAC E high846 elsif txcnt = 14 then -- data: DAC E high 752 847 txcnt <= txcnt + 1; 753 848 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); 754 849 tx_start_sig <= '1'; 755 850 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 756 elsif txcnt < 15then -- data: not used851 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 757 852 txcnt <= txcnt + 1; 758 853 tx_data_sig <= "00000000"; 759 854 tx_start_sig <= '1'; 760 855 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 761 elsif txcnt = 15 then -- check sum 856 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 857 txcnt <= txcnt + 1; 858 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 859 tx_start_sig <= '1'; 860 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 861 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 762 862 txcnt <= txcnt + 1; 763 863 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 790 890 tx_start_sig <= '1'; 791 891 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 792 elsif txcnt = 3 then -- mirrored command 892 elsif txcnt = 3 then -- firmware ID 893 txcnt <= txcnt + 1; 894 tx_data_sig <= FIRMWARE_ID; 895 tx_start_sig <= '1'; 896 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 897 elsif txcnt = 4 then -- mirrored command 793 898 txcnt <= txcnt + 1; 794 899 tx_data_sig <= "00000100"; 795 900 tx_start_sig <= '1'; 796 901 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 797 elsif txcnt = 4then -- data: enable pattern A7-0902 elsif txcnt = 5 then -- data: enable pattern A7-0 798 903 txcnt <= txcnt + 1; 799 904 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); 800 905 tx_start_sig <= '1'; 801 906 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 802 elsif txcnt = 5then -- data: enable pattern A8907 elsif txcnt = 6 then -- data: enable pattern A8 803 908 txcnt <= txcnt + 1; 804 909 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); 805 910 tx_start_sig <= '1'; 806 911 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 807 elsif txcnt = 6then -- data: enable pattern B7-0912 elsif txcnt = 7 then -- data: enable pattern B7-0 808 913 txcnt <= txcnt + 1; 809 914 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); 810 915 tx_start_sig <= '1'; 811 916 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 812 elsif txcnt = 7then -- data: enable pattern B8917 elsif txcnt = 8 then -- data: enable pattern B8 813 918 txcnt <= txcnt + 1; 814 919 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); 815 920 tx_start_sig <= '1'; 816 921 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 817 elsif txcnt = 8then -- data: enable pattern C7-0922 elsif txcnt = 9 then -- data: enable pattern C7-0 818 923 txcnt <= txcnt + 1; 819 924 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); 820 925 tx_start_sig <= '1'; 821 926 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 822 elsif txcnt = 9then -- data: enable pattern C8927 elsif txcnt = 10 then -- data: enable pattern C8 823 928 txcnt <= txcnt + 1; 824 929 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); 825 930 tx_start_sig <= '1'; 826 931 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 827 elsif txcnt = 1 0then -- data: enable pattern D7-0932 elsif txcnt = 11 then -- data: enable pattern D7-0 828 933 txcnt <= txcnt + 1; 829 934 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); 830 935 tx_start_sig <= '1'; 831 936 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 832 elsif txcnt = 1 1then -- data: enable pattern D8937 elsif txcnt = 12 then -- data: enable pattern D8 833 938 txcnt <= txcnt + 1; 834 939 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); 835 940 tx_start_sig <= '1'; 836 941 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 837 elsif txcnt < 15then -- data: not used942 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 838 943 txcnt <= txcnt + 1; 839 944 tx_data_sig <= "00000000"; 840 945 tx_start_sig <= '1'; 841 946 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 842 elsif txcnt = 15 then -- check sum 947 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 948 txcnt <= txcnt + 1; 949 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 950 tx_start_sig <= '1'; 951 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 952 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 843 953 txcnt <= txcnt + 1; 844 954 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 871 981 tx_start_sig <= '1'; 872 982 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 873 elsif txcnt = 3 then -- mirrored command 983 elsif txcnt = 3 then -- firmware ID 984 txcnt <= txcnt + 1; 985 tx_data_sig <= FIRMWARE_ID; 986 tx_start_sig <= '1'; 987 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 988 elsif txcnt = 4 then -- mirrored command 874 989 txcnt <= txcnt + 1; 875 990 tx_data_sig <= "00000111"; 876 991 tx_start_sig <= '1'; 877 992 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 878 elsif txcnt = 4then -- data: prescaling993 elsif txcnt = 5 then -- data: prescaling 879 994 txcnt <= txcnt + 1; 880 995 tx_data_sig <= prescaling_rs485_in; 881 996 tx_start_sig <= '1'; 882 997 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 883 elsif txcnt = 5then -- data: overflow register998 elsif txcnt = 6 then -- data: overflow register 884 999 txcnt <= txcnt + 1; 885 1000 tx_data_sig <= overflow_array_rs485_in; 886 1001 tx_start_sig <= '1'; 887 1002 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 888 elsif txcnt < 15then -- data: not used1003 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 889 1004 txcnt <= txcnt + 1; 890 1005 tx_data_sig <= "00000000"; 891 1006 tx_start_sig <= '1'; 892 1007 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 893 elsif txcnt = 15 then -- check sum 1008 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1009 txcnt <= txcnt + 1; 1010 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 1011 tx_start_sig <= '1'; 1012 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 1013 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 894 1014 txcnt <= txcnt + 1; 895 1015 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 922 1042 tx_start_sig <= '1'; 923 1043 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 924 elsif txcnt = 3 then -- mirrored command 1044 elsif txcnt = 3 then -- firmware ID 1045 txcnt <= txcnt + 1; 1046 tx_data_sig <= FIRMWARE_ID; 1047 tx_start_sig <= '1'; 1048 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1049 elsif txcnt = 4 then -- mirrored command 925 1050 txcnt <= txcnt + 1; 926 1051 tx_data_sig <= "00000101"; 927 1052 tx_start_sig <= '1'; 928 1053 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 929 elsif txcnt = 4then -- data: device DNA1054 elsif txcnt = 5 then -- data: device DNA 930 1055 txcnt <= txcnt + 1; 931 1056 tx_data_sig <= dna(7 downto 0); 932 1057 tx_start_sig <= '1'; 933 1058 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 934 elsif txcnt = 5then -- data: device DNA1059 elsif txcnt = 6 then -- data: device DNA 935 1060 txcnt <= txcnt + 1; 936 1061 tx_data_sig <= dna(15 downto 8); 937 1062 tx_start_sig <= '1'; 938 1063 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 939 elsif txcnt = 6then -- data: device DNA1064 elsif txcnt = 7 then -- data: device DNA 940 1065 txcnt <= txcnt + 1; 941 1066 tx_data_sig <= dna(23 downto 16); 942 1067 tx_start_sig <= '1'; 943 1068 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 944 elsif txcnt = 7then -- data: device DNA1069 elsif txcnt = 8 then -- data: device DNA 945 1070 txcnt <= txcnt + 1; 946 1071 tx_data_sig <= dna(31 downto 24); 947 1072 tx_start_sig <= '1'; 948 1073 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 949 elsif txcnt = 8then -- data: device DNA1074 elsif txcnt = 9 then -- data: device DNA 950 1075 txcnt <= txcnt + 1; 951 1076 tx_data_sig <= dna(39 downto 32); 952 1077 tx_start_sig <= '1'; 953 1078 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 954 elsif txcnt = 9then -- data: device DNA1079 elsif txcnt = 10 then -- data: device DNA 955 1080 txcnt <= txcnt + 1; 956 1081 tx_data_sig <= dna(47 downto 40); 957 1082 tx_start_sig <= '1'; 958 1083 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 959 elsif txcnt = 1 0then -- data: device DNA1084 elsif txcnt = 11 then -- data: device DNA 960 1085 txcnt <= txcnt + 1; 961 1086 tx_data_sig <= dna(55 downto 48); 962 1087 tx_start_sig <= '1'; 963 1088 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 964 elsif txcnt = 1 1then -- data: device DNA1089 elsif txcnt = 12 then -- data: device DNA 965 1090 txcnt <= txcnt + 1; 966 1091 tx_data_sig <= dna(63 downto 56); 967 1092 tx_start_sig <= '1'; 968 1093 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 969 elsif txcnt < 15then -- data: not used1094 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 970 1095 txcnt <= txcnt + 1; 971 1096 tx_data_sig <= "00000000"; 972 1097 tx_start_sig <= '1'; 973 1098 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 974 elsif txcnt = 15 then -- check sum 1099 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1100 txcnt <= txcnt + 1; 1101 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 1102 tx_start_sig <= '1'; 1103 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1104 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 975 1105 txcnt <= txcnt + 1; 976 1106 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! -
firmware/FTU/rs485/FTU_rs485_interface.vhd
r9928 r10037 34 34 -- FPGA 35 35 rx_data : OUT std_logic_vector (7 DOWNTO 0); 36 rx_busy : OUT std_logic := '0';36 --rx_busy : OUT std_logic := '0'; 37 37 rx_valid : OUT std_logic := '0'; 38 38 tx_data : IN std_logic_vector (7 DOWNTO 0); … … 122 122 rx_en <= flow_ctrl; 123 123 rx_data <= rx_sr; 124 rx_busy <= '1' when (rx_bitcnt < 11) else '0';124 --rx_busy <= '1' when (rx_bitcnt < 11) else '0'; 125 125 126 126 END ARCHITECTURE beha; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r10009 r10037 105 105 106 106 when DECODE => -- decode instruction 107 if(data_block(3 1 downto 24) = "00000000") then -- set DACs107 if(data_block(39 downto 32) = "00000000") then -- set DACs 108 108 int_new_DACs <= '1'; 109 109 int_new_enables <= '0'; … … 114 114 int_read_prescaling <= '0'; 115 115 int_ping_pong <= '0'; 116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block( 43 downto 32))),117 conv_integer(unsigned(data_block( 59 downto 48))),118 conv_integer(unsigned(data_block( 75 downto 64))),119 conv_integer(unsigned(data_block(9 1 downto 80))),116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(51 downto 40))), 117 conv_integer(unsigned(data_block(67 downto 56))), 118 conv_integer(unsigned(data_block(83 downto 72))), 119 conv_integer(unsigned(data_block(99 downto 88))), 120 120 DEFAULT_DAC(4), 121 121 DEFAULT_DAC(5), 122 122 DEFAULT_DAC(6), 123 conv_integer(unsigned(data_block(1 07 downto 96)))123 conv_integer(unsigned(data_block(115 downto 104))) 124 124 ); 125 125 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 126 elsif (data_block(3 1 downto 24) = "00000001") then -- read DACs126 elsif (data_block(39 downto 32) = "00000001") then -- read DACs 127 127 int_new_DACs <= '0'; 128 128 int_new_enables <= '0'; … … 134 134 int_ping_pong <= '0'; 135 135 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 136 elsif (data_block(3 1 downto 24) = "00000010") then -- read rates136 elsif (data_block(39 downto 32) = "00000010") then -- read rates 137 137 int_new_DACs <= '0'; 138 138 int_new_enables <= '0'; … … 144 144 int_ping_pong <= '0'; 145 145 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 146 elsif (data_block(3 1 downto 24) = "00000011") then -- set enables146 elsif (data_block(39 downto 32) = "00000011") then -- set enables 147 147 int_new_DACs <= '0'; 148 148 int_new_enables <= '1'; … … 153 153 int_read_prescaling <= '0'; 154 154 int_ping_pong <= '0'; 155 enable_array_rs485_out_sig <= (data_block( 47 downto 32),156 data_block( 63 downto 48),157 data_block( 79 downto 64),158 data_block( 95 downto 80)155 enable_array_rs485_out_sig <= (data_block(55 downto 40), 156 data_block(71 downto 56), 157 data_block(87 downto 72), 158 data_block(103 downto 88) 159 159 ); 160 160 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 161 elsif (data_block(3 1 downto 24) = "00000100") then -- read enables161 elsif (data_block(39 downto 32) = "00000100") then -- read enables 162 162 int_new_DACs <= '0'; 163 163 int_new_enables <= '0'; … … 169 169 int_ping_pong <= '0'; 170 170 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 171 elsif (data_block(3 1 downto 24) = "00000110") then -- set counter mode171 elsif (data_block(39 downto 32) = "00000110") then -- set counter mode 172 172 int_new_DACs <= '0'; 173 173 int_new_enables <= '0'; … … 178 178 int_read_prescaling <= '0'; 179 179 int_ping_pong <= '0'; 180 prescaling_rs485_out_sig <= data_block( 39 downto 32);181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 elsif (data_block(3 1 downto 24) = "00000111") then -- read counter mode180 prescaling_rs485_out_sig <= data_block(47 downto 40); 181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 elsif (data_block(39 downto 32) = "00000111") then -- read counter mode 183 183 int_new_DACs <= '0'; 184 184 int_new_enables <= '0'; … … 190 190 int_ping_pong <= '0'; 191 191 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 192 elsif (data_block(3 1 downto 24) = "00000101") then -- ping pong192 elsif (data_block(39 downto 32) = "00000101") then -- ping pong 193 193 int_new_DACs <= '0'; 194 194 int_new_enables <= '0';
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