- Timestamp:
- 11/10/10 15:08:54 (14 years ago)
- Location:
- firmware/FTU
- Files:
-
- 1 added
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTU/FTU_control.vhd
r10037 r10050 201 201 ram_dia_sig <= (others => '0'); 202 202 FTU_control_State <= INIT_RAM; 203 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default CRC errors204 ram_dia_sig <= (others => '0');205 FTU_control_State <= INIT_RAM;203 --elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default CRC errors 204 --ram_dia_sig <= (others => '0'); 205 --FTU_control_State <= INIT_RAM; 206 206 elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then -- empty RAM cells 207 207 ram_dia_sig <= (others => '0'); … … 302 302 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); 303 303 FTU_control_State <= CONFIG_ENABLE; 304 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then 304 --elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then 305 --ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); 306 --enable_array_sig(ram_enable_cntr - 1) <= ram_dob; 307 --enables_ready <= '1'; 308 --FTU_control_State <= CONFIG_ENABLE; 309 elsif (ram_enable_cntr < NO_OF_ENABLE) then 310 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); 311 enable_array_sig(ram_enable_cntr - 1) <= ram_dob; 312 FTU_control_State <= CONFIG_ENABLE; 313 elsif (ram_enable_cntr = NO_OF_ENABLE) then 305 314 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B); 306 315 enable_array_sig(ram_enable_cntr - 1) <= ram_dob; -
firmware/FTU/FTU_top_tb.vhd
r10037 r10050 244 244 wait for 5ns; 245 245 trigger_sig <= '0'; 246 wait; 246 wait for 1800us; 247 trigger_sig <= '1'; 248 wait for 5ns; 249 trigger_sig <= '0'; 250 wait for 50us; 251 trigger_sig <= '1'; 252 wait for 5ns; 253 trigger_sig <= '0'; 254 wait; 247 255 end process trigger_proc; 248 256 … … 292 300 assign_rs485("00000001"); --FTM firmware ID 293 301 wait for 0ns; 294 assign_rs485("00000 010"); --instruction302 assign_rs485("00000110"); --instruction 295 303 wait for 0us; 296 assign_rs485("000 00001"); --data byte 01304 assign_rs485("00010100"); --data byte 01 297 305 wait for 0ns; 298 306 assign_rs485("00000000"); --data byte 02 299 307 wait for 0ns; 300 assign_rs485("000000 10"); --data byte 03308 assign_rs485("00000000"); --data byte 03 301 309 wait for 0ns; 302 310 assign_rs485("00000000"); --data byte 04 303 311 wait for 0ns; 304 assign_rs485("00000 100"); --data byte 05312 assign_rs485("00000000"); --data byte 05 305 313 wait for 0ns; 306 314 assign_rs485("00000000"); --data byte 06 307 315 wait for 0ns; 308 assign_rs485("0000 1000"); --data byte 07316 assign_rs485("00000000"); --data byte 07 309 317 wait for 0ns; 310 318 assign_rs485("00000000"); --data byte 08 311 319 wait for 0ns; 312 assign_rs485("000 10000"); --data byte 09320 assign_rs485("00000000"); --data byte 09 313 321 wait for 0ns; 314 322 assign_rs485("00000000"); --data byte 10 … … 318 326 assign_rs485("00000000"); --data byte 12 319 327 wait for 0ns; 320 assign_rs485("0000000 1"); --data byte 13328 assign_rs485("00000000"); --data byte 13 321 329 wait for 0ns; 322 330 assign_rs485("00000000"); --data byte 14 323 331 wait for 0ns; 324 assign_rs485("000000 10"); --data byte 15332 assign_rs485("00000000"); --data byte 15 325 333 wait for 0ns; 326 334 assign_rs485("00000000"); --data byte 16 327 335 wait for 0ns; 328 assign_rs485("00000 100"); --data byte 17336 assign_rs485("00000000"); --data byte 17 329 337 wait for 0ns; 330 338 assign_rs485("00000000"); --data byte 18 331 339 wait for 0ns; 332 assign_rs485("0000 1000"); --data byte 19340 assign_rs485("00000000"); --data byte 19 333 341 wait for 0ns; 334 342 assign_rs485("00000000"); --data byte 20 335 343 wait for 0ns; 336 assign_rs485("000 10000"); --data byte 21344 assign_rs485("00000000"); --data byte 21 337 345 wait for 0ns; 338 346 assign_rs485("00000000"); --CRC error counter (not used) 339 347 wait for 0ns; 340 assign_rs485("0 0000000"); --check sum348 assign_rs485("01001101"); --check sum 341 349 --------------------------------------------------------------------------- 342 350 -- wait enough time and send another command … … 351 359 assign_rs485("00000001"); --FTM firmware ID 352 360 wait for 0ns; 353 assign_rs485("00000 101"); --instruction361 assign_rs485("00000000"); --instruction 354 362 wait for 0us; 355 363 assign_rs485("00000001"); --data byte 01 … … 357 365 assign_rs485("00000000"); --data byte 02 358 366 wait for 0ns; 359 assign_rs485("000000 10"); --data byte 03367 assign_rs485("00000000"); --data byte 03 360 368 wait for 0ns; 361 369 assign_rs485("00000000"); --data byte 04 362 370 wait for 0ns; 363 assign_rs485("00000 100"); --data byte 05371 assign_rs485("00000000"); --data byte 05 364 372 wait for 0ns; 365 373 assign_rs485("00000000"); --data byte 06 366 374 wait for 0ns; 367 assign_rs485("0000 1000"); --data byte 07375 assign_rs485("00000000"); --data byte 07 368 376 wait for 0ns; 369 377 assign_rs485("00000000"); --data byte 08 370 378 wait for 0ns; 371 assign_rs485("000 10000"); --data byte 09379 assign_rs485("00000000"); --data byte 09 372 380 wait for 0ns; 373 381 assign_rs485("00000000"); --data byte 10 … … 377 385 assign_rs485("00000000"); --data byte 12 378 386 wait for 0ns; 379 assign_rs485("0000000 1"); --data byte 13387 assign_rs485("00000000"); --data byte 13 380 388 wait for 0ns; 381 389 assign_rs485("00000000"); --data byte 14 382 390 wait for 0ns; 383 assign_rs485("000000 10"); --data byte 15391 assign_rs485("00000000"); --data byte 15 384 392 wait for 0ns; 385 393 assign_rs485("00000000"); --data byte 16 386 394 wait for 0ns; 387 assign_rs485("00000 100"); --data byte 17395 assign_rs485("00000000"); --data byte 17 388 396 wait for 0ns; 389 397 assign_rs485("00000000"); --data byte 18 390 398 wait for 0ns; 391 assign_rs485("0000 1000"); --data byte 19399 assign_rs485("00000000"); --data byte 19 392 400 wait for 0ns; 393 401 assign_rs485("00000000"); --data byte 20 394 402 wait for 0ns; 395 assign_rs485("000 10000"); --data byte 21403 assign_rs485("00000000"); --data byte 21 396 404 wait for 0ns; 397 405 assign_rs485("00000000"); --CRC error counter (not used) 398 406 wait for 0ns; 399 assign_rs485("0 0000000"); --check sum407 assign_rs485("01010010"); --check sum 400 408 --------------------------------------------------------------------------- 401 409 -- don't forget final wait! -
firmware/FTU/ftu_definitions.vhd
r10047 r10050 83 83 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 84 84 constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "00000001"; -- firmware version 85 86 --CRC setup 87 constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111"; -- 8-CCITT 88 constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111"; 85 89 86 90 --DNA identifier for simulation -
firmware/FTU/rs485/FTU_rs485_control.vhd
r10037 r10050 89 89 90 90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames 91 92 signal reset_crc_sig : std_logic := '0'; 93 signal crc_enable_sig : std_logic := '0'; 94 signal crc_input_sig : std_logic_vector(RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); 95 signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0'); 96 signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0) := (others => '0'); 97 signal crc_error_cnt_sig : integer range 0 to 255 := 0; 98 99 component ucrc_par 100 generic( 101 POLYNOMIAL : std_logic_vector; 102 INIT_VALUE : std_logic_vector; 103 DATA_WIDTH : integer range 2 to 256; 104 SYNC_RESET : integer range 0 to 1 105 ); 106 port( 107 clk_i : in std_logic; 108 rst_i : in std_logic; 109 clken_i : in std_logic; 110 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); 111 match_o : out std_logic; 112 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0) 113 ); 114 end component; 91 115 92 116 component FTU_rs485_receiver … … 107 131 block_valid : IN std_logic; 108 132 brd_add : IN std_logic_vector(5 downto 0); 133 crc_error_cnt : OUT integer range 0 to 255; 109 134 int_new_DACs : OUT std_logic; 110 135 int_new_enables : OUT std_logic; … … 139 164 end component; 140 165 141 type FTU_rs485_control_StateType is ( RECEIVE,166 type FTU_rs485_control_StateType is (INIT, RECEIVE, 142 167 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT, 143 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT, 168 READ_RATES_WAIT_2, READ_DAC_WAIT_2, READ_ENABLE_WAIT_2, READ_PRESCALING_WAIT_2, 169 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT, 170 SET_DAC_WAIT_2, SET_ENABLE_WAIT_2, SET_PRESCALING_WAIT_2, PING_PONG_WAIT_2, 144 171 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT, 145 172 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT); … … 147 174 148 175 begin 176 177 crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7); 178 179 Inst_ucrc_par : ucrc_par 180 generic map( 181 POLYNOMIAL => CRC_POLYNOMIAL, 182 INIT_VALUE => CRC_INIT_VALUE, 183 DATA_WIDTH => 216, 184 SYNC_RESET => 1 185 ) 186 port map( 187 clk_i => main_clk, 188 rst_i => reset_crc_sig, 189 clken_i => crc_enable_sig, 190 data_i => crc_input_sig, 191 match_o => open, 192 crc_o => crc_sig_inv 193 ); 149 194 150 195 Inst_FTU_rs485_receiver : FTU_rs485_receiver … … 164 209 block_valid => block_valid_sig, 165 210 brd_add => brd_add, 211 crc_error_cnt => crc_error_cnt_sig, 166 212 int_new_DACs => int_new_DACs_sig, 167 213 int_new_enables => int_new_enables_sig, … … 200 246 if Rising_edge(main_clk) then 201 247 case FTU_rs485_control_State is 248 249 when INIT => 250 reset_crc_sig <= '1'; 251 FTU_rs485_control_State <= RECEIVE; 202 252 203 when RECEIVE => -- default state, receiver on, no transmission 253 when RECEIVE => -- default state, receiver on, no transmission 254 reset_crc_sig <= '0'; 255 crc_enable_sig <= '0'; 204 256 tx_start_sig <= '0'; 205 257 if (int_new_DACs_sig = '1') then … … 304 356 if (DACs_ready = '1') then 305 357 new_DACs <= '0'; 306 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 358 crc_enable_sig <= '1'; 359 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 360 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 361 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 362 & "00000000" 363 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0) 364 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0) 365 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0) 366 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0) 367 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000000" 368 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 369 FTU_rs485_control_State <= SET_DAC_WAIT_2; 307 370 else 308 371 new_DACs <= '1'; … … 310 373 end if; 311 374 375 when SET_DAC_WAIT_2 => 376 crc_enable_sig <= '0'; 377 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 378 312 379 when SET_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM 313 380 if (enables_ready = '1') then 314 381 new_enables <= '0'; 315 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 382 crc_enable_sig <= '1'; 383 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 384 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 385 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 386 & "00000000" & "00000000" & "00000000" 387 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0) 388 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0) 389 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0) 390 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000011" 391 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 392 FTU_rs485_control_State <= SET_ENABLE_WAIT_2; 316 393 else 317 394 new_enables <= '1'; … … 319 396 end if; 320 397 398 when SET_ENABLE_WAIT_2 => 399 crc_enable_sig <= '0'; 400 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 401 321 402 when SET_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM 322 403 if (prescaling_ready = '1') then 323 404 new_prescaling <= '0'; 324 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 405 crc_enable_sig <= '1'; 406 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 407 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 408 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 409 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 410 & "00000000" & "00000000" & "00000000" & "00000000" 411 & overflow_array_rs485_in & prescaling_rs485_in & "00000110" 412 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 413 FTU_rs485_control_State <= SET_PRESCALING_WAIT_2; 325 414 else 326 415 new_prescaling <= '1'; … … 328 417 end if; 329 418 419 when SET_PRESCALING_WAIT_2 => 420 crc_enable_sig <= '0'; 421 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 422 330 423 when READ_RATES_WAIT => -- wait until FTU control says "done" and then answer to FTM 331 424 if (rates_ready = '1') then 332 425 read_rates <= '0'; 333 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 426 crc_enable_sig <= '1'; 427 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 428 & overflow_array_rs485_in 429 & conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16) 430 & conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0) 431 & conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16) 432 & conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0) 433 & conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16) 434 & conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0) 435 & conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16) 436 & conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0) 437 & conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24) & conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16) 438 & conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8) & conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0) & "00000010" 439 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 440 FTU_rs485_control_State <= READ_RATES_WAIT_2; 334 441 else 335 442 read_rates <= '1'; … … 337 444 end if; 338 445 446 when READ_RATES_WAIT_2 => 447 crc_enable_sig <= '0'; 448 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 449 339 450 when READ_DAC_WAIT => -- wait until FTU control says "done" and then answer to FTM 340 451 if (DACs_ready = '1') then 341 452 read_DACs <= '0'; 342 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 453 crc_enable_sig <= '1'; 454 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 455 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 456 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 457 & "00000000" 458 & conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0) 459 & conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0) 460 & conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0) 461 & conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0) 462 & conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8) & conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0) & "00000001" 463 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 464 FTU_rs485_control_State <= READ_DAC_WAIT_2; 343 465 else 344 466 read_DACs <= '1'; … … 346 468 end if; 347 469 470 when READ_DAC_WAIT_2 => 471 crc_enable_sig <= '0'; 472 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 473 348 474 when READ_ENABLE_WAIT => -- wait until FTU control says "done" and then answer to FTM 349 475 if (enables_ready = '1') then 350 476 read_enables <= '0'; 351 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 477 crc_enable_sig <= '1'; 478 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 479 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 480 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 481 & "00000000" & "00000000" & "00000000" 482 & enable_array_rs485_in(3)(15 downto 8) & enable_array_rs485_in(3)(7 downto 0) 483 & enable_array_rs485_in(2)(15 downto 8) & enable_array_rs485_in(2)(7 downto 0) 484 & enable_array_rs485_in(1)(15 downto 8) & enable_array_rs485_in(1)(7 downto 0) 485 & enable_array_rs485_in(0)(15 downto 8) & enable_array_rs485_in(0)(7 downto 0) & "00000100" 486 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 487 FTU_rs485_control_State <= READ_ENABLE_WAIT_2; 352 488 else 353 489 read_enables <= '1'; … … 355 491 end if; 356 492 493 when READ_ENABLE_WAIT_2 => 494 crc_enable_sig <= '0'; 495 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 496 357 497 when READ_PRESCALING_WAIT => -- wait until FTU control says "done" and then answer to FTM 358 498 if (prescaling_ready = '1') then 359 499 read_prescaling <= '0'; 360 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 500 crc_enable_sig <= '1'; 501 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 502 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 503 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 504 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 505 & "00000000" & "00000000" & "00000000" & "00000000" 506 & overflow_array_rs485_in & prescaling_rs485_in & "00000111" 507 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 508 FTU_rs485_control_State <= READ_PRESCALING_WAIT_2; 361 509 else 362 510 read_prescaling <= '1'; … … 364 512 end if; 365 513 514 when READ_PRESCALING_WAIT_2 => 515 crc_enable_sig <= '0'; 516 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 517 366 518 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM 367 519 if (ping_pong_ready = '1') then 368 520 ping_pong <= '0'; 369 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 521 crc_enable_sig <= '1'; 522 crc_input_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8) 523 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 524 & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" 525 & "00000000" & "00000000" & "00000000" 526 & dna(63 downto 0) & "00000101" 527 & FIRMWARE_ID & "00" & brd_add & FTM_ADDRESS & RS485_START_DELIM; 528 FTU_rs485_control_State <= PING_PONG_WAIT_2; 370 529 else 371 530 ping_pong <= '1'; 372 531 FTU_rs485_control_State <= PING_PONG_WAIT; 373 532 end if; 533 534 when PING_PONG_WAIT_2 => 535 crc_enable_sig <= '0'; 536 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 374 537 375 538 when SET_DAC_TRANSMIT => … … 457 620 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 458 621 txcnt <= txcnt + 1; 459 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!460 tx_start_sig <= '1'; 461 FTU_rs485_control_State <= READ_RATES_TRANSMIT;622 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 623 tx_start_sig <= '1'; 624 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 462 625 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 463 626 txcnt <= txcnt + 1; 464 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!627 tx_data_sig <= crc_sig; 465 628 tx_start_sig <= '1'; 466 629 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 467 630 else -- transmission finished 468 631 txcnt <= 0; 632 reset_crc_sig <= '1'; 469 633 FTU_rs485_control_State <= RECEIVE; 470 634 end if; … … 548 712 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 549 713 txcnt <= txcnt + 1; 550 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!714 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 551 715 tx_start_sig <= '1'; 552 716 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 553 717 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 554 718 txcnt <= txcnt + 1; 555 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!719 tx_data_sig <= crc_sig; 556 720 tx_start_sig <= '1'; 557 721 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 558 722 else -- transmission finished 559 723 txcnt <= 0; 724 reset_crc_sig <= '1'; 560 725 FTU_rs485_control_State <= RECEIVE; 561 726 end if; … … 604 769 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 605 770 txcnt <= txcnt + 1; 606 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!771 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 607 772 tx_start_sig <= '1'; 608 773 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 609 774 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 610 775 txcnt <= txcnt + 1; 611 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!776 tx_data_sig <= crc_sig; 612 777 tx_start_sig <= '1'; 613 778 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 614 779 else -- transmission finished 615 780 txcnt <= 0; 781 reset_crc_sig <= '1'; 616 782 FTU_rs485_control_State <= RECEIVE; 617 783 end if; … … 755 921 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 756 922 txcnt <= txcnt + 1; 757 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!923 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 758 924 tx_start_sig <= '1'; 759 925 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 760 926 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 761 927 txcnt <= txcnt + 1; 762 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!928 tx_data_sig <= crc_sig; 763 929 tx_start_sig <= '1'; 764 930 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 765 931 else -- transmission finished 766 932 txcnt <= 0; 933 reset_crc_sig <= '1'; 767 934 FTU_rs485_control_State <= RECEIVE; 768 935 end if; … … 856 1023 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 857 1024 txcnt <= txcnt + 1; 858 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1025 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 859 1026 tx_start_sig <= '1'; 860 1027 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 861 1028 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 862 1029 txcnt <= txcnt + 1; 863 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1030 tx_data_sig <= crc_sig; 864 1031 tx_start_sig <= '1'; 865 1032 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 866 1033 else -- transmission finished 867 1034 txcnt <= 0; 1035 reset_crc_sig <= '1'; 868 1036 FTU_rs485_control_State <= RECEIVE; 869 1037 end if; … … 947 1115 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 948 1116 txcnt <= txcnt + 1; 949 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1117 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 950 1118 tx_start_sig <= '1'; 951 1119 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 952 1120 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 953 1121 txcnt <= txcnt + 1; 954 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1122 tx_data_sig <= crc_sig; 955 1123 tx_start_sig <= '1'; 956 1124 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 957 1125 else -- transmission finished 958 1126 txcnt <= 0; 1127 reset_crc_sig <= '1'; 959 1128 FTU_rs485_control_State <= RECEIVE; 960 1129 end if; … … 1008 1177 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1009 1178 txcnt <= txcnt + 1; 1010 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1179 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 1011 1180 tx_start_sig <= '1'; 1012 1181 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 1013 1182 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 1014 1183 txcnt <= txcnt + 1; 1015 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1184 tx_data_sig <= crc_sig; 1016 1185 tx_start_sig <= '1'; 1017 1186 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 1018 1187 else -- transmission finished 1019 1188 txcnt <= 0; 1189 reset_crc_sig <= '1'; 1020 1190 FTU_rs485_control_State <= RECEIVE; 1021 1191 end if; … … 1026 1196 1027 1197 when PING_PONG_TRANSMIT => 1198 crc_enable_sig <= '0'; 1028 1199 if tx_busy_sig = '0' then 1029 1200 if txcnt = 0 then -- start delimiter … … 1099 1270 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1100 1271 txcnt <= txcnt + 1; 1101 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1272 tx_data_sig <= conv_std_logic_vector(crc_error_cnt_sig, 8); 1102 1273 tx_start_sig <= '1'; 1103 1274 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1104 1275 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 1105 1276 txcnt <= txcnt + 1; 1106 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!!1277 tx_data_sig <= crc_sig; 1107 1278 tx_start_sig <= '1'; 1108 1279 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1109 1280 else -- transmission finished 1110 1281 txcnt <= 0; 1282 reset_crc_sig <= '1'; 1111 1283 FTU_rs485_control_State <= RECEIVE; 1112 1284 end if; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r10047 r10050 39 39 block_valid : IN std_logic; 40 40 brd_add : IN std_logic_vector(5 downto 0); 41 crc_error_cnt : OUT integer range 0 to 255 := 0; 41 42 int_new_DACs : OUT std_logic := '0'; 42 43 int_new_enables : OUT std_logic := '0'; … … 56 57 57 58 signal block_valid_sr : std_logic_vector(3 downto 0) := (others => '0'); 59 signal reset_crc_sig : std_logic := '0'; 60 signal crc_enable_sig : std_logic := '0'; 61 signal crc_match_sig : std_logic := '0'; 62 signal data_block_sig : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0'); 63 signal crc_error_cntr : integer range 0 to 255 := 0; 58 64 59 65 signal dac_array_rs485_out_sig : dac_array_type := DEFAULT_DAC; … … 61 67 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0) := conv_std_logic_vector(DEFAULT_PRESCALING,8); 62 68 63 type FTU_rs485_interpreter_StateType is ( WAIT_FOR_DATA, CHECK_HEADER, DECODE);69 type FTU_rs485_interpreter_StateType is (INIT, WAIT_FOR_DATA, WAIT_CRC, CHECK_CRC, CHECK_HEADER, DECODE); 64 70 signal FTU_rs485_interpreter_State : FTU_rs485_interpreter_StateType; 71 72 component ucrc_par 73 generic( 74 POLYNOMIAL : std_logic_vector; 75 INIT_VALUE : std_logic_vector; 76 DATA_WIDTH : integer range 2 to 256; 77 SYNC_RESET : integer range 0 to 1 78 ); 79 port( 80 clk_i : in std_logic; 81 rst_i : in std_logic; 82 clken_i : in std_logic; 83 data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); 84 match_o : out std_logic; 85 crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0) 86 ); 87 end component; 65 88 66 89 begin 67 90 91 Inst_ucrc_par : ucrc_par 92 generic map( 93 POLYNOMIAL => CRC_POLYNOMIAL, 94 INIT_VALUE => CRC_INIT_VALUE, 95 DATA_WIDTH => 224, 96 SYNC_RESET => 1 97 ) 98 port map( 99 clk_i => clk, 100 rst_i => reset_crc_sig, 101 clken_i => crc_enable_sig, 102 data_i => data_block_sig, 103 match_o => crc_match_sig, 104 crc_o => open 105 ); 106 68 107 FTU_rs485_interpreter_FSM: process (clk) 69 108 begin 70 109 if Rising_edge(clk) then 71 110 case FTU_rs485_interpreter_State is 111 112 when INIT => 113 reset_crc_sig <= '1'; 114 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 72 115 73 when WAIT_FOR_DATA => -- default state, waiting for valid 16-byte block116 when WAIT_FOR_DATA => -- default state, waiting for valid 28-byte block 74 117 block_valid_sr <= block_valid_sr(2 downto 0) & block_valid; 75 118 int_new_DACs <= '0'; … … 82 125 int_ping_pong <= '0'; 83 126 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal 127 crc_enable_sig <= '1'; 128 data_block_sig <= data_block; 129 FTU_rs485_interpreter_State <= WAIT_CRC; 130 else 131 crc_enable_sig <= '0'; 132 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 133 end if; 134 reset_crc_sig <= '0'; 135 136 when WAIT_CRC => 137 crc_enable_sig <= '0'; 138 FTU_rs485_interpreter_State <= CHECK_CRC; 139 140 when CHECK_CRC => 141 reset_crc_sig <= '1'; 142 if (crc_match_sig = '1') then 84 143 FTU_rs485_interpreter_State <= CHECK_HEADER; 144 crc_error_cnt <= crc_error_cntr; 145 crc_error_cntr <= 0; 85 146 else 86 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 87 end if; 88 147 if crc_error_cntr < 255 then 148 crc_error_cntr <= crc_error_cntr + 1; 149 end if; 150 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 151 end if; 152 89 153 when CHECK_HEADER => -- check start delimiter and addresses 90 154 int_new_DACs <= '0'; … … 103 167 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 104 168 end if; 105 169 reset_crc_sig <= '0'; 170 106 171 when DECODE => -- decode instruction 107 172 if(data_block(39 downto 32) = "00000000") then -- set DACs
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