Changeset 10051 for firmware


Ignore:
Timestamp:
Nov 10, 2010, 4:21:52 PM (9 years ago)
Author:
weitzel
Message:
some code cleaning and more comments for FTU firmware
Location:
firmware/FTU
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTU/FTU_control.vhd

    r10050 r10051  
    201201            ram_dia_sig <= (others => '0');
    202202            FTU_control_State <= INIT_RAM;
    203           --elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then  -- default CRC errors
    204             --ram_dia_sig <= (others => '0');
    205             --FTU_control_State <= INIT_RAM;
    206203          elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then  -- empty RAM cells
    207204            ram_dia_sig <= (others => '0');
     
    276273          end if;
    277274
    278         when CONFIG_COUNTER =>
     275        when CONFIG_COUNTER =>  -- set prescaling value for counters
    279276          wait_cntr <= wait_cntr + 1;
    280277          new_rates_busy <= '1';
     
    296293          end if;
    297294         
    298         when CONFIG_ENABLE =>
     295        when CONFIG_ENABLE =>  -- set enable patterns for sum trigger stage
    299296          ram_enable_cntr <= ram_enable_cntr + 1;
    300297          new_rates_busy <= '1';
     
    302299            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
    303300            FTU_control_State <= CONFIG_ENABLE;
    304           --elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
    305             --ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
    306             --enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
    307             --enables_ready <= '1';
    308             --FTU_control_State <= CONFIG_ENABLE;
    309301          elsif (ram_enable_cntr < NO_OF_ENABLE) then
    310302            ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
     
    327319          end if;
    328320         
    329         when CONFIG_DAC =>
     321        when CONFIG_DAC =>  -- start to set thresholds for sum trigger patches
    330322          new_rates_busy <= '1';
    331323          ram_dac_cntr <= ram_dac_cntr + 1;
     
    354346          end if;
    355347         
    356         when CONFIG_DAC_WAIT =>
     348        when CONFIG_DAC_WAIT =>  -- wait until setting of thresholds has finished
    357349          if (config_ready = '1') then
    358350            new_DACs_in_RAM <= '0';
     
    591583          end if;
    592584
    593         when DO_PING_PONG =>  -- just answer to FTM
     585        when DO_PING_PONG =>  -- answer to FTM and send DNA
    594586          wait_cntr <= wait_cntr + 1;
    595587          if (wait_cntr = 0) then
     
    605597    end if;
    606598  end process FTU_control_FSM;
    607 
    608   --detect_new_rates: process(new_rates, new_rates_busy)
    609   --begin
    610     --if(new_rates_busy = '1') then
    611       --new_rates_sig <= '0';
    612     --elsif rising_edge(new_rates) then
    613       --new_rates_sig <= '1';
    614     --end if;
    615   --end process detect_new_rates;
    616599
    617600  detect_new_rates: process(clk_50MHz)
  • firmware/FTU/FTU_top.vhd

    r10037 r10051  
    5858    sck           : OUT STD_LOGIC;                  -- serial clock to DAC
    5959    mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
    60     clr           : OUT STD_LOGIC;                  -- clear signal to DAC
     60    clr           : OUT STD_LOGIC;                  -- clear signal to DAC, not used
    6161    cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
    6262   
  • firmware/FTU/ftu_definitions.vhd

    r10050 r10051  
    6060  constant CNTR_FREQ_DIVIDER : integer :=    25000;  -- for simulation, should normally be 1
    6161   
    62   --32byte dual-port RAM, port A: 8byte, port B: 16byte
     62  --64byte dual-port RAM, port A: 8byte, port B: 16byte
    6363  constant RAM_ADDR_WIDTH_A : integer := 6;
    6464  constant RAM_ADDR_WIDTH_B : integer := 5;
  • firmware/FTU/rs485/FTU_rs485_control.vhd

    r10050 r10051  
    247247      case FTU_rs485_control_State is
    248248
    249         when INIT =>
     249        when INIT =>  -- reset CRC register
    250250          reset_crc_sig <= '1';
    251251          FTU_rs485_control_State <= RECEIVE;
     
    373373          end if;
    374374
    375         when SET_DAC_WAIT_2 =>
     375        when SET_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
    376376          crc_enable_sig <= '0';
    377377          FTU_rs485_control_State <= SET_DAC_TRANSMIT;
     
    396396          end if;
    397397
    398         when SET_ENABLE_WAIT_2 =>
     398        when SET_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
    399399          crc_enable_sig <= '0';
    400400          FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
     
    417417          end if;
    418418
    419         when SET_PRESCALING_WAIT_2 =>
     419        when SET_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
    420420          crc_enable_sig <= '0';
    421421          FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
     
    444444          end if;
    445445
    446         when READ_RATES_WAIT_2 =>
     446        when READ_RATES_WAIT_2 =>  -- wait one cycle for CRC calculation
    447447          crc_enable_sig <= '0';
    448448          FTU_rs485_control_State <= READ_RATES_TRANSMIT;
     
    468468          end if;
    469469
    470         when READ_DAC_WAIT_2 =>
     470        when READ_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
    471471          crc_enable_sig <= '0';
    472472          FTU_rs485_control_State <= READ_DAC_TRANSMIT;
     
    491491          end if;
    492492
    493         when READ_ENABLE_WAIT_2 =>
     493        when READ_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
    494494          crc_enable_sig <= '0';
    495495          FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
     
    512512          end if;
    513513
    514         when READ_PRESCALING_WAIT_2 =>
     514        when READ_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
    515515          crc_enable_sig <= '0';
    516516          FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
     
    532532          end if;
    533533
    534         when PING_PONG_WAIT_2 =>
     534        when PING_PONG_WAIT_2 =>  -- wait one cycle for CRC calculation
    535535          crc_enable_sig <= '0';
    536536          FTU_rs485_control_State <= PING_PONG_TRANSMIT;
  • firmware/FTU/rs485/FTU_rs485_interpreter.vhd

    r10050 r10051  
    110110      case FTU_rs485_interpreter_State is
    111111
    112         when INIT =>
     112        when INIT =>  -- reset CRC register
    113113          reset_crc_sig <= '1';
    114114          FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
     
    134134          reset_crc_sig <= '0';
    135135
    136         when WAIT_CRC =>
     136        when WAIT_CRC =>  -- wait one cycle for CRC calculation
    137137          crc_enable_sig <= '0';
    138138          FTU_rs485_interpreter_State <= CHECK_CRC;
    139139         
    140         when CHECK_CRC =>
     140        when CHECK_CRC =>  -- check whether CRC matches
    141141          reset_crc_sig  <= '1';
    142142          if (crc_match_sig = '1') then
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