Changeset 10051

Timestamp:

11/10/10 16:21:52 (14 years ago)

Author:

weitzel

Message:

some code cleaning and more comments for FTU firmware

Location:

firmware/FTU

Files:

• FTU_control.vhd (modified) (8 diffs)
• FTU_top.vhd (modified) (1 diff)
• ftu_definitions.vhd (modified) (1 diff)
• rs485/FTU_rs485_control.vhd (modified) (9 diffs)
• rs485/FTU_rs485_interpreter.vhd (modified) (2 diffs)

firmware/FTU/FTU_control.vhd

@@ -201 +201 @@
             ram_dia_sig <= (others => '0');
             FTU_control_State <= INIT_RAM;
-          --elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then  -- default CRC errors
-            --ram_dia_sig <= (others => '0');
-            --FTU_control_State <= INIT_RAM;
           elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then  -- empty RAM cells
             ram_dia_sig <= (others => '0');
@@ -276 +273 @@
           end if;
 
-        when CONFIG_COUNTER =>
+        when CONFIG_COUNTER =>  -- set prescaling value for counters
           wait_cntr <= wait_cntr + 1;
           new_rates_busy <= '1';
@@ -296 +293 @@
           end if;
           
-        when CONFIG_ENABLE =>
+        when CONFIG_ENABLE =>  -- set enable patterns for sum trigger stage
           ram_enable_cntr <= ram_enable_cntr + 1;
           new_rates_busy <= '1';
@@ -302 +299 @@
             ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
             FTU_control_State <= CONFIG_ENABLE;
-          --elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
-            --ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
-            --enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
-            --enables_ready <= '1';
-            --FTU_control_State <= CONFIG_ENABLE;
           elsif (ram_enable_cntr < NO_OF_ENABLE) then
             ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
@@ -327 +319 @@
           end if;
           
-        when CONFIG_DAC =>
+        when CONFIG_DAC =>  -- start to set thresholds for sum trigger patches
           new_rates_busy <= '1';
           ram_dac_cntr <= ram_dac_cntr + 1;
@@ -354 +346 @@
           end if;
           
-        when CONFIG_DAC_WAIT =>
+        when CONFIG_DAC_WAIT =>  -- wait until setting of thresholds has finished
           if (config_ready = '1') then
             new_DACs_in_RAM <= '0';
@@ -591 +583 @@
           end if;
 
-        when DO_PING_PONG =>  -- just answer to FTM 
+        when DO_PING_PONG =>  -- answer to FTM and send DNA
           wait_cntr <= wait_cntr + 1;
           if (wait_cntr = 0) then
@@ -605 +597 @@
     end if;
   end process FTU_control_FSM;
-
-  --detect_new_rates: process(new_rates, new_rates_busy)
-  --begin
-    --if(new_rates_busy = '1') then
-      --new_rates_sig <= '0';
-    --elsif rising_edge(new_rates) then
-      --new_rates_sig <= '1';
-    --end if;
-  --end process detect_new_rates;
 
   detect_new_rates: process(clk_50MHz)

firmware/FTU/FTU_top.vhd

@@ -58 +58 @@
     sck           : OUT STD_LOGIC;                  -- serial clock to DAC
     mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
-    clr           : OUT STD_LOGIC;                  -- clear signal to DAC
+    clr           : OUT STD_LOGIC;                  -- clear signal to DAC, not used
     cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
     

firmware/FTU/ftu_definitions.vhd

@@ -60 +60 @@
   constant CNTR_FREQ_DIVIDER : integer :=    25000;  -- for simulation, should normally be 1 
     
-  --32byte dual-port RAM, port A: 8byte, port B: 16byte
+  --64byte dual-port RAM, port A: 8byte, port B: 16byte
   constant RAM_ADDR_WIDTH_A : integer := 6;
   constant RAM_ADDR_WIDTH_B : integer := 5;

firmware/FTU/rs485/FTU_rs485_control.vhd

@@ -247 +247 @@
       case FTU_rs485_control_State is
 
-        when INIT =>
+        when INIT =>  -- reset CRC register
           reset_crc_sig <= '1';
           FTU_rs485_control_State <= RECEIVE;
@@ -373 +373 @@
           end if;
 
-        when SET_DAC_WAIT_2 =>
+        when SET_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_DAC_TRANSMIT;
@@ -396 +396 @@
           end if;
 
-        when SET_ENABLE_WAIT_2 =>
+        when SET_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
@@ -417 +417 @@
           end if;
 
-        when SET_PRESCALING_WAIT_2 =>
+        when SET_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
@@ -444 +444 @@
           end if;
 
-        when READ_RATES_WAIT_2 =>
+        when READ_RATES_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_RATES_TRANSMIT;
@@ -468 +468 @@
           end if;
 
-        when READ_DAC_WAIT_2 =>
+        when READ_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_DAC_TRANSMIT;
@@ -491 +491 @@
           end if;
 
-        when READ_ENABLE_WAIT_2 =>
+        when READ_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
@@ -512 +512 @@
           end if;
 
-        when READ_PRESCALING_WAIT_2 =>
+        when READ_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
@@ -532 +532 @@
           end if;
 
-        when PING_PONG_WAIT_2 =>
+        when PING_PONG_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= PING_PONG_TRANSMIT;

firmware/FTU/rs485/FTU_rs485_interpreter.vhd

@@ -110 +110 @@
       case FTU_rs485_interpreter_State is
 
-        when INIT =>
+        when INIT =>  -- reset CRC register
           reset_crc_sig <= '1';
           FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
@@ -134 +134 @@
           reset_crc_sig <= '0';
 
-        when WAIT_CRC =>
+        when WAIT_CRC =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_interpreter_State <= CHECK_CRC;
           
-        when CHECK_CRC =>
+        when CHECK_CRC =>  -- check whether CRC matches
           reset_crc_sig  <= '1';
           if (crc_match_sig = '1') then