Changeset 10047 for firmware


Ignore:
Timestamp:
Oct 29, 2010, 1:43:30 PM (9 years ago)
Author:
weitzel
Message:
timeout implemented for FTU RS485 communication; new version of FTU docu
Location:
firmware/FTU
Files:
3 added
3 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTU/ftu_definitions.vhd

    r10037 r10047  
    7878  --communication with FTM
    7979  constant RS485_BAUD_RATE   : integer := 250000;  -- bits / sec in our case
     80  constant RS485_TIMEOUT     : integer := (INT_CLK_FREQUENCY * 2) / 1000;  -- 2ms @ 50MHz (100000 clk periods)
    8081  constant RS485_BLOCK_WIDTH : integer := 224;     -- 28 byte protocol
    8182  constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000";  -- start delimiter
  • firmware/FTU/rs485/FTU_rs485_interpreter.vhd

    r10037 r10047  
    9292          int_new_prescaling  <= '0';
    9393          int_read_rates      <= '0';
    94           int_read_DACs       <= '0'; 
    95           int_read_enables    <= '0'; 
     94          int_read_DACs       <= '0';
     95          int_read_enables    <= '0';
    9696          int_read_prescaling <= '0';
    9797          int_ping_pong       <= '0';
  • firmware/FTU/rs485/FTU_rs485_receiver.vhd

    r9928 r10047  
    1010--
    1111-- modified for FTU design by Q. Weitzel, 13 September 2010
     12-- timeout added, Q. Weitzel, 26 October 2010
    1213--
    1314
     
    3637ARCHITECTURE beha OF FTU_rs485_receiver IS
    3738 
    38   signal rxcnt : integer range 0 to RX_BYTES := 0;
    39   signal rxsr : std_logic_vector(3 downto 0) := (others => '0');
     39  signal rxcnt       : integer range 0 to RX_BYTES := 0;
     40  signal rxsr        : std_logic_vector(3 downto 0) := (others => '0');
     41  signal timeout_cnt : integer range 0 to RS485_TIMEOUT + 1 := 0;
    4042 
    4143BEGIN
    4244 
    43   rx_data_proc: process (rec_clk)
     45  rx_data_proc : process(rec_clk)
    4446  begin
    4547    if rising_edge(rec_clk) then
    4648      rxsr <= rxsr(2 downto 0) & rec_den;
    47       if (rxsr(3 downto 2) = "01") then -- identify rising edge
    48         rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
    49         rxcnt <= rxcnt + 1;
    50         if (rxcnt < RX_BYTES - 1) then
    51           rec_valid <= '0';
    52         else
    53           rxcnt <= 0;
    54           rec_valid <= '1';
     49      if (timeout_cnt = RS485_TIMEOUT) then
     50        rec_dout <= (others => '0');
     51        rxcnt <= 0;
     52        rec_valid <= '0';
     53      else       
     54        if (rxsr(3 downto 2) = "01") then -- identify rising edge
     55          rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
     56          rxcnt <= rxcnt + 1;
     57          if (rxcnt < RX_BYTES - 1) then
     58            rec_valid <= '0';
     59          else
     60            rxcnt <= 0;
     61            rec_valid <= '1';
     62          end if;
    5563        end if;
    5664      end if;
     65    end if;
     66  end process rx_data_proc;
     67
     68  rx_timeout_proc : process(rec_clk)
     69  begin
     70    if rising_edge(rec_clk) then
     71      if (rxcnt > 0) then
     72        timeout_cnt <= timeout_cnt + 1;
     73      else
     74        timeout_cnt <= 0;
     75      end if;
    5776    end if; 
    58   end process rx_data_proc;
    59    
     77  end process rx_timeout_proc;
     78 
    6079END ARCHITECTURE beha;
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