Changeset 10051 for firmware/FTU/rs485

Timestamp:

11/10/10 16:21:52 (14 years ago)

Author:

weitzel

Message:

some code cleaning and more comments for FTU firmware

Location:

firmware/FTU/rs485

Files:

• FTU_rs485_control.vhd (modified) (9 diffs)
• FTU_rs485_interpreter.vhd (modified) (2 diffs)

firmware/FTU/rs485/FTU_rs485_control.vhd

@@ -247 +247 @@
       case FTU_rs485_control_State is
 
-        when INIT =>
+        when INIT =>  -- reset CRC register
           reset_crc_sig <= '1';
           FTU_rs485_control_State <= RECEIVE;
@@ -373 +373 @@
           end if;
 
-        when SET_DAC_WAIT_2 =>
+        when SET_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_DAC_TRANSMIT;
@@ -396 +396 @@
           end if;
 
-        when SET_ENABLE_WAIT_2 =>
+        when SET_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_ENABLE_TRANSMIT;
@@ -417 +417 @@
           end if;
 
-        when SET_PRESCALING_WAIT_2 =>
+        when SET_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT;
@@ -444 +444 @@
           end if;
 
-        when READ_RATES_WAIT_2 =>
+        when READ_RATES_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_RATES_TRANSMIT;
@@ -468 +468 @@
           end if;
 
-        when READ_DAC_WAIT_2 =>
+        when READ_DAC_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_DAC_TRANSMIT;
@@ -491 +491 @@
           end if;
 
-        when READ_ENABLE_WAIT_2 =>
+        when READ_ENABLE_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_ENABLE_TRANSMIT;
@@ -512 +512 @@
           end if;
 
-        when READ_PRESCALING_WAIT_2 =>
+        when READ_PRESCALING_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT;
@@ -532 +532 @@
           end if;
 
-        when PING_PONG_WAIT_2 =>
+        when PING_PONG_WAIT_2 =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_control_State <= PING_PONG_TRANSMIT;

firmware/FTU/rs485/FTU_rs485_interpreter.vhd

@@ -110 +110 @@
       case FTU_rs485_interpreter_State is
 
-        when INIT =>
+        when INIT =>  -- reset CRC register
           reset_crc_sig <= '1';
           FTU_rs485_interpreter_State <= WAIT_FOR_DATA;
@@ -134 +134 @@
           reset_crc_sig <= '0';
 
-        when WAIT_CRC =>
+        when WAIT_CRC =>  -- wait one cycle for CRC calculation
           crc_enable_sig <= '0';
           FTU_rs485_interpreter_State <= CHECK_CRC;
           
-        when CHECK_CRC =>
+        when CHECK_CRC =>  -- check whether CRC matches
           reset_crc_sig  <= '1';
           if (crc_match_sig = '1') then