Changeset 10058 for firmware


Ignore:
Timestamp:
Nov 23, 2010, 2:44:36 PM (9 years ago)
Author:
weitzel
Message:
Some modifications and a test bench for FTM_test8
Location:
firmware/FTM/test_firmware/FTM_test8
Files:
1 added
2 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd

    r10046 r10058  
    1616-- Revision:
    1717-- Revision 0.01 - File Created
     18-- Revision 0.02 - Some modifications, November 15, 2010, Q. Weitzel
    1819-- Additional Comments:
    1920--
     
    2526use IEEE.STD_LOGIC_UNSIGNED.ALL;
    2627
    27 
    2828Library UNISIM;
    2929use UNISIM.vcomponents.all;
     
    3434--use UNISIM.VComponents.all;
    3535
    36 
    3736--  library FTM_definitions_test3;
    3837--  USE FTM_definitions_test3.ftm_array_types.all;
    3938
    40 
    41 
    4239entity FTM_test8 is
    4340  port(
    44 
    4541   
    4642-- Clock
    4743   clk   : IN  STD_LOGIC;                     -- external clock from
    4844                                              -- oscillator U47
    49 
    5045-- connection to the WIZnet W5300 ethernet controller
    5146-- on IO-Bank 1
     
    123118   LED_gn   : out STD_LOGIC_VECTOR(1 downto 0);    -- green
    124119
    125    
    126    
    127120-- Clock conditioner LMK03000
    128121-- on IO-Bank 3
     
    135128--   LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                 
    136129   
    137  
    138 
    139 
    140130-- various RS-485 Interfaces
    141131-- on IO-Bank 3
     
    280270end FTM_test8;
    281271
    282 
    283272architecture Behavioral of FTM_test8 is
    284273
    285 
    286 
    287 
    288  
    289         COMPONENT FTM_Test8_dcm
    290         PORT(
    291                 CLKIN_IN : IN std_logic;
    292                 RST_IN : IN std_logic;         
    293                 CLKFX_OUT : OUT std_logic;
    294                 CLK0_OUT : OUT std_logic;
    295                 LOCKED_OUT : OUT std_logic
    296                 );
    297         END COMPONENT;
    298 
    299 
     274  COMPONENT FTM_Test8_dcm
     275    PORT(
     276      CLKIN_IN : IN std_logic;
     277      RST_IN : IN std_logic;         
     278      CLKFX_OUT : OUT std_logic;
     279      CLK0_OUT : OUT std_logic;
     280      LOCKED_OUT : OUT std_logic
     281      );
     282  END COMPONENT;
    300283
    301284  component FTM_test8_rs485_interface
    302285    GENERIC(
    303       CLOCK_FREQUENCY : integer := 50000000;      -- Hertz
    304       BAUD_RATE       : integer := 250000         -- bits / sec
     286      CLOCK_FREQUENCY : integer;      -- Hertz
     287      BAUD_RATE       : integer       -- bits / sec
    305288    );
    306289    PORT(
     
    313296      -- FPGA
    314297      rx_data  : OUT    std_logic_vector(7 DOWNTO 0);
    315    --  rx_busy  : OUT    std_logic := '0';
     298      -- rx_busy  : OUT    std_logic := '0';
    316299      rx_valid : OUT    std_logic := '0';
    317300      tx_data  : IN     std_logic_vector(7 DOWNTO 0);
     
    323306  signal reset_sig   : STD_LOGIC := '0'; -- initialize reset to 0 at power up
    324307  signal clk_50M_sig : STD_LOGIC;
    325 
    326308 
    327309 -- signal enable_sig : enable_array_type := DEFAULT_ENABLE;                 
    328 
    329310 
    330311  signal rx_en_sig    : STD_LOGIC := '0';
     
    339320  signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType;
    340321
    341 
    342 
    343 
    344 
    345322begin
    346323
    347 Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP(
    348                 CLKIN_IN => clk,
    349                 RST_IN => reset_sig,
    350                 CLKFX_OUT => clk_50M_sig,
    351                 CLK0_OUT => open,
    352                 LOCKED_OUT => open
    353         );
    354 
    355 
     324  Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP(
     325    CLKIN_IN => clk,
     326    RST_IN => reset_sig,
     327    CLKFX_OUT => clk_50M_sig,
     328    CLK0_OUT => open,
     329    LOCKED_OUT => open
     330  );
    356331
    357332  Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface
     
    359334      CLOCK_FREQUENCY => 50000000,
    360335  --  BAUD_RATE       => 10000000       --simulation
    361       BAUD_RATE       => 25000          --implement
     336      BAUD_RATE       => 250000          --implement
    362337    )
    363338    port map(
     
    376351      tx_start => '0'
    377352    );
    378  
    379 --  enables_A <= enable_sig(0)(8 downto 0);
    380 --  enables_B <= enable_sig(1)(8 downto 0);
    381 --  enables_C <= enable_sig(2)(8 downto 0);
    382 --  enables_D <= enable_sig(3)(8 downto 0);
    383  
    384  
     353   
    385354  Bus1_Rx_En <= rx_en_sig;
    386355  Bus1_Tx_En <= tx_en_sig;
    387356  Bus1_TxD_0 <= tx_sig;
    388357  rx_sig     <= Bus1_RxD_0;
    389 
    390 
    391 
    392358 
    393359  --FTM main state machine (two-process implementation)
     
    405371    case FTM_test8_State is
    406372      when INIT =>
    407         reset_sig <= '0';
    408        
    409                   LED_red <= ("0000");
    410                  
     373        reset_sig <= '0';       
     374        LED_red <= "0000";       
    411375        if (rx_data_sig = "00110001" and rx_valid_sig = '1') then
    412376          FTM_test8_NextState <= RUN1;
     
    422386      when RUN1 =>
    423387        reset_sig <= '0';
    424        
    425        -- enable_sig <= ("0000000000000000","0000000111111111","0000000111111111","0000000111111111");
    426         LED_red <= ("0001");
    427        
     388        LED_red <= "0001";
    428389        if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
    429390          FTM_test8_NextState <= INIT;
     
    439400      when RUN2 =>
    440401        reset_sig <= '0';
    441        
    442       --  enable_sig <= ("0000000111111111","0000000000000000","0000000111111111","0000000111111111");
    443         LED_red <= ("0010");
    444        
     402        LED_red <= "0010";       
    445403        if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
    446404          FTM_test8_NextState <= INIT;
     
    456414      when RUN3 =>
    457415        reset_sig <= '0';
    458        
    459      --   enable_sig <= ("0000000111111111","0000000111111111","0000000000000000","0000000111111111");
    460         LED_red <= ("0100");
    461        
     416        LED_red <= "0100";
    462417        if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
    463418          FTM_test8_NextState <= INIT;
     
    473428      when RUN4 =>
    474429        reset_sig <= '0';
    475        
    476       --  enable_sig <= ("0000000111111111","0000000111111111","0000000111111111","0000000000000000");
    477         LED_red <= ("1000");
    478        
     430        LED_red <= "1000";       
    479431        if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
    480432          FTM_test8_NextState <= INIT;
     
    491443  end process FTM_test8_C_logic;
    492444 
    493 
    494 
    495 
    496 
    497 LED_ye  <= ("11");
    498 LED_gn  <= ("11");
    499 
    500 
    501  
     445  LED_ye  <= "11";
     446  LED_gn  <= "11";
    502447
    503448end Behavioral;
  • firmware/FTM/test_firmware/FTM_test8/ftm_board_test8.ucf

    r10046 r10058  
    173173
    174174# yellow
    175 # NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    176 # NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
     175 NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
     176 NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    177177
    178178# green
    179 # NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    180 # NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
     179 NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0 
     180 NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    181181
    182182
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