Changeset 10067 for firmware


Ignore:
Timestamp:
Dec 8, 2010, 4:14:34 PM (9 years ago)
Author:
weitzel
Message:
Skeleton of FTM_top and FTM_top_tb added
Location:
firmware/FTM
Files:
2 added
1 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/ftm_board.ucf

    r9879 r10067  
    4848NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
    4949
    50 # W5300 controll signals
     50# W5300 control signals
    5151# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
    5252# W_CS is also routed to testpoint JP7
     
    8383
    8484# temperature sensors
    85 NET SIO        LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
     85NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
    8686NET TS_CS<0>  LOC  = H21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select0
    8787NET TS_CS<1>  LOC  = J21  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select1
     
    151151NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
    152152NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
    153 NET Veto          LOC  = E4  | IOSTANDARD=LVCMOS33; #
    154 NET NIM_In<0>     LOC  = D3  | IOSTANDARD=LVCMOS33; #
    155 NET NIM_In<1>     LOC  = F4  | IOSTANDARD=LVCMOS33; #
    156 NET NIM_In<2>     LOC  = E3  | IOSTANDARD=LVCMOS33; #
     153NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
     154NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
     155NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
     156NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
    157157
    158158# on IO-Bank 0
    159 NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33; # input with global clock buffer
    160                                                      # available
     159# input pin with global clock buffer available
     160NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
    161161
    162162
     
    238238NET Aux_Tx_D     LOC  = Y2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    239239NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
    240 NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
    241                                                                   # Trigger-ID
     240NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
    242241
    243242# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
     
    286285# conversion stage
    287286#######################################################
    288 NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES+  Reset
    289 NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  RES-  IO-Bank 0
    290 
    291 NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33  | DIFF_TERM="False"; #   TRG+ Trigger
    292 NET TRG_n      LOC  = A15  | IOSTANDARD=LVDS_33   | DIFF_TERM="False";  #  TRG- IO-Bank 0
    293 
    294 NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; # TIM_Run+ Time Marker
    295 NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33  | DIFF_TERM="False" ; #  TIM_Run-
    296                                                                         #  on IO-Bank2
    297 NET TIM_Sel    LOC  = AD22 | IOSTANDARD=LVCMOS33;   # Time Marker selector
    298                                                     # IO-Bank 2
     287NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
     288NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
     289
     290NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
     291NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
     292
     293NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
     294NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
     295
     296NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
     297
    299298NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
    300299
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