Changeset 10138 for firmware


Ignore:
Timestamp:
Feb 8, 2011, 11:54:22 AM (9 years ago)
Author:
neise
Message:
 
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10121 r10138  
    172172          when CONFIG7 =>
    173173            if (drs_srin_write_ready = '1') then
     174              drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers
    174175              roi_max_int <= roi_max;
    175176              state_generate <= WRITE_DATA_IDLE;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd

    r10081 r10138  
    8585        when SRIN_WRITE_END =>
    8686          SRCLK_EN <= '0';
    87           srin_out <= '1';
     87          srin_out <= '0';
    8888          srin_write_ready <= '1';
    8989          srin_write_ack <= '0';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10129 r10138  
    163163
    164164-- DRS Registers
     165  constant DRS_ADDR_IDLE : std_logic_vector := "1001";
    165166  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 
    166167  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10137 r10138  
    144144signal local_fifo_channels : std_logic_vector (3 downto 0);
    145145
    146 signal data_valid_int : std_logic := '0';
     146
    147147
    148148
     
    162162        -- signals for synching in asynchronous input signals
    163163        ------------------------------------------------------------------------------
    164         signal w5300_interrupt_sr : std_logic_vector(1 downto 0);
     164        signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
     165         --?? not sure if this init value is good
     166         -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles.
     167         -- I hope!
     168        signal data_valid_sr : std_logic_vector(1 downto 0) := "00";
    165169        ------------------------------------------------------------------------------
    166170
     
    187191                -- synch asynchronous input in:
    188192                w5300_interrupt_sr <= w5300_interrupt_sr(1) & int;
     193                data_valid_sr <= data_valid_sr(1) & data_valid;
    189194               
    190195                        -- interrupt is handled synchronously
    191196                        -- W5300 pulls low its interrpt line in case of:
    192                         --      ??? I don't know ... connection loss ???
     197                        --      When Sockets time out and
     198                        -- When sockets receive disconnection request.
    193199                       
    194200                        if (w5300_interrupt_sr = "01") and (interrupt_ignore = '0') then
     
    560566                                            state_init <= MAIN;
    561567                                          end if;
    562                                        
    563           -- main "loop"
     568                                        -----------------------------------------
     569          -- MAIN "loop" --------------------------
     570          -----------------------------------------
     571         
    564572                                        when MAIN =>
    565573                                          socks_waiting <= '0';
     
    573581            data_valid_ack <= '0';
    574582            state_init <= MAIN1;
    575             data_valid_int <= data_valid;
     583            --data_valid_int <= data_valid;
    576584                                        when MAIN1 =>
    577585            if (chk_recv_cntr = 1000) then
     
    586594          when MAIN2 =>
    587595            busy <= '0';
    588                                           if (data_valid = '1') then
    589                                             data_valid_int <= '0';
     596                                          --if (data_valid = '1') then
     597                                          if (data_valid_sr = "01" or data_valid_sr = "11") then
     598                                            --data_valid_int <= '0';
    590599                                            busy <= '1';
    591600              local_write_length <= write_length;
     
    607616            next_state <= MAIN;
    608617            state_init <= WRITE_DATA;
     618
     619            -----------------------------------------
     620            -- END OF MAIN         ------------------
     621            -----------------------------------------
     622
    609623                                         
    610624
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

    r10129 r10138  
    333333(vvPair
    334334variable "date"
    335 value "04.02.2011"
     335value "08.02.2011"
    336336)
    337337(vvPair
    338338variable "day"
    339 value "Fr"
     339value "Di"
    340340)
    341341(vvPair
    342342variable "day_long"
    343 value "Freitag"
     343value "Dienstag"
    344344)
    345345(vvPair
    346346variable "dd"
    347 value "04"
     347value "08"
    348348)
    349349(vvPair
     
    485485(vvPair
    486486variable "time"
    487 value "12:56:44"
     487value "11:06:22"
    488488)
    489489(vvPair
     
    577577)
    578578xt "-172000,106800,-128500,107600"
    579 st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
     579st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
     580"
    580581)
    581582)
     
    595596)
    596597xt "-172000,42800,-132000,43600"
    597 st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     598st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     599"
    598600)
    599601)
     
    613615)
    614616xt "-172000,62000,-139500,62800"
    615 st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
     617st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
     618"
    616619)
    617620)
     
    631634)
    632635xt "-172000,80400,-132000,81200"
    633 st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
     636st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
     637"
    634638)
    635639)
     
    649653)
    650654xt "-172000,81200,-139500,82000"
    651 st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
     655st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
     656"
    652657)
    653658)
     
    667672)
    668673xt "-172000,34400,-132000,35200"
    669 st "wiz_reset              : std_logic                                    := '1'"
     674st "wiz_reset              : std_logic                                    := '1'
     675"
    670676)
    671677)
     
    685691)
    686692xt "-172000,32000,-143500,32800"
    687 st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
     693st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
     694"
    688695)
    689696)
     
    703710)
    704711xt "-172000,36800,-143000,37600"
    705 st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
     712st "wiz_data               : std_logic_vector(15 DOWNTO 0)
     713"
    706714)
    707715)
     
    721729)
    722730xt "-172000,32800,-132000,33600"
    723 st "wiz_cs                 : std_logic                                    := '1'"
     731st "wiz_cs                 : std_logic                                    := '1'
     732"
    724733)
    725734)
     
    739748)
    740749xt "-172000,35200,-132000,36000"
    741 st "wiz_wr                 : std_logic                                    := '1'"
     750st "wiz_wr                 : std_logic                                    := '1'
     751"
    742752)
    743753)
     
    757767)
    758768xt "-172000,33600,-132000,34400"
    759 st "wiz_rd                 : std_logic                                    := '1'"
     769st "wiz_rd                 : std_logic                                    := '1'
     770"
    760771)
    761772)
     
    774785)
    775786xt "-172000,13600,-153500,14400"
    776 st "wiz_int                : std_logic"
     787st "wiz_int                : std_logic
     788"
    777789)
    778790)
     
    12911303fg "0,65535,0"
    12921304)
    1293 xt "0,65625,750,66375"
     1305xt "0,70625,750,71375"
    12941306)
    12951307tg (CPTG
     
    13011313va (VaSet
    13021314)
    1303 xt "-17300,65500,-1000,66500"
     1315xt "-17300,70500,-1000,71500"
    13041316st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    13051317ju 2
    1306 blo "-1000,66300"
     1318blo "-1000,71300"
    13071319)
    13081320)
     
    13661378fg "0,65535,0"
    13671379)
    1368 xt "-21750,70625,-21000,71375"
     1380xt "-21750,69625,-21000,70375"
    13691381)
    13701382tg (CPTG
     
    13761388va (VaSet
    13771389)
    1378 xt "-20000,70500,-13200,71500"
     1390xt "-20000,69500,-13200,70500"
    13791391st "trigger_id : (47:0)"
    1380 blo "-20000,71300"
     1392blo "-20000,70300"
    13811393)
    13821394)
     
    14741486fg "0,65535,0"
    14751487)
    1476 xt "0,66625,750,67375"
     1488xt "0,71625,750,72375"
    14771489)
    14781490tg (CPTG
     
    14841496va (VaSet
    14851497)
    1486 xt "-6300,66500,-1000,67500"
     1498xt "-6300,71500,-1000,72500"
    14871499st "ram_write_ea"
    14881500ju 2
    1489 blo "-1000,67300"
     1501blo "-1000,72300"
    14901502)
    14911503)
     
    15091521fg "0,65535,0"
    15101522)
    1511 xt "0,67625,750,68375"
     1523xt "0,72625,750,73375"
    15121524)
    15131525tg (CPTG
     
    15191531va (VaSet
    15201532)
    1521 xt "-7300,67500,-1000,68500"
     1533xt "-7300,72500,-1000,73500"
    15221534st "ram_write_ready"
    15231535ju 2
    1524 blo "-1000,68300"
     1536blo "-1000,73300"
    15251537)
    15261538)
     
    15471559fg "0,65535,0"
    15481560)
    1549 xt "0,76625,750,77375"
     1561xt "0,78625,750,79375"
    15501562)
    15511563tg (CPTG
     
    15571569va (VaSet
    15581570)
    1559 xt "-4000,76500,-1000,77500"
     1571xt "-4000,78500,-1000,79500"
    15601572st "roi_max"
    15611573ju 2
    1562 blo "-1000,77300"
     1574blo "-1000,79300"
    15631575)
    15641576)
     
    16171629fg "0,65535,0"
    16181630)
    1619 xt "0,77625,750,78375"
     1631xt "0,79625,750,80375"
    16201632)
    16211633tg (CPTG
     
    16271639va (VaSet
    16281640)
    1629 xt "-10100,77500,-1000,78500"
     1641xt "-10100,79500,-1000,80500"
    16301642st "package_length : (15:0)"
    16311643ju 2
    1632 blo "-1000,78300"
     1644blo "-1000,80300"
    16331645)
    16341646)
     
    20162028fg "0,65535,0"
    20172029)
    2018 xt "0,74625,750,75375"
     2030xt "0,77625,750,78375"
    20192031)
    20202032tg (CPTG
     
    20262038va (VaSet
    20272039)
    2028 xt "-7700,74500,-1000,75500"
     2040xt "-7700,77500,-1000,78500"
    20292041st "config_ready_mm"
    20302042ju 2
    2031 blo "-1000,75300"
     2043blo "-1000,78300"
    20322044)
    20332045)
     
    21562168fg "0,65535,0"
    21572169)
    2158 xt "0,72625,750,73375"
     2170xt "0,75625,750,76375"
    21592171)
    21602172tg (CPTG
     
    21662178va (VaSet
    21672179)
    2168 xt "-7400,72500,-1000,73500"
     2180xt "-7400,75500,-1000,76500"
    21692181st "config_start_mm"
    21702182ju 2
    2171 blo "-1000,73300"
     2183blo "-1000,76300"
    21722184)
    21732185)
     
    23442356fg "0,65535,0"
    23452357)
    2346 xt "0,73625,750,74375"
     2358xt "0,76625,750,77375"
    23472359)
    23482360tg (CPTG
     
    23542366va (VaSet
    23552367)
    2356 xt "-8200,73500,-1000,74500"
     2368xt "-8200,76500,-1000,77500"
    23572369st "config_started_mm"
    23582370ju 2
    2359 blo "-1000,74300"
     2371blo "-1000,77300"
    23602372)
    23612373)
     
    26262638fg "0,65535,0"
    26272639)
    2628 xt "0,68625,750,69375"
     2640xt "0,73625,750,74375"
    26292641)
    26302642tg (CPTG
     
    26362648va (VaSet
    26372649)
    2638 xt "-8800,68500,-1000,69500"
     2650xt "-8800,73500,-1000,74500"
    26392651st "ram_write_ready_ack"
    26402652ju 2
    2641 blo "-1000,69300"
     2653blo "-1000,74300"
    26422654)
    26432655)
     
    28702882)
    28712883xt "-172000,9600,-143500,10400"
    2872 st "board_id               : std_logic_vector(3 DOWNTO 0)"
     2884st "board_id               : std_logic_vector(3 DOWNTO 0)
     2885"
    28732886)
    28742887)
     
    28892902)
    28902903xt "-172000,12800,-153500,13600"
    2891 st "trigger                : std_logic"
     2904st "trigger                : std_logic
     2905"
    28922906)
    28932907)
     
    32573271fg "0,65535,0"
    32583272)
    3259 xt "87250,71625,88000,72375"
     3273xt "87250,72625,88000,73375"
    32603274)
    32613275tg (CPTG
     
    32673281va (VaSet
    32683282)
    3269 xt "89000,71500,96900,72500"
     3283xt "89000,72500,96900,73500"
    32703284st "write_length : (16:0)"
    3271 blo "89000,72300"
     3285blo "89000,73300"
    32723286)
    32733287)
     
    32943308fg "0,65535,0"
    32953309)
    3296 xt "87250,72625,88000,73375"
     3310xt "87250,73625,88000,74375"
    32973311)
    32983312tg (CPTG
     
    33043318va (VaSet
    33053319)
    3306 xt "89000,72500,105300,73500"
     3320xt "89000,73500,105300,74500"
    33073321st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    3308 blo "89000,73300"
     3322blo "89000,74300"
    33093323)
    33103324)
     
    34063420fg "0,65535,0"
    34073421)
    3408 xt "87250,70625,88000,71375"
     3422xt "87250,71625,88000,72375"
    34093423)
    34103424tg (CPTG
     
    34163430va (VaSet
    34173431)
    3418 xt "89000,70500,93100,71500"
     3432xt "89000,71500,93100,72500"
    34193433st "data_valid"
    3420 blo "89000,71300"
     3434blo "89000,72300"
    34213435)
    34223436)
     
    34423456fg "0,65535,0"
    34433457)
    3444 xt "87250,69625,88000,70375"
     3458xt "87250,70625,88000,71375"
    34453459)
    34463460tg (CPTG
     
    34523466va (VaSet
    34533467)
    3454 xt "89000,69500,90900,70500"
     3468xt "89000,70500,90900,71500"
    34553469st "busy"
    3456 blo "89000,70300"
     3470blo "89000,71300"
    34573471)
    34583472)
     
    34803494fg "0,65535,0"
    34813495)
    3482 xt "87250,73625,88000,74375"
     3496xt "87250,74625,88000,75375"
    34833497)
    34843498tg (CPTG
     
    34903504va (VaSet
    34913505)
    3492 xt "89000,73500,96800,74500"
     3506xt "89000,74500,96800,75500"
    34933507st "fifo_channels : (3:0)"
    3494 blo "89000,74300"
     3508blo "89000,75300"
    34953509)
    34963510)
     
    35163530fg "0,65535,0"
    35173531)
    3518 xt "87250,74625,88000,75375"
     3532xt "87250,75625,88000,76375"
    35193533)
    35203534tg (CPTG
     
    35263540va (VaSet
    35273541)
    3528 xt "89000,74500,94700,75500"
     3542xt "89000,75500,94700,76500"
    35293543st "write_end_flag"
    3530 blo "89000,75300"
     3544blo "89000,76300"
    35313545)
    35323546)
     
    35503564fg "0,65535,0"
    35513565)
    3552 xt "87250,75625,88000,76375"
     3566xt "87250,76625,88000,77375"
    35533567)
    35543568tg (CPTG
     
    35603574va (VaSet
    35613575)
    3562 xt "89000,75500,95800,76500"
     3576xt "89000,76500,95800,77500"
    35633577st "write_header_flag"
    3564 blo "89000,76300"
     3578blo "89000,77300"
    35653579)
    35663580)
     
    39944008fg "0,65535,0"
    39954009)
    3996 xt "87250,76625,88000,77375"
     4010xt "87250,77625,88000,78375"
    39974011)
    39984012tg (CPTG
     
    40044018va (VaSet
    40054019)
    4006 xt "89000,76500,94600,77500"
     4020xt "89000,77500,94600,78500"
    40074021st "data_valid_ack"
    4008 blo "89000,77300"
     4022blo "89000,78300"
    40094023)
    40104024)
     
    46874701)
    46884702xt "-172000,10400,-143500,11200"
    4689 st "crate_id               : std_logic_vector(1 DOWNTO 0)"
     4703st "crate_id               : std_logic_vector(1 DOWNTO 0)
     4704"
    46904705)
    46914706)
     
    47034718fg "0,65535,0"
    47044719)
    4705 xt "-41000,67625,-40250,68375"
     4720xt "-41000,68625,-40250,69375"
    47064721)
    47074722tg (CPTG
     
    47134728va (VaSet
    47144729)
    4715 xt "-48800,67500,-42000,68500"
     4730xt "-48800,68500,-42000,69500"
    47164731st "trigger_id : (47:0)"
    47174732ju 2
    4718 blo "-42000,68300"
     4733blo "-42000,69300"
    47194734)
    47204735)
     
    47434758fg "0,65535,0"
    47444759)
    4745 xt "-52750,67625,-52000,68375"
     4760xt "-52750,68625,-52000,69375"
    47464761)
    47474762tg (CPTG
     
    47534768va (VaSet
    47544769)
    4755 xt "-51000,67500,-48200,68500"
     4770xt "-51000,68500,-48200,69500"
    47564771st "trigger"
    4757 blo "-51000,68300"
     4772blo "-51000,69300"
    47584773)
    47594774)
     
    47804795fg "0,65535,0"
    47814796)
    4782 xt "-52750,66625,-52000,67375"
     4797xt "-52750,67625,-52000,68375"
    47834798)
    47844799tg (CPTG
     
    47904805va (VaSet
    47914806)
    4792 xt "-51000,66500,-49700,67500"
     4807xt "-51000,67500,-49700,68500"
    47934808st "clk"
    4794 blo "-51000,67300"
     4809blo "-51000,68300"
    47954810)
    47964811)
     
    48144829lineWidth 2
    48154830)
    4816 xt "-52000,66000,-41000,70000"
     4831xt "-52000,67000,-41000,71000"
    48174832)
    48184833oxt "32000,2000,43000,12000"
     
    48284843font "Arial,8,1"
    48294844)
    4830 xt "-50300,70000,-43700,71000"
     4845xt "-50300,71000,-43700,72000"
    48314846st "FACT_FAD_LIB"
    4832 blo "-50300,70800"
     4847blo "-50300,71800"
    48334848tm "BdLibraryNameMgr"
    48344849)
     
    48394854font "Arial,8,1"
    48404855)
    4841 xt "-50300,71000,-43700,72000"
     4856xt "-50300,72000,-43700,73000"
    48424857st "trigger_counter"
    4843 blo "-50300,71800"
     4858blo "-50300,72800"
    48444859tm "CptNameMgr"
    48454860)
     
    48504865font "Arial,8,1"
    48514866)
    4852 xt "-50300,71000,-42700,72000"
     4867xt "-50300,72000,-42700,73000"
    48534868st "I_main_ext_trigger"
    4854 blo "-50300,71800"
     4869blo "-50300,72800"
    48554870tm "InstanceNameMgr"
    48564871)
     
    48674882font "Courier New,8,0"
    48684883)
    4869 xt "-52000,65000,-52000,65000"
     4884xt "-52000,66000,-52000,66000"
    48704885)
    48714886header ""
     
    48814896fg "49152,49152,49152"
    48824897)
    4883 xt "-51750,68250,-50250,69750"
     4898xt "-51750,69250,-50250,70750"
    48844899iconName "VhdlFileViewIcon.png"
    48854900iconMaskName "VhdlFileViewIcon.msk"
     
    49114926)
    49124927xt "-172000,98800,-139500,99600"
    4913 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
     4928st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
     4929"
    49144930)
    49154931)
     
    49314947)
    49324948xt "-172000,82000,-132000,82800"
    4933 st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     4949st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     4950"
    49344951)
    49354952)
     
    49474964fg "0,65535,0"
    49484965)
    4949 xt "31250,72625,32000,73375"
     4966xt "27250,70625,28000,71375"
    49504967)
    49514968tg (CPTG
     
    49584975font "arial,8,0"
    49594976)
    4960 xt "33000,72500,51400,73500"
     4977xt "29000,70500,47400,71500"
    49614978st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
    4962 blo "33000,73300"
     4979blo "29000,71300"
    49634980)
    49644981)
     
    49835000shape (Triangle
    49845001uid 2352,0
    4985 ro 90
     5002ro 180
    49865003va (VaSet
    49875004vasetType 1
    49885005fg "0,65535,0"
    49895006)
    4990 xt "31250,70625,32000,71375"
     5007xt "28625,67250,29375,68000"
    49915008)
    49925009tg (CPTG
    49935010uid 2353,0
    49945011ps "CptPortTextPlaceStrategy"
    4995 stg "VerticalLayoutStrategy"
     5012stg "RightVerticalLayoutStrategy"
    49965013f (Text
    49975014uid 2354,0
     5015ro 270
    49985016va (VaSet
    49995017font "arial,8,0"
    50005018)
    5001 xt "33000,70500,34300,71500"
     5019xt "28500,69000,29500,70300"
    50025020st "clk"
    5003 blo "33000,71300"
     5021ju 2
     5022blo "29300,69000"
    50045023)
    50055024)
     
    50245043fg "0,65535,0"
    50255044)
    5026 xt "31250,79625,32000,80375"
     5045xt "27250,77625,28000,78375"
    50275046)
    50285047tg (CPTG
     
    50355054font "arial,8,0"
    50365055)
    5037 xt "33000,79500,38100,80500"
     5056xt "29000,77500,34100,78500"
    50385057st "config_ready"
    5039 blo "33000,80300"
     5058blo "29000,78300"
    50405059)
    50415060)
     
    50625081fg "0,65535,0"
    50635082)
    5064 xt "31250,77625,32000,78375"
     5083xt "27250,75625,28000,76375"
    50655084)
    50665085tg (CPTG
     
    50735092font "arial,8,0"
    50745093)
    5075 xt "33000,77500,37800,78500"
     5094xt "29000,75500,33800,76500"
    50765095st "config_start"
    5077 blo "33000,78300"
     5096blo "29000,76300"
    50785097)
    50795098)
     
    50985117fg "0,65535,0"
    50995118)
    5100 xt "31250,73625,32000,74375"
     5119xt "27250,71625,28000,72375"
    51015120)
    51025121tg (CPTG
     
    51095128font "arial,8,0"
    51105129)
    5111 xt "33000,73500,38300,74500"
     5130xt "29000,71500,34300,72500"
    51125131st "ram_write_ea"
    5113 blo "33000,74300"
     5132blo "29000,72300"
    51145133)
    51155134)
     
    51365155fg "0,65535,0"
    51375156)
    5138 xt "31250,74625,32000,75375"
     5157xt "27250,72625,28000,73375"
    51395158)
    51405159tg (CPTG
     
    51475166font "arial,8,0"
    51485167)
    5149 xt "33000,74500,39300,75500"
     5168xt "29000,72500,35300,73500"
    51505169st "ram_write_ready"
    5151 blo "33000,75300"
     5170blo "29000,73300"
    51525171)
    51535172)
     
    51735192fg "0,65535,0"
    51745193)
    5175 xt "31250,80625,32000,81375"
     5194xt "27250,78625,28000,79375"
    51765195)
    51775196tg (CPTG
     
    51845203font "arial,8,0"
    51855204)
    5186 xt "33000,80500,36000,81500"
     5205xt "29000,78500,32000,79500"
    51875206st "roi_max"
    5188 blo "33000,81300"
     5207blo "29000,79300"
    51895208)
    51905209)
     
    52125231fg "0,65535,0"
    52135232)
    5214 xt "63000,70625,63750,71375"
     5233xt "59000,70625,59750,71375"
    52155234)
    52165235tg (CPTG
     
    52235242font "arial,8,0"
    52245243)
    5225 xt "58600,70500,62000,71500"
     5244xt "54600,70500,58000,71500"
    52265245st "wiz_busy"
    52275246ju 2
    5228 blo "62000,71300"
     5247blo "58000,71300"
    52295248)
    52305249)
     
    52495268fg "0,65535,0"
    52505269)
    5251 xt "63000,74625,63750,75375"
     5270xt "59000,74625,59750,75375"
    52525271)
    52535272tg (CPTG
     
    52605279font "arial,8,0"
    52615280)
    5262 xt "50200,74500,62000,75500"
     5281xt "46200,74500,58000,75500"
    52635282st "wiz_number_of_channels : (3:0)"
    52645283ju 2
    5265 blo "62000,75300"
     5284blo "58000,75300"
    52665285)
    52675286)
     
    52895308fg "0,65535,0"
    52905309)
    5291 xt "63000,73625,63750,74375"
     5310xt "59000,73625,59750,74375"
    52925311)
    52935312tg (CPTG
     
    53005319font "arial,8,0"
    53015320)
    5302 xt "42100,73500,62000,74500"
     5321xt "38100,73500,58000,74500"
    53035322st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
    53045323ju 2
    5305 blo "62000,74300"
     5324blo "58000,74300"
    53065325)
    53075326)
     
    53305349fg "0,65535,0"
    53315350)
    5332 xt "63000,71625,63750,72375"
     5351xt "59000,71625,59750,72375"
    53335352)
    53345353tg (CPTG
     
    53415360font "arial,8,0"
    53425361)
    5343 xt "56900,71500,62000,72500"
     5362xt "52900,71500,58000,72500"
    53445363st "wiz_write_ea"
    53455364ju 2
    5346 blo "62000,72300"
     5365blo "58000,72300"
    53475366)
    53485367)
     
    53695388fg "0,65535,0"
    53705389)
    5371 xt "63000,75625,63750,76375"
     5390xt "59000,75625,59750,76375"
    53725391)
    53735392tg (CPTG
     
    53805399font "arial,8,0"
    53815400)
    5382 xt "56500,75500,62000,76500"
     5401xt "52500,75500,58000,76500"
    53835402st "wiz_write_end"
    53845403ju 2
    5385 blo "62000,76300"
     5404blo "58000,76300"
    53865405)
    53875406)
     
    54085427fg "0,65535,0"
    54095428)
    5410 xt "63000,76625,63750,77375"
     5429xt "59000,76625,59750,77375"
    54115430)
    54125431tg (CPTG
     
    54195438font "arial,8,0"
    54205439)
    5421 xt "55400,76500,62000,77500"
     5440xt "51400,76500,58000,77500"
    54225441st "wiz_write_header"
    54235442ju 2
    5424 blo "62000,77300"
     5443blo "58000,77300"
    54255444)
    54265445)
     
    54475466fg "0,65535,0"
    54485467)
    5449 xt "63000,72625,63750,73375"
     5468xt "59000,72625,59750,73375"
    54505469)
    54515470tg (CPTG
     
    54585477font "arial,8,0"
    54595478)
    5460 xt "52600,72500,62000,73500"
     5479xt "48600,72500,58000,73500"
    54615480st "wiz_write_length : (16:0)"
    54625481ju 2
    5463 blo "62000,73300"
     5482blo "58000,73300"
    54645483)
    54655484)
     
    54875506fg "0,65535,0"
    54885507)
    5489 xt "31250,87625,32000,88375"
     5508xt "27250,85625,28000,86375"
    54905509)
    54915510tg (CPTG
     
    54985517font "arial,8,0"
    54995518)
    5500 xt "33000,87500,36400,88500"
     5519xt "29000,85500,32400,86500"
    55015520st "roi_array"
    5502 blo "33000,88300"
     5521blo "29000,86300"
    55035522)
    55045523)
     
    55255544fg "0,65535,0"
    55265545)
    5527 xt "31250,81625,32000,82375"
     5546xt "27250,79625,28000,80375"
    55285547)
    55295548tg (CPTG
     
    55365555font "arial,8,0"
    55375556)
    5538 xt "33000,81500,42100,82500"
     5557xt "29000,79500,38100,80500"
    55395558st "package_length : (15:0)"
    5540 blo "33000,82300"
     5559blo "29000,80300"
    55415560)
    55425561)
     
    55645583fg "0,65535,0"
    55655584)
    5566 xt "31250,78625,32000,79375"
     5585xt "27250,76625,28000,77375"
    55675586)
    55685587tg (CPTG
     
    55755594font "arial,8,0"
    55765595)
    5577 xt "33000,78500,38600,79500"
     5596xt "29000,76500,34600,77500"
    55785597st "config_started"
    5579 blo "33000,79300"
     5598blo "29000,77300"
    55805599)
    55815600)
     
    56025621fg "0,65535,0"
    56035622)
    5604 xt "63000,77625,63750,78375"
     5623xt "59000,77625,59750,78375"
    56055624)
    56065625tg (CPTG
     
    56135632font "arial,8,0"
    56145633)
    5615 xt "59000,77500,62000,78500"
     5634xt "55000,77500,58000,78500"
    56165635st "wiz_ack"
    56175636ju 2
    5618 blo "62000,78300"
     5637blo "58000,78300"
    56195638)
    56205639)
     
    56395658fg "0,65535,0"
    56405659)
    5641 xt "31250,75625,32000,76375"
     5660xt "27250,73625,28000,74375"
    56425661)
    56435662tg (CPTG
     
    56505669font "arial,8,0"
    56515670)
    5652 xt "33000,75500,40800,76500"
     5671xt "29000,73500,36800,74500"
    56535672st "ram_write_ready_ack"
    5654 blo "33000,76300"
     5673blo "29000,74300"
    56555674)
    56565675)
     
    56795698lineWidth 2
    56805699)
    5681 xt "32000,70000,63000,90000"
     5700xt "28000,68000,59000,88000"
    56825701)
    56835702oxt "15000,6000,23000,16000"
     
    56925711font "arial,8,1"
    56935712)
    5694 xt "32350,90000,38550,91000"
     5713xt "28350,88000,34550,89000"
    56955714st "FACT_FAD_lib"
    5696 blo "32350,90800"
     5715blo "28350,88800"
    56975716tm "BdLibraryNameMgr"
    56985717)
     
    57025721font "arial,8,1"
    57035722)
    5704 xt "32350,91000,39650,92000"
     5723xt "28350,89000,35650,90000"
    57055724st "memory_manager"
    5706 blo "32350,91800"
     5725blo "28350,89800"
    57075726tm "CptNameMgr"
    57085727)
     
    57125731font "arial,8,1"
    57135732)
    5714 xt "32350,92000,42850,93000"
     5733xt "28350,90000,38850,91000"
    57155734st "I_main_memory_manager"
    5716 blo "32350,92800"
     5735blo "28350,90800"
    57175736tm "InstanceNameMgr"
    57185737)
     
    57295748font "Courier New,8,0"
    57305749)
    5731 xt "32000,68400,61500,70000"
     5750xt "31000,66400,60500,68000"
    57325751st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer ) 
    57335752RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
     
    57555774fg "49152,49152,49152"
    57565775)
    5757 xt "32250,88250,33750,89750"
     5776xt "28250,86250,29750,87750"
    57585777iconName "VhdlFileViewIcon.png"
    57595778iconMaskName "VhdlFileViewIcon.msk"
     
    57815800)
    57825801xt "-172000,101200,-149500,102000"
    5783 st "SIGNAL wiz_busy               : std_logic"
     5802st "SIGNAL wiz_busy               : std_logic
     5803"
    57845804)
    57855805)
     
    58005820)
    58015821xt "-172000,103600,-128500,104400"
    5802 st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
     5822st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
     5823"
    58035824)
    58045825)
     
    58205841)
    58215842xt "-172000,106000,-122500,106800"
    5822 st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
     5843st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
     5844"
    58235845)
    58245846)
     
    58415863)
    58425864xt "-172000,102800,-122500,103600"
    5843 st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
     5865st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
     5866"
    58445867)
    58455868)
     
    58615884)
    58625885xt "-172000,102000,-122500,102800"
    5863 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
     5886st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
     5887"
    58645888)
    58655889)
     
    58805904)
    58815905xt "-172000,104400,-128500,105200"
    5882 st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
     5906st "SIGNAL wiz_write_end          : std_logic                                    := '0'
     5907"
    58835908)
    58845909)
     
    58995924)
    59005925xt "-172000,105200,-128500,106000"
    5901 st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
     5926st "SIGNAL wiz_write_header       : std_logic                                    := '0'
     5927"
    59025928)
    59035929)
     
    59165942)
    59175943xt "-172000,82800,-149500,83600"
    5918 st "SIGNAL ram_write_ea           : std_logic"
     5944st "SIGNAL ram_write_ea           : std_logic
     5945"
    59195946)
    59205947)
     
    59345961)
    59355962xt "-172000,83600,-128500,84400"
    5936 st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
     5963st "SIGNAL ram_write_ready        : std_logic                                    := '0'
     5964"
    59375965)
    59385966)
     
    59525980)
    59535981xt "-172000,54800,-128500,55600"
    5954 st "SIGNAL config_start           : std_logic                                    := '0'"
     5982st "SIGNAL config_start           : std_logic                                    := '0'
     5983"
    59555984)
    59565985)
     
    59695998)
    59705999xt "-172000,49200,-149500,50000"
    5971 st "SIGNAL config_ready           : std_logic"
     6000st "SIGNAL config_ready           : std_logic
     6001"
    59726002)
    59736003)
     
    59866016)
    59876017xt "-172000,86800,-148000,87600"
    5988 st "SIGNAL roi_max                : roi_max_type"
     6018st "SIGNAL roi_max                : roi_max_type
     6019"
    59896020)
    59906021)
     
    60046035)
    60056036xt "-172000,77200,-139500,78000"
    6006 st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
     6037st "SIGNAL package_length         : std_logic_vector(15 downto 0)
     6038"
    60076039)
    60086040)
     
    60226054)
    60236055xt "-172000,19200,-132000,20000"
    6024 st "adc_oeb                : std_logic                                    := '1'"
     6056st "adc_oeb                : std_logic                                    := '1'
     6057"
    60256058)
    60266059)
     
    61296162)
    61306163xt "-172000,86000,-147000,86800"
    6131 st "SIGNAL roi_array              : roi_array_type"
     6164st "SIGNAL roi_array              : roi_array_type
     6165"
    61326166)
    61336167)
     
    65626596)
    65636597xt "-172000,14400,-153500,15200"
    6564 st "CLK_25_PS              : std_logic"
     6598st "CLK_25_PS              : std_logic
     6599"
    65656600)
    65666601)
     
    66246659)
    66256660xt "-172000,15200,-153500,16000"
    6626 st "CLK_50                 : std_logic"
     6661st "CLK_50                 : std_logic
     6662"
    66276663)
    66286664)
     
    66416677)
    66426678xt "-172000,39600,-149500,40400"
    6643 st "SIGNAL CLK_25                 : std_logic"
     6679st "SIGNAL CLK_25                 : std_logic
     6680"
    66446681)
    66456682)
     
    67036740)
    67046741xt "-172000,3200,-153500,4000"
    6705 st "CLK                    : std_logic"
     6742st "CLK                    : std_logic
     6743"
    67066744)
    67076745)
     
    67216759)
    67226760xt "-172000,8800,-143500,9600"
    6723 st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
     6761st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
     6762"
    67246763)
    67256764)
     
    67386777)
    67396778xt "-172000,8000,-148000,8800"
    6740 st "adc_data_array         : adc_data_array_type"
     6779st "adc_data_array         : adc_data_array_type
     6780"
    67416781)
    67426782)
     
    68016841)
    68026842xt "-172000,66800,-128500,67600"
    6803 st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
     6843st "SIGNAL drs_clk_en             : std_logic                                    := '0'
     6844"
    68046845)
    68056846)
     
    68186859)
    68196860xt "-172000,73200,-143500,74000"
    6820 st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
     6861st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
     6862"
    68216863)
    68226864)
     
    68366878)
    68376879xt "-172000,67600,-128500,68400"
    6838 st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
     6880st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
     6881"
    68396882)
    68406883)
     
    68556898)
    68566899xt "-172000,25600,-126000,26400"
    6857 st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
     6900st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
     6901"
    68586902)
    68596903)
     
    68736917)
    68746918xt "-172000,26400,-132000,27200"
    6875 st "drs_dwrite             : std_logic                                    := '1'"
     6919st "drs_dwrite             : std_logic                                    := '1'
     6920"
    68766921)
    68776922)
     
    69807025)
    69817026xt "-172000,4800,-153500,5600"
    6982 st "SROUT_in_0             : std_logic"
     7027st "SROUT_in_0             : std_logic
     7028"
    69837029)
    69847030)
     
    69977043)
    69987044xt "-172000,5600,-153500,6400"
    6999 st "SROUT_in_1             : std_logic"
     7045st "SROUT_in_1             : std_logic
     7046"
    70007047)
    70017048)
     
    70147061)
    70157062xt "-172000,6400,-153500,7200"
    7016 st "SROUT_in_2             : std_logic"
     7063st "SROUT_in_2             : std_logic
     7064"
    70177065)
    70187066)
     
    70317079)
    70327080xt "-172000,7200,-153500,8000"
    7033 st "SROUT_in_3             : std_logic"
     7081st "SROUT_in_3             : std_logic
     7082"
    70347083)
    70357084)
     
    72287277)
    72297278xt "-172000,68400,-149500,69200"
    7230 st "SIGNAL drs_read_s_cell_ready  : std_logic"
     7279st "SIGNAL drs_read_s_cell_ready  : std_logic
     7280"
    72317281)
    72327282)
     
    78837933)
    78847934xt "-172000,16000,-132000,16800"
    7885 st "RSRLOAD                : std_logic                                    := '0'"
     7935st "RSRLOAD                : std_logic                                    := '0'
     7936"
    78867937)
    78877938)
     
    79467997)
    79477998xt "-172000,16800,-132000,17600"
    7948 st "SRCLK                  : std_logic                                    := '0'"
     7999st "SRCLK                  : std_logic                                    := '0'
     8000"
    79498001)
    79508002)
     
    85998651)
    86008652xt "-172000,45200,-140000,46000"
    8601 st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
     8653st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
     8654"
    86028655)
    86038656)
     
    86168669)
    86178670xt "-172000,47600,-149500,48400"
    8618 st "SIGNAL config_data_valid      : std_logic"
     8671st "SIGNAL config_data_valid      : std_logic
     8672"
    86198673)
    86208674)
     
    86338687)
    86348688xt "-172000,46000,-149500,46800"
    8635 st "SIGNAL config_busy            : std_logic"
     8689st "SIGNAL config_busy            : std_logic
     8690"
    86368691)
    86378692)
     
    86518706)
    86528707xt "-172000,46800,-139500,47600"
    8653 st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
     8708st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
     8709"
    86548710)
    86558711)
     
    86688724)
    86698725xt "-172000,60400,-149500,61200"
    8670 st "SIGNAL config_wr_en           : std_logic"
     8726st "SIGNAL config_wr_en           : std_logic
     8727"
    86718728)
    86728729)
     
    86858742)
    86868743xt "-172000,48400,-149500,49200"
    8687 st "SIGNAL config_rd_en           : std_logic"
     8744st "SIGNAL config_rd_en           : std_logic
     8745"
    86888746)
    86898747)
     
    87028760)
    87038761xt "-172000,61200,-147000,62000"
    8704 st "SIGNAL dac_array              : dac_array_type"
     8762st "SIGNAL dac_array              : dac_array_type
     8763"
    87058764)
    87068765)
     
    87198778)
    87208779xt "-172000,55600,-149500,56400"
    8721 st "SIGNAL config_start_cm        : std_logic"
     8780st "SIGNAL config_start_cm        : std_logic
     8781"
    87228782)
    87238783)
     
    87368796)
    87378797xt "-172000,50000,-149500,50800"
    8738 st "SIGNAL config_ready_cm        : std_logic"
     8798st "SIGNAL config_ready_cm        : std_logic
     8799"
    87398800)
    87408801)
     
    87568817)
    87578818xt "-172000,28000,-126000,28800"
    8758 st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
     8819st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
     8820"
    87598821)
    87608822)
     
    87738835)
    87748836xt "-172000,91600,-149500,92400"
    8775 st "SIGNAL sensor_ready           : std_logic"
     8837st "SIGNAL sensor_ready           : std_logic
     8838"
    87768839)
    87778840)
     
    87908853)
    87918854xt "-172000,90800,-145500,91600"
    8792 st "SIGNAL sensor_array           : sensor_array_type"
     8855st "SIGNAL sensor_array           : sensor_array_type
     8856"
    87938857)
    87948858)
     
    88078871)
    88088872xt "-172000,50800,-149500,51600"
    8809 st "SIGNAL config_ready_spi       : std_logic"
     8873st "SIGNAL config_ready_spi       : std_logic
     8874"
    88108875)
    88118876)
     
    88268891)
    88278892xt "-172000,42000,-140000,42800"
    8828 st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
     8893st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
     8894"
    88298895)
    88308896)
     
    88438909)
    88448910xt "-172000,41200,-144500,42000"
    8845 st "SIGNAL adc_data_array_int     : adc_data_array_type"
     8911st "SIGNAL adc_data_array_int     : adc_data_array_type
     8912"
    88468913)
    88478914)
     
    91339200)
    91349201xt "-172000,56400,-128500,57200"
    9135 st "SIGNAL config_start_spi       : std_logic                                    := '0'"
     9202st "SIGNAL config_start_spi       : std_logic                                    := '0'
     9203"
    91369204)
    91379205)
     
    96669734)
    96679735xt "-172000,30400,-153500,31200"
    9668 st "sclk                   : std_logic"
     9736st "sclk                   : std_logic
     9737"
    96699738)
    96709739)
     
    96859754)
    96869755xt "-172000,36000,-153500,36800"
    9687 st "sio                    : std_logic"
     9756st "sio                    : std_logic
     9757"
    96889758)
    96899759)
     
    97029772)
    97039773xt "-172000,24000,-153500,24800"
    9704 st "dac_cs                 : std_logic"
     9774st "dac_cs                 : std_logic
     9775"
    97059776)
    97069777)
     
    97209791)
    97219792xt "-172000,31200,-143500,32000"
    9722 st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
     9793st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
     9794"
    97239795)
    97249796)
     
    99189990)
    99199991xt "-172000,76400,-128500,77200"
    9920 st "SIGNAL new_config             : std_logic                                    := '0'"
     9992st "SIGNAL new_config             : std_logic                                    := '0'
     9993"
    99219994)
    99229995)
     
    993510008)
    993610009xt "-172000,57200,-149500,58000"
    9937 st "SIGNAL config_started         : std_logic"
     10010st "SIGNAL config_started         : std_logic
     10011"
    993810012)
    993910013)
     
    995310027)
    995410028xt "-172000,59600,-128500,60400"
    9955 st "SIGNAL config_started_spi     : std_logic                                    := '0'"
     10029st "SIGNAL config_started_spi     : std_logic                                    := '0'
     10030"
    995610031)
    995710032)
     
    997110046)
    997210047xt "-172000,58000,-128500,58800"
    9973 st "SIGNAL config_started_cu      : std_logic                                    := '0'"
     10048st "SIGNAL config_started_cu      : std_logic                                    := '0'
     10049"
    997410050)
    997510051)
     
    998810064)
    998910065xt "-172000,58800,-149500,59600"
    9990 st "SIGNAL config_started_mm      : std_logic"
     10066st "SIGNAL config_started_mm      : std_logic
     10067"
    999110068)
    999210069)
     
    1000610083)
    1000710084xt "-172000,28800,-132000,29600"
    10008 st "mosi                   : std_logic                                    := '0'"
     10085st "mosi                   : std_logic                                    := '0'
     10086"
    1000910087)
    1001010088)
     
    1007110149)
    1007210150xt "-172000,24800,-118500,25600"
    10073 st "denable                : std_logic                                    := '0' -- default domino wave off"
     10151st "denable                : std_logic                                    := '0' -- default domino wave off
     10152"
    1007410153)
    1007510154)
     
    1013310212)
    1013410213xt "-172000,75600,-128500,76400"
    10135 st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
     10214st "SIGNAL dwrite_enable          : std_logic                                    := '1'
     10215"
    1013610216)
    1013710217)
     
    1052010600)
    1052110601xt "-172000,74800,-128500,75600"
    10522 st "SIGNAL dwrite                 : std_logic                                    := '1'"
     10602st "SIGNAL dwrite                 : std_logic                                    := '1'
     10603"
    1052310604)
    1052410605)
     
    1089410975)
    1089510976xt "-172000,100400,-149500,101200"
    10896 st "SIGNAL wiz_ack                : std_logic"
     10977st "SIGNAL wiz_ack                : std_logic
     10978"
    1089710979)
    1089810980)
     
    1127711359)
    1127811360xt "-172000,89200,-149500,90000"
    11279 st "SIGNAL sclk1                  : std_logic"
     11361st "SIGNAL sclk1                  : std_logic
     11362"
    1128011363)
    1128111364)
     
    1129411377)
    1129511378xt "-172000,90000,-149500,90800"
    11296 st "SIGNAL sclk_enable            : std_logic"
     11379st "SIGNAL sclk_enable            : std_logic
     11380"
    1129711381)
    1129811382)
     
    1131211396)
    1131311397xt "-172000,18400,-132000,19200"
    11314 st "adc_clk_en             : std_logic                                    := '0'"
     11398st "adc_clk_en             : std_logic                                    := '0'
     11399"
    1131511400)
    1131611401)
     
    1176611851)
    1176711852xt "-172000,78000,-113000,78800"
    11768 st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards"
     11853st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
     11854"
    1176911855)
    1177011856)
     
    1178711873)
    1178811874xt "-172000,78800,-112000,79600"
    11789 st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once"
     11875st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
     11876"
    1179011877)
    1179111878)
     
    1180711894)
    1180811895xt "-172000,79600,-104500,80400"
    11809 st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift"
     11896st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift
     11897"
    1181011898)
    1181111899)
     
    1182511913)
    1182611914xt "-172000,94000,-128500,94800"
    11827 st "SIGNAL srclk_enable           : std_logic                                    := '0'"
     11915st "SIGNAL srclk_enable           : std_logic                                    := '0'
     11916"
    1182811917)
    1182911918)
     
    1220912298)
    1221012299xt "-172000,40400,-128500,41200"
    12211 st "SIGNAL SRCLK1                 : std_logic                                    := '0'"
     12300st "SIGNAL SRCLK1                 : std_logic                                    := '0'
     12301"
    1221212302)
    1221312303)
     
    1223112321xt "-172000,51600,-128500,53200"
    1223212322st "-- --
    12233 SIGNAL config_rw_ack          : std_logic                                    := '0'"
     12323SIGNAL config_rw_ack          : std_logic                                    := '0'
     12324"
    1223412325)
    1223512326)
     
    1225312344xt "-172000,53200,-128500,54800"
    1225412345st "-- --
    12255 SIGNAL config_rw_ready        : std_logic                                    := '0'"
     12346SIGNAL config_rw_ready        : std_logic                                    := '0'
     12347"
    1225612348)
    1225712349)
     
    1227012362)
    1227112363xt "-172000,87600,-149500,88400"
    12272 st "SIGNAL s_trigger              : std_logic"
     12364st "SIGNAL s_trigger              : std_logic
     12365"
    1227312366)
    1227412367)
     
    1228712380)
    1228812381xt "-172000,96400,-149500,97200"
    12289 st "SIGNAL start_srin_write_8b    : std_logic"
     12382st "SIGNAL start_srin_write_8b    : std_logic
     12383"
    1229012384)
    1229112385)
     
    1230512399)
    1230612400xt "-172000,94800,-128500,95600"
    12307 st "SIGNAL srin_write_ack         : std_logic                                    := '0'"
     12401st "SIGNAL srin_write_ack         : std_logic                                    := '0'
     12402"
    1230812403)
    1230912404)
     
    1232312418)
    1232412419xt "-172000,95600,-128500,96400"
    12325 st "SIGNAL srin_write_ready       : std_logic                                    := '0'"
     12420st "SIGNAL srin_write_ready       : std_logic                                    := '0'
     12421"
    1232612422)
    1232712423)
     
    1234212438)
    1234312439xt "-172000,74000,-122500,74800"
    12344 st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')"
     12440st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')
     12441"
    1234512442)
    1234612443)
     
    1236012457)
    1236112458xt "-172000,17600,-132000,18400"
    12362 st "SRIN_out               : std_logic                                    := '0'"
     12459st "SRIN_out               : std_logic                                    := '0'
     12460"
    1236312461)
    1236412462)
     
    1286312961)
    1286412962*431 (Net
    12865 uid 10449,0
    12866 decl (Decl
    12867 n "trigger_out"
    12868 t "std_logic"
    12869 preAdd 0
    12870 posAdd 0
    12871 o 120
    12872 suid 240,0
    12873 )
    12874 declText (MLText
    12875 uid 10450,0
    12876 va (VaSet
    12877 font "Courier New,8,0"
    12878 )
    12879 xt "-172000,99600,-149500,100400"
    12880 st "SIGNAL trigger_out            : std_logic"
    12881 )
    12882 )
    12883 *432 (Net
    1288412963uid 10465,0
    1288512964lang 2
     
    1290112980xt "-172000,84400,-128500,86000"
    1290212981st "-- --
    12903 SIGNAL ram_write_ready_ack    : std_logic                                    := '0'"
    12904 )
    12905 )
    12906 *433 (Net
     12982SIGNAL ram_write_ready_ack    : std_logic                                    := '0'
     12983"
     12984)
     12985)
     12986*432 (Net
    1290712987uid 10627,0
    1290812988decl (Decl
     
    1291812998)
    1291912999xt "-172000,92400,-149500,93200"
    12920 st "SIGNAL socks_connected        : std_logic"
    12921 )
    12922 )
    12923 *434 (Net
     13000st "SIGNAL socks_connected        : std_logic
     13001"
     13002)
     13003)
     13004*433 (Net
    1292413005uid 10635,0
    1292513006decl (Decl
     
    1293513016)
    1293613017xt "-172000,93200,-149500,94000"
    12937 st "SIGNAL socks_waiting          : std_logic"
    12938 )
    12939 )
    12940 *435 (Net
     13018st "SIGNAL socks_waiting          : std_logic
     13019"
     13020)
     13021)
     13022*434 (Net
    1294113023uid 10721,0
    1294213024decl (Decl
     
    1295213034)
    1295313035xt "-172000,27200,-153500,28000"
    12954 st "green                  : std_logic"
    12955 )
    12956 )
    12957 *436 (PortIoOut
     13036st "green                  : std_logic
     13037"
     13038)
     13039)
     13040*435 (PortIoOut
    1295813041uid 10729,0
    1295913042shape (CompositeShape
     
    1299913082)
    1300013083)
    13001 *437 (Net
     13084*436 (Net
    1300213085uid 10735,0
    1300313086decl (Decl
     
    1301313096)
    1301413097xt "-172000,22400,-153500,23200"
    13015 st "amber                  : std_logic"
    13016 )
    13017 )
    13018 *438 (PortIoOut
     13098st "amber                  : std_logic
     13099"
     13100)
     13101)
     13102*437 (PortIoOut
    1301913103uid 10743,0
    1302013104shape (CompositeShape
     
    1306013144)
    1306113145)
    13062 *439 (Net
     13146*438 (Net
    1306313147uid 10749,0
    1306413148decl (Decl
     
    1307413158)
    1307513159xt "-172000,29600,-153500,30400"
    13076 st "red                    : std_logic"
    13077 )
    13078 )
    13079 *440 (PortIoOut
     13160st "red                    : std_logic
     13161"
     13162)
     13163)
     13164*439 (PortIoOut
    1308013165uid 10757,0
    1308113166shape (CompositeShape
     
    1312113206)
    1312213207)
    13123 *441 (SaComponent
     13208*440 (SaComponent
    1312413209uid 11209,0
    1312513210optionalChildren [
    13126 *442 (CptPort
     13211*441 (CptPort
    1312713212uid 11181,0
    1312813213ps "OnEdgeStrategy"
     
    1315713242)
    1315813243)
    13159 *443 (CptPort
     13244*442 (CptPort
    1316013245uid 11185,0
    1316113246ps "OnEdgeStrategy"
     
    1319213277)
    1319313278)
    13194 *444 (CptPort
     13279*443 (CptPort
    1319513280uid 11189,0
    1319613281ps "OnEdgeStrategy"
     
    1322713312)
    1322813313)
    13229 *445 (CptPort
     13314*444 (CptPort
    1323013315uid 11193,0
    1323113316ps "OnEdgeStrategy"
     
    1326213347)
    1326313348)
    13264 *446 (CptPort
     13349*445 (CptPort
    1326513350uid 11197,0
    1326613351ps "OnEdgeStrategy"
     
    1329513380)
    1329613381)
    13297 *447 (CptPort
     13382*446 (CptPort
    1329813383uid 11201,0
    1329913384ps "OnEdgeStrategy"
     
    1332813413)
    1332913414)
    13330 *448 (CptPort
     13415*447 (CptPort
    1333113416uid 11205,0
    1333213417ps "OnEdgeStrategy"
     
    1336113446)
    1336213447)
    13363 *449 (CptPort
     13448*448 (CptPort
    1336413449uid 12693,0
    1336513450ps "OnEdgeStrategy"
     
    1341313498stg "VerticalLayoutStrategy"
    1341413499textVec [
    13415 *450 (Text
     13500*449 (Text
    1341613501uid 11212,0
    1341713502va (VaSet
     
    1342313508tm "BdLibraryNameMgr"
    1342413509)
    13425 *451 (Text
     13510*450 (Text
    1342613511uid 11213,0
    1342713512va (VaSet
     
    1343313518tm "CptNameMgr"
    1343413519)
    13435 *452 (Text
     13520*451 (Text
    1343613521uid 11214,0
    1343713522va (VaSet
     
    1350013585archFileType "UNKNOWN"
    1350113586)
    13502 *453 (Net
     13587*452 (Net
    1350313588uid 11403,0
    1350413589decl (Decl
     
    1351413599)
    1351513600xt "-172000,72400,-149500,73200"
    13516 st "SIGNAL drs_readout_started    : std_logic"
    13517 )
    13518 )
    13519 *454 (Net
     13601st "SIGNAL drs_readout_started    : std_logic
     13602"
     13603)
     13604)
     13605*453 (Net
    1352013606uid 11856,0
    1352113607decl (Decl
     
    1353113617)
    1353213618xt "-172000,98000,-149500,98800"
    13533 st "SIGNAL trigger_enable         : std_logic"
    13534 )
    13535 )
    13536 *455 (MWC
     13619st "SIGNAL trigger_enable         : std_logic
     13620"
     13621)
     13622)
     13623*454 (MWC
    1353713624uid 12295,0
    1353813625optionalChildren [
    13539 *456 (CptPort
     13626*455 (CptPort
    1354013627uid 12267,0
    1354113628optionalChildren [
    13542 *457 (Line
     13629*456 (Line
    1354313630uid 12271,0
    1354413631layer 5
     
    1355313640]
    1355413641)
    13555 *458 (Property
     13642*457 (Property
    1355613643uid 12272,0
    1355713644pclass "_MW_GEOM_"
     
    1360013687)
    1360113688)
    13602 *459 (CptPort
     13689*458 (CptPort
    1360313690uid 12273,0
    1360413691optionalChildren [
    13605 *460 (Line
     13692*459 (Line
    1360613693uid 12277,0
    1360713694layer 5
     
    1365513742)
    1365613743)
    13657 *461 (CptPort
     13744*460 (CptPort
    1365813745uid 12278,0
    1365913746optionalChildren [
    13660 *462 (Line
     13747*461 (Line
    1366113748uid 12282,0
    1366213749layer 5
     
    1370813795)
    1370913796)
    13710 *463 (CommentGraphic
     13797*462 (CommentGraphic
    1371113798uid 12283,0
    1371213799optionalChildren [
    13713 *464 (Property
     13800*463 (Property
    1371413801uid 12285,0
    1371513802pclass "_MW_GEOM_"
     
    1373513822oxt "7000,10000,7000,10000"
    1373613823)
    13737 *465 (CommentGraphic
     13824*464 (CommentGraphic
    1373813825uid 12286,0
    1373913826optionalChildren [
    13740 *466 (Property
     13827*465 (Property
    1374113828uid 12288,0
    1374213829pclass "_MW_GEOM_"
     
    1376213849oxt "7000,6000,7000,6000"
    1376313850)
    13764 *467 (Grouping
     13851*466 (Grouping
    1376513852uid 12289,0
    1376613853optionalChildren [
    13767 *468 (CommentGraphic
     13854*467 (CommentGraphic
    1376813855uid 12291,0
    1376913856shape (PolyLine2D
     
    1378613873oxt "7000,6000,9000,10000"
    1378713874)
    13788 *469 (CommentGraphic
     13875*468 (CommentGraphic
    1378913876uid 12293,0
    1379013877shape (Arc2D
     
    1383913926stg "VerticalLayoutStrategy"
    1384013927textVec [
    13841 *470 (Text
     13928*469 (Text
    1384213929uid 12298,0
    1384313930va (VaSet
     
    1384913936blo "-80500,73300"
    1385013937)
    13851 *471 (Text
     13938*470 (Text
    1385213939uid 12299,0
    1385313940va (VaSet
     
    1385813945blo "-80500,74300"
    1385913946)
    13860 *472 (Text
     13947*471 (Text
    1386113948uid 12300,0
    1386213949va (VaSet
     
    1390313990)
    1390413991)
    13905 *473 (Net
     13992*472 (Net
    1390613993uid 12304,0
    1390713994decl (Decl
     
    1391914006)
    1392014007xt "-172000,65200,-149500,66000"
    13921 st "SIGNAL dout                   : std_logic"
    13922 )
    13923 )
    13924 *474 (SaComponent
     14008st "SIGNAL dout                   : std_logic
     14009"
     14010)
     14011)
     14012*473 (SaComponent
    1392514013uid 12625,0
    1392614014optionalChildren [
    13927 *475 (CptPort
     14015*474 (CptPort
    1392814016uid 12605,0
    1392914017ps "OnEdgeStrategy"
     
    1395814046)
    1395914047)
    13960 *476 (CptPort
     14048*475 (CptPort
    1396114049uid 12609,0
    1396214050ps "OnEdgeStrategy"
     
    1399414082)
    1399514083)
    13996 *477 (CptPort
     14084*476 (CptPort
    1399714085uid 12613,0
    1399814086ps "OnEdgeStrategy"
     
    1402914117)
    1403014118)
    14031 *478 (CptPort
     14119*477 (CptPort
    1403214120uid 12617,0
    1403314121ps "OnEdgeStrategy"
     
    1406314151)
    1406414152)
    14065 *479 (CptPort
     14153*478 (CptPort
    1406614154uid 12621,0
    1406714155ps "OnEdgeStrategy"
     
    1409914187)
    1410014188)
    14101 *480 (CptPort
     14189*479 (CptPort
    1410214190uid 12673,0
    1410314191ps "OnEdgeStrategy"
     
    1414914237stg "VerticalLayoutStrategy"
    1415014238textVec [
    14151 *481 (Text
     14239*480 (Text
    1415214240uid 12628,0
    1415314241va (VaSet
     
    1415914247tm "BdLibraryNameMgr"
    1416014248)
    14161 *482 (Text
     14249*481 (Text
    1416214250uid 12629,0
    1416314251va (VaSet
     
    1416914257tm "CptNameMgr"
    1417014258)
    14171 *483 (Text
     14259*482 (Text
    1417214260uid 12630,0
    1417314261va (VaSet
     
    1421614304archFileType "UNKNOWN"
    1421714305)
    14218 *484 (Net
     14306*483 (Net
    1421914307uid 12641,0
    1422014308decl (Decl
     
    1423214320)
    1423314321xt "-172000,66000,-149500,66800"
    14234 st "SIGNAL dout1                  : std_logic"
    14235 )
    14236 )
    14237 *485 (Net
     14322st "SIGNAL dout1                  : std_logic
     14323"
     14324)
     14325)
     14326*484 (Net
    1423814327uid 12647,0
    1423914328decl (Decl
     
    1425614345st "-- --
    1425714346--      drs_dwrite : out std_logic := '1';
    14258 SIGNAL drs_readout_ready      : std_logic                                    := '0'"
    14259 )
    14260 )
    14261 *486 (Net
     14347SIGNAL drs_readout_ready      : std_logic                                    := '0'
     14348"
     14349)
     14350)
     14351*485 (Net
    1426214352uid 12653,0
    1426314353decl (Decl
     
    1427314363)
    1427414364xt "-172000,71600,-149500,72400"
    14275 st "SIGNAL drs_readout_ready_ack  : std_logic"
    14276 )
    14277 )
    14278 *487 (Net
     14365st "SIGNAL drs_readout_ready_ack  : std_logic
     14366"
     14367)
     14368)
     14369*486 (Net
    1427914370uid 12705,0
    1428014371decl (Decl
     
    1429014381)
    1429114382xt "-172000,20000,-153500,20800"
    14292 st "additional_flasher_out : std_logic"
    14293 )
    14294 )
    14295 *488 (PortIoOut
     14383st "additional_flasher_out : std_logic
     14384"
     14385)
     14386)
     14387*487 (PortIoOut
    1429614388uid 12713,0
    1429714389shape (CompositeShape
     
    1433714429)
    1433814430)
    14339 *489 (SaComponent
     14431*488 (SaComponent
    1434014432uid 13117,0
    1434114433optionalChildren [
    14342 *490 (CptPort
     14434*489 (CptPort
    1434314435uid 13101,0
    1434414436ps "OnEdgeStrategy"
     
    1435014442fg "0,65535,0"
    1435114443)
    14352 xt "63000,61625,63750,62375"
     14444xt "72000,61625,72750,62375"
    1435314445)
    1435414446tg (CPTG
     
    1436014452va (VaSet
    1436114453)
    14362 xt "60100,61500,62000,62500"
     14454xt "69100,61500,71000,62500"
    1436314455st "CLK"
    1436414456ju 2
    14365 blo "62000,62300"
     14457blo "71000,62300"
    1436614458)
    1436714459)
     
    1437414466)
    1437514467)
    14376 *491 (CptPort
     14468*490 (CptPort
    1437714469uid 13105,0
    1437814470ps "OnEdgeStrategy"
     
    1438414476fg "0,65535,0"
    1438514477)
    14386 xt "63000,62625,63750,63375"
     14478xt "72000,62625,72750,63375"
    1438714479)
    1438814480tg (CPTG
     
    1439414486va (VaSet
    1439514487)
    14396 xt "59400,62500,62000,63500"
     14488xt "68400,62500,71000,63500"
    1439714489st "enable"
    1439814490ju 2
    14399 blo "62000,63300"
     14491blo "71000,63300"
    1440014492)
    1440114493)
     
    1440814500)
    1440914501)
    14410 *492 (CptPort
     14502*491 (CptPort
    1441114503uid 13109,0
    1441214504ps "OnEdgeStrategy"
     
    1441814510fg "0,65535,0"
    1441914511)
    14420 xt "63000,63625,63750,64375"
     14512xt "72000,63625,72750,64375"
    1442114513)
    1442214514tg (CPTG
     
    1442814520va (VaSet
    1442914521)
    14430 xt "55900,63500,62000,64500"
     14522xt "64900,63500,71000,64500"
    1443114523st "multiplier : (7:0)"
    1443214524ju 2
    14433 blo "62000,64300"
     14525blo "71000,64300"
    1443414526)
    1443514527)
     
    1444314535)
    1444414536)
    14445 *493 (CptPort
     14537*492 (CptPort
    1444614538uid 13113,0
    1444714539ps "OnEdgeStrategy"
     
    1445314545fg "0,65535,0"
    1445414546)
    14455 xt "50250,61625,51000,62375"
     14547xt "59250,61625,60000,62375"
    1445614548)
    1445714549tg (CPTG
     
    1446314555va (VaSet
    1446414556)
    14465 xt "52000,61500,54800,62500"
     14557xt "61000,61500,63800,62500"
    1446614558st "trigger"
    14467 blo "52000,62300"
     14559blo "61000,62300"
    1446814560)
    1446914561)
     
    1448614578lineWidth 2
    1448714579)
    14488 xt "51000,61000,63000,65000"
     14580xt "60000,61000,72000,65000"
    1448914581)
    1449014582oxt "0,0,8000,10000"
     
    1449414586stg "VerticalLayoutStrategy"
    1449514587textVec [
     14588*493 (Text
     14589uid 13120,0
     14590va (VaSet
     14591font "Arial,8,1"
     14592)
     14593xt "62350,65000,68550,66000"
     14594st "FACT_FAD_lib"
     14595blo "62350,65800"
     14596tm "BdLibraryNameMgr"
     14597)
    1449614598*494 (Text
    14497 uid 13120,0
     14599uid 13121,0
    1449814600va (VaSet
    1449914601font "Arial,8,1"
    1450014602)
    14501 xt "53350,65000,59550,66000"
    14502 st "FACT_FAD_lib"
    14503 blo "53350,65800"
    14504 tm "BdLibraryNameMgr"
     14603xt "62350,66000,69650,67000"
     14604st "continous_pulser"
     14605blo "62350,66800"
     14606tm "CptNameMgr"
    1450514607)
    1450614608*495 (Text
    14507 uid 13121,0
     14609uid 13122,0
    1450814610va (VaSet
    1450914611font "Arial,8,1"
    1451014612)
    14511 xt "53350,66000,60650,67000"
    14512 st "continous_pulser"
    14513 blo "53350,66800"
    14514 tm "CptNameMgr"
    14515 )
    14516 *496 (Text
    14517 uid 13122,0
    14518 va (VaSet
    14519 font "Arial,8,1"
    14520 )
    14521 xt "53350,67000,55150,68000"
     14613xt "62350,67000,64150,68000"
    1452214614st "U_3"
    14523 blo "53350,67800"
     14615blo "62350,67800"
    1452414616tm "InstanceNameMgr"
    1452514617)
     
    1453614628font "Courier New,8,0"
    1453714629)
    14538 xt "44000,60200,71500,61000"
     14630xt "53000,60200,80500,61000"
    1453914631st "MINIMAL_TRIGGER_WAIT_TIME = 250000    ( integer )  "
    1454014632)
     
    1455614648fg "49152,49152,49152"
    1455714649)
    14558 xt "51250,63250,52750,64750"
     14650xt "60250,63250,61750,64750"
    1455914651iconName "VhdlFileViewIcon.png"
    1456014652iconMaskName "VhdlFileViewIcon.msk"
     
    1456714659archFileType "UNKNOWN"
    1456814660)
    14569 *497 (Net
     14661*496 (Net
    1457014662uid 13157,0
    1457114663decl (Decl
     
    1458214674)
    1458314675xt "-172000,43600,-128500,44400"
    14584 st "SIGNAL c_trigger_enable       : std_logic                                    := '0'"
    14585 )
    14586 )
    14587 *498 (Net
     14676st "SIGNAL c_trigger_enable       : std_logic                                    := '0'
     14677"
     14678)
     14679)
     14680*497 (Net
    1458814681uid 13163,0
    1458914682decl (Decl
     
    1460314696)
    1460414697xt "-172000,44400,-112000,45200"
    14605 st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes"
    14606 )
    14607 )
    14608 *499 (Net
     14698st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes
     14699"
     14700)
     14701)
     14702*498 (Net
    1460914703uid 13206,0
    1461014704decl (Decl
     
    1462014714)
    1462114715xt "-172000,88400,-149500,89200"
    14622 st "SIGNAL s_trigger_0            : std_logic"
    14623 )
    14624 )
    14625 *500 (Net
     14716st "SIGNAL s_trigger_0            : std_logic
     14717"
     14718)
     14719)
     14720*499 (Net
    1462614721uid 13208,0
    1462714722decl (Decl
     
    1463714732)
    1463814733xt "-172000,97200,-149500,98000"
    14639 st "SIGNAL trigger1               : std_logic"
    14640 )
    14641 )
    14642 *501 (MWC
     14734st "SIGNAL trigger1               : std_logic
     14735"
     14736)
     14737)
     14738*500 (MWC
    1464314739uid 13266,0
    1464414740optionalChildren [
    14645 *502 (CptPort
     14741*501 (CptPort
    1464614742uid 13230,0
    1464714743optionalChildren [
    14648 *503 (Line
     14744*502 (Line
    1464914745uid 13234,0
    1465014746layer 5
     
    1465314749vasetType 3
    1465414750)
    14655 xt "40408,62000,42000,62000"
    14656 pts [
    14657 "42000,62000"
    14658 "40408,62000"
     14751xt "52408,62000,54000,62000"
     14752pts [
     14753"54000,62000"
     14754"52408,62000"
    1465914755]
    1466014756)
     
    1466914765fg "0,65535,65535"
    1467014766)
    14671 xt "42000,61625,42750,62375"
     14767xt "54000,61625,54750,62375"
    1467214768)
    1467314769tg (CPTG
     
    1468214778font "arial,8,0"
    1468314779)
    14684 xt "205750,61700,207550,62700"
     14780xt "217750,61700,219550,62700"
    1468514781st "din1"
    1468614782ju 2
    14687 blo "207550,62500"
     14783blo "219550,62500"
    1468814784)
    1468914785)
     
    1469714793)
    1469814794)
    14699 *504 (CptPort
     14795*503 (CptPort
    1470014796uid 13235,0
    1470114797optionalChildren [
    14702 *505 (Property
     14798*504 (Property
    1470314799uid 13239,0
    1470414800pclass "_MW_GEOM_"
     
    1470614802ptn "String"
    1470714803)
    14708 *506 (Line
     14804*505 (Line
    1470914805uid 13240,0
    1471014806layer 5
     
    1471314809vasetType 3
    1471414810)
    14715 xt "36000,61000,37000,61000"
    14716 pts [
    14717 "36000,61000"
    14718 "37000,61000"
     14811xt "48000,61000,49000,61000"
     14812pts [
     14813"48000,61000"
     14814"49000,61000"
    1471914815]
    1472014816)
     
    1472914825fg "0,65535,65535"
    1473014826)
    14731 xt "35250,60625,36000,61375"
     14827xt "47250,60625,48000,61375"
    1473214828)
    1473314829tg (CPTG
     
    1474214838font "arial,8,0"
    1474314839)
    14744 xt "202500,60532,204300,61532"
     14840xt "214500,60532,216300,61532"
    1474514841st "dout"
    14746 blo "202500,61332"
     14842blo "214500,61332"
    1474714843)
    1474814844)
     
    1475714853)
    1475814854)
    14759 *507 (CptPort
     14855*506 (CptPort
    1476014856uid 13241,0
    1476114857optionalChildren [
    14762 *508 (Line
     14858*507 (Line
    1476314859uid 13245,0
    1476414860layer 5
     
    1476714863vasetType 3
    1476814864)
    14769 xt "40408,60000,42000,60000"
    14770 pts [
    14771 "42000,60000"
    14772 "40408,60000"
     14865xt "52408,60000,54000,60000"
     14866pts [
     14867"54000,60000"
     14868"52408,60000"
    1477314869]
    1477414870)
     
    1478314879fg "0,65535,65535"
    1478414880)
    14785 xt "42000,59625,42750,60375"
     14881xt "54000,59625,54750,60375"
    1478614882)
    1478714883tg (CPTG
     
    1479614892font "arial,8,0"
    1479714893)
    14798 xt "205635,59294,207435,60294"
     14894xt "217635,59294,219435,60294"
    1479914895st "din0"
    1480014896ju 2
    14801 blo "207435,60094"
     14897blo "219435,60094"
    1480214898)
    1480314899)
     
    1481114907)
    1481214908)
    14813 *509 (CommentGraphic
     14909*508 (CommentGraphic
    1481414910uid 13246,0
    1481514911shape (Arc2D
    1481614912pts [
    14817 "37000,61000"
    14818 "38737,59521"
    14819 "41000,59004"
     14913"49000,61000"
     14914"50737,59521"
     14915"53000,59004"
    1482014916]
    1482114917uid 13247,0
     
    1482814924lineColor "26368,26368,26368"
    1482914925)
    14830 xt "37000,59003,41000,61000"
     14926xt "49000,59003,53000,61000"
    1483114927)
    1483214928oxt "7000,6003,11000,8000"
    1483314929)
    14834 *510 (CommentGraphic
     14930*509 (CommentGraphic
    1483514931uid 13248,0
    1483614932shape (Arc2D
    1483714933pts [
    14838 "41004,62998"
    14839 "38551,62394"
    14840 "37000,61005"
     14934"53004,62998"
     14935"50551,62394"
     14936"49000,61005"
    1484114937]
    1484214938uid 13249,0
     
    1484914945lineColor "26368,26368,26368"
    1485014946)
    14851 xt "37000,61005,41004,62999"
     14947xt "49000,61005,53004,62999"
    1485214948)
    1485314949oxt "7000,8005,11004,10000"
    1485414950)
    14855 *511 (Grouping
     14951*510 (Grouping
    1485614952uid 13250,0
    1485714953optionalChildren [
    14858 *512 (CommentGraphic
     14954*511 (CommentGraphic
    1485914955uid 13252,0
    1486014956optionalChildren [
    14861 *513 (Property
     14957*512 (Property
    1486214958uid 13254,0
    1486314959pclass "_MW_GEOM_"
     
    1486814964shape (CustomPolygon
    1486914965pts [
    14870 "41000,62998"
    14871 "38952,62132"
    14872 "37000,61000"
    14873 "38048,60156"
    14874 "39817,59211"
    14875 "41000,59000"
    14876 "41000,62998"
     14966"53000,62998"
     14967"50952,62132"
     14968"49000,61000"
     14969"50048,60156"
     14970"51817,59211"
     14971"53000,59000"
     14972"53000,62998"
    1487714973]
    1487814974uid 13253,0
     
    1488614982fillStyle 1
    1488714983)
    14888 xt "37000,59000,41000,62998"
     14984xt "49000,59000,53000,62998"
    1488914985)
    1489014986oxt "7000,6000,11000,9998"
    1489114987)
    14892 *514 (CommentGraphic
     14988*513 (CommentGraphic
    1489314989uid 13255,0
    1489414990optionalChildren [
    14895 *515 (Property
     14991*514 (Property
    1489614992uid 13257,0
    1489714993pclass "_MW_GEOM_"
     
    1490214998shape (Arc2D
    1490314999pts [
    14904 "41000,63000"
    14905 "40237,61001"
    14906 "41000,59000"
     15000"53000,63000"
     15001"52237,61001"
     15002"53000,59000"
    1490715003]
    1490815004uid 13256,0
     
    1491715013fillStyle 1
    1491815014)
    14919 xt "40236,59000,41000,63000"
     15015xt "52236,59000,53000,63000"
    1492015016)
    1492115017oxt "10238,6000,11000,10000"
     
    1493115027lineWidth 2
    1493215028)
    14933 xt "37000,59000,41000,63000"
     15029xt "49000,59000,53000,63000"
    1493415030)
    1493515031oxt "7000,6000,11000,10000"
    1493615032)
    14937 *516 (CommentGraphic
     15033*515 (CommentGraphic
    1493815034uid 13258,0
    1493915035shape (PolyLine2D
    1494015036pts [
    14941 "37000,61000"
    14942 "37000,61000"
     15037"49000,61000"
     15038"49000,61000"
    1494315039]
    1494415040uid 13259,0
     
    1495015046fg "49152,49152,49152"
    1495115047)
    14952 xt "37000,61000,37000,61000"
     15048xt "49000,61000,49000,61000"
    1495315049)
    1495415050oxt "7000,8000,7000,8000"
    1495515051)
    14956 *517 (CommentGraphic
     15052*516 (CommentGraphic
    1495715053uid 13260,0
    1495815054optionalChildren [
    14959 *518 (Property
     15055*517 (Property
    1496015056uid 13262,0
    1496115057pclass "_MW_GEOM_"
     
    1496615062shape (PolyLine2D
    1496715063pts [
    14968 "41000,59000"
    14969 "41000,59000"
     15064"53000,59000"
     15065"53000,59000"
    1497015066]
    1497115067uid 13261,0
     
    1497715073fg "49152,49152,49152"
    1497815074)
    14979 xt "41000,59000,41000,59000"
     15075xt "53000,59000,53000,59000"
    1498015076)
    1498115077oxt "11000,6000,11000,6000"
    1498215078)
    14983 *519 (CommentGraphic
     15079*518 (CommentGraphic
    1498415080uid 13263,0
    1498515081optionalChildren [
    14986 *520 (Property
     15082*519 (Property
    1498715083uid 13265,0
    1498815084pclass "_MW_GEOM_"
     
    1499315089shape (PolyLine2D
    1499415090pts [
    14995 "41000,63000"
    14996 "41000,63000"
     15091"53000,63000"
     15092"53000,63000"
    1499715093]
    1499815094uid 13264,0
     
    1500415100fg "49152,49152,49152"
    1500515101)
    15006 xt "41000,63000,41000,63000"
     15102xt "53000,63000,53000,63000"
    1500715103)
    1500815104oxt "11000,10000,11000,10000"
     
    1501715113lineWidth -1
    1501815114)
    15019 xt "36000,59000,42000,63000"
     15115xt "48000,59000,54000,63000"
    1502015116fos 1
    1502115117)
     
    1502715123stg "VerticalLayoutStrategy"
    1502815124textVec [
    15029 *521 (Text
     15125*520 (Text
    1503015126uid 13269,0
    1503115127va (VaSet
     
    1503315129font "arial,8,0"
    1503415130)
    15035 xt "37500,61500,42300,62500"
     15131xt "49500,61500,54300,62500"
    1503615132st "moduleware"
    15037 blo "37500,62300"
     15133blo "49500,62300"
     15134)
     15135*521 (Text
     15136uid 13270,0
     15137va (VaSet
     15138font "arial,8,0"
     15139)
     15140xt "49500,62500,50600,63500"
     15141st "or"
     15142blo "49500,63300"
    1503815143)
    1503915144*522 (Text
    15040 uid 13270,0
     15145uid 13271,0
    1504115146va (VaSet
    1504215147font "arial,8,0"
    1504315148)
    15044 xt "37500,62500,38600,63500"
    15045 st "or"
    15046 blo "37500,63300"
    15047 )
    15048 *523 (Text
    15049 uid 13271,0
    15050 va (VaSet
    15051 font "arial,8,0"
    15052 )
    15053 xt "37500,63500,39700,64500"
     15149xt "49500,63500,51700,64500"
    1505415150st "U_13"
    15055 blo "37500,64300"
     15151blo "49500,64300"
    1505615152tm "InstanceNameMgr"
    1505715153)
     
    1506815164font "arial,8,0"
    1506915165)
    15070 xt "21000,50000,21000,50000"
     15166xt "33000,50000,33000,50000"
    1507115167)
    1507215168header ""
     
    1509115187)
    1509215188)
    15093 *524 (PortIoIn
     15189*523 (PortIoIn
    1509415190uid 13689,0
    1509515191shape (CompositeShape
     
    1513615232)
    1513715233)
    15138 *525 (Net
     15234*524 (Net
    1513915235uid 13701,0
    1514015236decl (Decl
     
    1515115247)
    1515215248xt "-172000,4000,-143500,4800"
    15153 st "D_T_in                 : std_logic_vector(1 DOWNTO 0)"
    15154 )
    15155 )
    15156 *526 (PortIoIn
     15249st "D_T_in                 : std_logic_vector(1 DOWNTO 0)
     15250"
     15251)
     15252)
     15253*525 (PortIoIn
    1515715254uid 14042,0
    1515815255shape (CompositeShape
     
    1519915296)
    1520015297)
    15201 *527 (Net
     15298*526 (Net
    1520215299uid 14054,0
    1520315300decl (Decl
     
    1521415311)
    1521515312xt "-172000,11200,-121500,12000"
    15216 st "drs_refclk_in          : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
    15217 )
    15218 )
    15219 *528 (PortIoIn
     15313st "drs_refclk_in          : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit
     15314"
     15315)
     15316)
     15317*527 (PortIoIn
    1522015318uid 14165,0
    1522115319shape (CompositeShape
     
    1526215360)
    1526315361)
    15264 *529 (Net
     15362*528 (Net
    1526515363uid 14177,0
    1526615364decl (Decl
     
    1527815376)
    1527915377xt "-172000,12000,-114000,12800"
    15280 st "plllock_in             : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
    15281 )
    15282 )
    15283 *530 (SaComponent
     15378st "plllock_in             : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
     15379"
     15380)
     15381)
     15382*529 (SaComponent
    1528415383uid 14417,0
    1528515384optionalChildren [
    15286 *531 (CptPort
     15385*530 (CptPort
    1528715386uid 14397,0
    1528815387ps "OnEdgeStrategy"
     
    1531715416)
    1531815417)
    15319 *532 (CptPort
     15418*531 (CptPort
    1532015419uid 14401,0
    1532115420ps "OnEdgeStrategy"
     
    1535015449)
    1535115450)
    15352 *533 (CptPort
     15451*532 (CptPort
    1535315452uid 14405,0
    1535415453ps "OnEdgeStrategy"
     
    1538715486)
    1538815487)
    15389 *534 (CptPort
     15488*533 (CptPort
    1539015489uid 14409,0
    1539115490ps "OnEdgeStrategy"
     
    1542315522)
    1542415523)
    15425 *535 (CptPort
     15524*534 (CptPort
    1542615525uid 14413,0
    1542715526ps "OnEdgeStrategy"
     
    1547615575stg "VerticalLayoutStrategy"
    1547715576textVec [
    15478 *536 (Text
     15577*535 (Text
    1547915578uid 14420,0
    1548015579va (VaSet
     
    1548615585tm "BdLibraryNameMgr"
    1548715586)
    15488 *537 (Text
     15587*536 (Text
    1548915588uid 14421,0
    1549015589va (VaSet
     
    1549615595tm "CptNameMgr"
    1549715596)
    15498 *538 (Text
     15597*537 (Text
    1549915598uid 14422,0
    1550015599va (VaSet
     
    1554415643archFileType "UNKNOWN"
    1554515644)
    15546 *539 (Net
     15645*538 (Net
    1554715646uid 14477,0
    1554815647decl (Decl
     
    1556115660)
    1556215661xt "-172000,20800,-118500,21600"
    15563 st "alarm_refclk_too_high  : std_logic                                    := '0' -- default domino wave off"
    15564 )
    15565 )
    15566 *540 (PortIoOut
     15662st "alarm_refclk_too_high  : std_logic                                    := '0' -- default domino wave off
     15663"
     15664)
     15665)
     15666*539 (PortIoOut
    1556715667uid 14485,0
    1556815668shape (CompositeShape
     
    1560815708)
    1560915709)
    15610 *541 (Net
     15710*540 (Net
    1561115711uid 14491,0
    1561215712decl (Decl
     
    1562515725)
    1562615726xt "-172000,21600,-118500,22400"
    15627 st "alarm_refclk_too_low   : std_logic                                    := '0' -- default domino wave off"
    15628 )
    15629 )
    15630 *542 (PortIoOut
     15727st "alarm_refclk_too_low   : std_logic                                    := '0' -- default domino wave off
     15728"
     15729)
     15730)
     15731*541 (PortIoOut
    1563115732uid 14499,0
    1563215733shape (CompositeShape
     
    1567215773)
    1567315774)
    15674 *543 (Net
     15775*542 (Net
    1567515776uid 14620,0
    1567615777decl (Decl
     
    1568815789)
    1568915790xt "-172000,23200,-126000,24000"
    15690 st "counter_result         : std_logic_vector(11 downto 0)                := (others => '0')"
    15691 )
    15692 )
    15693 *544 (PortIoOut
     15791st "counter_result         : std_logic_vector(11 downto 0)                := (others => '0')
     15792"
     15793)
     15794)
     15795*543 (PortIoOut
    1569415796uid 14628,0
    1569515797shape (CompositeShape
     
    1573515837)
    1573615838)
    15737 *545 (MWC
     15839*544 (MWC
    1573815840uid 14991,0
    1573915841optionalChildren [
    15740 *546 (CptPort
     15842*545 (CptPort
    1574115843uid 14963,0
    1574215844optionalChildren [
    15743 *547 (Line
     15845*546 (Line
    1574415846uid 14967,0
    1574515847layer 5
     
    1575415856]
    1575515857)
    15756 *548 (Property
     15858*547 (Property
    1575715859uid 14968,0
    1575815860pclass "_MW_GEOM_"
     
    1580215904)
    1580315905)
    15804 *549 (CptPort
     15906*548 (CptPort
    1580515907uid 14969,0
    1580615908optionalChildren [
    15807 *550 (Line
     15909*549 (Line
    1580815910uid 14973,0
    1580915911layer 5
     
    1585815960)
    1585915961)
    15860 *551 (CptPort
     15962*550 (CptPort
    1586115963uid 14974,0
    1586215964optionalChildren [
    15863 *552 (Line
     15965*551 (Line
    1586415966uid 14978,0
    1586515967layer 5
     
    1591416016)
    1591516017)
    15916 *553 (CommentGraphic
     16018*552 (CommentGraphic
    1591716019uid 14979,0
    1591816020optionalChildren [
    15919 *554 (Property
     16021*553 (Property
    1592016022uid 14981,0
    1592116023pclass "_MW_GEOM_"
     
    1594116043oxt "7000,10000,7000,10000"
    1594216044)
    15943 *555 (CommentGraphic
     16045*554 (CommentGraphic
    1594416046uid 14982,0
    1594516047optionalChildren [
    15946 *556 (Property
     16048*555 (Property
    1594716049uid 14984,0
    1594816050pclass "_MW_GEOM_"
     
    1596816070oxt "7000,6000,7000,6000"
    1596916071)
    15970 *557 (Grouping
     16072*556 (Grouping
    1597116073uid 14985,0
    1597216074optionalChildren [
    15973 *558 (CommentGraphic
     16075*557 (CommentGraphic
    1597416076uid 14987,0
    1597516077shape (PolyLine2D
     
    1599216094oxt "7000,6000,9000,10000"
    1599316095)
    15994 *559 (CommentGraphic
     16096*558 (CommentGraphic
    1599516097uid 14989,0
    1599616098shape (Arc2D
     
    1604516147stg "VerticalLayoutStrategy"
    1604616148textVec [
    16047 *560 (Text
     16149*559 (Text
    1604816150uid 14994,0
    1604916151va (VaSet
     
    1605516157blo "162500,76300"
    1605616158)
    16057 *561 (Text
     16159*560 (Text
    1605816160uid 14995,0
    1605916161va (VaSet
     
    1606416166blo "162500,77300"
    1606516167)
    16066 *562 (Text
     16168*561 (Text
    1606716169uid 14996,0
    1606816170va (VaSet
     
    1610916211)
    1611016212)
    16111 *563 (MWC
     16213*562 (MWC
    1611216214uid 15036,0
    1611316215optionalChildren [
    16114 *564 (CptPort
     16216*563 (CptPort
    1611516217uid 15005,0
    1611616218optionalChildren [
    16117 *565 (Property
     16219*564 (Property
    1611816220uid 15009,0
    1611916221pclass "_MW_GEOM_"
     
    1612116223ptn "String"
    1612216224)
    16123 *566 (Line
     16225*565 (Line
    1612416226uid 15010,0
    1612516227layer 5
     
    1617616278)
    1617716279)
    16178 *567 (CommentGraphic
     16280*566 (CommentGraphic
    1617916281uid 15016,0
    1618016282shape (Arc2D
     
    1619816300oxt "110003,265000,112000,269000"
    1619916301)
    16200 *568 (CommentGraphic
     16302*567 (CommentGraphic
    1620116303uid 15018,0
    1620216304shape (Arc2D
     
    1622016322oxt "112005,265000,114000,269004"
    1622116323)
    16222 *569 (Grouping
     16324*568 (Grouping
    1622316325uid 15020,0
    1622416326optionalChildren [
    16225 *570 (CommentGraphic
     16327*569 (CommentGraphic
    1622616328uid 15022,0
    1622716329optionalChildren [
    16228 *571 (Property
     16330*570 (Property
    1622916331uid 15024,0
    1623016332pclass "_MW_GEOM_"
     
    1625816360oxt "110000,265000,113998,269000"
    1625916361)
    16260 *572 (CommentGraphic
     16362*571 (CommentGraphic
    1626116363uid 15025,0
    1626216364optionalChildren [
    16263 *573 (Property
     16365*572 (Property
    1626416366uid 15027,0
    1626516367pclass "_MW_GEOM_"
     
    1630516407oxt "110000,265000,114000,269000"
    1630616408)
    16307 *574 (CommentGraphic
     16409*573 (CommentGraphic
    1630816410uid 15028,0
    1630916411shape (PolyLine2D
     
    1632516427oxt "112000,265000,112000,265000"
    1632616428)
    16327 *575 (CommentGraphic
     16429*574 (CommentGraphic
    1632816430uid 15030,0
    1632916431optionalChildren [
    16330 *576 (Property
     16432*575 (Property
    1633116433uid 15032,0
    1633216434pclass "_MW_GEOM_"
     
    1635316455oxt "110000,269000,110000,269000"
    1635416456)
    16355 *577 (CommentGraphic
     16457*576 (CommentGraphic
    1635616458uid 15033,0
    1635716459optionalChildren [
    16358 *578 (Property
     16460*577 (Property
    1635916461uid 15035,0
    1636016462pclass "_MW_GEOM_"
     
    1638116483oxt "114000,269000,114000,269000"
    1638216484)
    16383 *579 (CptPort
     16485*578 (CptPort
    1638416486uid 15160,0
    1638516487optionalChildren [
    16386 *580 (Line
     16488*579 (Line
    1638716489uid 15164,0
    1638816490sl 0
     
    1643616538)
    1643716539)
    16438 *581 (CptPort
     16540*580 (CptPort
    1643916541uid 15165,0
    1644016542optionalChildren [
    16441 *582 (Line
     16543*581 (Line
    1644216544uid 15169,0
    1644316545sl 0
     
    1651116613stg "VerticalLayoutStrategy"
    1651216614textVec [
    16513 *583 (Text
     16615*582 (Text
    1651416616uid 15039,0
    1651516617va (VaSet
     
    1652116623blo "148500,89300"
    1652216624)
    16523 *584 (Text
     16625*583 (Text
    1652416626uid 15040,0
    1652516627va (VaSet
     
    1653016632blo "148500,90300"
    1653116633)
    16532 *585 (Text
     16634*584 (Text
    1653316635uid 15041,0
    1653416636va (VaSet
     
    1657516677)
    1657616678)
    16577 *586 (MWC
     16679*585 (MWC
    1657816680uid 15058,0
    1657916681optionalChildren [
    16580 *587 (CptPort
     16682*586 (CptPort
    1658116683uid 15045,0
    1658216684optionalChildren [
    16583 *588 (Line
     16685*587 (Line
    1658416686uid 15049,0
    1658516687layer 5
     
    1664316745)
    1664416746)
    16645 *589 (CptPort
     16747*588 (CptPort
    1664616748uid 15050,0
    1664716749optionalChildren [
    16648 *590 (Line
     16750*589 (Line
    1664916751uid 15054,0
    1665016752layer 5
     
    1665916761]
    1666016762)
    16661 *591 (Circle
     16763*590 (Circle
    1666216764uid 15055,0
    1666316765va (VaSet
     
    1672116823)
    1672216824)
    16723 *592 (CommentGraphic
     16825*591 (CommentGraphic
    1672416826uid 15056,0
    1672516827shape (CustomPolygon
     
    1676316865stg "VerticalLayoutStrategy"
    1676416866textVec [
    16765 *593 (Text
     16867*592 (Text
    1676616868uid 15061,0
    1676716869va (VaSet
     
    1677316875blo "155350,77900"
    1677416876)
    16775 *594 (Text
     16877*593 (Text
    1677616878uid 15062,0
    1677716879va (VaSet
     
    1678216884blo "155350,78900"
    1678316885)
    16784 *595 (Text
     16886*594 (Text
    1678516887uid 15063,0
    1678616888va (VaSet
     
    1682716929)
    1682816930)
    16829 *596 (Net
     16931*595 (Net
    1683016932uid 15077,0
    1683116933decl (Decl
     
    1684416946)
    1684516947xt "-172000,63600,-115000,64400"
    16846 st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off"
    16847 )
    16848 )
    16849 *597 (Net
     16948st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off
     16949"
     16950)
     16951)
     16952*596 (Net
    1685016953uid 15079,0
    1685116954decl (Decl
     
    1686416967)
    1686516968xt "-172000,64400,-115000,65200"
    16866 st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off"
    16867 )
    16868 )
    16869 *598 (Net
     16969st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off
     16970"
     16971)
     16972)
     16973*597 (Net
    1687016974uid 15126,0
    1687116975decl (Decl
     
    1688416988)
    1688516989xt "-172000,62800,-115000,63600"
    16886 st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off"
     16990st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off
     16991"
     16992)
     16993)
     16994*598 (Net
     16995uid 15492,0
     16996decl (Decl
     16997n "trigger_out"
     16998t "std_logic"
     16999o 123
     17000suid 301,0
     17001i "'0'"
     17002)
     17003declText (MLText
     17004uid 15493,0
     17005va (VaSet
     17006font "Courier New,8,0"
     17007)
     17008xt "-172000,99600,-128500,100400"
     17009st "SIGNAL trigger_out            : std_logic                                    := '0'
     17010"
    1688717011)
    1688817012)
     
    1747917603lineWidth 2
    1748017604)
    17481 xt "-40250,68000,-21750,71000"
    17482 pts [
    17483 "-40250,68000"
    17484 "-36000,68000"
    17485 "-36000,71000"
    17486 "-21750,71000"
     17605xt "-40250,69000,-21750,70000"
     17606pts [
     17607"-40250,69000"
     17608"-36000,69000"
     17609"-36000,70000"
     17610"-21750,70000"
    1748717611]
    1748817612)
     
    1751817642lineWidth 2
    1751917643)
    17520 xt "750,66000,31250,73000"
    17521 pts [
    17522 "31250,73000"
    17523 "27000,73000"
    17524 "27000,66000"
    17525 "750,66000"
     17644xt "750,71000,27250,71000"
     17645pts [
     17646"27250,71000"
     17647"750,71000"
    1752617648]
    1752717649)
     
    1754217664va (VaSet
    1754317665)
    17544 xt "2000,65000,18700,66000"
     17666xt "1000,70000,17700,71000"
    1754517667st "ram_start_addr : (RAMADDRWIDTH64b-1:0)"
    17546 blo "2000,65800"
     17668blo "1000,70800"
    1754717669tm "WireNameMgr"
    1754817670)
     
    1755717679vasetType 3
    1755817680)
    17559 xt "63750,70000,87250,71000"
    17560 pts [
    17561 "63750,71000"
    17562 "78000,71000"
    17563 "78000,70000"
    17564 "87250,70000"
     17681xt "59750,71000,87250,71000"
     17682pts [
     17683"59750,71000"
     17684"87250,71000"
    1756517685]
    1756617686)
     
    1758017700va (VaSet
    1758117701)
    17582 xt "64000,70000,67400,71000"
     17702xt "60000,70000,63400,71000"
    1758317703st "wiz_busy"
    17584 blo "64000,70800"
     17704blo "60000,70800"
    1758517705tm "WireNameMgr"
    1758617706)
     
    1759517715vasetType 3
    1759617716)
    17597 xt "63750,71000,87250,72000"
    17598 pts [
    17599 "63750,72000"
    17600 "84000,72000"
    17601 "84000,71000"
    17602 "87250,71000"
     17717xt "59750,72000,87250,72000"
     17718pts [
     17719"59750,72000"
     17720"87250,72000"
    1760317721]
    1760417722)
     
    1761817736va (VaSet
    1761917737)
    17620 xt "64000,71000,69100,72000"
     17738xt "60000,71000,65100,72000"
    1762117739st "wiz_write_ea"
    17622 blo "64000,71800"
     17740blo "60000,71800"
    1762317741tm "WireNameMgr"
    1762417742)
     
    1763417752lineWidth 2
    1763517753)
    17636 xt "63750,72000,87250,79000"
    17637 pts [
    17638 "63750,73000"
    17639 "67000,73000"
    17640 "67000,79000"
    17641 "85000,79000"
    17642 "85000,72000"
    17643 "87250,72000"
     17754xt "59750,73000,87250,73000"
     17755pts [
     17756"59750,73000"
     17757"87250,73000"
    1764417758]
    1764517759)
     
    1766017774va (VaSet
    1766117775)
    17662 xt "64000,72000,73400,73000"
     17776xt "60000,72000,69400,73000"
    1766317777st "wiz_write_length : (16:0)"
    17664 blo "64000,72800"
     17778blo "60000,72800"
    1766517779tm "WireNameMgr"
    1766617780)
     
    1767617790lineWidth 2
    1767717791)
    17678 xt "63750,73000,87250,74000"
    17679 pts [
    17680 "63750,74000"
    17681 "84000,74000"
    17682 "84000,73000"
    17683 "87250,73000"
     17792xt "59750,74000,87250,74000"
     17793pts [
     17794"59750,74000"
     17795"87250,74000"
    1768417796]
    1768517797)
     
    1770017812va (VaSet
    1770117813)
    17702 xt "64000,73000,82800,74000"
     17814xt "60000,73000,78800,74000"
    1770317815st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
    17704 blo "64000,73800"
     17816blo "60000,73800"
    1770517817tm "WireNameMgr"
    1770617818)
     
    1771617828lineWidth 2
    1771717829)
    17718 xt "63750,74000,87250,80000"
    17719 pts [
    17720 "63750,75000"
    17721 "66000,75000"
    17722 "66000,80000"
    17723 "86000,80000"
    17724 "86000,74000"
    17725 "87250,74000"
     17830xt "59750,75000,87250,75000"
     17831pts [
     17832"59750,75000"
     17833"87250,75000"
    1772617834]
    1772717835)
     
    1774217850va (VaSet
    1774317851)
    17744 xt "64000,74000,75800,75000"
     17852xt "60000,74000,71800,75000"
    1774517853st "wiz_number_of_channels : (3:0)"
    17746 blo "64000,74800"
     17854blo "60000,74800"
    1774717855tm "WireNameMgr"
    1774817856)
     
    1775717865vasetType 3
    1775817866)
    17759 xt "63750,75000,87250,76000"
    17760 pts [
    17761 "63750,76000"
    17762 "84000,76000"
    17763 "84000,75000"
    17764 "87250,75000"
     17867xt "59750,76000,87250,76000"
     17868pts [
     17869"59750,76000"
     17870"87250,76000"
    1776517871]
    1776617872)
     
    1778017886va (VaSet
    1778117887)
    17782 xt "64000,75000,69500,76000"
     17888xt "60000,75000,65500,76000"
    1778317889st "wiz_write_end"
    17784 blo "64000,75800"
     17890blo "60000,75800"
    1778517891tm "WireNameMgr"
    1778617892)
     
    1779517901vasetType 3
    1779617902)
    17797 xt "63750,76000,87250,77000"
    17798 pts [
    17799 "63750,77000"
    17800 "71000,77000"
    17801 "71000,76000"
    17802 "87250,76000"
     17903xt "59750,77000,87250,77000"
     17904pts [
     17905"59750,77000"
     17906"87250,77000"
    1780317907]
    1780417908)
     
    1781817922va (VaSet
    1781917923)
    17820 xt "64000,76000,70600,77000"
     17924xt "60000,76000,66600,77000"
    1782117925st "wiz_write_header"
    17822 blo "64000,76800"
     17926blo "60000,76800"
    1782317927tm "WireNameMgr"
    1782417928)
     
    1783317937vasetType 3
    1783417938)
    17835 xt "750,67000,31250,74000"
    17836 pts [
    17837 "750,67000"
    17838 "26000,67000"
    17839 "26000,74000"
    17840 "31250,74000"
     17939xt "750,72000,27250,72000"
     17940pts [
     17941"750,72000"
     17942"27250,72000"
    1784117943]
    1784217944)
     
    1785617958va (VaSet
    1785717959)
    17858 xt "2000,66000,7300,67000"
     17960xt "1000,71000,6300,72000"
    1785917961st "ram_write_ea"
    17860 blo "2000,66800"
     17962blo "1000,71800"
    1786117963tm "WireNameMgr"
    1786217964)
     
    1787117973vasetType 3
    1787217974)
    17873 xt "750,68000,31250,75000"
    17874 pts [
    17875 "750,68000"
    17876 "25000,68000"
    17877 "25000,75000"
    17878 "31250,75000"
     17975xt "750,73000,27250,73000"
     17976pts [
     17977"750,73000"
     17978"27250,73000"
    1787917979]
    1788017980)
     
    1789417994va (VaSet
    1789517995)
    17896 xt "2000,67000,8300,68000"
     17996xt "1000,72000,7300,73000"
    1789717997st "ram_write_ready"
    17898 blo "2000,67800"
     17998blo "1000,72800"
    1789917999tm "WireNameMgr"
    1790018000)
     
    1790918009vasetType 3
    1791018010)
    17911 xt "750,73000,31250,78000"
    17912 pts [
    17913 "750,73000"
    17914 "23000,73000"
    17915 "23000,78000"
    17916 "31250,78000"
     18011xt "750,76000,27250,76000"
     18012pts [
     18013"750,76000"
     18014"27250,76000"
    1791718015]
    1791818016)
     
    1793318031va (VaSet
    1793418032)
    17935 xt "1000,72000,5800,73000"
     18033xt "1000,75000,5800,76000"
    1793618034st "config_start"
    17937 blo "1000,72800"
     18035blo "1000,75800"
    1793818036tm "WireNameMgr"
    1793918037)
     
    1794818046vasetType 3
    1794918047)
    17950 xt "750,75000,31250,80000"
    17951 pts [
    17952 "750,75000"
    17953 "21000,75000"
    17954 "21000,80000"
    17955 "31250,80000"
     18048xt "750,78000,27250,78000"
     18049pts [
     18050"750,78000"
     18051"27250,78000"
    1795618052]
    1795718053)
     
    1797118067va (VaSet
    1797218068)
    17973 xt "1000,74000,6100,75000"
     18069xt "1000,77000,6100,78000"
    1797418070st "config_ready"
    17975 blo "1000,74800"
     18071blo "1000,77800"
    1797618072tm "WireNameMgr"
    1797718073)
     
    1798618082vasetType 3
    1798718083)
    17988 xt "750,77000,31250,81000"
    17989 pts [
    17990 "750,77000"
    17991 "20000,77000"
    17992 "20000,81000"
    17993 "31250,81000"
     18084xt "750,79000,27250,79000"
     18085pts [
     18086"750,79000"
     18087"27250,79000"
    1799418088]
    1799518089)
     
    1800918103va (VaSet
    1801018104)
    18011 xt "1000,76000,4000,77000"
     18105xt "1000,78000,4000,79000"
    1801218106st "roi_max"
    18013 blo "1000,76800"
     18107blo "1000,78800"
    1801418108tm "WireNameMgr"
    1801518109)
     
    1802518119lineWidth 2
    1802618120)
    18027 xt "750,78000,31250,82000"
    18028 pts [
    18029 "750,78000"
    18030 "19000,78000"
    18031 "19000,82000"
    18032 "31250,82000"
     18121xt "750,80000,27250,80000"
     18122pts [
     18123"750,80000"
     18124"27250,80000"
    1803318125]
    1803418126)
     
    1804918141va (VaSet
    1805018142)
    18051 xt "1000,77000,10100,78000"
     18143xt "1000,79000,10100,80000"
    1805218144st "package_length : (15:0)"
    18053 blo "1000,77800"
     18145blo "1000,79800"
    1805418146tm "WireNameMgr"
    1805518147)
     
    1923819330vasetType 3
    1923919331)
    19240 xt "18000,88000,31250,88000"
     19332xt "18000,86000,27250,88000"
    1924119333pts [
    1924219334"18000,88000"
    19243 "31250,88000"
     19335"24000,88000"
     19336"24000,86000"
     19337"27250,86000"
    1924419338]
    1924519339)
     
    1925919353va (VaSet
    1926019354)
    19261 xt "28000,87000,31400,88000"
     19355xt "24000,85000,27400,86000"
    1926219356st "roi_array"
    19263 blo "28000,87800"
     19357blo "24000,85800"
    1926419358tm "WireNameMgr"
    1926519359)
     
    1953119625optionalChildren [
    1953219626&651
    19533 *672 (BdJunction
    19534 uid 6086,0
    19535 ps "OnConnectorStrategy"
    19536 shape (Circle
    19537 uid 6087,0
    19538 va (VaSet
    19539 vasetType 1
    19540 )
    19541 xt "27600,46600,28400,47400"
    19542 radius 400
    19543 )
    19544 )
    1954519627]
    1954619628shape (OrthoPolyLine
     
    1958419666on &188
    1958519667)
    19586 *673 (Wire
     19668*672 (Wire
    1958719669uid 5626,0
    1958819670shape (OrthoPolyLine
     
    1962019702on &266
    1962119703)
    19622 *674 (Wire
     19704*673 (Wire
    1962319705uid 5634,0
    1962419706shape (OrthoPolyLine
     
    1965819740on &265
    1965919741)
    19660 *675 (Wire
     19742*674 (Wire
    1966119743uid 5646,0
    1966219744shape (OrthoPolyLine
     
    1969419776on &185
    1969519777)
    19696 *676 (Wire
     19778*675 (Wire
    1969719779uid 5745,0
    1969819780shape (OrthoPolyLine
     
    1973219814on &276
    1973319815)
    19734 *677 (Wire
     19816*676 (Wire
    1973519817uid 5805,0
    1973619818shape (OrthoPolyLine
     
    1976619848on &187
    1976719849)
    19768 *678 (Wire
     19850*677 (Wire
    1976919851uid 5813,0
    1977019852shape (OrthoPolyLine
     
    1980419886on &293
    1980519887)
    19806 *679 (Wire
     19888*678 (Wire
    1980719889uid 5821,0
    1980819890shape (OrthoPolyLine
     
    1984219924on &294
    1984319925)
    19844 *680 (Wire
     19926*679 (Wire
    1984519927uid 5829,0
    1984619928shape (OrthoPolyLine
     
    1988019962on &295
    1988119963)
    19882 *681 (Wire
     19964*680 (Wire
    1988319965uid 5837,0
    1988419966shape (OrthoPolyLine
     
    1992020002on &296
    1992120003)
    19922 *682 (Wire
     20004*681 (Wire
    1992320005uid 5950,0
    1992420006shape (OrthoPolyLine
     
    1995820040on &301
    1995920041)
    19960 *683 (Wire
     20042*682 (Wire
    1996120043uid 5962,0
    1996220044shape (OrthoPolyLine
     
    1999620078on &302
    1999720079)
    19998 *684 (Wire
     20080*683 (Wire
    1999920081uid 6002,0
    2000020082shape (OrthoPolyLine
     
    2003420116on &304
    2003520117)
    20036 *685 (Wire
     20118*684 (Wire
    2003720119uid 6008,0
    2003820120shape (OrthoPolyLine
     
    2007220154on &303
    2007320155)
    20074 *686 (Wire
     20156*685 (Wire
    2007520157uid 6018,0
    2007620158shape (OrthoPolyLine
     
    2007920161vasetType 3
    2008020162)
    20081 xt "750,74000,31250,79000"
    20082 pts [
    20083 "750,74000"
    20084 "22000,74000"
    20085 "22000,79000"
    20086 "31250,79000"
     20163xt "750,77000,27250,77000"
     20164pts [
     20165"750,77000"
     20166"27250,77000"
    2008720167]
    2008820168)
     
    2010220182va (VaSet
    2010320183)
    20104 xt "1000,73000,8200,74000"
     20184xt "1000,76000,8200,77000"
    2010520185st "config_started_mm"
    20106 blo "1000,73800"
     20186blo "1000,76800"
    2010720187tm "WireNameMgr"
    2010820188)
     
    2011020190on &305
    2011120191)
    20112 *687 (Wire
     20192*686 (Wire
    2011320193uid 6064,0
    2011420194shape (OrthoPolyLine
     
    2014520225on &258
    2014620226)
    20147 *688 (Wire
     20227*687 (Wire
    2014820228uid 6072,0
    2014920229shape (OrthoPolyLine
     
    2018420264on &188
    2018520265)
    20186 *689 (Wire
    20187 uid 6082,0
    20188 shape (OrthoPolyLine
    20189 uid 6083,0
    20190 va (VaSet
    20191 vasetType 3
    20192 lineColor "0,32896,0"
    20193 )
    20194 xt "28000,47000,31250,71000"
    20195 pts [
    20196 "31250,71000"
    20197 "28000,71000"
    20198 "28000,47000"
    20199 ]
    20200 )
    20201 start &134
    20202 end &672
    20203 sat 32
    20204 eat 32
    20205 stc 0
    20206 st 0
    20207 sf 1
    20208 si 0
    20209 tg (WTG
    20210 uid 6084,0
    20211 ps "ConnStartEndStrategy"
    20212 stg "STSignalDisplayStrategy"
    20213 f (Text
    20214 uid 6085,0
    20215 va (VaSet
    20216 )
    20217 xt "28000,70000,31100,71000"
    20218 st "CLK_25"
    20219 blo "28000,70800"
    20220 tm "WireNameMgr"
    20221 )
    20222 )
    20223 on &188
    20224 )
    20225 *690 (Wire
     20266*688 (Wire
    2022620267uid 6160,0
    2022720268shape (OrthoPolyLine
     
    2026120302on &306
    2026220303)
    20263 *691 (Wire
     20304*689 (Wire
    2026420305uid 6276,0
    2026520306shape (OrthoPolyLine
     
    2026820309vasetType 3
    2026920310)
    20270 xt "-61000,67000,-52750,67000"
    20271 pts [
    20272 "-61000,67000"
    20273 "-52750,67000"
     20311xt "-61000,68000,-52750,68000"
     20312pts [
     20313"-61000,68000"
     20314"-52750,68000"
    2027420315]
    2027520316)
     
    2028720328va (VaSet
    2028820329)
    20289 xt "-58000,66000,-53500,67000"
     20330xt "-58000,67000,-53500,68000"
    2029020331st "CLK_25_PS"
    20291 blo "-58000,66800"
     20332blo "-58000,67800"
    2029220333tm "WireNameMgr"
    2029320334)
     
    2029520336on &185
    2029620337)
    20297 *692 (Wire
     20338*690 (Wire
    2029820339uid 6362,0
    2029920340shape (OrthoPolyLine
     
    2030820349]
    2030920350)
    20310 start &546
     20351start &545
    2031120352end &309
    2031220353ss 0
     
    2033420375on &308
    2033520376)
    20336 *693 (Wire
     20377*691 (Wire
    2033720378uid 6452,0
    2033820379shape (OrthoPolyLine
     
    2037020411on &310
    2037120412)
    20372 *694 (Wire
     20413*692 (Wire
    2037320414uid 6540,0
    2037420415shape (OrthoPolyLine
     
    2038420425)
    2038520426start &315
    20386 end &477
     20427end &476
    2038720428sat 32
    2038820429eat 32
     
    2040720448on &329
    2040820449)
    20409 *695 (Wire
     20450*693 (Wire
    2041020451uid 6548,0
    2041120452shape (OrthoPolyLine
     
    2044420485on &310
    2044520486)
    20446 *696 (Wire
     20487*694 (Wire
    2044720488uid 8416,0
    2044820489shape (OrthoPolyLine
     
    2045120492vasetType 3
    2045220493)
    20453 xt "63750,77000,87250,78000"
    20454 pts [
    20455 "63750,78000"
    20456 "84000,78000"
    20457 "84000,77000"
    20458 "87250,77000"
     20494xt "59750,78000,87250,78000"
     20495pts [
     20496"59750,78000"
     20497"87250,78000"
    2045920498]
    2046020499)
     
    2047420513va (VaSet
    2047520514)
    20476 xt "64000,77000,67000,78000"
     20515xt "60000,77000,63000,78000"
    2047720516st "wiz_ack"
    20478 blo "64000,77800"
     20517blo "60000,77800"
    2047920518tm "WireNameMgr"
    2048020519)
     
    2048220521on &341
    2048320522)
    20484 *697 (Wire
     20523*695 (Wire
    2048520524uid 8732,0
    2048620525shape (OrthoPolyLine
     
    2052020559on &360
    2052120560)
    20522 *698 (Wire
     20561*696 (Wire
    2052320562uid 8738,0
    2052420563shape (OrthoPolyLine
     
    2055620595on &361
    2055720596)
    20558 *699 (Wire
     20597*697 (Wire
    2055920598uid 8752,0
    2056020599shape (OrthoPolyLine
     
    2059120630on &361
    2059220631)
    20593 *700 (Wire
     20632*698 (Wire
    2059420633uid 9006,0
    2059520634shape (OrthoPolyLine
     
    2062920668on &362
    2063020669)
    20631 *701 (Wire
     20670*699 (Wire
    2063220671uid 9233,0
    2063320672shape (OrthoPolyLine
     
    2066420703on &376
    2066520704)
    20666 *702 (Wire
     20705*700 (Wire
    2066720706uid 9241,0
    2066820707shape (OrthoPolyLine
     
    2069920738on &377
    2070020739)
    20701 *703 (Wire
     20740*701 (Wire
    2070220741uid 9253,0
    2070320742shape (OrthoPolyLine
     
    2073320772on &376
    2073420773)
    20735 *704 (Wire
     20774*702 (Wire
    2073620775uid 9261,0
    2073720776shape (OrthoPolyLine
     
    2076720806on &377
    2076820807)
    20769 *705 (Wire
     20808*703 (Wire
    2077020809uid 9943,0
    2077120810shape (OrthoPolyLine
     
    2080220841on &378
    2080320842)
    20804 *706 (Wire
     20843*704 (Wire
    2080520844uid 9951,0
    2080620845shape (OrthoPolyLine
     
    2083720876on &379
    2083820877)
    20839 *707 (Wire
     20878*705 (Wire
    2084020879uid 10010,0
    2084120880shape (OrthoPolyLine
     
    2087520914on &398
    2087620915)
    20877 *708 (Wire
     20916*706 (Wire
    2087820917uid 10018,0
    2087920918shape (OrthoPolyLine
     
    2091120950on &379
    2091220951)
    20913 *709 (Wire
     20952*707 (Wire
    2091420953uid 10036,0
    2091520954shape (OrthoPolyLine
     
    2094520984on &378
    2094620985)
    20947 *710 (Wire
     20986*708 (Wire
    2094820987uid 10194,0
    2094920988shape (OrthoPolyLine
     
    2098521024on &399
    2098621025)
    20987 *711 (Wire
     21026*709 (Wire
    2098821027uid 10202,0
    2098921028shape (OrthoPolyLine
     
    2102321062on &400
    2102421063)
    21025 *712 (Wire
     21064*710 (Wire
    2102621065uid 10266,0
    2102721066shape (OrthoPolyLine
     
    2105621095)
    2105721096)
    21058 on &499
    21059 )
    21060 *713 (Wire
     21097on &498
     21098)
     21099*711 (Wire
    2106121100uid 10298,0
    2106221101shape (OrthoPolyLine
     
    2109421133on &402
    2109521134)
    21096 *714 (Wire
     21135*712 (Wire
    2109721136uid 10304,0
    2109821137shape (OrthoPolyLine
     
    2113021169on &403
    2113121170)
    21132 *715 (Wire
     21171*713 (Wire
    2113321172uid 10310,0
    2113421173shape (OrthoPolyLine
     
    2116621205on &404
    2116721206)
    21168 *716 (Wire
     21207*714 (Wire
    2116921208uid 10316,0
    2117021209shape (OrthoPolyLine
     
    2120421243on &405
    2120521244)
    21206 *717 (Wire
     21245*715 (Wire
    2120721246uid 10322,0
    2120821247shape (OrthoPolyLine
     
    2124221281on &406
    2124321282)
    21244 *718 (Wire
     21283*716 (Wire
    2124521284uid 10431,0
    2124621285shape (OrthoPolyLine
     
    2127921318on &401
    2128021319)
    21281 *719 (Wire
    21282 uid 10439,0
    21283 optionalChildren [
    21284 *720 (BdJunction
    21285 uid 12639,0
    21286 ps "OnConnectorStrategy"
    21287 shape (Circle
    21288 uid 12640,0
    21289 va (VaSet
    21290 vasetType 1
    21291 )
    21292 xt "-54400,71600,-53600,72400"
    21293 radius 400
    21294 )
    21295 )
    21296 ]
    21297 shape (OrthoPolyLine
    21298 uid 10440,0
    21299 va (VaSet
    21300 vasetType 3
    21301 )
    21302 xt "-54000,68000,-21750,72000"
    21303 pts [
    21304 "-21750,72000"
    21305 "-54000,72000"
    21306 "-54000,68000"
    21307 "-52750,68000"
    21308 ]
    21309 )
    21310 start &30
    21311 end &125
    21312 sat 32
    21313 eat 32
    21314 st 0
    21315 sf 1
    21316 si 0
    21317 tg (WTG
    21318 uid 10441,0
    21319 ps "ConnStartEndStrategy"
    21320 stg "STSignalDisplayStrategy"
    21321 f (Text
    21322 uid 10442,0
    21323 va (VaSet
    21324 )
    21325 xt "-25750,71000,-21150,72000"
    21326 st "trigger_out"
    21327 blo "-25750,71800"
    21328 tm "WireNameMgr"
    21329 )
    21330 )
    21331 on &431
    21332 )
    21333 *721 (Wire
     21320*717 (Wire
    2133421321uid 10467,0
    2133521322shape (OrthoPolyLine
     
    2133821325vasetType 3
    2133921326)
    21340 xt "750,69000,31250,76000"
    21341 pts [
    21342 "31250,76000"
    21343 "24000,76000"
    21344 "24000,69000"
    21345 "750,69000"
     21327xt "750,74000,27250,74000"
     21328pts [
     21329"27250,74000"
     21330"750,74000"
    2134621331]
    2134721332)
     
    2136221347va (VaSet
    2136321348)
    21364 xt "2000,68000,9800,69000"
     21349xt "1000,73000,8800,74000"
    2136521350st "ram_write_ready_ack"
    21366 blo "2000,68800"
     21351blo "1000,73800"
    2136721352tm "WireNameMgr"
    2136821353)
    2136921354)
    21370 on &432
    21371 )
    21372 *722 (Wire
     21355on &431
     21356)
     21357*718 (Wire
    2137321358uid 10629,0
    2137421359shape (OrthoPolyLine
     
    2140321388)
    2140421389)
    21405 on &433
    21406 )
    21407 *723 (Wire
     21390on &432
     21391)
     21392*719 (Wire
    2140821393uid 10637,0
    2140921394shape (OrthoPolyLine
     
    2143821423)
    2143921424)
    21440 on &434
    21441 )
    21442 *724 (Wire
     21425on &433
     21426)
     21427*720 (Wire
    2144321428uid 10685,0
    2144421429shape (OrthoPolyLine
     
    2145321438]
    2145421439)
    21455 end &447
     21440end &446
    2145621441sat 16
    2145721442eat 32
     
    2147321458)
    2147421459)
    21475 on &434
    21476 )
    21477 *725 (Wire
     21460on &433
     21461)
     21462*721 (Wire
    2147821463uid 10691,0
    2147921464shape (OrthoPolyLine
     
    2148821473]
    2148921474)
    21490 end &448
     21475end &447
    2149121476sat 16
    2149221477eat 32
     
    2150821493)
    2150921494)
    21510 on &433
    21511 )
    21512 *726 (Wire
     21495on &432
     21496)
     21497*722 (Wire
    2151321498uid 10699,0
    2151421499shape (OrthoPolyLine
     
    2152421509]
    2152521510)
    21526 end &442
     21511end &441
    2152721512sat 16
    2152821513eat 32
     
    2154621531on &187
    2154721532)
    21548 *727 (Wire
     21533*723 (Wire
    2154921534uid 10707,0
    2155021535shape (OrthoPolyLine
     
    2155921544]
    2156021545)
    21561 end &446
     21546end &445
    2156221547sat 16
    2156321548eat 32
     
    2157921564)
    2158021565)
    21581 on &453
    21582 )
    21583 *728 (Wire
     21566on &452
     21567)
     21568*724 (Wire
    2158421569uid 10723,0
    2158521570shape (OrthoPolyLine
     
    2159421579]
    2159521580)
    21596 start &443
    21597 end &436
     21581start &442
     21582end &435
    2159821583sat 32
    2159921584eat 32
     
    2161721602)
    2161821603)
    21619 on &435
    21620 )
    21621 *729 (Wire
     21604on &434
     21605)
     21606*725 (Wire
    2162221607uid 10737,0
    2162321608shape (OrthoPolyLine
     
    2163221617]
    2163321618)
    21634 start &444
    21635 end &438
     21619start &443
     21620end &437
    2163621621sat 32
    2163721622eat 32
     
    2165521640)
    2165621641)
    21657 on &437
    21658 )
    21659 *730 (Wire
     21642on &436
     21643)
     21644*726 (Wire
    2166021645uid 10751,0
    2166121646shape (OrthoPolyLine
     
    2167021655]
    2167121656)
    21672 start &445
    21673 end &440
     21657start &444
     21658end &439
    2167421659sat 32
    2167521660eat 32
     
    2169321678)
    2169421679)
    21695 on &439
    21696 )
    21697 *731 (Wire
     21680on &438
     21681)
     21682*727 (Wire
    2169821683uid 11405,0
    2169921684shape (OrthoPolyLine
     
    2172921714)
    2173021715)
    21731 on &453
    21732 )
    21733 *732 (Wire
     21716on &452
     21717)
     21718*728 (Wire
    2173421719uid 11858,0
    2173521720shape (OrthoPolyLine
     
    2176421749)
    2176521750)
    21766 on &454
    21767 )
    21768 *733 (Wire
     21751on &453
     21752)
     21753*729 (Wire
    2176921754uid 11952,0
    2177021755shape (OrthoPolyLine
     
    2177921764]
    2178021765)
    21781 end &461
     21766end &460
    2178221767sat 16
    2178321768eat 32
     
    2180021785)
    2180121786)
    21802 on &454
    21803 )
    21804 *734 (Wire
     21787on &453
     21788)
     21789*730 (Wire
    2180521790uid 12306,0
    2180621791shape (OrthoPolyLine
     
    2181621801)
    2181721802start &411
    21818 end &459
     21803end &458
    2181921804sat 32
    2182021805eat 32
     
    2183821823)
    2183921824)
    21840 on &473
    21841 )
    21842 *735 (Wire
    21843 uid 12635,0
    21844 shape (OrthoPolyLine
    21845 uid 12636,0
    21846 va (VaSet
    21847 vasetType 3
    21848 )
    21849 xt "-55250,72000,-54000,72000"
    21850 pts [
    21851 "-54000,72000"
    21852 "-55250,72000"
    21853 ]
    21854 )
    21855 start &720
    21856 end &476
    21857 sat 32
    21858 eat 32
    21859 stc 0
    21860 st 0
    21861 sf 1
    21862 si 0
    21863 tg (WTG
    21864 uid 12637,0
    21865 ps "ConnStartEndStrategy"
    21866 stg "STSignalDisplayStrategy"
    21867 f (Text
    21868 uid 12638,0
    21869 va (VaSet
    21870 )
    21871 xt "-54000,71000,-49400,72000"
    21872 st "trigger_out"
    21873 blo "-54000,71800"
    21874 tm "WireNameMgr"
    21875 )
    21876 )
    21877 on &431
    21878 )
    21879 *736 (Wire
     21825on &472
     21826)
     21827*731 (Wire
    2188021828uid 12643,0
    2188121829shape (OrthoPolyLine
     
    2189221840]
    2189321841)
    21894 start &456
    21895 end &475
     21842start &455
     21843end &474
    2189621844sat 32
    2189721845eat 32
     
    2191521863)
    2191621864)
    21917 on &484
    21918 )
    21919 *737 (Wire
     21865on &483
     21866)
     21867*732 (Wire
    2192021868uid 12649,0
    2192121869shape (OrthoPolyLine
     
    2192721875pts [
    2192821876"-21750,74000"
    21929 "-38000,74000"
    2193021877"-55250,74000"
    2193121878]
    2193221879)
    2193321880start &66
    21934 end &478
     21881end &477
    2193521882sat 32
    2193621883eat 32
     
    2195221899)
    2195321900)
    21954 on &485
    21955 )
    21956 *738 (Wire
     21901on &484
     21902)
     21903*733 (Wire
    2195721904uid 12655,0
    2195821905shape (OrthoPolyLine
     
    2196921916)
    2197021917start &67
    21971 end &479
     21918end &478
    2197221919sat 32
    2197321920eat 32
     
    2198921936)
    2199021937)
    21991 on &486
    21992 )
    21993 *739 (Wire
     21938on &485
     21939)
     21940*734 (Wire
    2199421941uid 12687,0
    2199521942shape (OrthoPolyLine
     
    2200721954]
    2200821955)
    22009 end &480
     21956end &479
    2201021957sat 16
    2201121958eat 32
     
    2202921976on &188
    2203021977)
    22031 *740 (Wire
     21978*735 (Wire
    2203221979uid 12707,0
    2203321980shape (OrthoPolyLine
     
    2204221989]
    2204321990)
    22044 start &449
    22045 end &488
     21991start &448
     21992end &487
    2204621993sat 32
    2204721994eat 32
     
    2206522012)
    2206622013)
    22067 on &487
    22068 )
    22069 *741 (Wire
     22014on &486
     22015)
     22016*736 (Wire
    2207022017uid 13143,0
    2207122018shape (OrthoPolyLine
     
    2207422021vasetType 3
    2207522022)
    22076 xt "63750,62000,69000,62000"
    22077 pts [
    22078 "69000,62000"
    22079 "63750,62000"
    22080 ]
    22081 )
    22082 end &490
     22023xt "72750,62000,78000,62000"
     22024pts [
     22025"78000,62000"
     22026"72750,62000"
     22027]
     22028)
     22029end &489
    2208322030sat 16
    2208422031eat 32
     
    2209422041va (VaSet
    2209522042)
    22096 xt "65000,61000,68100,62000"
     22043xt "74000,61000,77100,62000"
    2209722044st "CLK_25"
    22098 blo "65000,61800"
     22045blo "74000,61800"
    2209922046tm "WireNameMgr"
    2210022047)
     
    2210222049on &188
    2210322050)
    22104 *742 (Wire
     22051*737 (Wire
    2210522052uid 13159,0
    2210622053shape (OrthoPolyLine
     
    2210922056vasetType 3
    2211022057)
    22111 xt "63750,63000,87250,67000"
     22058xt "72750,63000,87250,67000"
    2211222059pts [
    2211322060"87250,67000"
    22114 "79000,67000"
    22115 "79000,63000"
    22116 "63750,63000"
     22061"77000,67000"
     22062"77000,63000"
     22063"72750,63000"
    2211722064]
    2211822065)
    2211922066start &114
    22120 end &491
     22067end &490
    2212122068sat 32
    2212222069eat 32
     
    2213822085)
    2213922086)
    22140 on &497
    22141 )
    22142 *743 (Wire
     22087on &496
     22088)
     22089*738 (Wire
    2214322090uid 13165,0
    2214422091shape (OrthoPolyLine
     
    2214822095lineWidth 2
    2214922096)
    22150 xt "63750,64000,87250,68000"
     22097xt "72750,64000,87250,68000"
    2215122098pts [
    2215222099"87250,68000"
    22153 "78000,68000"
    22154 "78000,64000"
    22155 "63750,64000"
     22100"76000,68000"
     22101"76000,64000"
     22102"72750,64000"
    2215622103]
    2215722104)
    2215822105start &115
    22159 end &492
     22106end &491
    2216022107sat 32
    2216122108eat 32
     
    2217822125)
    2217922126)
    22180 on &498
    22181 )
    22182 *744 (Wire
     22127on &497
     22128)
     22129*739 (Wire
    2218322130uid 13210,0
    2218422131shape (OrthoPolyLine
     
    2218722134vasetType 3
    2218822135)
    22189 xt "42000,62000,50250,62000"
    22190 pts [
    22191 "50250,62000"
    22192 "42000,62000"
    22193 ]
    22194 )
    22195 start &493
    22196 end &502
     22136xt "54000,62000,59250,62000"
     22137pts [
     22138"59250,62000"
     22139"54000,62000"
     22140]
     22141)
     22142start &492
     22143end &501
    2219722144sat 32
    2219822145eat 32
     
    2220822155va (VaSet
    2220922156)
    22210 xt "46250,61000,49450,62000"
     22157xt "53250,61000,56450,62000"
    2221122158st "trigger1"
    22212 blo "46250,61800"
     22159blo "53250,61800"
    2221322160tm "WireNameMgr"
    2221422161)
    2221522162)
    22216 on &500
    22217 )
    22218 *745 (Wire
     22163on &499
     22164)
     22165*740 (Wire
    2221922166uid 13216,0
    2222022167shape (OrthoPolyLine
     
    2222322170vasetType 3
    2222422171)
    22225 xt "42000,60000,45000,60000"
    22226 pts [
    22227 "45000,60000"
    22228 "42000,60000"
    22229 ]
    22230 )
    22231 end &507
     22172xt "54000,60000,59000,60000"
     22173pts [
     22174"59000,60000"
     22175"54000,60000"
     22176]
     22177)
     22178end &506
    2223222179sat 16
    2223322180eat 32
     
    2224322190uid 13221,0
    2224422191va (VaSet
    22245 isHidden 1
    22246 )
    22247 xt "43000,59000,47800,60000"
     22192)
     22193xt "54000,59000,58800,60000"
    2224822194st "s_trigger_0"
    22249 blo "43000,59800"
     22195blo "54000,59800"
    2225022196tm "WireNameMgr"
    2225122197)
    2225222198)
    22253 on &499
    22254 )
    22255 *746 (Wire
     22199on &498
     22200)
     22201*741 (Wire
    2225622202uid 13224,0
    2225722203shape (OrthoPolyLine
     
    2226022206vasetType 3
    2226122207)
    22262 xt "33000,61000,36000,61000"
    22263 pts [
    22264 "36000,61000"
    22265 "33000,61000"
    22266 ]
    22267 )
    22268 start &504
     22208xt "45000,61000,48000,61000"
     22209pts [
     22210"48000,61000"
     22211"45000,61000"
     22212]
     22213)
     22214start &503
    2226922215sat 32
    2227022216eat 16
     
    2228022226uid 13229,0
    2228122227va (VaSet
    22282 isHidden 1
    22283 )
    22284 xt "34000,60000,37600,61000"
     22228)
     22229xt "45000,60000,48600,61000"
    2228522230st "s_trigger"
    22286 blo "34000,60800"
     22231blo "45000,60800"
    2228722232tm "WireNameMgr"
    2228822233)
     
    2229022235on &401
    2229122236)
    22292 *747 (Wire
     22237*742 (Wire
    2229322238uid 13695,0
    2229422239shape (OrthoPolyLine
     
    2230422249]
    2230522250)
    22306 start &524
     22251start &523
    2230722252end &116
    2230822253sat 32
     
    2232722272)
    2232822273)
    22329 on &525
    22330 )
    22331 *748 (Wire
     22274on &524
     22275)
     22276*743 (Wire
    2233222277uid 13921,0
    2233322278shape (OrthoPolyLine
     
    2236622311on &71
    2236722312)
    22368 *749 (Wire
     22313*744 (Wire
    2236922314uid 13929,0
    2237022315shape (OrthoPolyLine
     
    2240322348on &122
    2240422349)
    22405 *750 (Wire
     22350*745 (Wire
    2240622351uid 14048,0
    2240722352shape (OrthoPolyLine
     
    2241622361]
    2241722362)
    22418 start &526
    22419 end &532
     22363start &525
     22364end &531
    2242022365sat 32
    2242122366eat 32
     
    2243822383)
    2243922384)
    22440 on &527
    22441 )
    22442 *751 (Wire
     22385on &526
     22386)
     22387*746 (Wire
    2244322388uid 14171,0
    2244422389shape (OrthoPolyLine
     
    2245422399]
    2245522400)
    22456 start &528
     22401start &527
    2245722402sat 32
    2245822403eat 16
     
    2247622421)
    2247722422)
    22478 on &529
    22479 )
    22480 *752 (Wire
     22423on &528
     22424)
     22425*747 (Wire
    2248122426uid 14427,0
    2248222427shape (OrthoPolyLine
     
    2249122436]
    2249222437)
    22493 end &531
     22438end &530
    2249422439sat 16
    2249522440eat 32
     
    2251322458on &187
    2251422459)
    22515 *753 (Wire
     22460*748 (Wire
    2251622461uid 14479,0
    2251722462shape (OrthoPolyLine
     
    2252622471]
    2252722472)
    22528 start &534
    22529 end &540
     22473start &533
     22474end &539
    2253022475sat 32
    2253122476eat 32
     
    2254922494)
    2255022495)
    22551 on &539
    22552 )
    22553 *754 (Wire
     22496on &538
     22497)
     22498*749 (Wire
    2255422499uid 14493,0
    2255522500shape (OrthoPolyLine
     
    2256422509]
    2256522510)
    22566 start &535
    22567 end &542
     22511start &534
     22512end &541
    2256822513sat 32
    2256922514eat 32
     
    2258722532)
    2258822533)
    22589 on &541
    22590 )
    22591 *755 (Wire
     22534on &540
     22535)
     22536*750 (Wire
    2259222537uid 14622,0
    2259322538shape (OrthoPolyLine
     
    2260322548]
    2260422549)
    22605 start &533
    22606 end &544
     22550start &532
     22551end &543
    2260722552sat 32
    2260822553eat 32
     
    2262722572)
    2262822573)
    22629 on &543
    22630 )
    22631 *756 (Wire
     22574on &542
     22575)
     22576*751 (Wire
    2263222577uid 15071,0
    2263322578shape (OrthoPolyLine
     
    2264322588)
    2264422589start &101
    22645 end &549
     22590end &548
    2264622591sat 32
    2264722592eat 32
     
    2266322608)
    2266422609)
    22665 on &596
    22666 )
    22667 *757 (Wire
     22610on &595
     22611)
     22612*752 (Wire
    2266822613uid 15081,0
    2266922614shape (OrthoPolyLine
     
    2267822623]
    2267922624)
    22680 start &551
    22681 end &589
     22625start &550
     22626end &588
    2268222627sat 32
    2268322628eat 32
     
    2270122646)
    2270222647)
    22703 on &597
    22704 )
    22705 *758 (Wire
     22648on &596
     22649)
     22650*753 (Wire
    2270622651uid 15122,0
    2270722652shape (OrthoPolyLine
     
    2271722662]
    2271822663)
    22719 start &587
    22720 end &564
     22664start &586
     22665end &563
    2272122666sat 32
    2272222667eat 32
     
    2273922684)
    2274022685)
    22741 on &598
    22742 )
    22743 *759 (Wire
     22686on &597
     22687)
     22688*754 (Wire
    2274422689uid 15130,0
    2274522690shape (OrthoPolyLine
     
    2275422699]
    2275522700)
    22756 end &579
     22701end &578
    2275722702es 0
    2275822703sat 16
     
    2277722722)
    2277822723)
    22779 on &541
    22780 )
    22781 *760 (Wire
     22724on &540
     22725)
     22726*755 (Wire
    2278222727uid 15138,0
    2278322728shape (OrthoPolyLine
     
    2279222737]
    2279322738)
    22794 end &581
     22739end &580
    2279522740es 0
    2279622741sat 16
     
    2281522760)
    2281622761)
    22817 on &539
     22762on &538
     22763)
     22764*756 (Wire
     22765uid 15379,0
     22766shape (OrthoPolyLine
     22767uid 15380,0
     22768va (VaSet
     22769vasetType 3
     22770)
     22771xt "29000,64000,29000,67250"
     22772pts [
     22773"29000,64000"
     22774"29000,67250"
     22775]
     22776)
     22777end &134
     22778sat 16
     22779eat 32
     22780st 0
     22781sf 1
     22782si 0
     22783tg (WTG
     22784uid 15383,0
     22785ps "ConnStartEndStrategy"
     22786stg "STSignalDisplayStrategy"
     22787f (Text
     22788uid 15384,0
     22789va (VaSet
     22790)
     22791xt "29000,64000,32100,65000"
     22792st "CLK_25"
     22793blo "29000,64800"
     22794tm "WireNameMgr"
     22795)
     22796)
     22797on &188
     22798)
     22799*757 (Wire
     22800uid 15494,0
     22801optionalChildren [
     22802*758 (BdJunction
     22803uid 15502,0
     22804ps "OnConnectorStrategy"
     22805shape (Circle
     22806uid 15503,0
     22807va (VaSet
     22808vasetType 1
     22809)
     22810xt "-54400,71600,-53600,72400"
     22811radius 400
     22812)
     22813)
     22814]
     22815shape (OrthoPolyLine
     22816uid 15495,0
     22817va (VaSet
     22818vasetType 3
     22819)
     22820xt "-55250,72000,-21750,72000"
     22821pts [
     22822"-55250,72000"
     22823"-21750,72000"
     22824]
     22825)
     22826start &475
     22827end &30
     22828sat 32
     22829eat 32
     22830st 0
     22831sf 1
     22832si 0
     22833tg (WTG
     22834uid 15496,0
     22835ps "ConnStartEndStrategy"
     22836stg "STSignalDisplayStrategy"
     22837f (Text
     22838uid 15497,0
     22839va (VaSet
     22840)
     22841xt "-53250,71000,-48650,72000"
     22842st "trigger_out"
     22843blo "-53250,71800"
     22844tm "WireNameMgr"
     22845)
     22846)
     22847on &598
     22848)
     22849*759 (Wire
     22850uid 15498,0
     22851shape (OrthoPolyLine
     22852uid 15499,0
     22853va (VaSet
     22854vasetType 3
     22855)
     22856xt "-54000,69000,-52750,72000"
     22857pts [
     22858"-52750,69000"
     22859"-54000,69000"
     22860"-54000,72000"
     22861]
     22862)
     22863start &125
     22864end &758
     22865sat 32
     22866eat 32
     22867stc 0
     22868st 0
     22869sf 1
     22870si 0
     22871tg (WTG
     22872uid 15500,0
     22873ps "ConnStartEndStrategy"
     22874stg "STSignalDisplayStrategy"
     22875f (Text
     22876uid 15501,0
     22877va (VaSet
     22878)
     22879xt "-58000,69000,-53400,70000"
     22880st "trigger_out"
     22881blo "-58000,69800"
     22882tm "WireNameMgr"
     22883)
     22884)
     22885on &598
    2281822886)
    2281922887]
     
    2282922897color "26368,26368,26368"
    2283022898)
    22831 packageList *761 (PackageList
     22899packageList *760 (PackageList
    2283222900uid 41,0
    2283322901stg "VerticalLayoutStrategy"
    2283422902textVec [
    22835 *762 (Text
     22903*761 (Text
    2283622904uid 42,0
    2283722905va (VaSet
     
    2284222910blo "-163000,-15200"
    2284322911)
    22844 *763 (MLText
     22912*762 (MLText
    2284522913uid 43,0
    2284622914va (VaSet
     
    2286722935stg "VerticalLayoutStrategy"
    2286822936textVec [
    22869 *764 (Text
     22937*763 (Text
    2287022938uid 45,0
    2287122939va (VaSet
     
    2287722945blo "20000,800"
    2287822946)
    22879 *765 (Text
     22947*764 (Text
    2288022948uid 46,0
    2288122949va (VaSet
     
    2288722955blo "20000,1800"
    2288822956)
    22889 *766 (MLText
     22957*765 (MLText
    2289022958uid 47,0
    2289122959va (VaSet
     
    2289722965tm "BdCompilerDirectivesTextMgr"
    2289822966)
    22899 *767 (Text
     22967*766 (Text
    2290022968uid 48,0
    2290122969va (VaSet
     
    2290722975blo "20000,4800"
    2290822976)
    22909 *768 (MLText
     22977*767 (MLText
    2291022978uid 49,0
    2291122979va (VaSet
     
    2291522983tm "BdCompilerDirectivesTextMgr"
    2291622984)
    22917 *769 (Text
     22985*768 (Text
    2291822986uid 50,0
    2291922987va (VaSet
     
    2292522993blo "20000,5800"
    2292622994)
    22927 *770 (MLText
     22995*769 (MLText
    2292822996uid 51,0
    2292922997va (VaSet
     
    2293723005)
    2293823006windowSize "0,0,1281,1024"
    22939 viewArea "-25598,42048,41245,97173"
     23007viewArea "-65700,47500,1143,102625"
    2294023008cachedDiagramExtent "-174000,-25425,428157,346294"
    2294123009pageSetupInfo (PageSetupInfo
     
    2296323031hasePageBreakOrigin 1
    2296423032pageBreakOrigin "-73000,0"
    22965 lastUid 15275,0
     23033lastUid 15505,0
    2296623034defaultCommentText (CommentText
    2296723035shape (Rectangle
     
    2302523093stg "VerticalLayoutStrategy"
    2302623094textVec [
    23027 *771 (Text
     23095*770 (Text
    2302823096va (VaSet
    2302923097font "Arial,8,1"
     
    2303423102tm "BdLibraryNameMgr"
    2303523103)
    23036 *772 (Text
     23104*771 (Text
    2303723105va (VaSet
    2303823106font "Arial,8,1"
     
    2304323111tm "BlkNameMgr"
    2304423112)
    23045 *773 (Text
     23113*772 (Text
    2304623114va (VaSet
    2304723115font "Arial,8,1"