Ignore:
Timestamp:
02/08/11 11:54:22 (14 years ago)
Author:
neise
Message:
 
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10121 r10138  
    172172          when CONFIG7 =>
    173173            if (drs_srin_write_ready = '1') then
     174              drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers
    174175              roi_max_int <= roi_max;
    175176              state_generate <= WRITE_DATA_IDLE;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/drs_pulser_dummy.vhd

    r10081 r10138  
    8585        when SRIN_WRITE_END =>
    8686          SRCLK_EN <= '0';
    87           srin_out <= '1';
     87          srin_out <= '0';
    8888          srin_write_ready <= '1';
    8989          srin_write_ack <= '0';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10129 r10138  
    163163
    164164-- DRS Registers
     165  constant DRS_ADDR_IDLE : std_logic_vector := "1001";
    165166  constant DRS_CONFIG_REG : std_logic_vector := "1100"; 
    166167  constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101"; 
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10137 r10138  
    144144signal local_fifo_channels : std_logic_vector (3 downto 0);
    145145
    146 signal data_valid_int : std_logic := '0';
     146
    147147
    148148
     
    162162        -- signals for synching in asynchronous input signals
    163163        ------------------------------------------------------------------------------
    164         signal w5300_interrupt_sr : std_logic_vector(1 downto 0);
     164        signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
     165         --?? not sure if this init value is good
     166         -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles.
     167         -- I hope!
     168        signal data_valid_sr : std_logic_vector(1 downto 0) := "00";
    165169        ------------------------------------------------------------------------------
    166170
     
    187191                -- synch asynchronous input in:
    188192                w5300_interrupt_sr <= w5300_interrupt_sr(1) & int;
     193                data_valid_sr <= data_valid_sr(1) & data_valid;
    189194               
    190195                        -- interrupt is handled synchronously
    191196                        -- W5300 pulls low its interrpt line in case of:
    192                         --      ??? I don't know ... connection loss ???
     197                        --      When Sockets time out and
     198                        -- When sockets receive disconnection request.
    193199                       
    194200                        if (w5300_interrupt_sr = "01") and (interrupt_ignore = '0') then
     
    560566                                            state_init <= MAIN;
    561567                                          end if;
    562                                        
    563           -- main "loop"
     568                                        -----------------------------------------
     569          -- MAIN "loop" --------------------------
     570          -----------------------------------------
     571         
    564572                                        when MAIN =>
    565573                                          socks_waiting <= '0';
     
    573581            data_valid_ack <= '0';
    574582            state_init <= MAIN1;
    575             data_valid_int <= data_valid;
     583            --data_valid_int <= data_valid;
    576584                                        when MAIN1 =>
    577585            if (chk_recv_cntr = 1000) then
     
    586594          when MAIN2 =>
    587595            busy <= '0';
    588                                           if (data_valid = '1') then
    589                                             data_valid_int <= '0';
     596                                          --if (data_valid = '1') then
     597                                          if (data_valid_sr = "01" or data_valid_sr = "11") then
     598                                            --data_valid_int <= '0';
    590599                                            busy <= '1';
    591600              local_write_length <= write_length;
     
    607616            next_state <= MAIN;
    608617            state_init <= WRITE_DATA;
     618
     619            -----------------------------------------
     620            -- END OF MAIN         ------------------
     621            -----------------------------------------
     622
    609623                                         
    610624
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

    r10129 r10138  
    333333(vvPair
    334334variable "date"
    335 value "04.02.2011"
     335value "08.02.2011"
    336336)
    337337(vvPair
    338338variable "day"
    339 value "Fr"
     339value "Di"
    340340)
    341341(vvPair
    342342variable "day_long"
    343 value "Freitag"
     343value "Dienstag"
    344344)
    345345(vvPair
    346346variable "dd"
    347 value "04"
     347value "08"
    348348)
    349349(vvPair
     
    485485(vvPair
    486486variable "time"
    487 value "12:56:44"
     487value "11:06:22"
    488488)
    489489(vvPair
     
    577577)
    578578xt "-172000,106800,-128500,107600"
    579 st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
     579st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
     580"
    580581)
    581582)
     
    595596)
    596597xt "-172000,42800,-132000,43600"
    597 st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     598st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     599"
    598600)
    599601)
     
    613615)
    614616xt "-172000,62000,-139500,62800"
    615 st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
     617st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
     618"
    616619)
    617620)
     
    631634)
    632635xt "-172000,80400,-132000,81200"
    633 st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
     636st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
     637"
    634638)
    635639)
     
    649653)
    650654xt "-172000,81200,-139500,82000"
    651 st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
     655st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
     656"
    652657)
    653658)
     
    667672)
    668673xt "-172000,34400,-132000,35200"
    669 st "wiz_reset              : std_logic                                    := '1'"
     674st "wiz_reset              : std_logic                                    := '1'
     675"
    670676)
    671677)
     
    685691)
    686692xt "-172000,32000,-143500,32800"
    687 st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
     693st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
     694"
    688695)
    689696)
     
    703710)
    704711xt "-172000,36800,-143000,37600"
    705 st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
     712st "wiz_data               : std_logic_vector(15 DOWNTO 0)
     713"
    706714)
    707715)
     
    721729)
    722730xt "-172000,32800,-132000,33600"
    723 st "wiz_cs                 : std_logic                                    := '1'"
     731st "wiz_cs                 : std_logic                                    := '1'
     732"
    724733)
    725734)
     
    739748)
    740749xt "-172000,35200,-132000,36000"
    741 st "wiz_wr                 : std_logic                                    := '1'"
     750st "wiz_wr                 : std_logic                                    := '1'
     751"
    742752)
    743753)
     
    757767)
    758768xt "-172000,33600,-132000,34400"
    759 st "wiz_rd                 : std_logic                                    := '1'"
     769st "wiz_rd                 : std_logic                                    := '1'
     770"
    760771)
    761772)
     
    774785)
    775786xt "-172000,13600,-153500,14400"
    776 st "wiz_int                : std_logic"
     787st "wiz_int                : std_logic
     788"
    777789)
    778790)
     
    12911303fg "0,65535,0"
    12921304)
    1293 xt "0,65625,750,66375"
     1305xt "0,70625,750,71375"
    12941306)
    12951307tg (CPTG
     
    13011313va (VaSet
    13021314)
    1303 xt "-17300,65500,-1000,66500"
     1315xt "-17300,70500,-1000,71500"
    13041316st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    13051317ju 2
    1306 blo "-1000,66300"
     1318blo "-1000,71300"
    13071319)
    13081320)
     
    13661378fg "0,65535,0"
    13671379)
    1368 xt "-21750,70625,-21000,71375"
     1380xt "-21750,69625,-21000,70375"
    13691381)
    13701382tg (CPTG
     
    13761388va (VaSet
    13771389)
    1378 xt "-20000,70500,-13200,71500"
     1390xt "-20000,69500,-13200,70500"
    13791391st "trigger_id : (47:0)"
    1380 blo "-20000,71300"
     1392blo "-20000,70300"
    13811393)
    13821394)
     
    14741486fg "0,65535,0"
    14751487)
    1476 xt "0,66625,750,67375"
     1488xt "0,71625,750,72375"
    14771489)
    14781490tg (CPTG
     
    14841496va (VaSet
    14851497)
    1486 xt "-6300,66500,-1000,67500"
     1498xt "-6300,71500,-1000,72500"
    14871499st "ram_write_ea"
    14881500ju 2
    1489 blo "-1000,67300"
     1501blo "-1000,72300"
    14901502)
    14911503)
     
    15091521fg "0,65535,0"
    15101522)
    1511 xt "0,67625,750,68375"
     1523xt "0,72625,750,73375"
    15121524)
    15131525tg (CPTG
     
    15191531va (VaSet
    15201532)
    1521 xt "-7300,67500,-1000,68500"
     1533xt "-7300,72500,-1000,73500"
    15221534st "ram_write_ready"
    15231535ju 2
    1524 blo "-1000,68300"
     1536blo "-1000,73300"
    15251537)
    15261538)
     
    15471559fg "0,65535,0"
    15481560)
    1549 xt "0,76625,750,77375"
     1561xt "0,78625,750,79375"
    15501562)
    15511563tg (CPTG
     
    15571569va (VaSet
    15581570)
    1559 xt "-4000,76500,-1000,77500"
     1571xt "-4000,78500,-1000,79500"
    15601572st "roi_max"
    15611573ju 2
    1562 blo "-1000,77300"
     1574blo "-1000,79300"
    15631575)
    15641576)
     
    16171629fg "0,65535,0"
    16181630)
    1619 xt "0,77625,750,78375"
     1631xt "0,79625,750,80375"
    16201632)
    16211633tg (CPTG
     
    16271639va (VaSet
    16281640)
    1629 xt "-10100,77500,-1000,78500"
     1641xt "-10100,79500,-1000,80500"
    16301642st "package_length : (15:0)"
    16311643ju 2
    1632 blo "-1000,78300"
     1644blo "-1000,80300"
    16331645)
    16341646)
     
    20162028fg "0,65535,0"
    20172029)
    2018 xt "0,74625,750,75375"
     2030xt "0,77625,750,78375"
    20192031)
    20202032tg (CPTG
     
    20262038va (VaSet
    20272039)
    2028 xt "-7700,74500,-1000,75500"
     2040xt "-7700,77500,-1000,78500"
    20292041st "config_ready_mm"
    20302042ju 2
    2031 blo "-1000,75300"
     2043blo "-1000,78300"
    20322044)
    20332045)
     
    21562168fg "0,65535,0"
    21572169)
    2158 xt "0,72625,750,73375"
     2170xt "0,75625,750,76375"
    21592171)
    21602172tg (CPTG
     
    21662178va (VaSet
    21672179)
    2168 xt "-7400,72500,-1000,73500"
     2180xt "-7400,75500,-1000,76500"
    21692181st "config_start_mm"
    21702182ju 2
    2171 blo "-1000,73300"
     2183blo "-1000,76300"
    21722184)
    21732185)
     
    23442356fg "0,65535,0"
    23452357)
    2346 xt "0,73625,750,74375"
     2358xt "0,76625,750,77375"
    23472359)
    23482360tg (CPTG
     
    23542366va (VaSet
    23552367)
    2356 xt "-8200,73500,-1000,74500"
     2368xt "-8200,76500,-1000,77500"
    23572369st "config_started_mm"
    23582370ju 2
    2359 blo "-1000,74300"
     2371blo "-1000,77300"
    23602372)
    23612373)
     
    26262638fg "0,65535,0"
    26272639)
    2628 xt "0,68625,750,69375"
     2640xt "0,73625,750,74375"
    26292641)
    26302642tg (CPTG
     
    26362648va (VaSet
    26372649)
    2638 xt "-8800,68500,-1000,69500"
     2650xt "-8800,73500,-1000,74500"
    26392651st "ram_write_ready_ack"
    26402652ju 2
    2641 blo "-1000,69300"
     2653blo "-1000,74300"
    26422654)
    26432655)
     
    28702882)
    28712883xt "-172000,9600,-143500,10400"
    2872 st "board_id               : std_logic_vector(3 DOWNTO 0)"
     2884st "board_id               : std_logic_vector(3 DOWNTO 0)
     2885"
    28732886)
    28742887)
     
    28892902)
    28902903xt "-172000,12800,-153500,13600"
    2891 st "trigger                : std_logic"
     2904st "trigger                : std_logic
     2905"
    28922906)
    28932907)
     
    32573271fg "0,65535,0"
    32583272)
    3259 xt "87250,71625,88000,72375"
     3273xt "87250,72625,88000,73375"
    32603274)
    32613275tg (CPTG
     
    32673281va (VaSet
    32683282)
    3269 xt "89000,71500,96900,72500"
     3283xt "89000,72500,96900,73500"
    32703284st "write_length : (16:0)"
    3271 blo "89000,72300"
     3285blo "89000,73300"
    32723286)
    32733287)
     
    32943308fg "0,65535,0"
    32953309)
    3296 xt "87250,72625,88000,73375"
     3310xt "87250,73625,88000,74375"
    32973311)
    32983312tg (CPTG
     
    33043318va (VaSet
    33053319)
    3306 xt "89000,72500,105300,73500"
     3320xt "89000,73500,105300,74500"
    33073321st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    3308 blo "89000,73300"
     3322blo "89000,74300"
    33093323)
    33103324)
     
    34063420fg "0,65535,0"
    34073421)
    3408 xt "87250,70625,88000,71375"
     3422xt "87250,71625,88000,72375"
    34093423)
    34103424tg (CPTG
     
    34163430va (VaSet
    34173431)
    3418 xt "89000,70500,93100,71500"
     3432xt "89000,71500,93100,72500"
    34193433st "data_valid"
    3420 blo "89000,71300"
     3434blo "89000,72300"
    34213435)
    34223436)
     
    34423456fg "0,65535,0"
    34433457)
    3444 xt "87250,69625,88000,70375"
     3458xt "87250,70625,88000,71375"
    34453459)
    34463460tg (CPTG
     
    34523466va (VaSet
    34533467)
    3454 xt "89000,69500,90900,70500"
     3468xt "89000,70500,90900,71500"
    34553469st "busy"
    3456 blo "89000,70300"
     3470blo "89000,71300"
    34573471)
    34583472)
     
    34803494fg "0,65535,0"
    34813495)
    3482 xt "87250,73625,88000,74375"
     3496xt "87250,74625,88000,75375"
    34833497)
    34843498tg (CPTG
     
    34903504va (VaSet
    34913505)
    3492 xt "89000,73500,96800,74500"
     3506xt "89000,74500,96800,75500"
    34933507st "fifo_channels : (3:0)"
    3494 blo "89000,74300"
     3508blo "89000,75300"
    34953509)
    34963510)
     
    35163530fg "0,65535,0"
    35173531)
    3518 xt "87250,74625,88000,75375"
     3532xt "87250,75625,88000,76375"
    35193533)
    35203534tg (CPTG
     
    35263540va (VaSet
    35273541)
    3528 xt "89000,74500,94700,75500"
     3542xt "89000,75500,94700,76500"
    35293543st "write_end_flag"
    3530 blo "89000,75300"
     3544blo "89000,76300"
    35313545)
    35323546)
     
    35503564fg "0,65535,0"
    35513565)
    3552 xt "87250,75625,88000,76375"
     3566xt "87250,76625,88000,77375"
    35533567)
    35543568tg (CPTG
     
    35603574va (VaSet
    35613575)
    3562 xt "89000,75500,95800,76500"
     3576xt "89000,76500,95800,77500"
    35633577st "write_header_flag"
    3564 blo "89000,76300"
     3578blo "89000,77300"
    35653579)
    35663580)
     
    39944008fg "0,65535,0"
    39954009)
    3996 xt "87250,76625,88000,77375"
     4010xt "87250,77625,88000,78375"
    39974011)
    39984012tg (CPTG
     
    40044018va (VaSet
    40054019)
    4006 xt "89000,76500,94600,77500"
     4020xt "89000,77500,94600,78500"
    40074021st "data_valid_ack"
    4008 blo "89000,77300"
     4022blo "89000,78300"
    40094023)
    40104024)
     
    46874701)
    46884702xt "-172000,10400,-143500,11200"
    4689 st "crate_id               : std_logic_vector(1 DOWNTO 0)"
     4703st "crate_id               : std_logic_vector(1 DOWNTO 0)
     4704"
    46904705)
    46914706)
     
    47034718fg "0,65535,0"
    47044719)
    4705 xt "-41000,67625,-40250,68375"
     4720xt "-41000,68625,-40250,69375"
    47064721)
    47074722tg (CPTG
     
    47134728va (VaSet
    47144729)
    4715 xt "-48800,67500,-42000,68500"
     4730xt "-48800,68500,-42000,69500"
    47164731st "trigger_id : (47:0)"
    47174732ju 2
    4718 blo "-42000,68300"
     4733blo "-42000,69300"
    47194734)
    47204735)
     
    47434758fg "0,65535,0"
    47444759)
    4745 xt "-52750,67625,-52000,68375"
     4760xt "-52750,68625,-52000,69375"
    47464761)
    47474762tg (CPTG
     
    47534768va (VaSet
    47544769)
    4755 xt "-51000,67500,-48200,68500"
     4770xt "-51000,68500,-48200,69500"
    47564771st "trigger"
    4757 blo "-51000,68300"
     4772blo "-51000,69300"
    47584773)
    47594774)
     
    47804795fg "0,65535,0"
    47814796)
    4782 xt "-52750,66625,-52000,67375"
     4797xt "-52750,67625,-52000,68375"
    47834798)
    47844799tg (CPTG
     
    47904805va (VaSet
    47914806)
    4792 xt "-51000,66500,-49700,67500"
     4807xt "-51000,67500,-49700,68500"
    47934808st "clk"
    4794 blo "-51000,67300"
     4809blo "-51000,68300"
    47954810)
    47964811)
     
    48144829lineWidth 2
    48154830)
    4816 xt "-52000,66000,-41000,70000"
     4831xt "-52000,67000,-41000,71000"
    48174832)
    48184833oxt "32000,2000,43000,12000"
     
    48284843font "Arial,8,1"
    48294844)
    4830 xt "-50300,70000,-43700,71000"
     4845xt "-50300,71000,-43700,72000"
    48314846st "FACT_FAD_LIB"
    4832 blo "-50300,70800"
     4847blo "-50300,71800"
    48334848tm "BdLibraryNameMgr"
    48344849)
     
    48394854font "Arial,8,1"
    48404855)
    4841 xt "-50300,71000,-43700,72000"
     4856xt "-50300,72000,-43700,73000"
    48424857st "trigger_counter"
    4843 blo "-50300,71800"
     4858blo "-50300,72800"
    48444859tm "CptNameMgr"
    48454860)
     
    48504865font "Arial,8,1"
    48514866)
    4852 xt "-50300,71000,-42700,72000"
     4867xt "-50300,72000,-42700,73000"
    48534868st "I_main_ext_trigger"
    4854 blo "-50300,71800"
     4869blo "-50300,72800"
    48554870tm "InstanceNameMgr"
    48564871)
     
    48674882font "Courier New,8,0"
    48684883)
    4869 xt "-52000,65000,-52000,65000"
     4884xt "-52000,66000,-52000,66000"
    48704885)
    48714886header ""
     
    48814896fg "49152,49152,49152"
    48824897)
    4883 xt "-51750,68250,-50250,69750"
     4898xt "-51750,69250,-50250,70750"
    48844899iconName "VhdlFileViewIcon.png"
    48854900iconMaskName "VhdlFileViewIcon.msk"
     
    49114926)
    49124927xt "-172000,98800,-139500,99600"
    4913 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
     4928st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
     4929"
    49144930)
    49154931)
     
    49314947)
    49324948xt "-172000,82000,-132000,82800"
    4933 st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     4949st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     4950"
    49344951)
    49354952)
     
    49474964fg "0,65535,0"
    49484965)
    4949 xt "31250,72625,32000,73375"
     4966xt "27250,70625,28000,71375"
    49504967)
    49514968tg (CPTG
     
    49584975font "arial,8,0"
    49594976)
    4960 xt "33000,72500,51400,73500"
     4977xt "29000,70500,47400,71500"
    49614978st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
    4962 blo "33000,73300"
     4979blo "29000,71300"
    49634980)
    49644981)
     
    49835000shape (Triangle
    49845001uid 2352,0
    4985 ro 90
     5002ro 180
    49865003va (VaSet
    49875004vasetType 1
    49885005fg "0,65535,0"
    49895006)
    4990 xt "31250,70625,32000,71375"
     5007xt "28625,67250,29375,68000"
    49915008)
    49925009tg (CPTG
    49935010uid 2353,0
    49945011ps "CptPortTextPlaceStrategy"
    4995 stg "VerticalLayoutStrategy"
     5012stg "RightVerticalLayoutStrategy"
    49965013f (Text
    49975014uid 2354,0
     5015ro 270
    49985016va (VaSet
    49995017font "arial,8,0"
    50005018)
    5001 xt "33000,70500,34300,71500"
     5019xt "28500,69000,29500,70300"
    50025020st "clk"
    5003 blo "33000,71300"
     5021ju 2
     5022blo "29300,69000"
    50045023)
    50055024)
     
    50245043fg "0,65535,0"
    50255044)
    5026 xt "31250,79625,32000,80375"
     5045xt "27250,77625,28000,78375"
    50275046)
    50285047tg (CPTG
     
    50355054font "arial,8,0"
    50365055)
    5037 xt "33000,79500,38100,80500"
     5056xt "29000,77500,34100,78500"
    50385057st "config_ready"
    5039 blo "33000,80300"
     5058blo "29000,78300"
    50405059)
    50415060)
     
    50625081fg "0,65535,0"
    50635082)
    5064 xt "31250,77625,32000,78375"
     5083xt "27250,75625,28000,76375"
    50655084)
    50665085tg (CPTG
     
    50735092font "arial,8,0"
    50745093)
    5075 xt "33000,77500,37800,78500"
     5094xt "29000,75500,33800,76500"
    50765095st "config_start"
    5077 blo "33000,78300"
     5096blo "29000,76300"
    50785097)
    50795098)
     
    50985117fg "0,65535,0"
    50995118)
    5100 xt "31250,73625,32000,74375"
     5119xt "27250,71625,28000,72375"
    51015120)
    51025121tg (CPTG
     
    51095128font "arial,8,0"
    51105129)
    5111 xt "33000,73500,38300,74500"
     5130xt "29000,71500,34300,72500"
    51125131st "ram_write_ea"
    5113 blo "33000,74300"
     5132blo "29000,72300"
    51145133)
    51155134)
     
    51365155fg "0,65535,0"
    51375156)
    5138 xt "31250,74625,32000,75375"
     5157xt "27250,72625,28000,73375"
    51395158)
    51405159tg (CPTG
     
    51475166font "arial,8,0"
    51485167)
    5149 xt "33000,74500,39300,75500"
     5168xt "29000,72500,35300,73500"
    51505169st "ram_write_ready"
    5151 blo "33000,75300"
     5170blo "29000,73300"
    51525171)
    51535172)
     
    51735192fg "0,65535,0"
    51745193)
    5175 xt "31250,80625,32000,81375"
     5194xt "27250,78625,28000,79375"
    51765195)
    51775196tg (CPTG
     
    51845203font "arial,8,0"
    51855204)
    5186 xt "33000,80500,36000,81500"
     5205xt "29000,78500,32000,79500"
    51875206st "roi_max"
    5188 blo "33000,81300"
     5207blo "29000,79300"
    51895208)
    51905209)
     
    52125231fg "0,65535,0"
    52135232)
    5214 xt "63000,70625,63750,71375"
     5233xt "59000,70625,59750,71375"
    52155234)
    52165235tg (CPTG
     
    52235242font "arial,8,0"
    52245243)
    5225 xt "58600,70500,62000,71500"
     5244xt "54600,70500,58000,71500"
    52265245st "wiz_busy"
    52275246ju 2
    5228 blo "62000,71300"
     5247blo "58000,71300"
    52295248)
    52305249)
     
    52495268fg "0,65535,0"
    52505269)
    5251 xt "63000,74625,63750,75375"
     5270xt "59000,74625,59750,75375"
    52525271)
    52535272tg (CPTG
     
    52605279font "arial,8,0"
    52615280)
    5262 xt "50200,74500,62000,75500"
     5281xt "46200,74500,58000,75500"
    52635282st "wiz_number_of_channels : (3:0)"
    52645283ju 2
    5265 blo "62000,75300"
     5284blo "58000,75300"
    52665285)
    52675286)
     
    52895308fg "0,65535,0"
    52905309)
    5291 xt "63000,73625,63750,74375"
     5310xt "59000,73625,59750,74375"
    52925311)
    52935312tg (CPTG
     
    53005319font "arial,8,0"
    53015320)
    5302 xt "42100,73500,62000,74500"
     5321xt "38100,73500,58000,74500"
    53035322st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
    53045323ju 2
    5305 blo "62000,74300"
     5324blo "58000,74300"
    53065325)
    53075326)
     
    53305349fg "0,65535,0"
    53315350)
    5332 xt "63000,71625,63750,72375"
     5351xt "59000,71625,59750,72375"
    53335352)
    53345353tg (CPTG
     
    53415360font "arial,8,0"
    53425361)
    5343 xt "56900,71500,62000,72500"
     5362xt "52900,71500,58000,72500"
    53445363st "wiz_write_ea"
    53455364ju 2
    5346 blo "62000,72300"
     5365blo "58000,72300"
    53475366)
    53485367)
     
    53695388fg "0,65535,0"
    53705389)
    5371 xt "63000,75625,63750,76375"
     5390xt "59000,75625,59750,76375"
    53725391)
    53735392tg (CPTG
     
    53805399font "arial,8,0"
    53815400)
    5382 xt "56500,75500,62000,76500"
     5401xt "52500,75500,58000,76500"
    53835402st "wiz_write_end"
    53845403ju 2
    5385 blo "62000,76300"
     5404blo "58000,76300"
    53865405)
    53875406)
     
    54085427fg "0,65535,0"
    54095428)
    5410 xt "63000,76625,63750,77375"
     5429xt "59000,76625,59750,77375"
    54115430)
    54125431tg (CPTG
     
    54195438font "arial,8,0"
    54205439)
    5421 xt "55400,76500,62000,77500"
     5440xt "51400,76500,58000,77500"
    54225441st "wiz_write_header"
    54235442ju 2
    5424 blo "62000,77300"
     5443blo "58000,77300"
    54255444)
    54265445)
     
    54475466fg "0,65535,0"
    54485467)
    5449 xt "63000,72625,63750,73375"
     5468xt "59000,72625,59750,73375"
    54505469)
    54515470tg (CPTG
     
    54585477font "arial,8,0"
    54595478)
    5460 xt "52600,72500,62000,73500"
     5479xt "48600,72500,58000,73500"
    54615480st "wiz_write_length : (16:0)"
    54625481ju 2
    5463 blo "62000,73300"
     5482blo "58000,73300"
    54645483)
    54655484)
     
    54875506fg "0,65535,0"
    54885507)
    5489 xt "31250,87625,32000,88375"
     5508xt "27250,85625,28000,86375"
    54905509)
    54915510tg (CPTG
     
    54985517font "arial,8,0"
    54995518)
    5500 xt "33000,87500,36400,88500"
     5519xt "29000,85500,32400,86500"
    55015520st "roi_array"
    5502 blo "33000,88300"
     5521blo "29000,86300"
    55035522)
    55045523)
     
    55255544fg "0,65535,0"
    55265545)
    5527 xt "31250,81625,32000,82375"
     5546xt "27250,79625,28000,80375"
    55285547)
    55295548tg (CPTG
     
    55365555font "arial,8,0"
    55375556)
    5538 xt "33000,81500,42100,82500"
     5557xt "29000,79500,38100,80500"
    55395558st "package_length : (15:0)"
    5540 blo "33000,82300"
     5559blo "29000,80300"
    55415560)
    55425561)
     
    55645583fg "0,65535,0"
    55655584)
    5566 xt "31250,78625,32000,79375"
     5585xt "27250,76625,28000,77375"
    55675586)
    55685587tg (CPTG
     
    55755594font "arial,8,0"
    55765595)
    5577 xt "33000,78500,38600,79500"
     5596xt "29000,76500,34600,77500"
    55785597st "config_started"
    5579 blo "33000,79300"
     5598blo "29000,77300"
    55805599)
    55815600)
     
    56025621fg "0,65535,0"
    56035622)
    5604 xt "63000,77625,63750,78375"
     5623xt "59000,77625,59750,78375"
    56055624)
    56065625tg (CPTG
     
    56135632font "arial,8,0"
    56145633)
    5615 xt "59000,77500,62000,78500"
     5634xt "55000,77500,58000,78500"
    56165635st "wiz_ack"
    56175636ju 2
    5618 blo "62000,78300"
     5637blo "58000,78300"
    56195638)
    56205639)
     
    56395658fg "0,65535,0"
    56405659)
    5641 xt "31250,75625,32000,76375"
     5660xt "27250,73625,28000,74375"
    56425661)
    56435662tg (CPTG
     
    56505669font "arial,8,0"
    56515670)
    5652 xt "33000,75500,40800,76500"
     5671xt "29000,73500,36800,74500"
    56535672st "ram_write_ready_ack"
    5654 blo "33000,76300"
     5673blo "29000,74300"
    56555674)
    56565675)
     
    56795698lineWidth 2
    56805699)
    5681 xt "32000,70000,63000,90000"
     5700xt "28000,68000,59000,88000"
    56825701)
    56835702oxt "15000,6000,23000,16000"
     
    56925711font "arial,8,1"
    56935712)
    5694 xt "32350,90000,38550,91000"
     5713xt "28350,88000,34550,89000"
    56955714st "FACT_FAD_lib"
    5696 blo "32350,90800"
     5715blo "28350,88800"
    56975716tm "BdLibraryNameMgr"
    56985717)
     
    57025721font "arial,8,1"
    57035722)
    5704 xt "32350,91000,39650,92000"
     5723xt "28350,89000,35650,90000"
    57055724st "memory_manager"
    5706 blo "32350,91800"
     5725blo "28350,89800"
    57075726tm "CptNameMgr"
    57085727)
     
    57125731font "arial,8,1"
    57135732)
    5714 xt "32350,92000,42850,93000"
     5733xt "28350,90000,38850,91000"
    57155734st "I_main_memory_manager"
    5716 blo "32350,92800"
     5735blo "28350,90800"
    57175736tm "InstanceNameMgr"
    57185737)
     
    57295748font "Courier New,8,0"
    57305749)
    5731 xt "32000,68400,61500,70000"
     5750xt "31000,66400,60500,68000"
    57325751st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer ) 
    57335752RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
     
    57555774fg "49152,49152,49152"
    57565775)
    5757 xt "32250,88250,33750,89750"
     5776xt "28250,86250,29750,87750"
    57585777iconName "VhdlFileViewIcon.png"
    57595778iconMaskName "VhdlFileViewIcon.msk"
     
    57815800)
    57825801xt "-172000,101200,-149500,102000"
    5783 st "SIGNAL wiz_busy               : std_logic"
     5802st "SIGNAL wiz_busy               : std_logic
     5803"
    57845804)
    57855805)
     
    58005820)
    58015821xt "-172000,103600,-128500,104400"
    5802 st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
     5822st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
     5823"
    58035824)
    58045825)
     
    58205841)
    58215842xt "-172000,106000,-122500,106800"
    5822 st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
     5843st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
     5844"
    58235845)
    58245846)
     
    58415863)
    58425864xt "-172000,102800,-122500,103600"
    5843 st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
     5865st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
     5866"
    58445867)
    58455868)
     
    58615884)
    58625885xt "-172000,102000,-122500,102800"
    5863 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
     5886st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
     5887"
    58645888)
    58655889)
     
    58805904)
    58815905xt "-172000,104400,-128500,105200"
    5882 st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
     5906st "SIGNAL wiz_write_end          : std_logic                                    := '0'
     5907"
    58835908)
    58845909)
     
    58995924)
    59005925xt "-172000,105200,-128500,106000"
    5901 st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
     5926st "SIGNAL wiz_write_header       : std_logic                                    := '0'
     5927"
    59025928)
    59035929)
     
    59165942)
    59175943xt "-172000,82800,-149500,83600"
    5918 st "SIGNAL ram_write_ea           : std_logic"
     5944st "SIGNAL ram_write_ea           : std_logic
     5945"
    59195946)
    59205947)
     
    59345961)
    59355962xt "-172000,83600,-128500,84400"
    5936 st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
     5963st "SIGNAL ram_write_ready        : std_logic                                    := '0'
     5964"
    59375965)
    59385966)
     
    59525980)
    59535981xt "-172000,54800,-128500,55600"
    5954 st "SIGNAL config_start           : std_logic                                    := '0'"
     5982st "SIGNAL config_start           : std_logic                                    := '0'
     5983"
    59555984)
    59565985)
     
    59695998)
    59705999xt "-172000,49200,-149500,50000"
    5971 st "SIGNAL config_ready           : std_logic"
     6000st "SIGNAL config_ready           : std_logic
     6001"
    59726002)
    59736003)
     
    59866016)
    59876017xt "-172000,86800,-148000,87600"
    5988 st "SIGNAL roi_max                : roi_max_type"
     6018st "SIGNAL roi_max                : roi_max_type
     6019"
    59896020)
    59906021)
     
    60046035)
    60056036xt "-172000,77200,-139500,78000"
    6006 st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
     6037st "SIGNAL package_length         : std_logic_vector(15 downto 0)
     6038"
    60076039)
    60086040)
     
    60226054)
    60236055xt "-172000,19200,-132000,20000"
    6024 st "adc_oeb                : std_logic                                    := '1'"
     6056st "adc_oeb                : std_logic                                    := '1'
     6057"
    60256058)
    60266059)
     
    61296162)
    61306163xt "-172000,86000,-147000,86800"
    6131 st "SIGNAL roi_array              : roi_array_type"
     6164st "SIGNAL roi_array              : roi_array_type
     6165"
    61326166)
    61336167)
     
    65626596)
    65636597xt "-172000,14400,-153500,15200"
    6564 st "CLK_25_PS              : std_logic"
     6598st "CLK_25_PS              : std_logic
     6599"
    65656600)
    65666601)
     
    66246659)
    66256660xt "-172000,15200,-153500,16000"
    6626 st "CLK_50                 : std_logic"
     6661st "CLK_50                 : std_logic
     6662"
    66276663)
    66286664)
     
    66416677)
    66426678xt "-172000,39600,-149500,40400"
    6643 st "SIGNAL CLK_25                 : std_logic"
     6679st "SIGNAL CLK_25                 : std_logic
     6680"
    66446681)
    66456682)
     
    67036740)
    67046741xt "-172000,3200,-153500,4000"
    6705 st "CLK                    : std_logic"
     6742st "CLK                    : std_logic
     6743"
    67066744)
    67076745)
     
    67216759)
    67226760xt "-172000,8800,-143500,9600"
    6723 st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
     6761st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
     6762"
    67246763)
    67256764)
     
    67386777)
    67396778xt "-172000,8000,-148000,8800"
    6740 st "adc_data_array         : adc_data_array_type"
     6779st "adc_data_array         : adc_data_array_type
     6780"
    67416781)
    67426782)
     
    68016841)
    68026842xt "-172000,66800,-128500,67600"
    6803 st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
     6843st "SIGNAL drs_clk_en             : std_logic                                    := '0'
     6844"
    68046845)
    68056846)
     
    68186859)
    68196860xt "-172000,73200,-143500,74000"
    6820 st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
     6861st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
     6862"
    68216863)
    68226864)
     
    68366878)
    68376879xt "-172000,67600,-128500,68400"
    6838 st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
     6880st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
     6881"
    68396882)
    68406883)
     
    68556898)
    68566899xt "-172000,25600,-126000,26400"
    6857 st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
     6900st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
     6901"
    68586902)
    68596903)
     
    68736917)
    68746918xt "-172000,26400,-132000,27200"
    6875 st "drs_dwrite             : std_logic                                    := '1'"
     6919st "drs_dwrite             : std_logic                                    := '1'
     6920"
    68766921)
    68776922)
     
    69807025)
    69817026xt "-172000,4800,-153500,5600"
    6982 st "SROUT_in_0             : std_logic"
     7027st "SROUT_in_0             : std_logic
     7028"
    69837029)
    69847030)
     
    69977043)
    69987044xt "-172000,5600,-153500,6400"
    6999 st "SROUT_in_1             : std_logic"
     7045st "SROUT_in_1             : std_logic
     7046"
    70007047)
    70017048)
     
    70147061)
    70157062xt "-172000,6400,-153500,7200"
    7016 st "SROUT_in_2             : std_logic"
     7063st "SROUT_in_2             : std_logic
     7064"
    70177065)
    70187066)
     
    70317079)
    70327080xt "-172000,7200,-153500,8000"
    7033 st "SROUT_in_3             : std_logic"
     7081st "SROUT_in_3             : std_logic
     7082"
    70347083)
    70357084)
     
    72287277)
    72297278xt "-172000,68400,-149500,69200"
    7230 st "SIGNAL drs_read_s_cell_ready  : std_logic"
     7279st "SIGNAL drs_read_s_cell_ready  : std_logic
     7280"
    72317281)
    72327282)
     
    78837933)
    78847934xt "-172000,16000,-132000,16800"
    7885 st "RSRLOAD                : std_logic                                    := '0'"
     7935st "RSRLOAD                : std_logic                                    := '0'
     7936"
    78867937)
    78877938)
     
    79467997)
    79477998xt "-172000,16800,-132000,17600"
    7948 st "SRCLK                  : std_logic                                    := '0'"
     7999st "SRCLK                  : std_logic                                    := '0'
     8000"
    79498001)
    79508002)
     
    85998651)
    86008652xt "-172000,45200,-140000,46000"
    8601 st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
     8653st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
     8654"
    86028655)
    86038656)
     
    86168669)
    86178670xt "-172000,47600,-149500,48400"
    8618 st "SIGNAL config_data_valid      : std_logic"
     8671st "SIGNAL config_data_valid      : std_logic
     8672"
    86198673)
    86208674)
     
    86338687)
    86348688xt "-172000,46000,-149500,46800"
    8635 st "SIGNAL config_busy            : std_logic"
     8689st "SIGNAL config_busy            : std_logic
     8690"
    86368691)
    86378692)
     
    86518706)
    86528707xt "-172000,46800,-139500,47600"
    8653 st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
     8708st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
     8709"
    86548710)
    86558711)
     
    86688724)
    86698725xt "-172000,60400,-149500,61200"
    8670 st "SIGNAL config_wr_en           : std_logic"
     8726st "SIGNAL config_wr_en           : std_logic
     8727"
    86718728)
    86728729)
     
    86858742)
    86868743xt "-172000,48400,-149500,49200"
    8687 st "SIGNAL config_rd_en           : std_logic"
     8744st "SIGNAL config_rd_en           : std_logic
     8745"
    86888746)
    86898747)
     
    87028760)
    87038761xt "-172000,61200,-147000,62000"
    8704 st "SIGNAL dac_array              : dac_array_type"
     8762st "SIGNAL dac_array              : dac_array_type
     8763"
    87058764)
    87068765)
     
    87198778)
    87208779xt "-172000,55600,-149500,56400"
    8721 st "SIGNAL config_start_cm        : std_logic"
     8780st "SIGNAL config_start_cm        : std_logic
     8781"
    87228782)
    87238783)
     
    87368796)
    87378797xt "-172000,50000,-149500,50800"
    8738 st "SIGNAL config_ready_cm        : std_logic"
     8798st "SIGNAL config_ready_cm        : std_logic
     8799"
    87398800)
    87408801)
     
    87568817)
    87578818xt "-172000,28000,-126000,28800"
    8758 st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
     8819st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')
     8820"
    87598821)
    87608822)
     
    87738835)
    87748836xt "-172000,91600,-149500,92400"
    8775 st "SIGNAL sensor_ready           : std_logic"
     8837st "SIGNAL sensor_ready           : std_logic
     8838"
    87768839)
    87778840)
     
    87908853)
    87918854xt "-172000,90800,-145500,91600"
    8792 st "SIGNAL sensor_array           : sensor_array_type"
     8855st "SIGNAL sensor_array           : sensor_array_type
     8856"
    87938857)
    87948858)
     
    88078871)
    88088872xt "-172000,50800,-149500,51600"
    8809 st "SIGNAL config_ready_spi       : std_logic"
     8873st "SIGNAL config_ready_spi       : std_logic
     8874"
    88108875)
    88118876)
     
    88268891)
    88278892xt "-172000,42000,-140000,42800"
    8828 st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
     8893st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)
     8894"
    88298895)
    88308896)
     
    88438909)
    88448910xt "-172000,41200,-144500,42000"
    8845 st "SIGNAL adc_data_array_int     : adc_data_array_type"
     8911st "SIGNAL adc_data_array_int     : adc_data_array_type
     8912"
    88468913)
    88478914)
     
    91339200)
    91349201xt "-172000,56400,-128500,57200"
    9135 st "SIGNAL config_start_spi       : std_logic                                    := '0'"
     9202st "SIGNAL config_start_spi       : std_logic                                    := '0'
     9203"
    91369204)
    91379205)
     
    96669734)
    96679735xt "-172000,30400,-153500,31200"
    9668 st "sclk                   : std_logic"
     9736st "sclk                   : std_logic
     9737"
    96699738)
    96709739)
     
    96859754)
    96869755xt "-172000,36000,-153500,36800"
    9687 st "sio                    : std_logic"
     9756st "sio                    : std_logic
     9757"
    96889758)
    96899759)
     
    97029772)
    97039773xt "-172000,24000,-153500,24800"
    9704 st "dac_cs                 : std_logic"
     9774st "dac_cs                 : std_logic
     9775"
    97059776)
    97069777)
     
    97209791)
    97219792xt "-172000,31200,-143500,32000"
    9722 st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
     9793st "sensor_cs              : std_logic_vector(3 DOWNTO 0)
     9794"
    97239795)
    97249796)
     
    99189990)
    99199991xt "-172000,76400,-128500,77200"
    9920 st "SIGNAL new_config             : std_logic                                    := '0'"
     9992st "SIGNAL new_config             : std_logic                                    := '0'
     9993"
    99219994)
    99229995)
     
    993510008)
    993610009xt "-172000,57200,-149500,58000"
    9937 st "SIGNAL config_started         : std_logic"
     10010st "SIGNAL config_started         : std_logic
     10011"
    993810012)
    993910013)
     
    995310027)
    995410028xt "-172000,59600,-128500,60400"
    9955 st "SIGNAL config_started_spi     : std_logic                                    := '0'"
     10029st "SIGNAL config_started_spi     : std_logic                                    := '0'
     10030"
    995610031)
    995710032)
     
    997110046)
    997210047xt "-172000,58000,-128500,58800"
    9973 st "SIGNAL config_started_cu      : std_logic                                    := '0'"
     10048st "SIGNAL config_started_cu      : std_logic                                    := '0'
     10049"
    997410050)
    997510051)
     
    998810064)
    998910065xt "-172000,58800,-149500,59600"
    9990 st "SIGNAL config_started_mm      : std_logic"
     10066st "SIGNAL config_started_mm      : std_logic
     10067"
    999110068)
    999210069)
     
    1000610083)
    1000710084xt "-172000,28800,-132000,29600"
    10008 st "mosi                   : std_logic                                    := '0'"
     10085st "mosi                   : std_logic                                    := '0'
     10086"
    1000910087)
    1001010088)
     
    1007110149)
    1007210150xt "-172000,24800,-118500,25600"
    10073 st "denable                : std_logic                                    := '0' -- default domino wave off"
     10151st "denable                : std_logic                                    := '0' -- default domino wave off
     10152"
    1007410153)
    1007510154)
     
    1013310212)
    1013410213xt "-172000,75600,-128500,76400"
    10135 st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
     10214st "SIGNAL dwrite_enable          : std_logic                                    := '1'
     10215"
    1013610216)
    1013710217)
     
    1052010600)
    1052110601xt "-172000,74800,-128500,75600"
    10522 st "SIGNAL dwrite                 : std_logic                                    := '1'"
     10602st "SIGNAL dwrite                 : std_logic                                    := '1'
     10603"
    1052310604)
    1052410605)
     
    1089410975)
    1089510976xt "-172000,100400,-149500,101200"
    10896 st "SIGNAL wiz_ack                : std_logic"
     10977st "SIGNAL wiz_ack                : std_logic
     10978"
    1089710979)
    1089810980)
     
    1127711359)
    1127811360xt "-172000,89200,-149500,90000"
    11279 st "SIGNAL sclk1                  : std_logic"
     11361st "SIGNAL sclk1                  : std_logic
     11362"
    1128011363)
    1128111364)
     
    1129411377)
    1129511378xt "-172000,90000,-149500,90800"
    11296 st "SIGNAL sclk_enable            : std_logic"
     11379st "SIGNAL sclk_enable            : std_logic
     11380"
    1129711381)
    1129811382)
     
    1131211396)
    1131311397xt "-172000,18400,-132000,19200"
    11314 st "adc_clk_en             : std_logic                                    := '0'"
     11398st "adc_clk_en             : std_logic                                    := '0'
     11399"
    1131511400)
    1131611401)
     
    1176611851)
    1176711852xt "-172000,78000,-113000,78800"
    11768 st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards"
     11853st "SIGNAL ps_direction           : std_logic                                    := '1' -- default phase shift upwards
     11854"
    1176911855)
    1177011856)
     
    1178711873)
    1178811874xt "-172000,78800,-112000,79600"
    11789 st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once"
     11875st "SIGNAL ps_do_phase_shift      : std_logic                                    := '0' --pulse this to phase shift once
     11876"
    1179011877)
    1179111878)
     
    1180711894)
    1180811895xt "-172000,79600,-104500,80400"
    11809 st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift"
     11896st "SIGNAL ps_reset               : std_logic                                    := '0' -- pulse this to reset the variable phase shift
     11897"
    1181011898)
    1181111899)
     
    1182511913)
    1182611914xt "-172000,94000,-128500,94800"
    11827 st "SIGNAL srclk_enable           : std_logic                                    := '0'"
     11915st "SIGNAL srclk_enable           : std_logic                                    := '0'
     11916"
    1182811917)
    1182911918)
     
    1220912298)
    1221012299xt "-172000,40400,-128500,41200"
    12211 st "SIGNAL SRCLK1                 : std_logic                                    := '0'"
     12300st "SIGNAL SRCLK1                 : std_logic                                    := '0'
     12301"
    1221212302)
    1221312303)
     
    1223112321xt "-172000,51600,-128500,53200"
    1223212322st "-- --
    12233 SIGNAL config_rw_ack          : std_logic                                    := '0'"
     12323SIGNAL config_rw_ack          : std_logic                                    := '0'
     12324"
    1223412325)
    1223512326)
     
    1225312344xt "-172000,53200,-128500,54800"
    1225412345st "-- --
    12255 SIGNAL config_rw_ready        : std_logic                                    := '0'"
     12346SIGNAL config_rw_ready        : std_logic                                    := '0'
     12347"
    1225612348)
    1225712349)
     
    1227012362)
    1227112363xt "-172000,87600,-149500,88400"
    12272 st "SIGNAL s_trigger              : std_logic"
     12364st "SIGNAL s_trigger              : std_logic
     12365"
    1227312366)
    1227412367)
     
    1228712380)
    1228812381xt "-172000,96400,-149500,97200"
    12289 st "SIGNAL start_srin_write_8b    : std_logic"
     12382st "SIGNAL start_srin_write_8b    : std_logic
     12383"
    1229012384)
    1229112385)
     
    1230512399)
    1230612400xt "-172000,94800,-128500,95600"
    12307 st "SIGNAL srin_write_ack         : std_logic                                    := '0'"
     12401st "SIGNAL srin_write_ack         : std_logic                                    := '0'
     12402"
    1230812403)
    1230912404)
     
    1232312418)
    1232412419xt "-172000,95600,-128500,96400"
    12325 st "SIGNAL srin_write_ready       : std_logic                                    := '0'"
     12420st "SIGNAL srin_write_ready       : std_logic                                    := '0'
     12421"
    1232612422)
    1232712423)
     
    1234212438)
    1234312439xt "-172000,74000,-122500,74800"
    12344 st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')"
     12440st "SIGNAL drs_srin_data          : std_logic_vector(7 downto 0)                 := (others => '0')
     12441"
    1234512442)
    1234612443)
     
    1236012457)
    1236112458xt "-172000,17600,-132000,18400"
    12362 st "SRIN_out               : std_logic                                    := '0'"
     12459st "SRIN_out               : std_logic                                    := '0'
     12460"
    1236312461)
    1236412462)
     
    1286312961)
    1286412962*431 (Net
    12865 uid 10449,0
    12866 decl (Decl
    12867 n "trigger_out"
    12868 t "std_logic"
    12869 preAdd 0
    12870 posAdd 0
    12871 o 120
    12872 suid 240,0
    12873 )
    12874 declText (MLText
    12875 uid 10450,0
    12876 va (VaSet
    12877 font "Courier New,8,0"
    12878 )
    12879 xt "-172000,99600,-149500,100400"
    12880 st "SIGNAL trigger_out            : std_logic"
    12881 )
    12882 )
    12883 *432 (Net
    1288412963uid 10465,0
    1288512964lang 2
     
    1290112980xt "-172000,84400,-128500,86000"
    1290212981st "-- --
    12903 SIGNAL ram_write_ready_ack    : std_logic                                    := '0'"
    12904 )
    12905 )
    12906 *433 (Net
     12982SIGNAL ram_write_ready_ack    : std_logic                                    := '0'
     12983"
     12984)
     12985)
     12986*432 (Net
    1290712987uid 10627,0
    1290812988decl (Decl
     
    1291812998)
    1291912999xt "-172000,92400,-149500,93200"
    12920 st "SIGNAL socks_connected        : std_logic"
    12921 )
    12922 )
    12923 *434 (Net
     13000st "SIGNAL socks_connected        : std_logic
     13001"
     13002)
     13003)
     13004*433 (Net
    1292413005uid 10635,0
    1292513006decl (Decl
     
    1293513016)
    1293613017xt "-172000,93200,-149500,94000"
    12937 st "SIGNAL socks_waiting          : std_logic"
    12938 )
    12939 )
    12940 *435 (Net
     13018st "SIGNAL socks_waiting          : std_logic
     13019"
     13020)
     13021)
     13022*434 (Net
    1294113023uid 10721,0
    1294213024decl (Decl
     
    1295213034)
    1295313035xt "-172000,27200,-153500,28000"
    12954 st "green                  : std_logic"
    12955 )
    12956 )
    12957 *436 (PortIoOut
     13036st "green                  : std_logic
     13037"
     13038)
     13039)
     13040*435 (PortIoOut
    1295813041uid 10729,0
    1295913042shape (CompositeShape
     
    1299913082)
    1300013083)
    13001 *437 (Net
     13084*436 (Net
    1300213085uid 10735,0
    1300313086decl (Decl
     
    1301313096)
    1301413097xt "-172000,22400,-153500,23200"
    13015 st "amber                  : std_logic"
    13016 )
    13017 )
    13018 *438 (PortIoOut
     13098st "amber                  : std_logic
     13099"
     13100)
     13101)
     13102*437 (PortIoOut
    1301913103uid 10743,0
    1302013104shape (CompositeShape
     
    1306013144)
    1306113145)
    13062 *439 (Net
     13146*438 (Net
    1306313147uid 10749,0
    1306413148decl (Decl
     
    1307413158)
    1307513159xt "-172000,29600,-153500,30400"
    13076 st "red                    : std_logic"
    13077 )
    13078 )
    13079 *440 (PortIoOut
     13160st "red                    : std_logic
     13161"
     13162)
     13163)
     13164*439 (PortIoOut
    1308013165uid 10757,0
    1308113166shape (CompositeShape
     
    1312113206)
    1312213207)
    13123 *441 (SaComponent
     13208*440 (SaComponent
    1312413209uid 11209,0
    1312513210optionalChildren [
    13126 *442 (CptPort
     13211*441 (CptPort
    1312713212uid 11181,0
    1312813213ps "OnEdgeStrategy"
     
    1315713242)
    1315813243)
    13159 *443 (CptPort
     13244*442 (CptPort
    1316013245uid 11185,0
    1316113246ps "OnEdgeStrategy"
     
    1319213277)
    1319313278)
    13194 *444 (CptPort
     13279*443 (CptPort
    1319513280uid 11189,0
    1319613281ps "OnEdgeStrategy"
     
    1322713312)
    1322813313)
    13229 *445 (CptPort
     13314*444 (CptPort
    1323013315uid 11193,0
    1323113316ps "OnEdgeStrategy"
     
    1326213347)
    1326313348)
    13264 *446 (CptPort
     13349*445 (CptPort
    1326513350uid 11197,0
    1326613351ps "OnEdgeStrategy"
     
    1329513380)
    1329613381)
    13297 *447 (CptPort
     13382*446 (CptPort
    1329813383uid 11201,0
    1329913384ps "OnEdgeStrategy"
     
    1332813413)
    1332913414)
    13330 *448 (CptPort
     13415*447 (CptPort
    1333113416uid 11205,0
    1333213417ps "OnEdgeStrategy"
     
    1336113446)
    1336213447)
    13363 *449 (CptPort
     13448*448 (CptPort
    1336413449uid 12693,0
    1336513450ps "OnEdgeStrategy"
     
    1341313498stg "VerticalLayoutStrategy"
    1341413499textVec [
    13415 *450 (Text
     13500*449 (Text
    1341613501uid 11212,0
    1341713502va (VaSet
     
    1342313508tm "BdLibraryNameMgr"
    1342413509)
    13425 *451 (Text
     13510*450 (Text
    1342613511uid 11213,0
    1342713512va (VaSet
     
    1343313518tm "CptNameMgr"
    1343413519)
    13435 *452 (Text
     13520*451 (Text
    1343613521uid 11214,0
    1343713522va (VaSet
     
    1350013585archFileType "UNKNOWN"
    1350113586)
    13502 *453 (Net
     13587*452 (Net
    1350313588uid 11403,0
    1350413589decl (Decl
     
    1351413599)
    1351513600xt "-172000,72400,-149500,73200"
    13516 st "SIGNAL drs_readout_started    : std_logic"
    13517 )
    13518 )
    13519 *454 (Net
     13601st "SIGNAL drs_readout_started    : std_logic
     13602"
     13603)
     13604)
     13605*453 (Net
    1352013606uid 11856,0
    1352113607decl (Decl
     
    1353113617)
    1353213618xt "-172000,98000,-149500,98800"
    13533 st "SIGNAL trigger_enable         : std_logic"
    13534 )
    13535 )
    13536 *455 (MWC
     13619st "SIGNAL trigger_enable         : std_logic
     13620"
     13621)
     13622)
     13623*454 (MWC
    1353713624uid 12295,0
    1353813625optionalChildren [
    13539 *456 (CptPort
     13626*455 (CptPort
    1354013627uid 12267,0
    1354113628optionalChildren [
    13542 *457 (Line
     13629*456 (Line
    1354313630uid 12271,0
    1354413631layer 5
     
    1355313640]
    1355413641)
    13555 *458 (Property
     13642*457 (Property
    1355613643uid 12272,0
    1355713644pclass "_MW_GEOM_"
     
    1360013687)
    1360113688)
    13602 *459 (CptPort
     13689*458 (CptPort
    1360313690uid 12273,0
    1360413691optionalChildren [
    13605 *460 (Line
     13692*459 (Line
    1360613693uid 12277,0
    1360713694layer 5
     
    1365513742)
    1365613743)
    13657 *461 (CptPort
     13744*460 (CptPort
    1365813745uid 12278,0
    1365913746optionalChildren [
    13660 *462 (Line
     13747*461 (Line
    1366113748uid 12282,0
    1366213749layer 5
     
    1370813795)
    1370913796)
    13710 *463 (CommentGraphic
     13797*462 (CommentGraphic
    1371113798uid 12283,0
    1371213799optionalChildren [
    13713 *464 (Property
     13800*463 (Property
    1371413801uid 12285,0
    1371513802pclass "_MW_GEOM_"
     
    1373513822oxt "7000,10000,7000,10000"
    1373613823)
    13737 *465 (CommentGraphic
     13824*464 (CommentGraphic
    1373813825uid 12286,0
    1373913826optionalChildren [
    13740 *466 (Property
     13827*465 (Property
    1374113828uid 12288,0
    1374213829pclass "_MW_GEOM_"
     
    1376213849oxt "7000,6000,7000,6000"
    1376313850)
    13764 *467 (Grouping
     13851*466 (Grouping
    1376513852uid 12289,0
    1376613853optionalChildren [
    13767 *468 (CommentGraphic
     13854*467 (CommentGraphic
    1376813855uid 12291,0
    1376913856shape (PolyLine2D
     
    1378613873oxt "7000,6000,9000,10000"
    1378713874)
    13788 *469 (CommentGraphic
     13875*468 (CommentGraphic
    1378913876uid 12293,0
    1379013877shape (Arc2D
     
    1383913926stg "VerticalLayoutStrategy"
    1384013927textVec [
    13841 *470 (Text
     13928*469 (Text
    1384213929uid 12298,0
    1384313930va (VaSet
     
    1384913936blo "-80500,73300"
    1385013937)
    13851 *471 (Text
     13938*470 (Text
    1385213939uid 12299,0
    1385313940va (VaSet
     
    1385813945blo "-80500,74300"
    1385913946)
    13860 *472 (Text
     13947*471 (Text
    1386113948uid 12300,0
    1386213949va (VaSet
     
    1390313990)
    1390413991)
    13905 *473 (Net
     13992*472 (Net
    1390613993uid 12304,0
    1390713994decl (Decl
     
    1391914006)
    1392014007xt "-172000,65200,-149500,66000"
    13921 st "SIGNAL dout                   : std_logic"
    13922 )
    13923 )
    13924 *474 (SaComponent
     14008st "SIGNAL dout                   : std_logic
     14009"
     14010)
     14011)
     14012*473 (SaComponent
    1392514013uid 12625,0
    1392614014optionalChildren [
    13927 *475 (CptPort
     14015*474 (CptPort
    1392814016uid 12605,0
    1392914017ps "OnEdgeStrategy"
     
    1395814046)
    1395914047)
    13960 *476 (CptPort
     14048*475 (CptPort
    1396114049uid 12609,0
    1396214050ps "OnEdgeStrategy"
     
    1399414082)
    1399514083)
    13996 *477 (CptPort
     14084*476 (CptPort
    1399714085uid 12613,0
    1399814086ps "OnEdgeStrategy"
     
    1402914117)
    1403014118)
    14031 *478 (CptPort
     14119*477 (CptPort
    1403214120uid 12617,0
    1403314121ps "OnEdgeStrategy"
     
    1406314151)
    1406414152)
    14065 *479 (CptPort
     14153*478 (CptPort
    1406614154uid 12621,0
    1406714155ps "OnEdgeStrategy"
     
    1409914187)
    1410014188)
    14101 *480 (CptPort
     14189*479 (CptPort
    1410214190uid 12673,0
    1410314191ps "OnEdgeStrategy"
     
    1414914237stg "VerticalLayoutStrategy"
    1415014238textVec [
    14151 *481 (Text
     14239*480 (Text
    1415214240uid 12628,0
    1415314241va (VaSet
     
    1415914247tm "BdLibraryNameMgr"
    1416014248)
    14161 *482 (Text
     14249*481 (Text
    1416214250uid 12629,0
    1416314251va (VaSet
     
    1416914257tm "CptNameMgr"
    1417014258)
    14171 *483 (Text
     14259*482 (Text
    1417214260uid 12630,0
    1417314261va (VaSet
     
    1421614304archFileType "UNKNOWN"
    1421714305)
    14218 *484 (Net
     14306*483 (Net
    1421914307uid 12641,0
    1422014308decl (Decl
     
    1423214320)
    1423314321xt "-172000,66000,-149500,66800"
    14234 st "SIGNAL dout1                  : std_logic"
    14235 )
    14236 )
    14237 *485 (Net
     14322st "SIGNAL dout1                  : std_logic
     14323"
     14324)
     14325)
     14326*484 (Net
    1423814327uid 12647,0
    1423914328decl (Decl
     
    1425614345st "-- --
    1425714346--      drs_dwrite : out std_logic := '1';
    14258 SIGNAL drs_readout_ready      : std_logic                                    := '0'"
    14259 )
    14260 )
    14261 *486 (Net
     14347SIGNAL drs_readout_ready      : std_logic                                    := '0'
     14348"
     14349)
     14350)
     14351*485 (Net
    1426214352uid 12653,0
    1426314353decl (Decl
     
    1427314363)
    1427414364xt "-172000,71600,-149500,72400"
    14275 st "SIGNAL drs_readout_ready_ack  : std_logic"
    14276 )
    14277 )
    14278 *487 (Net
     14365st "SIGNAL drs_readout_ready_ack  : std_logic
     14366"
     14367)
     14368)
     14369*486 (Net
    1427914370uid 12705,0
    1428014371decl (Decl
     
    1429014381)
    1429114382xt "-172000,20000,-153500,20800"
    14292 st "additional_flasher_out : std_logic"
    14293 )
    14294 )
    14295 *488 (PortIoOut
     14383st "additional_flasher_out : std_logic
     14384"
     14385)
     14386)
     14387*487 (PortIoOut
    1429614388uid 12713,0
    1429714389shape (CompositeShape
     
    1433714429)
    1433814430)
    14339 *489 (SaComponent
     14431*488 (SaComponent
    1434014432uid 13117,0
    1434114433optionalChildren [
    14342 *490 (CptPort
     14434*489 (CptPort
    1434314435uid 13101,0
    1434414436ps "OnEdgeStrategy"
     
    1435014442fg "0,65535,0"
    1435114443)
    14352 xt "63000,61625,63750,62375"
     14444xt "72000,61625,72750,62375"
    1435314445)
    1435414446tg (CPTG
     
    1436014452va (VaSet
    1436114453)
    14362 xt "60100,61500,62000,62500"
     14454xt "69100,61500,71000,62500"
    1436314455st "CLK"
    1436414456ju 2
    14365 blo "62000,62300"
     14457blo "71000,62300"
    1436614458)
    1436714459)
     
    1437414466)
    1437514467)
    14376 *491 (CptPort
     14468*490 (CptPort
    1437714469uid 13105,0
    1437814470ps "OnEdgeStrategy"
     
    1438414476fg "0,65535,0"
    1438514477)
    14386 xt "63000,62625,63750,63375"
     14478xt "72000,62625,72750,63375"
    1438714479)
    1438814480tg (CPTG
     
    1439414486va (VaSet
    1439514487)
    14396 xt "59400,62500,62000,63500"
     14488xt "68400,62500,71000,63500"
    1439714489st "enable"
    1439814490ju 2
    14399 blo "62000,63300"
     14491blo "71000,63300"
    1440014492)
    1440114493)
     
    1440814500)
    1440914501)
    14410 *492 (CptPort
     14502*491 (CptPort
    1441114503uid 13109,0
    1441214504ps "OnEdgeStrategy"
     
    1441814510fg "0,65535,0"
    1441914511)
    14420 xt "63000,63625,63750,64375"
     14512xt "72000,63625,72750,64375"
    1442114513)
    1442214514tg (CPTG
     
    1442814520va (VaSet
    1442914521)
    14430 xt "55900,63500,62000,64500"
     14522xt "64900,63500,71000,64500"
    1443114523st "multiplier : (7:0)"
    1443214524ju 2
    14433 blo "62000,64300"
     14525blo "71000,64300"
    1443414526)
    1443514527)
     
    1444314535)
    1444414536)
    14445 *493 (CptPort
     14537*492 (CptPort
    1444614538uid 13113,0
    1444714539ps "OnEdgeStrategy"
     
    1445314545fg "0,65535,0"
    1445414546)
    14455 xt "50250,61625,51000,62375"
     14547xt "59250,61625,60000,62375"
    1445614548)
    1445714549tg (CPTG
     
    1446314555va (VaSet
    1446414556)
    14465 xt "52000,61500,54800,62500"
     14557xt "61000,61500,63800,62500"
    1446614558st "trigger"
    14467 blo "52000,62300"
     14559blo "61000,62300"
    1446814560)
    1446914561)
     
    1448614578lineWidth 2
    1448714579)
    14488 xt "51000,61000,63000,65000"
     14580xt "60000,61000,72000,65000"
    1448914581)
    1449014582oxt "0,0,8000,10000"
     
    1449414586stg "VerticalLayoutStrategy"
    1449514587textVec [
     14588*493 (Text
     14589uid 13120,0
     14590va (VaSet
     14591font "Arial,8,1"
     14592)
     14593xt "62350,65000,68550,66000"
     14594st "FACT_FAD_lib"
     14595blo "62350,65800"
     14596tm "BdLibraryNameMgr"
     14597)
    1449614598*494 (Text
    14497 uid 13120,0
     14599uid 13121,0
    1449814600va (VaSet
    1449914601font "Arial,8,1"
    1450014602)
    14501 xt "53350,65000,59550,66000"
    14502 st "FACT_FAD_lib"
    14503 blo "53350,65800"
    14504 tm "BdLibraryNameMgr"
     14603xt "62350,66000,69650,67000"
     14604st "continous_pulser"
     14605blo "62350,66800"
     14606tm "CptNameMgr"
    1450514607)
    1450614608*495 (Text
    14507 uid 13121,0
     14609uid 13122,0
    1450814610va (VaSet
    1450914611font "Arial,8,1"
    1451014612)
    14511 xt "53350,66000,60650,67000"
    14512 st "continous_pulser"
    14513 blo "53350,66800"
    14514 tm "CptNameMgr"
    14515 )
    14516 *496 (Text
    14517 uid 13122,0
    14518 va (VaSet
    14519 font "Arial,8,1"
    14520 )
    14521 xt "53350,67000,55150,68000"
     14613xt "62350,67000,64150,68000"
    1452214614st "U_3"
    14523 blo "53350,67800"
     14615blo "62350,67800"
    1452414616tm "InstanceNameMgr"
    1452514617)
     
    1453614628font "Courier New,8,0"
    1453714629)
    14538 xt "44000,60200,71500,61000"
     14630xt "53000,60200,80500,61000"
    1453914631st "MINIMAL_TRIGGER_WAIT_TIME = 250000    ( integer )  "
    1454014632)
     
    1455614648fg "49152,49152,49152"
    1455714649)
    14558 xt "51250,63250,52750,64750"
     14650xt "60250,63250,61750,64750"
    1455914651iconName "VhdlFileViewIcon.png"
    1456014652iconMaskName "VhdlFileViewIcon.msk"
     
    1456714659archFileType "UNKNOWN"
    1456814660)
    14569 *497 (Net
     14661*496 (Net
    1457014662uid 13157,0
    1457114663decl (Decl
     
    1458214674)
    1458314675xt "-172000,43600,-128500,44400"
    14584 st "SIGNAL c_trigger_enable       : std_logic                                    := '0'"
    14585 )
    14586 )
    14587 *498 (Net
     14676st "SIGNAL c_trigger_enable       : std_logic                                    := '0'
     14677"
     14678)
     14679)
     14680*497 (Net
    1458814681uid 13163,0
    1458914682decl (Decl
     
    1460314696)
    1460414697xt "-172000,44400,-112000,45200"
    14605 st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes"
    14606 )
    14607 )
    14608 *499 (Net
     14698st "SIGNAL c_trigger_mult         : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '1') --subject to changes
     14699"
     14700)
     14701)
     14702*498 (Net
    1460914703uid 13206,0
    1461014704decl (Decl
     
    1462014714)
    1462114715xt "-172000,88400,-149500,89200"
    14622 st "SIGNAL s_trigger_0            : std_logic"
    14623 )
    14624 )
    14625 *500 (Net
     14716st "SIGNAL s_trigger_0            : std_logic
     14717"
     14718)
     14719)
     14720*499 (Net
    1462614721uid 13208,0
    1462714722decl (Decl
     
    1463714732)
    1463814733xt "-172000,97200,-149500,98000"
    14639 st "SIGNAL trigger1               : std_logic"
    14640 )
    14641 )
    14642 *501 (MWC
     14734st "SIGNAL trigger1               : std_logic
     14735"
     14736)
     14737)
     14738*500 (MWC
    1464314739uid 13266,0
    1464414740optionalChildren [
    14645 *502 (CptPort
     14741*501 (CptPort
    1464614742uid 13230,0
    1464714743optionalChildren [
    14648 *503 (Line
     14744*502 (Line
    1464914745uid 13234,0
    1465014746layer 5
     
    1465314749vasetType 3
    1465414750)
    14655 xt "40408,62000,42000,62000"
    14656 pts [
    14657 "42000,62000"
    14658 "40408,62000"
     14751xt "52408,62000,54000,62000"
     14752pts [
     14753"54000,62000"
     14754"52408,62000"
    1465914755]
    1466014756)
     
    1466914765fg "0,65535,65535"
    1467014766)
    14671 xt "42000,61625,42750,62375"
     14767xt "54000,61625,54750,62375"
    1467214768)
    1467314769tg (CPTG
     
    1468214778font "arial,8,0"
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    1633116433uid 15032,0
    1633216434pclass "_MW_GEOM_"
     
    1635316455oxt "110000,269000,110000,269000"
    1635416456)
    16355 *577 (CommentGraphic
     16457*576 (CommentGraphic
    1635616458uid 15033,0
    1635716459optionalChildren [
    16358 *578 (Property
     16460*577 (Property
    1635916461uid 15035,0
    1636016462pclass "_MW_GEOM_"
     
    1638116483oxt "114000,269000,114000,269000"
    1638216484)
    16383 *579 (CptPort
     16485*578 (CptPort
    1638416486uid 15160,0
    1638516487optionalChildren [
    16386 *580 (Line
     16488*579 (Line
    1638716489uid 15164,0
    1638816490sl 0
     
    1643616538)
    1643716539)
    16438 *581 (CptPort
     16540*580 (CptPort
    1643916541uid 15165,0
    1644016542optionalChildren [
    16441 *582 (Line
     16543*581 (Line
    1644216544uid 15169,0
    1644316545sl 0
     
    1651116613stg "VerticalLayoutStrategy"
    1651216614textVec [
    16513 *583 (Text
     16615*582 (Text
    1651416616uid 15039,0
    1651516617va (VaSet
     
    1652116623blo "148500,89300"
    1652216624)
    16523 *584 (Text
     16625*583 (Text
    1652416626uid 15040,0
    1652516627va (VaSet
     
    1653016632blo "148500,90300"
    1653116633)
    16532 *585 (Text
     16634*584 (Text
    1653316635uid 15041,0
    1653416636va (VaSet
     
    1657516677)
    1657616678)
    16577 *586 (MWC
     16679*585 (MWC
    1657816680uid 15058,0
    1657916681optionalChildren [
    16580 *587 (CptPort
     16682*586 (CptPort
    1658116683uid 15045,0
    1658216684optionalChildren [
    16583 *588 (Line
     16685*587 (Line
    1658416686uid 15049,0
    1658516687layer 5
     
    1664316745)
    1664416746)
    16645 *589 (CptPort
     16747*588 (CptPort
    1664616748uid 15050,0
    1664716749optionalChildren [
    16648 *590 (Line
     16750*589 (Line
    1664916751uid 15054,0
    1665016752layer 5
     
    1665916761]
    1666016762)
    16661 *591 (Circle
     16763*590 (Circle
    1666216764uid 15055,0
    1666316765va (VaSet
     
    1672116823)
    1672216824)
    16723 *592 (CommentGraphic
     16825*591 (CommentGraphic
    1672416826uid 15056,0
    1672516827shape (CustomPolygon
     
    1676316865stg "VerticalLayoutStrategy"
    1676416866textVec [
    16765 *593 (Text
     16867*592 (Text
    1676616868uid 15061,0
    1676716869va (VaSet
     
    1677316875blo "155350,77900"
    1677416876)
    16775 *594 (Text
     16877*593 (Text
    1677616878uid 15062,0
    1677716879va (VaSet
     
    1678216884blo "155350,78900"
    1678316885)
    16784 *595 (Text
     16886*594 (Text
    1678516887uid 15063,0
    1678616888va (VaSet
     
    1682716929)
    1682816930)
    16829 *596 (Net
     16931*595 (Net
    1683016932uid 15077,0
    1683116933decl (Decl
     
    1684416946)
    1684516947xt "-172000,63600,-115000,64400"
    16846 st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off"
    16847 )
    16848 )
    16849 *597 (Net
     16948st "SIGNAL denable_prim           : std_logic                                    := '0' -- default domino wave off
     16949"
     16950)
     16951)
     16952*596 (Net
    1685016953uid 15079,0
    1685116954decl (Decl
     
    1686416967)
    1686516968xt "-172000,64400,-115000,65200"
    16866 st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off"
    16867 )
    16868 )
    16869 *598 (Net
     16969st "SIGNAL din1                   : std_logic                                    := '0' -- default domino wave off
     16970"
     16971)
     16972)
     16973*597 (Net
    1687016974uid 15126,0
    1687116975decl (Decl
     
    1688416988)
    1688516989xt "-172000,62800,-115000,63600"
    16886 st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off"
     16990st "SIGNAL denable_inhibit        : std_logic                                    := '0' -- default domino wave off
     16991"
     16992)
     16993)
     16994*598 (Net
     16995uid 15492,0
     16996decl (Decl
     16997n "trigger_out"
     16998t "std_logic"
     16999o 123
     17000suid 301,0
     17001i "'0'"
     17002)
     17003declText (MLText
     17004uid 15493,0
     17005va (VaSet
     17006font "Courier New,8,0"
     17007)
     17008xt "-172000,99600,-128500,100400"
     17009st "SIGNAL trigger_out            : std_logic                                    := '0'
     17010"
    1688717011)
    1688817012)
     
    1747917603lineWidth 2
    1748017604)
    17481 xt "-40250,68000,-21750,71000"
    17482 pts [
    17483 "-40250,68000"
    17484 "-36000,68000"
    17485 "-36000,71000"
    17486 "-21750,71000"
     17605xt "-40250,69000,-21750,70000"
     17606pts [
     17607"-40250,69000"
     17608"-36000,69000"
     17609"-36000,70000"
     17610"-21750,70000"
    1748717611]
    1748817612)
     
    1751817642lineWidth 2
    1751917643)
    17520 xt "750,66000,31250,73000"
    17521 pts [
    17522 "31250,73000"
    17523 "27000,73000"
    17524 "27000,66000"
    17525 "750,66000"
     17644xt "750,71000,27250,71000"
     17645pts [
     17646"27250,71000"
     17647"750,71000"
    1752617648]
    1752717649)
     
    1754217664va (VaSet
    1754317665)
    17544 xt "2000,65000,18700,66000"
     17666xt "1000,70000,17700,71000"
    1754517667st "ram_start_addr : (RAMADDRWIDTH64b-1:0)"
    17546 blo "2000,65800"
     17668blo "1000,70800"
    1754717669tm "WireNameMgr"
    1754817670)
     
    1755717679vasetType 3
    1755817680)
    17559 xt "63750,70000,87250,71000"
    17560 pts [
    17561 "63750,71000"
    17562 "78000,71000"
    17563 "78000,70000"
    17564 "87250,70000"
     17681xt "59750,71000,87250,71000"
     17682pts [
     17683"59750,71000"
     17684"87250,71000"
    1756517685]
    1756617686)
     
    1758017700va (VaSet
    1758117701)
    17582 xt "64000,70000,67400,71000"
     17702xt "60000,70000,63400,71000"
    1758317703st "wiz_busy"
    17584 blo "64000,70800"
     17704blo "60000,70800"
    1758517705tm "WireNameMgr"
    1758617706)
     
    1759517715vasetType 3
    1759617716)
    17597 xt "63750,71000,87250,72000"
    17598 pts [
    17599 "63750,72000"
    17600 "84000,72000"
    17601 "84000,71000"
    17602 "87250,71000"
     17717xt "59750,72000,87250,72000"
     17718pts [
     17719"59750,72000"
     17720"87250,72000"
    1760317721]
    1760417722)
     
    1761817736va (VaSet
    1761917737)
    17620 xt "64000,71000,69100,72000"
     17738xt "60000,71000,65100,72000"
    1762117739st "wiz_write_ea"
    17622 blo "64000,71800"
     17740blo "60000,71800"
    1762317741tm "WireNameMgr"
    1762417742)
     
    1763417752lineWidth 2
    1763517753)
    17636 xt "63750,72000,87250,79000"
    17637 pts [
    17638 "63750,73000"
    17639 "67000,73000"
    17640 "67000,79000"
    17641 "85000,79000"
    17642 "85000,72000"
    17643 "87250,72000"
     17754xt "59750,73000,87250,73000"
     17755pts [
     17756"59750,73000"
     17757"87250,73000"
    1764417758]
    1764517759)
     
    1766017774va (VaSet
    1766117775)
    17662 xt "64000,72000,73400,73000"
     17776xt "60000,72000,69400,73000"
    1766317777st "wiz_write_length : (16:0)"
    17664 blo "64000,72800"
     17778blo "60000,72800"
    1766517779tm "WireNameMgr"
    1766617780)
     
    1767617790lineWidth 2
    1767717791)
    17678 xt "63750,73000,87250,74000"
    17679 pts [
    17680 "63750,74000"
    17681 "84000,74000"
    17682 "84000,73000"
    17683 "87250,73000"
     17792xt "59750,74000,87250,74000"
     17793pts [
     17794"59750,74000"
     17795"87250,74000"
    1768417796]
    1768517797)
     
    1770017812va (VaSet
    1770117813)
    17702 xt "64000,73000,82800,74000"
     17814xt "60000,73000,78800,74000"
    1770317815st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
    17704 blo "64000,73800"
     17816blo "60000,73800"
    1770517817tm "WireNameMgr"
    1770617818)
     
    1771617828lineWidth 2
    1771717829)
    17718 xt "63750,74000,87250,80000"
    17719 pts [
    17720 "63750,75000"
    17721 "66000,75000"
    17722 "66000,80000"
    17723 "86000,80000"
    17724 "86000,74000"
    17725 "87250,74000"
     17830xt "59750,75000,87250,75000"
     17831pts [
     17832"59750,75000"
     17833"87250,75000"
    1772617834]
    1772717835)
     
    1774217850va (VaSet
    1774317851)
    17744 xt "64000,74000,75800,75000"
     17852xt "60000,74000,71800,75000"
    1774517853st "wiz_number_of_channels : (3:0)"
    17746 blo "64000,74800"
     17854blo "60000,74800"
    1774717855tm "WireNameMgr"
    1774817856)
     
    1775717865vasetType 3
    1775817866)
    17759 xt "63750,75000,87250,76000"
    17760 pts [
    17761 "63750,76000"
    17762 "84000,76000"
    17763 "84000,75000"
    17764 "87250,75000"
     17867xt "59750,76000,87250,76000"
     17868pts [
     17869"59750,76000"
     17870"87250,76000"
    1776517871]
    1776617872)
     
    1778017886va (VaSet
    1778117887)
    17782 xt "64000,75000,69500,76000"
     17888xt "60000,75000,65500,76000"
    1778317889st "wiz_write_end"
    17784 blo "64000,75800"
     17890blo "60000,75800"
    1778517891tm "WireNameMgr"
    1778617892)
     
    1779517901vasetType 3
    1779617902)
    17797 xt "63750,76000,87250,77000"
    17798 pts [
    17799 "63750,77000"
    17800 "71000,77000"
    17801 "71000,76000"
    17802 "87250,76000"
     17903xt "59750,77000,87250,77000"
     17904pts [
     17905"59750,77000"
     17906"87250,77000"
    1780317907]
    1780417908)
     
    1781817922va (VaSet
    1781917923)
    17820 xt "64000,76000,70600,77000"
     17924xt "60000,76000,66600,77000"
    1782117925st "wiz_write_header"
    17822 blo "64000,76800"
     17926blo "60000,76800"
    1782317927tm "WireNameMgr"
    1782417928)
     
    1783317937vasetType 3
    1783417938)
    17835 xt "750,67000,31250,74000"
    17836 pts [
    17837 "750,67000"
    17838 "26000,67000"
    17839 "26000,74000"
    17840 "31250,74000"
     17939xt "750,72000,27250,72000"
     17940pts [
     17941"750,72000"
     17942"27250,72000"
    1784117943]
    1784217944)
     
    1785617958va (VaSet
    1785717959)
    17858 xt "2000,66000,7300,67000"
     17960xt "1000,71000,6300,72000"
    1785917961st "ram_write_ea"
    17860 blo "2000,66800"
     17962blo "1000,71800"
    1786117963tm "WireNameMgr"
    1786217964)
     
    1787117973vasetType 3
    1787217974)
    17873 xt "750,68000,31250,75000"
    17874 pts [
    17875 "750,68000"
    17876 "25000,68000"
    17877 "25000,75000"
    17878 "31250,75000"
     17975xt "750,73000,27250,73000"
     17976pts [
     17977"750,73000"
     17978"27250,73000"
    1787917979]
    1788017980)
     
    1789417994va (VaSet
    1789517995)
    17896 xt "2000,67000,8300,68000"
     17996xt "1000,72000,7300,73000"
    1789717997st "ram_write_ready"
    17898 blo "2000,67800"
     17998blo "1000,72800"
    1789917999tm "WireNameMgr"
    1790018000)
     
    1790918009vasetType 3
    1791018010)
    17911 xt "750,73000,31250,78000"
    17912 pts [
    17913 "750,73000"
    17914 "23000,73000"
    17915 "23000,78000"
    17916 "31250,78000"
     18011xt "750,76000,27250,76000"
     18012pts [
     18013"750,76000"
     18014"27250,76000"
    1791718015]
    1791818016)
     
    1793318031va (VaSet
    1793418032)
    17935 xt "1000,72000,5800,73000"
     18033xt "1000,75000,5800,76000"
    1793618034st "config_start"
    17937 blo "1000,72800"
     18035blo "1000,75800"
    1793818036tm "WireNameMgr"
    1793918037)
     
    1794818046vasetType 3
    1794918047)
    17950 xt "750,75000,31250,80000"
    17951 pts [
    17952 "750,75000"
    17953 "21000,75000"
    17954 "21000,80000"
    17955 "31250,80000"
     18048xt "750,78000,27250,78000"
     18049pts [
     18050"750,78000"
     18051"27250,78000"
    1795618052]
    1795718053)
     
    1797118067va (VaSet
    1797218068)
    17973 xt "1000,74000,6100,75000"
     18069xt "1000,77000,6100,78000"
    1797418070st "config_ready"
    17975 blo "1000,74800"
     18071blo "1000,77800"
    1797618072tm "WireNameMgr"
    1797718073)
     
    1798618082vasetType 3
    1798718083)
    17988 xt "750,77000,31250,81000"
    17989 pts [
    17990 "750,77000"
    17991 "20000,77000"
    17992 "20000,81000"
    17993 "31250,81000"
     18084xt "750,79000,27250,79000"
     18085pts [
     18086"750,79000"
     18087"27250,79000"
    1799418088]
    1799518089)
     
    1800918103va (VaSet
    1801018104)
    18011 xt "1000,76000,4000,77000"
     18105xt "1000,78000,4000,79000"
    1801218106st "roi_max"
    18013 blo "1000,76800"
     18107blo "1000,78800"
    1801418108tm "WireNameMgr"
    1801518109)
     
    1802518119lineWidth 2
    1802618120)
    18027 xt "750,78000,31250,82000"
    18028 pts [
    18029 "750,78000"
    18030 "19000,78000"
    18031 "19000,82000"
    18032 "31250,82000"
     18121xt "750,80000,27250,80000"
     18122pts [
     18123"750,80000"
     18124"27250,80000"
    1803318125]
    1803418126)
     
    1804918141va (VaSet
    1805018142)
    18051 xt "1000,77000,10100,78000"
     18143xt "1000,79000,10100,80000"
    1805218144st "package_length : (15:0)"
    18053 blo "1000,77800"
     18145blo "1000,79800"
    1805418146tm "WireNameMgr"
    1805518147)
     
    1923819330vasetType 3
    1923919331)
    19240 xt "18000,88000,31250,88000"
     19332xt "18000,86000,27250,88000"
    1924119333pts [
    1924219334"18000,88000"
    19243 "31250,88000"
     19335"24000,88000"
     19336"24000,86000"
     19337"27250,86000"
    1924419338]
    1924519339)
     
    1925919353va (VaSet
    1926019354)
    19261 xt "28000,87000,31400,88000"
     19355xt "24000,85000,27400,86000"
    1926219356st "roi_array"
    19263 blo "28000,87800"
     19357blo "24000,85800"
    1926419358tm "WireNameMgr"
    1926519359)
     
    1953119625optionalChildren [
    1953219626&651
    19533 *672 (BdJunction
    19534 uid 6086,0
    19535 ps "OnConnectorStrategy"
    19536 shape (Circle
    19537 uid 6087,0
    19538 va (VaSet
    19539 vasetType 1
    19540 )
    19541 xt "27600,46600,28400,47400"
    19542 radius 400
    19543 )
    19544 )
    1954519627]
    1954619628shape (OrthoPolyLine
     
    1958419666on &188
    1958519667)
    19586 *673 (Wire
     19668*672 (Wire
    1958719669uid 5626,0
    1958819670shape (OrthoPolyLine
     
    1962019702on &266
    1962119703)
    19622 *674 (Wire
     19704*673 (Wire
    1962319705uid 5634,0
    1962419706shape (OrthoPolyLine
     
    1965819740on &265
    1965919741)
    19660 *675 (Wire
     19742*674 (Wire
    1966119743uid 5646,0
    1966219744shape (OrthoPolyLine
     
    1969419776on &185
    1969519777)
    19696 *676 (Wire
     19778*675 (Wire
    1969719779uid 5745,0
    1969819780shape (OrthoPolyLine
     
    1973219814on &276
    1973319815)
    19734 *677 (Wire
     19816*676 (Wire
    1973519817uid 5805,0
    1973619818shape (OrthoPolyLine
     
    1976619848on &187
    1976719849)
    19768 *678 (Wire
     19850*677 (Wire
    1976919851uid 5813,0
    1977019852shape (OrthoPolyLine
     
    1980419886on &293
    1980519887)
    19806 *679 (Wire
     19888*678 (Wire
    1980719889uid 5821,0
    1980819890shape (OrthoPolyLine
     
    1984219924on &294
    1984319925)
    19844 *680 (Wire
     19926*679 (Wire
    1984519927uid 5829,0
    1984619928shape (OrthoPolyLine
     
    1988019962on &295
    1988119963)
    19882 *681 (Wire
     19964*680 (Wire
    1988319965uid 5837,0
    1988419966shape (OrthoPolyLine
     
    1992020002on &296
    1992120003)
    19922 *682 (Wire
     20004*681 (Wire
    1992320005uid 5950,0
    1992420006shape (OrthoPolyLine
     
    1995820040on &301
    1995920041)
    19960 *683 (Wire
     20042*682 (Wire
    1996120043uid 5962,0
    1996220044shape (OrthoPolyLine
     
    1999620078on &302
    1999720079)
    19998 *684 (Wire
     20080*683 (Wire
    1999920081uid 6002,0
    2000020082shape (OrthoPolyLine
     
    2003420116on &304
    2003520117)
    20036 *685 (Wire
     20118*684 (Wire
    2003720119uid 6008,0
    2003820120shape (OrthoPolyLine
     
    2007220154on &303
    2007320155)
    20074 *686 (Wire
     20156*685 (Wire
    2007520157uid 6018,0
    2007620158shape (OrthoPolyLine
     
    2007920161vasetType 3
    2008020162)
    20081 xt "750,74000,31250,79000"
    20082 pts [
    20083 "750,74000"
    20084 "22000,74000"
    20085 "22000,79000"
    20086 "31250,79000"
     20163xt "750,77000,27250,77000"
     20164pts [
     20165"750,77000"
     20166"27250,77000"
    2008720167]
    2008820168)
     
    2010220182va (VaSet
    2010320183)
    20104 xt "1000,73000,8200,74000"
     20184xt "1000,76000,8200,77000"
    2010520185st "config_started_mm"
    20106 blo "1000,73800"
     20186blo "1000,76800"
    2010720187tm "WireNameMgr"
    2010820188)
     
    2011020190on &305
    2011120191)
    20112 *687 (Wire
     20192*686 (Wire
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     20227*687 (Wire
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    20198 "28000,47000"
    20199 ]
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    20204 eat 32
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     20304*689 (Wire
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     20312pts [
     20313"-61000,68000"
     20314"-52750,68000"
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    2027520316)
     
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    2046020499)
     
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     20517blo "60000,77800"
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    2048020519)
     
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     20843*704 (Wire
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     20916*706 (Wire
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    2087920918shape (OrthoPolyLine
     
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     20952*707 (Wire
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     21026*709 (Wire
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     21064*710 (Wire
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    21059 )
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     21097on &498
     21098)
     21099*711 (Wire
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     21135*712 (Wire
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    2109821137shape (OrthoPolyLine
     
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    2113121170)
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     21171*713 (Wire
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    2113421173shape (OrthoPolyLine
     
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    2116721206)
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     21207*714 (Wire
    2116921208uid 10316,0
    2117021209shape (OrthoPolyLine
     
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    2120521244)
    21206 *717 (Wire
     21245*715 (Wire
    2120721246uid 10322,0
    2120821247shape (OrthoPolyLine
     
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    2124321282)
    21244 *718 (Wire
     21283*716 (Wire
    2124521284uid 10431,0
    2124621285shape (OrthoPolyLine
     
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    2128021319)
    21281 *719 (Wire
    21282 uid 10439,0
    21283 optionalChildren [
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    21285 uid 12639,0
    21286 ps "OnConnectorStrategy"
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    21295 )
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    21305 "-54000,72000"
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    21307 "-52750,68000"
    21308 ]
    21309 )
    21310 start &30
    21311 end &125
    21312 sat 32
    21313 eat 32
    21314 st 0
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    21320 stg "STSignalDisplayStrategy"
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    21322 uid 10442,0
    21323 va (VaSet
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    21327 blo "-25750,71800"
    21328 tm "WireNameMgr"
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    21330 )
    21331 on &431
    21332 )
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     21320*717 (Wire
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    21341 pts [
    21342 "31250,76000"
    21343 "24000,76000"
    21344 "24000,69000"
    21345 "750,69000"
     21327xt "750,74000,27250,74000"
     21328pts [
     21329"27250,74000"
     21330"750,74000"
    2134621331]
    2134721332)
     
    2136221347va (VaSet
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     21349xt "1000,73000,8800,74000"
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     21351blo "1000,73800"
    2136721352tm "WireNameMgr"
    2136821353)
    2136921354)
    21370 on &432
    21371 )
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     21355on &431
     21356)
     21357*718 (Wire
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    2137421359shape (OrthoPolyLine
     
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    21405 on &433
    21406 )
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     21390on &432
     21391)
     21392*719 (Wire
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    21441 )
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     21425on &433
     21426)
     21427*720 (Wire
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    2145321438]
    2145421439)
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     21440end &446
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    2145721442eat 32
     
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    2147421459)
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    21476 )
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     21460on &433
     21461)
     21462*721 (Wire
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    2150921494)
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    21511 )
    21512 *726 (Wire
     21495on &432
     21496)
     21497*722 (Wire
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    2152521510)
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     21511end &441
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    2154721532)
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     21533*723 (Wire
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    2156021545)
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     21546end &445
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    2156321548eat 32
     
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    2158021565)
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    21582 )
    21583 *728 (Wire
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     21567)
     21568*724 (Wire
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    2159521580)
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     21581start &442
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    2159821583sat 32
    2159921584eat 32
     
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    2161821603)
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    21620 )
    21621 *729 (Wire
     21604on &434
     21605)
     21606*725 (Wire
    2162221607uid 10737,0
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    2163321618)
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     21619start &443
     21620end &437
    2163621621sat 32
    2163721622eat 32
     
    2165521640)
    2165621641)
    21657 on &437
    21658 )
    21659 *730 (Wire
     21642on &436
     21643)
     21644*726 (Wire
    2166021645uid 10751,0
    2166121646shape (OrthoPolyLine
     
    2167021655]
    2167121656)
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    21673 end &440
     21657start &444
     21658end &439
    2167421659sat 32
    2167521660eat 32
     
    2169321678)
    2169421679)
    21695 on &439
    21696 )
    21697 *731 (Wire
     21680on &438
     21681)
     21682*727 (Wire
    2169821683uid 11405,0
    2169921684shape (OrthoPolyLine
     
    2172921714)
    2173021715)
    21731 on &453
    21732 )
    21733 *732 (Wire
     21716on &452
     21717)
     21718*728 (Wire
    2173421719uid 11858,0
    2173521720shape (OrthoPolyLine
     
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    2176521750)
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    21767 )
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     21751on &453
     21752)
     21753*729 (Wire
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    2178021765)
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     21766end &460
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    2180121786)
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    21803 )
    21804 *734 (Wire
     21787on &453
     21788)
     21789*730 (Wire
    2180521790uid 12306,0
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     21803end &458
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    2183921824)
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    21841 )
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    21847 vasetType 3
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    21850 pts [
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    21852 "-55250,72000"
    21853 ]
    21854 )
    21855 start &720
    21856 end &476
    21857 sat 32
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    21867 f (Text
    21868 uid 12638,0
    21869 va (VaSet
    21870 )
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    21872 st "trigger_out"
    21873 blo "-54000,71800"
    21874 tm "WireNameMgr"
    21875 )
    21876 )
    21877 on &431
    21878 )
    21879 *736 (Wire
     21825on &472
     21826)
     21827*731 (Wire
    2188021828uid 12643,0
    2188121829shape (OrthoPolyLine
     
    2189221840]
    2189321841)
    21894 start &456
    21895 end &475
     21842start &455
     21843end &474
    2189621844sat 32
    2189721845eat 32
     
    2191521863)
    2191621864)
    21917 on &484
    21918 )
    21919 *737 (Wire
     21865on &483
     21866)
     21867*732 (Wire
    2192021868uid 12649,0
    2192121869shape (OrthoPolyLine
     
    2192721875pts [
    2192821876"-21750,74000"
    21929 "-38000,74000"
    2193021877"-55250,74000"
    2193121878]
    2193221879)
    2193321880start &66
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     21881end &477
    2193521882sat 32
    2193621883eat 32
     
    2195221899)
    2195321900)
    21954 on &485
    21955 )
    21956 *738 (Wire
     21901on &484
     21902)
     21903*733 (Wire
    2195721904uid 12655,0
    2195821905shape (OrthoPolyLine
     
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     21918end &478
    2197221919sat 32
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    2199021937)
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    21992 )
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     21938on &485
     21939)
     21940*734 (Wire
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    2200721954]
    2200821955)
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     21956end &479
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    2201121958eat 32
     
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    2203021977)
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     21978*735 (Wire
    2203221979uid 12707,0
    2203321980shape (OrthoPolyLine
     
    2204221989]
    2204321990)
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    22045 end &488
     21991start &448
     21992end &487
    2204621993sat 32
    2204721994eat 32
     
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    2206622013)
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    22068 )
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     22014on &486
     22015)
     22016*736 (Wire
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    22078 "69000,62000"
    22079 "63750,62000"
    22080 ]
    22081 )
    22082 end &490
     22023xt "72750,62000,78000,62000"
     22024pts [
     22025"78000,62000"
     22026"72750,62000"
     22027]
     22028)
     22029end &489
    2208322030sat 16
    2208422031eat 32
     
    2209422041va (VaSet
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     22043xt "74000,61000,77100,62000"
    2209722044st "CLK_25"
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     22045blo "74000,61800"
    2209922046tm "WireNameMgr"
    2210022047)
     
    2210222049on &188
    2210322050)
    22104 *742 (Wire
     22051*737 (Wire
    2210522052uid 13159,0
    2210622053shape (OrthoPolyLine
     
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    2211022057)
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     22058xt "72750,63000,87250,67000"
    2211222059pts [
    2211322060"87250,67000"
    22114 "79000,67000"
    22115 "79000,63000"
    22116 "63750,63000"
     22061"77000,67000"
     22062"77000,63000"
     22063"72750,63000"
    2211722064]
    2211822065)
    2211922066start &114
    22120 end &491
     22067end &490
    2212122068sat 32
    2212222069eat 32
     
    2213822085)
    2213922086)
    22140 on &497
    22141 )
    22142 *743 (Wire
     22087on &496
     22088)
     22089*738 (Wire
    2214322090uid 13165,0
    2214422091shape (OrthoPolyLine
     
    2214822095lineWidth 2
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    22150 xt "63750,64000,87250,68000"
     22097xt "72750,64000,87250,68000"
    2215122098pts [
    2215222099"87250,68000"
    22153 "78000,68000"
    22154 "78000,64000"
    22155 "63750,64000"
     22100"76000,68000"
     22101"76000,64000"
     22102"72750,64000"
    2215622103]
    2215722104)
    2215822105start &115
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     22106end &491
    2216022107sat 32
    2216122108eat 32
     
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    2217922126)
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    22181 )
    22182 *744 (Wire
     22127on &497
     22128)
     22129*739 (Wire
    2218322130uid 13210,0
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    2218722134vasetType 3
    2218822135)
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    22190 pts [
    22191 "50250,62000"
    22192 "42000,62000"
    22193 ]
    22194 )
    22195 start &493
    22196 end &502
     22136xt "54000,62000,59250,62000"
     22137pts [
     22138"59250,62000"
     22139"54000,62000"
     22140]
     22141)
     22142start &492
     22143end &501
    2219722144sat 32
    2219822145eat 32
     
    2220822155va (VaSet
    2220922156)
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     22157xt "53250,61000,56450,62000"
    2221122158st "trigger1"
    22212 blo "46250,61800"
     22159blo "53250,61800"
    2221322160tm "WireNameMgr"
    2221422161)
    2221522162)
    22216 on &500
    22217 )
    22218 *745 (Wire
     22163on &499
     22164)
     22165*740 (Wire
    2221922166uid 13216,0
    2222022167shape (OrthoPolyLine
     
    2222322170vasetType 3
    2222422171)
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    22227 "45000,60000"
    22228 "42000,60000"
    22229 ]
    22230 )
    22231 end &507
     22172xt "54000,60000,59000,60000"
     22173pts [
     22174"59000,60000"
     22175"54000,60000"
     22176]
     22177)
     22178end &506
    2223222179sat 16
    2223322180eat 32
     
    2224322190uid 13221,0
    2224422191va (VaSet
    22245 isHidden 1
    22246 )
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     22192)
     22193xt "54000,59000,58800,60000"
    2224822194st "s_trigger_0"
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     22195blo "54000,59800"
    2225022196tm "WireNameMgr"
    2225122197)
    2225222198)
    22253 on &499
    22254 )
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     22199on &498
     22200)
     22201*741 (Wire
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    22264 "36000,61000"
    22265 "33000,61000"
    22266 ]
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     22210"48000,61000"
     22211"45000,61000"
     22212]
     22213)
     22214start &503
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    2227022216eat 16
     
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    2228122227va (VaSet
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     22228)
     22229xt "45000,60000,48600,61000"
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     22231blo "45000,60800"
    2228722232tm "WireNameMgr"
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    2229122236)
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     22237*742 (Wire
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     22275)
     22276*743 (Wire
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     22313*744 (Wire
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     22350*745 (Wire
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    2241722362)
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     22363start &525
     22364end &531
    2242022365sat 32
    2242122366eat 32
     
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    22441 )
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     22386)
     22387*746 (Wire
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    2245522400)
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     22401start &527
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    2245822403eat 16
     
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    2247722422)
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    22479 )
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     22423on &528
     22424)
     22425*747 (Wire
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     22438end &530
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    2249522440eat 32
     
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     22460*748 (Wire
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     22473start &533
     22474end &539
    2253022475sat 32
    2253122476eat 32
     
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    2255022495)
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    22552 )
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     22496on &538
     22497)
     22498*749 (Wire
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    2256522510)
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    22567 end &542
     22511start &534
     22512end &541
    2256822513sat 32
    2256922514eat 32
     
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    2258822533)
    22589 on &541
    22590 )
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     22534on &540
     22535)
     22536*750 (Wire
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    2259322538shape (OrthoPolyLine
     
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    2260422549)
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    22606 end &544
     22550start &532
     22551end &543
    2260722552sat 32
    2260822553eat 32
     
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    2262822573)
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    22630 )
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     22574on &542
     22575)
     22576*751 (Wire
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    2264422589start &101
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     22590end &548
    2264622591sat 32
    2264722592eat 32
     
    2266322608)
    2266422609)
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    22666 )
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     22610on &595
     22611)
     22612*752 (Wire
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    2267922624)
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    22681 end &589
     22625start &550
     22626end &588
    2268222627sat 32
    2268322628eat 32
     
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    2270222647)
    22703 on &597
    22704 )
    22705 *758 (Wire
     22648on &596
     22649)
     22650*753 (Wire
    2270622651uid 15122,0
    2270722652shape (OrthoPolyLine
     
    2271722662]
    2271822663)
    22719 start &587
    22720 end &564
     22664start &586
     22665end &563
    2272122666sat 32
    2272222667eat 32
     
    2273922684)
    2274022685)
    22741 on &598
    22742 )
    22743 *759 (Wire
     22686on &597
     22687)
     22688*754 (Wire
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    2274522690shape (OrthoPolyLine
     
    2275422699]
    2275522700)
    22756 end &579
     22701end &578
    2275722702es 0
    2275822703sat 16
     
    2277722722)
    2277822723)
    22779 on &541
    22780 )
    22781 *760 (Wire
     22724on &540
     22725)
     22726*755 (Wire
    2278222727uid 15138,0
    2278322728shape (OrthoPolyLine
     
    2279222737]
    2279322738)
    22794 end &581
     22739end &580
    2279522740es 0
    2279622741sat 16
     
    2281522760)
    2281622761)
    22817 on &539
     22762on &538
     22763)
     22764*756 (Wire
     22765uid 15379,0
     22766shape (OrthoPolyLine
     22767uid 15380,0
     22768va (VaSet
     22769vasetType 3
     22770)
     22771xt "29000,64000,29000,67250"
     22772pts [
     22773"29000,64000"
     22774"29000,67250"
     22775]
     22776)
     22777end &134
     22778sat 16
     22779eat 32
     22780st 0
     22781sf 1
     22782si 0
     22783tg (WTG
     22784uid 15383,0
     22785ps "ConnStartEndStrategy"
     22786stg "STSignalDisplayStrategy"
     22787f (Text
     22788uid 15384,0
     22789va (VaSet
     22790)
     22791xt "29000,64000,32100,65000"
     22792st "CLK_25"
     22793blo "29000,64800"
     22794tm "WireNameMgr"
     22795)
     22796)
     22797on &188
     22798)
     22799*757 (Wire
     22800uid 15494,0
     22801optionalChildren [
     22802*758 (BdJunction
     22803uid 15502,0
     22804ps "OnConnectorStrategy"
     22805shape (Circle
     22806uid 15503,0
     22807va (VaSet
     22808vasetType 1
     22809)
     22810xt "-54400,71600,-53600,72400"
     22811radius 400
     22812)
     22813)
     22814]
     22815shape (OrthoPolyLine
     22816uid 15495,0
     22817va (VaSet
     22818vasetType 3
     22819)
     22820xt "-55250,72000,-21750,72000"
     22821pts [
     22822"-55250,72000"
     22823"-21750,72000"
     22824]
     22825)
     22826start &475
     22827end &30
     22828sat 32
     22829eat 32
     22830st 0
     22831sf 1
     22832si 0
     22833tg (WTG
     22834uid 15496,0
     22835ps "ConnStartEndStrategy"
     22836stg "STSignalDisplayStrategy"
     22837f (Text
     22838uid 15497,0
     22839va (VaSet
     22840)
     22841xt "-53250,71000,-48650,72000"
     22842st "trigger_out"
     22843blo "-53250,71800"
     22844tm "WireNameMgr"
     22845)
     22846)
     22847on &598
     22848)
     22849*759 (Wire
     22850uid 15498,0
     22851shape (OrthoPolyLine
     22852uid 15499,0
     22853va (VaSet
     22854vasetType 3
     22855)
     22856xt "-54000,69000,-52750,72000"
     22857pts [
     22858"-52750,69000"
     22859"-54000,69000"
     22860"-54000,72000"
     22861]
     22862)
     22863start &125
     22864end &758
     22865sat 32
     22866eat 32
     22867stc 0
     22868st 0
     22869sf 1
     22870si 0
     22871tg (WTG
     22872uid 15500,0
     22873ps "ConnStartEndStrategy"
     22874stg "STSignalDisplayStrategy"
     22875f (Text
     22876uid 15501,0
     22877va (VaSet
     22878)
     22879xt "-58000,69000,-53400,70000"
     22880st "trigger_out"
     22881blo "-58000,69800"
     22882tm "WireNameMgr"
     22883)
     22884)
     22885on &598
    2281822886)
    2281922887]
     
    2282922897color "26368,26368,26368"
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     22899packageList *760 (PackageList
    2283222900uid 41,0
    2283322901stg "VerticalLayoutStrategy"
    2283422902textVec [
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     22903*761 (Text
    2283622904uid 42,0
    2283722905va (VaSet
     
    2284222910blo "-163000,-15200"
    2284322911)
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     22912*762 (MLText
    2284522913uid 43,0
    2284622914va (VaSet
     
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    2286822936textVec [
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     22937*763 (Text
    2287022938uid 45,0
    2287122939va (VaSet
     
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    2287822946)
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     22947*764 (Text
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    2288822956)
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     22957*765 (MLText
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    2289122959va (VaSet
     
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     22967*766 (Text
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    2290822976)
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     22977*767 (MLText
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    2291122979va (VaSet
     
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     22985*768 (Text
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    2291922987va (VaSet
     
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    2296723035shape (Rectangle
     
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     23095*770 (Text
    2302823096va (VaSet
    2302923097font "Arial,8,1"
     
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     23104*771 (Text
    2303723105va (VaSet
    2303823106font "Arial,8,1"
     
    2304323111tm "BlkNameMgr"
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     23113*772 (Text
    2304623114va (VaSet
    2304723115font "Arial,8,1"
     
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    2309523163textVec [
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     23164*773 (Text
    2309723165va (VaSet
    2309823166font "Arial,8,1"
     
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     23180*775 (Text
    2311323181va (VaSet
    2311423182font "Arial,8,1"
     
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    2316023228textVec [
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     23229*776 (Text
    2316223230va (VaSet
    2316323231font "Arial,8,1"
     
    2316823236tm "BdLibraryNameMgr"
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     23238*777 (Text
    2317123239va (VaSet
    2317223240font "Arial,8,1"
     
    2317723245tm "CptNameMgr"
    2317823246)
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     23247*778 (Text
    2318023248va (VaSet
    2318123249font "Arial,8,1"
     
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    2323223300textVec [
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     23301*779 (Text
    2323423302va (VaSet
    2323523303font "Arial,8,1"
     
    2323923307blo "500,4300"
    2324023308)
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     23309*780 (Text
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    2324323311font "Arial,8,1"
     
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    2324823316)
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     23317*781 (Text
    2325023318va (VaSet
    2325123319font "Arial,8,1"
     
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    2329323361textVec [
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     23362*782 (Text
    2329523363va (VaSet
    2329623364font "Arial,8,1"
     
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    2330123369)
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     23370*783 (Text
    2330323371va (VaSet
    2330423372font "Arial,8,1"
     
    2330823376blo "50,5300"
    2330923377)
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     23378*784 (Text
    2331123379va (VaSet
    2331223380font "Arial,8,1"
     
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    2335023418textVec [
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     23419*785 (Text
    2335223420va (VaSet
    2335323421font "Arial,8,1"
     
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    2335923427)
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     23428*786 (Text
    2336123429va (VaSet
    2336223430font "Arial,8,1"
     
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    2376223830textVec [
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     23831*787 (Text
    2376423832va (VaSet
    2376523833font "Arial,8,1"
     
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    2377023838)
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     23839*788 (MLText
    2377223840va (VaSet
    2377323841)
     
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     23891*789 (Text
    2382423892va (VaSet
    2382523893font "Arial,8,1"
     
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    2383023898)
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     23899*790 (MLText
    2383223900va (VaSet
    2383323901)
     
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    2397024038ldm (LogicalDM
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    23982 )
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     24045*792 (RefLabelRowHdr
     24046)
     24047*793 (TitleRowHdr
     24048)
     24049*794 (FilterRowHdr
     24050)
     24051*795 (RefLabelColHdr
    2398424052tm "RefLabelColHdrMgr"
    2398524053)
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     24054*796 (RowExpandColHdr
    2398724055tm "RowExpandColHdrMgr"
    2398824056)
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     24057*797 (GroupColHdr
    2399024058tm "GroupColHdrMgr"
    2399124059)
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     24060*798 (NameColHdr
    2399324061tm "BlockDiagramNameColHdrMgr"
    2399424062)
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     24063*799 (ModeColHdr
    2399624064tm "BlockDiagramModeColHdrMgr"
    2399724065)
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     24066*800 (TypeColHdr
    2399924067tm "BlockDiagramTypeColHdrMgr"
    2400024068)
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     24069*801 (BoundsColHdr
    2400224070tm "BlockDiagramBoundsColHdrMgr"
    2400324071)
    24004 *803 (InitColHdr
     24072*802 (InitColHdr
    2400524073tm "BlockDiagramInitColHdrMgr"
    2400624074)
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     24075*803 (EolColHdr
    2400824076tm "BlockDiagramEolColHdrMgr"
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    2401224080m 4
     
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     24157*810 (LeafLogPort
    2409024158port (LogicalPort
    2409124159m 1
     
    2410024168uid 536,0
    2410124169)
    24102 *812 (LeafLogPort
     24170*811 (LeafLogPort
    2410324171port (LogicalPort
    2410424172m 2
     
    2411324181uid 538,0
    2411424182)
     24183*812 (LeafLogPort
     24184port (LogicalPort
     24185m 1
     24186decl (Decl
     24187n "wiz_cs"
     24188t "std_logic"
     24189o 44
     24190suid 14,0
     24191i "'1'"
     24192)
     24193)
     24194uid 540,0
     24195)
    2411524196*813 (LeafLogPort
    2411624197port (LogicalPort
    2411724198m 1
    2411824199decl (Decl
    24119 n "wiz_cs"
    24120 t "std_logic"
    24121 o 44
    24122 suid 14,0
     24200n "wiz_wr"
     24201t "std_logic"
     24202o 47
     24203suid 15,0
    2412324204i "'1'"
    2412424205)
    2412524206)
    24126 uid 540,0
     24207uid 542,0
    2412724208)
    2412824209*814 (LeafLogPort
     
    2413024211m 1
    2413124212decl (Decl
    24132 n "wiz_wr"
    24133 t "std_logic"
    24134 o 47
    24135 suid 15,0
    24136 i "'1'"
    24137 )
    24138 )
    24139 uid 542,0
    24140 )
    24141 *815 (LeafLogPort
    24142 port (LogicalPort
    24143 m 1
    24144 decl (Decl
    2414524213n "wiz_rd"
    2414624214t "std_logic"
     
    2415224220uid 546,0
    2415324221)
    24154 *816 (LeafLogPort
     24222*815 (LeafLogPort
    2415524223port (LogicalPort
    2415624224decl (Decl
     
    2416324231uid 548,0
    2416424232)
    24165 *817 (LeafLogPort
     24233*816 (LeafLogPort
    2416624234port (LogicalPort
    2416724235decl (Decl
     
    2417524243uid 1455,0
    2417624244)
    24177 *818 (LeafLogPort
     24245*817 (LeafLogPort
    2417824246port (LogicalPort
    2417924247decl (Decl
     
    2418824256uid 1457,0
    2418924257)
    24190 *819 (LeafLogPort
     24258*818 (LeafLogPort
    2419124259port (LogicalPort
    2419224260decl (Decl
     
    2420024268uid 1694,0
    2420124269)
    24202 *820 (LeafLogPort
     24270*819 (LeafLogPort
    2420324271port (LogicalPort
    2420424272lang 2
     
    2421624284uid 1993,0
    2421724285)
    24218 *821 (LeafLogPort
     24286*820 (LeafLogPort
    2421924287port (LogicalPort
    2422024288m 4
     
    2423124299uid 2305,0
    2423224300)
     24301*821 (LeafLogPort
     24302port (LogicalPort
     24303lang 2
     24304m 4
     24305decl (Decl
     24306n "wiz_busy"
     24307t "std_logic"
     24308o 122
     24309suid 38,0
     24310)
     24311)
     24312uid 2510,0
     24313)
    2423324314*822 (LeafLogPort
    2423424315port (LogicalPort
     
    2423624317m 4
    2423724318decl (Decl
    24238 n "wiz_busy"
    24239 t "std_logic"
    24240 o 122
    24241 suid 38,0
    24242 )
    24243 )
    24244 uid 2510,0
    24245 )
    24246 *823 (LeafLogPort
    24247 port (LogicalPort
    24248 lang 2
    24249 m 4
    24250 decl (Decl
    2425124319n "wiz_write_ea"
    2425224320t "std_logic"
     
    2425824326uid 2512,0
    2425924327)
    24260 *824 (LeafLogPort
     24328*823 (LeafLogPort
    2426124329port (LogicalPort
    2426224330lang 2
     
    2427324341uid 2514,0
    2427424342)
    24275 *825 (LeafLogPort
     24343*824 (LeafLogPort
    2427624344port (LogicalPort
    2427724345lang 2
     
    2428924357uid 2516,0
    2429024358)
    24291 *826 (LeafLogPort
     24359*825 (LeafLogPort
    2429224360port (LogicalPort
    2429324361lang 2
     
    2430424372uid 2518,0
    2430524373)
     24374*826 (LeafLogPort
     24375port (LogicalPort
     24376lang 2
     24377m 4
     24378decl (Decl
     24379n "wiz_write_end"
     24380t "std_logic"
     24381o 126
     24382suid 43,0
     24383i "'0'"
     24384)
     24385)
     24386uid 2520,0
     24387)
    2430624388*827 (LeafLogPort
    2430724389port (LogicalPort
     
    2430924391m 4
    2431024392decl (Decl
    24311 n "wiz_write_end"
    24312 t "std_logic"
    24313 o 126
    24314 suid 43,0
    24315 i "'0'"
    24316 )
    24317 )
    24318 uid 2520,0
    24319 )
    24320 *828 (LeafLogPort
    24321 port (LogicalPort
    24322 lang 2
    24323 m 4
    24324 decl (Decl
    2432524393n "wiz_write_header"
    2432624394t "std_logic"
     
    2433224400uid 2522,0
    2433324401)
     24402*828 (LeafLogPort
     24403port (LogicalPort
     24404m 4
     24405decl (Decl
     24406n "ram_write_ea"
     24407t "std_logic"
     24408o 100
     24409suid 48,0
     24410)
     24411)
     24412uid 2604,0
     24413)
    2433424414*829 (LeafLogPort
    2433524415port (LogicalPort
    2433624416m 4
    2433724417decl (Decl
    24338 n "ram_write_ea"
    24339 t "std_logic"
    24340 o 100
    24341 suid 48,0
    24342 )
    24343 )
    24344 uid 2604,0
     24418n "ram_write_ready"
     24419t "std_logic"
     24420o 101
     24421suid 49,0
     24422i "'0'"
     24423)
     24424)
     24425uid 2606,0
    2434524426)
    2434624427*830 (LeafLogPort
     
    2434824429m 4
    2434924430decl (Decl
    24350 n "ram_write_ready"
    24351 t "std_logic"
    24352 o 101
    24353 suid 49,0
     24431n "config_start"
     24432t "std_logic"
     24433o 67
     24434suid 50,0
    2435424435i "'0'"
    2435524436)
    2435624437)
    24357 uid 2606,0
     24438uid 2608,0
    2435824439)
    2435924440*831 (LeafLogPort
     
    2436124442m 4
    2436224443decl (Decl
    24363 n "config_start"
    24364 t "std_logic"
    24365 o 67
    24366 suid 50,0
    24367 i "'0'"
    24368 )
    24369 )
    24370 uid 2608,0
    24371 )
    24372 *832 (LeafLogPort
    24373 port (LogicalPort
    24374 m 4
    24375 decl (Decl
    2437624444n "config_ready"
    2437724445t "std_logic"
     
    2438224450uid 2610,0
    2438324451)
    24384 *833 (LeafLogPort
     24452*832 (LeafLogPort
    2438524453port (LogicalPort
    2438624454m 4
     
    2439424462uid 2612,0
    2439524463)
    24396 *834 (LeafLogPort
     24464*833 (LeafLogPort
    2439724465port (LogicalPort
    2439824466m 4
     
    2440724475uid 2646,0
    2440824476)
    24409 *835 (LeafLogPort
     24477*834 (LeafLogPort
    2441024478port (LogicalPort
    2441124479m 1
     
    2442024488uid 2812,0
    2442124489)
    24422 *836 (LeafLogPort
     24490*835 (LeafLogPort
    2442324491port (LogicalPort
    2442424492m 4
     
    2443224500uid 2962,0
    2443324501)
     24502*836 (LeafLogPort
     24503port (LogicalPort
     24504m 1
     24505decl (Decl
     24506n "CLK_25_PS"
     24507t "std_logic"
     24508o 15
     24509suid 81,0
     24510)
     24511)
     24512uid 3902,0
     24513)
    2443424514*837 (LeafLogPort
    2443524515port (LogicalPort
    2443624516m 1
    2443724517decl (Decl
    24438 n "CLK_25_PS"
    24439 t "std_logic"
    24440 o 15
    24441 suid 81,0
    24442 )
    24443 )
    24444 uid 3902,0
     24518n "CLK_50"
     24519t "std_logic"
     24520o 16
     24521suid 90,0
     24522)
     24523)
     24524uid 4070,0
    2444524525)
    2444624526*838 (LeafLogPort
    2444724527port (LogicalPort
    24448 m 1
    24449 decl (Decl
    24450 n "CLK_50"
    24451 t "std_logic"
    24452 o 16
    24453 suid 90,0
    24454 )
    24455 )
    24456 uid 4070,0
     24528m 4
     24529decl (Decl
     24530n "CLK_25"
     24531t "std_logic"
     24532o 50
     24533suid 91,0
     24534)
     24535)
     24536uid 4212,0
    2445724537)
    2445824538*839 (LeafLogPort
    2445924539port (LogicalPort
    24460 m 4
    24461 decl (Decl
    24462 n "CLK_25"
    24463 t "std_logic"
    24464 o 50
    24465 suid 91,0
    24466 )
    24467 )
    24468 uid 4212,0
    24469 )
    24470 *840 (LeafLogPort
    24471 port (LogicalPort
    2447224540decl (Decl
    2447324541n "CLK"
     
    2447924547uid 4234,0
    2448024548)
    24481 *841 (LeafLogPort
     24549*840 (LeafLogPort
    2448224550port (LogicalPort
    2448324551decl (Decl
     
    2449124559uid 4262,0
    2449224560)
    24493 *842 (LeafLogPort
     24561*841 (LeafLogPort
    2449424562port (LogicalPort
    2449524563decl (Decl
     
    2450224570uid 4276,0
    2450324571)
    24504 *843 (LeafLogPort
     24572*842 (LeafLogPort
    2450524573port (LogicalPort
    2450624574m 4
     
    2451524583uid 4563,0
    2451624584)
    24517 *844 (LeafLogPort
     24585*843 (LeafLogPort
    2451824586port (LogicalPort
    2451924587m 4
     
    2452724595uid 4565,0
    2452824596)
    24529 *845 (LeafLogPort
     24597*844 (LeafLogPort
    2453024598port (LogicalPort
    2453124599m 4
     
    2454024608uid 4569,0
    2454124609)
    24542 *846 (LeafLogPort
     24610*845 (LeafLogPort
    2454324611port (LogicalPort
    2454424612m 1
     
    2455424622uid 4585,0
    2455524623)
    24556 *847 (LeafLogPort
     24624*846 (LeafLogPort
    2455724625port (LogicalPort
    2455824626m 1
     
    2456724635uid 4587,0
    2456824636)
     24637*847 (LeafLogPort
     24638port (LogicalPort
     24639decl (Decl
     24640n "SROUT_in_0"
     24641t "std_logic"
     24642o 2
     24643suid 112,0
     24644)
     24645)
     24646uid 4733,0
     24647)
    2456924648*848 (LeafLogPort
    2457024649port (LogicalPort
    2457124650decl (Decl
    24572 n "SROUT_in_0"
    24573 t "std_logic"
    24574 o 2
    24575 suid 112,0
    24576 )
    24577 )
    24578 uid 4733,0
     24651n "SROUT_in_1"
     24652t "std_logic"
     24653o 3
     24654suid 113,0
     24655)
     24656)
     24657uid 4735,0
    2457924658)
    2458024659*849 (LeafLogPort
    2458124660port (LogicalPort
    2458224661decl (Decl
    24583 n "SROUT_in_1"
    24584 t "std_logic"
    24585 o 3
    24586 suid 113,0
    24587 )
    24588 )
    24589 uid 4735,0
     24662n "SROUT_in_2"
     24663t "std_logic"
     24664o 4
     24665suid 114,0
     24666)
     24667)
     24668uid 4737,0
    2459024669)
    2459124670*850 (LeafLogPort
    2459224671port (LogicalPort
    2459324672decl (Decl
    24594 n "SROUT_in_2"
    24595 t "std_logic"
    24596 o 4
    24597 suid 114,0
    24598 )
    24599 )
    24600 uid 4737,0
     24673n "SROUT_in_3"
     24674t "std_logic"
     24675o 5
     24676suid 115,0
     24677)
     24678)
     24679uid 4739,0
    2460124680)
    2460224681*851 (LeafLogPort
    2460324682port (LogicalPort
    24604 decl (Decl
    24605 n "SROUT_in_3"
    24606 t "std_logic"
    24607 o 5
    24608 suid 115,0
    24609 )
    24610 )
    24611 uid 4739,0
     24683m 4
     24684decl (Decl
     24685n "drs_read_s_cell_ready"
     24686t "std_logic"
     24687o 84
     24688suid 116,0
     24689)
     24690)
     24691uid 4749,0
    2461224692)
    2461324693*852 (LeafLogPort
    2461424694port (LogicalPort
    24615 m 4
    24616 decl (Decl
    24617 n "drs_read_s_cell_ready"
    24618 t "std_logic"
    24619 o 84
    24620 suid 116,0
    24621 )
    24622 )
    24623 uid 4749,0
     24695m 1
     24696decl (Decl
     24697n "RSRLOAD"
     24698t "std_logic"
     24699o 23
     24700suid 117,0
     24701i "'0'"
     24702)
     24703)
     24704uid 4974,0
    2462424705)
    2462524706*853 (LeafLogPort
     
    2462724708m 1
    2462824709decl (Decl
    24629 n "RSRLOAD"
    24630 t "std_logic"
    24631 o 23
    24632 suid 117,0
    24633 i "'0'"
    24634 )
    24635 )
    24636 uid 4974,0
    24637 )
    24638 *854 (LeafLogPort
    24639 port (LogicalPort
    24640 m 1
    24641 decl (Decl
    2464224710n "SRCLK"
    2464324711t "std_logic"
     
    2464924717uid 4976,0
    2465024718)
    24651 *855 (LeafLogPort
     24719*854 (LeafLogPort
    2465224720port (LogicalPort
    2465324721m 4
     
    2466224730uid 5198,0
    2466324731)
     24732*855 (LeafLogPort
     24733port (LogicalPort
     24734m 4
     24735decl (Decl
     24736n "config_data_valid"
     24737t "std_logic"
     24738o 60
     24739suid 120,0
     24740)
     24741)
     24742uid 5200,0
     24743)
    2466424744*856 (LeafLogPort
    2466524745port (LogicalPort
    2466624746m 4
    2466724747decl (Decl
    24668 n "config_data_valid"
    24669 t "std_logic"
    24670 o 60
    24671 suid 120,0
    24672 )
    24673 )
    24674 uid 5200,0
    24675 )
    24676 *857 (LeafLogPort
    24677 port (LogicalPort
    24678 m 4
    24679 decl (Decl
    2468024748n "config_busy"
    2468124749t "std_logic"
     
    2468624754uid 5202,0
    2468724755)
    24688 *858 (LeafLogPort
     24756*857 (LeafLogPort
    2468924757port (LogicalPort
    2469024758m 4
     
    2469924767uid 5204,0
    2470024768)
     24769*858 (LeafLogPort
     24770port (LogicalPort
     24771m 4
     24772decl (Decl
     24773n "config_wr_en"
     24774t "std_logic"
     24775o 74
     24776suid 123,0
     24777)
     24778)
     24779uid 5206,0
     24780)
    2470124781*859 (LeafLogPort
    2470224782port (LogicalPort
    2470324783m 4
    2470424784decl (Decl
    24705 n "config_wr_en"
    24706 t "std_logic"
    24707 o 74
    24708 suid 123,0
    24709 )
    24710 )
    24711 uid 5206,0
    24712 )
    24713 *860 (LeafLogPort
    24714 port (LogicalPort
    24715 m 4
    24716 decl (Decl
    2471724785n "config_rd_en"
    2471824786t "std_logic"
     
    2472324791uid 5208,0
    2472424792)
    24725 *861 (LeafLogPort
     24793*860 (LeafLogPort
    2472624794port (LogicalPort
    2472724795m 4
     
    2473524803uid 5210,0
    2473624804)
     24805*861 (LeafLogPort
     24806port (LogicalPort
     24807m 4
     24808decl (Decl
     24809n "config_start_cm"
     24810t "std_logic"
     24811o 68
     24812suid 131,0
     24813)
     24814)
     24815uid 5212,0
     24816)
    2473724817*862 (LeafLogPort
    2473824818port (LogicalPort
    2473924819m 4
    2474024820decl (Decl
    24741 n "config_start_cm"
    24742 t "std_logic"
    24743 o 68
    24744 suid 131,0
    24745 )
    24746 )
    24747 uid 5212,0
    24748 )
    24749 *863 (LeafLogPort
    24750 port (LogicalPort
    24751 m 4
    24752 decl (Decl
    2475324821n "config_ready_cm"
    2475424822t "std_logic"
     
    2475924827uid 5214,0
    2476024828)
    24761 *864 (LeafLogPort
     24829*863 (LeafLogPort
    2476224830port (LogicalPort
    2476324831m 1
     
    2477424842uid 5226,0
    2477524843)
    24776 *865 (LeafLogPort
     24844*864 (LeafLogPort
    2477724845port (LogicalPort
    2477824846m 4
     
    2478624854uid 5502,0
    2478724855)
    24788 *866 (LeafLogPort
     24856*865 (LeafLogPort
    2478924857port (LogicalPort
    2479024858m 4
     
    2479824866uid 5504,0
    2479924867)
    24800 *867 (LeafLogPort
     24868*866 (LeafLogPort
    2480124869port (LogicalPort
    2480224870m 4
     
    2481024878uid 5600,0
    2481124879)
    24812 *868 (LeafLogPort
     24880*867 (LeafLogPort
    2481324881port (LogicalPort
    2481424882lang 10
     
    2482424892uid 5642,0
    2482524893)
    24826 *869 (LeafLogPort
     24894*868 (LeafLogPort
    2482724895port (LogicalPort
    2482824896m 4
     
    2483624904uid 5644,0
    2483724905)
    24838 *870 (LeafLogPort
     24906*869 (LeafLogPort
    2483924907port (LogicalPort
    2484024908m 4
     
    2484924917uid 5751,0
    2485024918)
    24851 *871 (LeafLogPort
     24919*870 (LeafLogPort
    2485224920port (LogicalPort
    2485324921m 1
     
    2486124929uid 5867,0
    2486224930)
    24863 *872 (LeafLogPort
     24931*871 (LeafLogPort
    2486424932port (LogicalPort
    2486524933m 2
     
    2487524943uid 5869,0
    2487624944)
    24877 *873 (LeafLogPort
     24945*872 (LeafLogPort
    2487824946port (LogicalPort
    2487924947m 1
     
    2488724955uid 5871,0
    2488824956)
    24889 *874 (LeafLogPort
     24957*873 (LeafLogPort
    2489024958port (LogicalPort
    2489124959m 1
     
    2490024968uid 5873,0
    2490124969)
     24970*874 (LeafLogPort
     24971port (LogicalPort
     24972m 4
     24973decl (Decl
     24974n "new_config"
     24975t "std_logic"
     24976o 92
     24977suid 155,0
     24978i "'0'"
     24979)
     24980)
     24981uid 5966,0
     24982)
    2490224983*875 (LeafLogPort
    2490324984port (LogicalPort
    2490424985m 4
    2490524986decl (Decl
    24906 n "new_config"
    24907 t "std_logic"
    24908 o 92
    24909 suid 155,0
    24910 i "'0'"
    24911 )
    24912 )
    24913 uid 5966,0
     24987n "config_started"
     24988t "std_logic"
     24989o 70
     24990suid 156,0
     24991)
     24992)
     24993uid 5968,0
    2491424994)
    2491524995*876 (LeafLogPort
     
    2491724997m 4
    2491824998decl (Decl
    24919 n "config_started"
    24920 t "std_logic"
    24921 o 70
    24922 suid 156,0
    24923 )
    24924 )
    24925 uid 5968,0
     24999n "config_started_spi"
     25000t "std_logic"
     25001o 73
     25002suid 159,0
     25003i "'0'"
     25004)
     25005)
     25006uid 6022,0
    2492625007)
    2492725008*877 (LeafLogPort
     
    2492925010m 4
    2493025011decl (Decl
    24931 n "config_started_spi"
    24932 t "std_logic"
    24933 o 73
    24934 suid 159,0
     25012n "config_started_cu"
     25013t "std_logic"
     25014o 71
     25015suid 160,0
    2493525016i "'0'"
    2493625017)
    2493725018)
    24938 uid 6022,0
     25019uid 6024,0
    2493925020)
    2494025021*878 (LeafLogPort
     
    2494225023m 4
    2494325024decl (Decl
    24944 n "config_started_cu"
    24945 t "std_logic"
    24946 o 71
    24947 suid 160,0
    24948 i "'0'"
    24949 )
    24950 )
    24951 uid 6024,0
    24952 )
    24953 *879 (LeafLogPort
    24954 port (LogicalPort
    24955 m 4
    24956 decl (Decl
    2495725025n "config_started_mm"
    2495825026t "std_logic"
     
    2496325031uid 6026,0
    2496425032)
    24965 *880 (LeafLogPort
     25033*879 (LeafLogPort
    2496625034port (LogicalPort
    2496725035m 1
     
    2497625044uid 6172,0
    2497725045)
    24978 *881 (LeafLogPort
     25046*880 (LeafLogPort
    2497925047port (LogicalPort
    2498025048m 1
     
    2499125059uid 6374,0
    2499225060)
     25061*881 (LeafLogPort
     25062port (LogicalPort
     25063m 4
     25064decl (Decl
     25065n "dwrite_enable"
     25066t "std_logic"
     25067o 91
     25068suid 167,0
     25069i "'1'"
     25070)
     25071)
     25072uid 6464,0
     25073)
    2499325074*882 (LeafLogPort
    2499425075port (LogicalPort
    2499525076m 4
    2499625077decl (Decl
    24997 n "dwrite_enable"
    24998 t "std_logic"
    24999 o 91
    25000 suid 167,0
    25001 i "'1'"
    25002 )
    25003 )
    25004 uid 6464,0
    25005 )
    25006 *883 (LeafLogPort
    25007 port (LogicalPort
    25008 m 4
    25009 decl (Decl
    2501025078n "dwrite"
    2501125079t "std_logic"
     
    2501725085uid 6554,0
    2501825086)
    25019 *884 (LeafLogPort
     25087*883 (LeafLogPort
    2502025088port (LogicalPort
    2502125089lang 2
     
    2503025098uid 8420,0
    2503125099)
     25100*884 (LeafLogPort
     25101port (LogicalPort
     25102m 4
     25103decl (Decl
     25104n "sclk1"
     25105t "std_logic"
     25106o 107
     25107suid 191,0
     25108)
     25109)
     25110uid 8758,0
     25111)
    2503225112*885 (LeafLogPort
    2503325113port (LogicalPort
    2503425114m 4
    2503525115decl (Decl
    25036 n "sclk1"
    25037 t "std_logic"
    25038 o 107
    25039 suid 191,0
    25040 )
    25041 )
    25042 uid 8758,0
    25043 )
    25044 *886 (LeafLogPort
    25045 port (LogicalPort
    25046 m 4
    25047 decl (Decl
    2504825116n "sclk_enable"
    2504925117t "std_logic"
     
    2505425122uid 8760,0
    2505525123)
    25056 *887 (LeafLogPort
     25124*886 (LeafLogPort
    2505725125port (LogicalPort
    2505825126m 1
     
    2506725135uid 9018,0
    2506825136)
    25069 *888 (LeafLogPort
     25137*887 (LeafLogPort
    2507025138port (LogicalPort
    2507125139m 4
     
    2508225150uid 9247,0
    2508325151)
    25084 *889 (LeafLogPort
     25152*888 (LeafLogPort
    2508525153port (LogicalPort
    2508625154m 4
     
    2509825166uid 9249,0
    2509925167)
    25100 *890 (LeafLogPort
     25168*889 (LeafLogPort
    2510125169port (LogicalPort
    2510225170m 4
     
    2511325181uid 10024,0
    2511425182)
     25183*890 (LeafLogPort
     25184port (LogicalPort
     25185m 4
     25186decl (Decl
     25187n "srclk_enable"
     25188t "std_logic"
     25189o 113
     25190suid 222,0
     25191i "'0'"
     25192)
     25193)
     25194uid 10026,0
     25195)
    2511525196*891 (LeafLogPort
    2511625197port (LogicalPort
    2511725198m 4
    2511825199decl (Decl
    25119 n "srclk_enable"
    25120 t "std_logic"
    25121 o 113
    25122 suid 222,0
    25123 i "'0'"
    25124 )
    25125 )
    25126 uid 10026,0
    25127 )
    25128 *892 (LeafLogPort
    25129 port (LogicalPort
    25130 m 4
    25131 decl (Decl
    2513225200n "SRCLK1"
    2513325201t "std_logic"
     
    2513925207uid 10028,0
    2514025208)
    25141 *893 (LeafLogPort
     25209*892 (LeafLogPort
    2514225210port (LogicalPort
    2514325211m 4
     
    2515525223uid 10208,0
    2515625224)
    25157 *894 (LeafLogPort
     25225*893 (LeafLogPort
    2515825226port (LogicalPort
    2515925227m 4
     
    2517125239uid 10210,0
    2517225240)
     25241*894 (LeafLogPort
     25242port (LogicalPort
     25243m 4
     25244decl (Decl
     25245n "s_trigger"
     25246t "std_logic"
     25247o 105
     25248suid 230,0
     25249)
     25250)
     25251uid 10294,0
     25252)
    2517325253*895 (LeafLogPort
    2517425254port (LogicalPort
    2517525255m 4
    2517625256decl (Decl
    25177 n "s_trigger"
    25178 t "std_logic"
    25179 o 105
    25180 suid 230,0
    25181 )
    25182 )
    25183 uid 10294,0
     25257n "start_srin_write_8b"
     25258t "std_logic"
     25259o 116
     25260suid 231,0
     25261)
     25262)
     25263uid 10334,0
    2518425264)
    2518525265*896 (LeafLogPort
     
    2518725267m 4
    2518825268decl (Decl
    25189 n "start_srin_write_8b"
    25190 t "std_logic"
    25191 o 116
    25192 suid 231,0
    25193 )
    25194 )
    25195 uid 10334,0
     25269n "srin_write_ack"
     25270t "std_logic"
     25271o 114
     25272suid 232,0
     25273i "'0'"
     25274)
     25275)
     25276uid 10336,0
    2519625277)
    2519725278*897 (LeafLogPort
     
    2519925280m 4
    2520025281decl (Decl
    25201 n "srin_write_ack"
    25202 t "std_logic"
    25203 o 114
    25204 suid 232,0
    25205 i "'0'"
    25206 )
    25207 )
    25208 uid 10336,0
    25209 )
    25210 *898 (LeafLogPort
    25211 port (LogicalPort
    25212 m 4
    25213 decl (Decl
    2521425282n "srin_write_ready"
    2521525283t "std_logic"
     
    2522125289uid 10338,0
    2522225290)
    25223 *899 (LeafLogPort
     25291*898 (LeafLogPort
    2522425292port (LogicalPort
    2522525293m 4
     
    2523525303uid 10340,0
    2523625304)
    25237 *900 (LeafLogPort
     25305*899 (LeafLogPort
    2523825306port (LogicalPort
    2523925307m 1
     
    2524825316uid 10342,0
    2524925317)
    25250 *901 (LeafLogPort
    25251 port (LogicalPort
    25252 m 4
    25253 decl (Decl
    25254 n "trigger_out"
    25255 t "std_logic"
    25256 preAdd 0
    25257 posAdd 0
    25258 o 120
    25259 suid 240,0
    25260 )
    25261 )
    25262 uid 10473,0
    25263 )
    25264 *902 (LeafLogPort
     25318*900 (LeafLogPort
    2526525319port (LogicalPort
    2526625320lang 2
     
    2527925333uid 10475,0
    2528025334)
     25335*901 (LeafLogPort
     25336port (LogicalPort
     25337m 4
     25338decl (Decl
     25339n "socks_connected"
     25340t "std_logic"
     25341o 111
     25342suid 243,0
     25343)
     25344)
     25345uid 10763,0
     25346)
     25347*902 (LeafLogPort
     25348port (LogicalPort
     25349m 4
     25350decl (Decl
     25351n "socks_waiting"
     25352t "std_logic"
     25353o 112
     25354suid 244,0
     25355)
     25356)
     25357uid 10765,0
     25358)
    2528125359*903 (LeafLogPort
    2528225360port (LogicalPort
    25283 m 4
    25284 decl (Decl
    25285 n "socks_connected"
    25286 t "std_logic"
    25287 o 111
    25288 suid 243,0
    25289 )
    25290 )
    25291 uid 10763,0
     25361m 1
     25362decl (Decl
     25363n "green"
     25364t "std_logic"
     25365o 34
     25366suid 248,0
     25367)
     25368)
     25369uid 10767,0
    2529225370)
    2529325371*904 (LeafLogPort
    2529425372port (LogicalPort
    25295 m 4
    25296 decl (Decl
    25297 n "socks_waiting"
    25298 t "std_logic"
    25299 o 112
    25300 suid 244,0
    25301 )
    25302 )
    25303 uid 10765,0
     25373m 1
     25374decl (Decl
     25375n "amber"
     25376t "std_logic"
     25377o 29
     25378suid 249,0
     25379)
     25380)
     25381uid 10769,0
    2530425382)
    2530525383*905 (LeafLogPort
     
    2530725385m 1
    2530825386decl (Decl
    25309 n "green"
    25310 t "std_logic"
    25311 o 34
    25312 suid 248,0
    25313 )
    25314 )
    25315 uid 10767,0
     25387n "red"
     25388t "std_logic"
     25389o 39
     25390suid 250,0
     25391)
     25392)
     25393uid 10771,0
    2531625394)
    2531725395*906 (LeafLogPort
    2531825396port (LogicalPort
    25319 m 1
    25320 decl (Decl
    25321 n "amber"
    25322 t "std_logic"
    25323 o 29
    25324 suid 249,0
    25325 )
    25326 )
    25327 uid 10769,0
     25397m 4
     25398decl (Decl
     25399n "drs_readout_started"
     25400t "std_logic"
     25401o 87
     25402suid 252,0
     25403)
     25404)
     25405uid 11411,0
    2532825406)
    2532925407*907 (LeafLogPort
    2533025408port (LogicalPort
    25331 m 1
    25332 decl (Decl
    25333 n "red"
    25334 t "std_logic"
    25335 o 39
    25336 suid 250,0
    25337 )
    25338 )
    25339 uid 10771,0
    25340 )
    25341 *908 (LeafLogPort
    25342 port (LogicalPort
    25343 m 4
    25344 decl (Decl
    25345 n "drs_readout_started"
    25346 t "std_logic"
    25347 o 87
    25348 suid 252,0
    25349 )
    25350 )
    25351 uid 11411,0
    25352 )
    25353 *909 (LeafLogPort
    25354 port (LogicalPort
    2535525409m 4
    2535625410decl (Decl
     
    2536325417uid 11966,0
    2536425418)
    25365 *910 (LeafLogPort
     25419*908 (LeafLogPort
    2536625420port (LogicalPort
    2536725421m 4
     
    2537725431uid 12310,0
    2537825432)
    25379 *911 (LeafLogPort
     25433*909 (LeafLogPort
    2538025434port (LogicalPort
    2538125435m 4
     
    2539125445uid 12659,0
    2539225446)
    25393 *912 (LeafLogPort
     25447*910 (LeafLogPort
    2539425448port (LogicalPort
    2539525449m 4
     
    2540825462uid 12661,0
    2540925463)
     25464*911 (LeafLogPort
     25465port (LogicalPort
     25466m 4
     25467decl (Decl
     25468n "drs_readout_ready_ack"
     25469t "std_logic"
     25470o 86
     25471suid 267,0
     25472)
     25473)
     25474uid 12663,0
     25475)
     25476*912 (LeafLogPort
     25477port (LogicalPort
     25478m 1
     25479decl (Decl
     25480n "additional_flasher_out"
     25481t "std_logic"
     25482o 28
     25483suid 272,0
     25484)
     25485)
     25486uid 12719,0
     25487)
    2541025488*913 (LeafLogPort
    2541125489port (LogicalPort
    2541225490m 4
    2541325491decl (Decl
    25414 n "drs_readout_ready_ack"
    25415 t "std_logic"
    25416 o 86
    25417 suid 267,0
    25418 )
    25419 )
    25420 uid 12663,0
    25421 )
    25422 *914 (LeafLogPort
    25423 port (LogicalPort
    25424 m 1
    25425 decl (Decl
    25426 n "additional_flasher_out"
    25427 t "std_logic"
    25428 o 28
    25429 suid 272,0
    25430 )
    25431 )
    25432 uid 12719,0
    25433 )
    25434 *915 (LeafLogPort
    25435 port (LogicalPort
    25436 m 4
    25437 decl (Decl
    2543825492n "c_trigger_enable"
    2543925493t "std_logic"
     
    2544525499uid 13275,0
    2544625500)
    25447 *916 (LeafLogPort
     25501*914 (LeafLogPort
    2544825502port (LogicalPort
    2544925503m 4
     
    2546125515uid 13277,0
    2546225516)
    25463 *917 (LeafLogPort
     25517*915 (LeafLogPort
    2546425518port (LogicalPort
    2546525519m 4
     
    2547325527uid 13279,0
    2547425528)
    25475 *918 (LeafLogPort
     25529*916 (LeafLogPort
    2547625530port (LogicalPort
    2547725531m 4
     
    2548525539uid 13281,0
    2548625540)
    25487 *919 (LeafLogPort
     25541*917 (LeafLogPort
    2548825542port (LogicalPort
    2548925543decl (Decl
     
    2549825552scheme 0
    2549925553)
    25500 *920 (LeafLogPort
     25554*918 (LeafLogPort
    2550125555port (LogicalPort
    2550225556decl (Decl
     
    2551125565scheme 0
    2551225566)
    25513 *921 (LeafLogPort
     25567*919 (LeafLogPort
    2551425568port (LogicalPort
    2551525569decl (Decl
     
    2552525579scheme 0
    2552625580)
    25527 *922 (LeafLogPort
     25581*920 (LeafLogPort
    2552825582port (LogicalPort
    2552925583m 1
     
    2554025594uid 14507,0
    2554125595)
    25542 *923 (LeafLogPort
     25596*921 (LeafLogPort
    2554325597port (LogicalPort
    2554425598m 1
     
    2555525609uid 14509,0
    2555625610)
    25557 *924 (LeafLogPort
     25611*922 (LeafLogPort
    2555825612port (LogicalPort
    2555925613m 1
     
    2556925623uid 14634,0
    2557025624)
    25571 *925 (LeafLogPort
     25625*923 (LeafLogPort
    2557225626port (LogicalPort
    2557325627m 4
     
    2558425638uid 15144,0
    2558525639)
    25586 *926 (LeafLogPort
     25640*924 (LeafLogPort
    2558725641port (LogicalPort
    2558825642m 4
     
    2559925653uid 15146,0
    2560025654)
    25601 *927 (LeafLogPort
     25655*925 (LeafLogPort
    2560225656port (LogicalPort
    2560325657m 4
     
    2561425668uid 15148,0
    2561525669)
     25670*926 (LeafLogPort
     25671port (LogicalPort
     25672m 4
     25673decl (Decl
     25674n "trigger_out"
     25675t "std_logic"
     25676o 123
     25677suid 301,0
     25678i "'0'"
     25679)
     25680)
     25681uid 15504,0
     25682)
    2561625683]
    2561725684)
     
    2562125688uid 67,0
    2562225689optionalChildren [
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     25690*927 (Sheet
    2562425691sheetRow (SheetRow
    2562525692headerVa (MVa
     
    2563825705font "Tahoma,10,0"
    2563925706)
    25640 emptyMRCItem *929 (MRCItem
    25641 litem &792
     25707emptyMRCItem *928 (MRCItem
     25708litem &791
    2564225709pos 123
    2564325710dimension 20
     
    2564525712uid 69,0
    2564625713optionalChildren [
    25647 *930 (MRCItem
    25648 litem &793
     25714*929 (MRCItem
     25715litem &792
    2564925716pos 0
    2565025717dimension 20
    2565125718uid 70,0
    2565225719)
    25653 *931 (MRCItem
    25654 litem &794
     25720*930 (MRCItem
     25721litem &793
    2565525722pos 1
    2565625723dimension 23
    2565725724uid 71,0
    2565825725)
    25659 *932 (MRCItem
    25660 litem &795
     25726*931 (MRCItem
     25727litem &794
    2566125728pos 2
    2566225729hidden 1
     
    2566425731uid 72,0
    2566525732)
    25666 *933 (MRCItem
    25667 litem &805
     25733*932 (MRCItem
     25734litem &804
    2566825735pos 37
    2566925736dimension 20
    2567025737uid 517,0
    2567125738)
    25672 *934 (MRCItem
    25673 litem &806
     25739*933 (MRCItem
     25740litem &805
    2567425741pos 38
    2567525742dimension 20
    2567625743uid 519,0
    2567725744)
    25678 *935 (MRCItem
    25679 litem &807
     25745*934 (MRCItem
     25746litem &806
    2568025747pos 39
    2568125748dimension 20
    2568225749uid 521,0
    2568325750)
    25684 *936 (MRCItem
    25685 litem &808
     25751*935 (MRCItem
     25752litem &807
    2568625753pos 40
    2568725754dimension 20
    2568825755uid 531,0
    2568925756)
    25690 *937 (MRCItem
    25691 litem &809
     25757*936 (MRCItem
     25758litem &808
    2569225759pos 41
    2569325760dimension 20
    2569425761uid 533,0
    2569525762)
    25696 *938 (MRCItem
    25697 litem &810
     25763*937 (MRCItem
     25764litem &809
    2569825765pos 0
    2569925766dimension 20
    2570025767uid 535,0
    2570125768)
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    25703 litem &811
     25769*938 (MRCItem
     25770litem &810
    2570425771pos 1
    2570525772dimension 20
    2570625773uid 537,0
    2570725774)
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    25709 litem &812
     25775*939 (MRCItem
     25776litem &811
    2571025777pos 2
    2571125778dimension 20
    2571225779uid 539,0
    2571325780)
    25714 *941 (MRCItem
    25715 litem &813
     25781*940 (MRCItem
     25782litem &812
    2571625783pos 3
    2571725784dimension 20
    2571825785uid 541,0
    2571925786)
    25720 *942 (MRCItem
    25721 litem &814
     25787*941 (MRCItem
     25788litem &813
    2572225789pos 4
    2572325790dimension 20
    2572425791uid 543,0
    2572525792)
    25726 *943 (MRCItem
    25727 litem &815
     25793*942 (MRCItem
     25794litem &814
    2572825795pos 5
    2572925796dimension 20
    2573025797uid 547,0
    2573125798)
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    25733 litem &816
     25799*943 (MRCItem
     25800litem &815
    2573425801pos 6
    2573525802dimension 20
    2573625803uid 549,0
    2573725804)
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    25739 litem &817
     25805*944 (MRCItem
     25806litem &816
    2574025807pos 8
    2574125808dimension 20
    2574225809uid 1456,0
    2574325810)
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    25745 litem &818
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     25812litem &817
    2574625813pos 7
    2574725814dimension 20
    2574825815uid 1458,0
    2574925816)
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    25751 litem &819
     25817*946 (MRCItem
     25818litem &818
    2575225819pos 9
    2575325820dimension 20
    2575425821uid 1695,0
    2575525822)
    25756 *948 (MRCItem
    25757 litem &820
     25823*947 (MRCItem
     25824litem &819
    2575825825pos 42
    2575925826dimension 20
    2576025827uid 1994,0
    2576125828)
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    25763 litem &821
     25829*948 (MRCItem
     25830litem &820
    2576425831pos 43
    2576525832dimension 20
    2576625833uid 2306,0
    2576725834)
    25768 *950 (MRCItem
    25769 litem &822
     25835*949 (MRCItem
     25836litem &821
    2577025837pos 44
    2577125838dimension 20
    2577225839uid 2511,0
    2577325840)
    25774 *951 (MRCItem
    25775 litem &823
     25841*950 (MRCItem
     25842litem &822
    2577625843pos 45
    2577725844dimension 20
    2577825845uid 2513,0
    2577925846)
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    25781 litem &824
     25847*951 (MRCItem
     25848litem &823
    2578225849pos 46
    2578325850dimension 20
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    26364 pos 116
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    2636526438dimension 20
    26366 uid 14164,0
     26439uid 14510,0
    2636726440)
    2636826441*1050 (MRCItem
    2636926442litem &922
    26370 pos 117
     26443pos 118
    2637126444dimension 20
    26372 uid 14508,0
     26445uid 14635,0
    2637326446)
    2637426447*1051 (MRCItem
    2637526448litem &923
    26376 pos 118
     26449pos 119
    2637726450dimension 20
    26378 uid 14510,0
     26451uid 15145,0
    2637926452)
    2638026453*1052 (MRCItem
    2638126454litem &924
    26382 pos 119
     26455pos 120
    2638326456dimension 20
    26384 uid 14635,0
     26457uid 15147,0
    2638526458)
    2638626459*1053 (MRCItem
    2638726460litem &925
    26388 pos 120
     26461pos 121
    2638926462dimension 20
    26390 uid 15145,0
     26463uid 15149,0
    2639126464)
    2639226465*1054 (MRCItem
    2639326466litem &926
    26394 pos 121
    26395 dimension 20
    26396 uid 15147,0
    26397 )
    26398 *1055 (MRCItem
    26399 litem &927
    2640026467pos 122
    2640126468dimension 20
    26402 uid 15149,0
     26469uid 15505,0
    2640326470)
    2640426471]
     
    2641326480uid 73,0
    2641426481optionalChildren [
    26415 *1056 (MRCItem
    26416 litem &796
     26482*1055 (MRCItem
     26483litem &795
    2641726484pos 0
    2641826485dimension 20
    2641926486uid 74,0
    2642026487)
    26421 *1057 (MRCItem
    26422 litem &798
     26488*1056 (MRCItem
     26489litem &797
    2642326490pos 1
    2642426491dimension 50
    2642526492uid 75,0
    2642626493)
    26427 *1058 (MRCItem
    26428 litem &799
     26494*1057 (MRCItem
     26495litem &798
    2642926496pos 2
    2643026497dimension 100
    2643126498uid 76,0
    2643226499)
    26433 *1059 (MRCItem
    26434 litem &800
     26500*1058 (MRCItem
     26501litem &799
    2643526502pos 3
    2643626503dimension 50
    2643726504uid 77,0
    2643826505)
    26439 *1060 (MRCItem
    26440 litem &801
     26506*1059 (MRCItem
     26507litem &800
    2644126508pos 4
    2644226509dimension 100
    2644326510uid 78,0
    2644426511)
    26445 *1061 (MRCItem
    26446 litem &802
     26512*1060 (MRCItem
     26513litem &801
    2644726514pos 5
    2644826515dimension 100
    2644926516uid 79,0
    2645026517)
    26451 *1062 (MRCItem
    26452 litem &803
     26518*1061 (MRCItem
     26519litem &802
    2645326520pos 6
    2645426521dimension 50
    2645526522uid 80,0
    2645626523)
    26457 *1063 (MRCItem
    26458 litem &804
     26524*1062 (MRCItem
     26525litem &803
    2645926526pos 7
    2646026527dimension 290
     
    2647626543genericsCommonDM (CommonDM
    2647726544ldm (LogicalDM
    26478 emptyRow *1064 (LEmptyRow
     26545emptyRow *1063 (LEmptyRow
    2647926546)
    2648026547uid 83,0
    2648126548optionalChildren [
    26482 *1065 (RefLabelRowHdr
    26483 )
    26484 *1066 (TitleRowHdr
    26485 )
    26486 *1067 (FilterRowHdr
    26487 )
    26488 *1068 (RefLabelColHdr
     26549*1064 (RefLabelRowHdr
     26550)
     26551*1065 (TitleRowHdr
     26552)
     26553*1066 (FilterRowHdr
     26554)
     26555*1067 (RefLabelColHdr
    2648926556tm "RefLabelColHdrMgr"
    2649026557)
    26491 *1069 (RowExpandColHdr
     26558*1068 (RowExpandColHdr
    2649226559tm "RowExpandColHdrMgr"
    2649326560)
    26494 *1070 (GroupColHdr
     26561*1069 (GroupColHdr
    2649526562tm "GroupColHdrMgr"
    2649626563)
    26497 *1071 (NameColHdr
     26564*1070 (NameColHdr
    2649826565tm "GenericNameColHdrMgr"
    2649926566)
    26500 *1072 (TypeColHdr
     26567*1071 (TypeColHdr
    2650126568tm "GenericTypeColHdrMgr"
    2650226569)
    26503 *1073 (InitColHdr
     26570*1072 (InitColHdr
    2650426571tm "GenericValueColHdrMgr"
    2650526572)
    26506 *1074 (PragmaColHdr
     26573*1073 (PragmaColHdr
    2650726574tm "GenericPragmaColHdrMgr"
    2650826575)
    26509 *1075 (EolColHdr
     26576*1074 (EolColHdr
    2651026577tm "GenericEolColHdrMgr"
    2651126578)
    26512 *1076 (LogGeneric
     26579*1075 (LogGeneric
    2651326580generic (GiElement
    2651426581name "RAMADDRWIDTH64b"
     
    2652526592uid 95,0
    2652626593optionalChildren [
    26527 *1077 (Sheet
     26594*1076 (Sheet
    2652826595sheetRow (SheetRow
    2652926596headerVa (MVa
     
    2654226609font "Tahoma,10,0"
    2654326610)
    26544 emptyMRCItem *1078 (MRCItem
    26545 litem &1064
     26611emptyMRCItem *1077 (MRCItem
     26612litem &1063
    2654626613pos 1
    2654726614dimension 20
     
    2654926616uid 97,0
    2655026617optionalChildren [
    26551 *1079 (MRCItem
    26552 litem &1065
     26618*1078 (MRCItem
     26619litem &1064
    2655326620pos 0
    2655426621dimension 20
    2655526622uid 98,0
    2655626623)
    26557 *1080 (MRCItem
    26558 litem &1066
     26624*1079 (MRCItem
     26625litem &1065
    2655926626pos 1
    2656026627dimension 23
    2656126628uid 99,0
    2656226629)
    26563 *1081 (MRCItem
    26564 litem &1067
     26630*1080 (MRCItem
     26631litem &1066
    2656526632pos 2
    2656626633hidden 1
     
    2656826635uid 100,0
    2656926636)
    26570 *1082 (MRCItem
    26571 litem &1076
     26637*1081 (MRCItem
     26638litem &1075
    2657226639pos 0
    2657326640dimension 20
     
    2658526652uid 101,0
    2658626653optionalChildren [
    26587 *1083 (MRCItem
    26588 litem &1068
     26654*1082 (MRCItem
     26655litem &1067
    2658926656pos 0
    2659026657dimension 20
    2659126658uid 102,0
    2659226659)
    26593 *1084 (MRCItem
    26594 litem &1070
     26660*1083 (MRCItem
     26661litem &1069
    2659526662pos 1
    2659626663dimension 50
    2659726664uid 103,0
    2659826665)
    26599 *1085 (MRCItem
    26600 litem &1071
     26666*1084 (MRCItem
     26667litem &1070
    2660126668pos 2
    2660226669dimension 186
    2660326670uid 104,0
    2660426671)
    26605 *1086 (MRCItem
    26606 litem &1072
     26672*1085 (MRCItem
     26673litem &1071
    2660726674pos 3
    2660826675dimension 96
    2660926676uid 105,0
    2661026677)
    26611 *1087 (MRCItem
    26612 litem &1073
     26678*1086 (MRCItem
     26679litem &1072
    2661326680pos 4
    2661426681dimension 50
    2661526682uid 106,0
    2661626683)
    26617 *1088 (MRCItem
    26618 litem &1074
     26684*1087 (MRCItem
     26685litem &1073
    2661926686pos 5
    2662026687dimension 50
    2662126688uid 107,0
    2662226689)
    26623 *1089 (MRCItem
    26624 litem &1075
     26690*1088 (MRCItem
     26691litem &1074
    2662526692pos 6
    2662626693dimension 80
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak

    r10129 r10138  
    333333(vvPair
    334334variable "date"
    335 value "04.02.2011"
     335value "08.02.2011"
    336336)
    337337(vvPair
    338338variable "day"
    339 value "Fr"
     339value "Di"
    340340)
    341341(vvPair
    342342variable "day_long"
    343 value "Freitag"
     343value "Dienstag"
    344344)
    345345(vvPair
    346346variable "dd"
    347 value "04"
     347value "08"
    348348)
    349349(vvPair
     
    485485(vvPair
    486486variable "time"
    487 value "11:32:44"
     487value "11:05:26"
    488488)
    489489(vvPair
     
    576576font "Courier New,8,0"
    577577)
    578 xt "-172000,106800,-128500,107600"
     578xt "-172000,106000,-128500,106800"
    579579st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
    580580"
     
    13031303fg "0,65535,0"
    13041304)
    1305 xt "0,65625,750,66375"
     1305xt "0,70625,750,71375"
    13061306)
    13071307tg (CPTG
     
    13131313va (VaSet
    13141314)
    1315 xt "-17300,65500,-1000,66500"
     1315xt "-17300,70500,-1000,71500"
    13161316st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    13171317ju 2
    1318 blo "-1000,66300"
     1318blo "-1000,71300"
    13191319)
    13201320)
     
    13781378fg "0,65535,0"
    13791379)
    1380 xt "-21750,70625,-21000,71375"
     1380xt "-21750,69625,-21000,70375"
    13811381)
    13821382tg (CPTG
     
    13881388va (VaSet
    13891389)
    1390 xt "-20000,70500,-13200,71500"
     1390xt "-20000,69500,-13200,70500"
    13911391st "trigger_id : (47:0)"
    1392 blo "-20000,71300"
     1392blo "-20000,70300"
    13931393)
    13941394)
     
    14861486fg "0,65535,0"
    14871487)
    1488 xt "0,66625,750,67375"
     1488xt "0,71625,750,72375"
    14891489)
    14901490tg (CPTG
     
    14961496va (VaSet
    14971497)
    1498 xt "-6300,66500,-1000,67500"
     1498xt "-6300,71500,-1000,72500"
    14991499st "ram_write_ea"
    15001500ju 2
    1501 blo "-1000,67300"
     1501blo "-1000,72300"
    15021502)
    15031503)
     
    15211521fg "0,65535,0"
    15221522)
    1523 xt "0,67625,750,68375"
     1523xt "0,72625,750,73375"
    15241524)
    15251525tg (CPTG
     
    15311531va (VaSet
    15321532)
    1533 xt "-7300,67500,-1000,68500"
     1533xt "-7300,72500,-1000,73500"
    15341534st "ram_write_ready"
    15351535ju 2
    1536 blo "-1000,68300"
     1536blo "-1000,73300"
    15371537)
    15381538)
     
    15591559fg "0,65535,0"
    15601560)
    1561 xt "0,76625,750,77375"
     1561xt "0,78625,750,79375"
    15621562)
    15631563tg (CPTG
     
    15691569va (VaSet
    15701570)
    1571 xt "-4000,76500,-1000,77500"
     1571xt "-4000,78500,-1000,79500"
    15721572st "roi_max"
    15731573ju 2
    1574 blo "-1000,77300"
     1574blo "-1000,79300"
    15751575)
    15761576)
     
    16291629fg "0,65535,0"
    16301630)
    1631 xt "0,77625,750,78375"
     1631xt "0,79625,750,80375"
    16321632)
    16331633tg (CPTG
     
    16391639va (VaSet
    16401640)
    1641 xt "-10100,77500,-1000,78500"
     1641xt "-10100,79500,-1000,80500"
    16421642st "package_length : (15:0)"
    16431643ju 2
    1644 blo "-1000,78300"
     1644blo "-1000,80300"
    16451645)
    16461646)
     
    20282028fg "0,65535,0"
    20292029)
    2030 xt "0,74625,750,75375"
     2030xt "0,77625,750,78375"
    20312031)
    20322032tg (CPTG
     
    20382038va (VaSet
    20392039)
    2040 xt "-7700,74500,-1000,75500"
     2040xt "-7700,77500,-1000,78500"
    20412041st "config_ready_mm"
    20422042ju 2
    2043 blo "-1000,75300"
     2043blo "-1000,78300"
    20442044)
    20452045)
     
    21682168fg "0,65535,0"
    21692169)
    2170 xt "0,72625,750,73375"
     2170xt "0,75625,750,76375"
    21712171)
    21722172tg (CPTG
     
    21782178va (VaSet
    21792179)
    2180 xt "-7400,72500,-1000,73500"
     2180xt "-7400,75500,-1000,76500"
    21812181st "config_start_mm"
    21822182ju 2
    2183 blo "-1000,73300"
     2183blo "-1000,76300"
    21842184)
    21852185)
     
    23562356fg "0,65535,0"
    23572357)
    2358 xt "0,73625,750,74375"
     2358xt "0,76625,750,77375"
    23592359)
    23602360tg (CPTG
     
    23662366va (VaSet
    23672367)
    2368 xt "-8200,73500,-1000,74500"
     2368xt "-8200,76500,-1000,77500"
    23692369st "config_started_mm"
    23702370ju 2
    2371 blo "-1000,74300"
     2371blo "-1000,77300"
    23722372)
    23732373)
     
    26382638fg "0,65535,0"
    26392639)
    2640 xt "0,68625,750,69375"
     2640xt "0,73625,750,74375"
    26412641)
    26422642tg (CPTG
     
    26482648va (VaSet
    26492649)
    2650 xt "-8800,68500,-1000,69500"
     2650xt "-8800,73500,-1000,74500"
    26512651st "ram_write_ready_ack"
    26522652ju 2
    2653 blo "-1000,69300"
     2653blo "-1000,74300"
    26542654)
    26552655)
     
    27992799font "Arial,8,1"
    28002800)
    2801 xt "-20700,97000,-14500,98000"
     2801xt "-20700,98000,-14500,99000"
    28022802st "FACT_FAD_lib"
    2803 blo "-20700,97800"
     2803blo "-20700,98800"
    28042804tm "BdLibraryNameMgr"
    28052805)
     
    28092809font "Arial,8,1"
    28102810)
    2811 xt "-20700,98000,-14300,99000"
     2811xt "-20700,99000,-14300,100000"
    28122812st "data_generator"
    2813 blo "-20700,98800"
     2813blo "-20700,99800"
    28142814tm "CptNameMgr"
    28152815)
     
    28192819font "Arial,8,1"
    28202820)
    2821 xt "-20700,99000,-11100,100000"
     2821xt "-20700,100000,-11100,101000"
    28222822st "I_main_data_generator"
    2823 blo "-20700,99800"
     2823blo "-20700,100800"
    28242824tm "InstanceNameMgr"
    28252825)
     
    32713271fg "0,65535,0"
    32723272)
    3273 xt "87250,71625,88000,72375"
     3273xt "87250,72625,88000,73375"
    32743274)
    32753275tg (CPTG
     
    32813281va (VaSet
    32823282)
    3283 xt "89000,71500,96900,72500"
     3283xt "89000,72500,96900,73500"
    32843284st "write_length : (16:0)"
    3285 blo "89000,72300"
     3285blo "89000,73300"
    32863286)
    32873287)
     
    33083308fg "0,65535,0"
    33093309)
    3310 xt "87250,72625,88000,73375"
     3310xt "87250,73625,88000,74375"
    33113311)
    33123312tg (CPTG
     
    33183318va (VaSet
    33193319)
    3320 xt "89000,72500,105300,73500"
     3320xt "89000,73500,105300,74500"
    33213321st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
    3322 blo "89000,73300"
     3322blo "89000,74300"
    33233323)
    33243324)
     
    34203420fg "0,65535,0"
    34213421)
    3422 xt "87250,70625,88000,71375"
     3422xt "87250,71625,88000,72375"
    34233423)
    34243424tg (CPTG
     
    34303430va (VaSet
    34313431)
    3432 xt "89000,70500,93100,71500"
     3432xt "89000,71500,93100,72500"
    34333433st "data_valid"
    3434 blo "89000,71300"
     3434blo "89000,72300"
    34353435)
    34363436)
     
    34563456fg "0,65535,0"
    34573457)
    3458 xt "87250,69625,88000,70375"
     3458xt "87250,70625,88000,71375"
    34593459)
    34603460tg (CPTG
     
    34663466va (VaSet
    34673467)
    3468 xt "89000,69500,90900,70500"
     3468xt "89000,70500,90900,71500"
    34693469st "busy"
    3470 blo "89000,70300"
     3470blo "89000,71300"
    34713471)
    34723472)
     
    34943494fg "0,65535,0"
    34953495)
    3496 xt "87250,73625,88000,74375"
     3496xt "87250,74625,88000,75375"
    34973497)
    34983498tg (CPTG
     
    35043504va (VaSet
    35053505)
    3506 xt "89000,73500,96800,74500"
     3506xt "89000,74500,96800,75500"
    35073507st "fifo_channels : (3:0)"
    3508 blo "89000,74300"
     3508blo "89000,75300"
    35093509)
    35103510)
     
    35303530fg "0,65535,0"
    35313531)
    3532 xt "87250,74625,88000,75375"
     3532xt "87250,75625,88000,76375"
    35333533)
    35343534tg (CPTG
     
    35403540va (VaSet
    35413541)
    3542 xt "89000,74500,94700,75500"
     3542xt "89000,75500,94700,76500"
    35433543st "write_end_flag"
    3544 blo "89000,75300"
     3544blo "89000,76300"
    35453545)
    35463546)
     
    35643564fg "0,65535,0"
    35653565)
    3566 xt "87250,75625,88000,76375"
     3566xt "87250,76625,88000,77375"
    35673567)
    35683568tg (CPTG
     
    35743574va (VaSet
    35753575)
    3576 xt "89000,75500,95800,76500"
     3576xt "89000,76500,95800,77500"
    35773577st "write_header_flag"
    3578 blo "89000,76300"
     3578blo "89000,77300"
    35793579)
    35803580)
     
    40084008fg "0,65535,0"
    40094009)
    4010 xt "87250,76625,88000,77375"
     4010xt "87250,77625,88000,78375"
    40114011)
    40124012tg (CPTG
     
    40184018va (VaSet
    40194019)
    4020 xt "89000,76500,94600,77500"
     4020xt "89000,77500,94600,78500"
    40214021st "data_valid_ack"
    4022 blo "89000,77300"
     4022blo "89000,78300"
    40234023)
    40244024)
     
    47184718fg "0,65535,0"
    47194719)
    4720 xt "-41000,67625,-40250,68375"
     4720xt "-41000,68625,-40250,69375"
    47214721)
    47224722tg (CPTG
     
    47284728va (VaSet
    47294729)
    4730 xt "-48800,67500,-42000,68500"
     4730xt "-48800,68500,-42000,69500"
    47314731st "trigger_id : (47:0)"
    47324732ju 2
    4733 blo "-42000,68300"
     4733blo "-42000,69300"
    47344734)
    47354735)
     
    47584758fg "0,65535,0"
    47594759)
    4760 xt "-52750,67625,-52000,68375"
     4760xt "-52750,68625,-52000,69375"
    47614761)
    47624762tg (CPTG
     
    47684768va (VaSet
    47694769)
    4770 xt "-51000,67500,-48200,68500"
     4770xt "-51000,68500,-48200,69500"
    47714771st "trigger"
    4772 blo "-51000,68300"
     4772blo "-51000,69300"
    47734773)
    47744774)
     
    47954795fg "0,65535,0"
    47964796)
    4797 xt "-52750,66625,-52000,67375"
     4797xt "-52750,67625,-52000,68375"
    47984798)
    47994799tg (CPTG
     
    48054805va (VaSet
    48064806)
    4807 xt "-51000,66500,-49700,67500"
     4807xt "-51000,67500,-49700,68500"
    48084808st "clk"
    4809 blo "-51000,67300"
     4809blo "-51000,68300"
    48104810)
    48114811)
     
    48294829lineWidth 2
    48304830)
    4831 xt "-52000,66000,-41000,70000"
     4831xt "-52000,67000,-41000,71000"
    48324832)
    48334833oxt "32000,2000,43000,12000"
     
    48434843font "Arial,8,1"
    48444844)
    4845 xt "-50300,70000,-43700,71000"
     4845xt "-50300,71000,-43700,72000"
    48464846st "FACT_FAD_LIB"
    4847 blo "-50300,70800"
     4847blo "-50300,71800"
    48484848tm "BdLibraryNameMgr"
    48494849)
     
    48544854font "Arial,8,1"
    48554855)
    4856 xt "-50300,71000,-43700,72000"
     4856xt "-50300,72000,-43700,73000"
    48574857st "trigger_counter"
    4858 blo "-50300,71800"
     4858blo "-50300,72800"
    48594859tm "CptNameMgr"
    48604860)
     
    48654865font "Arial,8,1"
    48664866)
    4867 xt "-50300,71000,-42700,72000"
     4867xt "-50300,72000,-42700,73000"
    48684868st "I_main_ext_trigger"
    4869 blo "-50300,71800"
     4869blo "-50300,72800"
    48704870tm "InstanceNameMgr"
    48714871)
     
    48824882font "Courier New,8,0"
    48834883)
    4884 xt "-52000,65000,-52000,65000"
     4884xt "-52000,66000,-52000,66000"
    48854885)
    48864886header ""
     
    48964896fg "49152,49152,49152"
    48974897)
    4898 xt "-51750,68250,-50250,69750"
     4898xt "-51750,69250,-50250,70750"
    48994899iconName "VhdlFileViewIcon.png"
    49004900iconMaskName "VhdlFileViewIcon.msk"
     
    49644964fg "0,65535,0"
    49654965)
    4966 xt "31250,72625,32000,73375"
     4966xt "27250,70625,28000,71375"
    49674967)
    49684968tg (CPTG
     
    49754975font "arial,8,0"
    49764976)
    4977 xt "33000,72500,51400,73500"
     4977xt "29000,70500,47400,71500"
    49784978st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
    4979 blo "33000,73300"
     4979blo "29000,71300"
    49804980)
    49814981)
     
    50005000shape (Triangle
    50015001uid 2352,0
    5002 ro 90
     5002ro 180
    50035003va (VaSet
    50045004vasetType 1
    50055005fg "0,65535,0"
    50065006)
    5007 xt "31250,70625,32000,71375"
     5007xt "28625,67250,29375,68000"
    50085008)
    50095009tg (CPTG
    50105010uid 2353,0
    50115011ps "CptPortTextPlaceStrategy"
    5012 stg "VerticalLayoutStrategy"
     5012stg "RightVerticalLayoutStrategy"
    50135013f (Text
    50145014uid 2354,0
     5015ro 270
    50155016va (VaSet
    50165017font "arial,8,0"
    50175018)
    5018 xt "33000,70500,34300,71500"
     5019xt "28500,69000,29500,70300"
    50195020st "clk"
    5020 blo "33000,71300"
     5021ju 2
     5022blo "29300,69000"
    50215023)
    50225024)
     
    50415043fg "0,65535,0"
    50425044)
    5043 xt "31250,79625,32000,80375"
     5045xt "27250,77625,28000,78375"
    50445046)
    50455047tg (CPTG
     
    50525054font "arial,8,0"
    50535055)
    5054 xt "33000,79500,38100,80500"
     5056xt "29000,77500,34100,78500"
    50555057st "config_ready"
    5056 blo "33000,80300"
     5058blo "29000,78300"
    50575059)
    50585060)
     
    50795081fg "0,65535,0"
    50805082)
    5081 xt "31250,77625,32000,78375"
     5083xt "27250,75625,28000,76375"
    50825084)
    50835085tg (CPTG
     
    50905092font "arial,8,0"
    50915093)
    5092 xt "33000,77500,37800,78500"
     5094xt "29000,75500,33800,76500"
    50935095st "config_start"
    5094 blo "33000,78300"
     5096blo "29000,76300"
    50955097)
    50965098)
     
    51155117fg "0,65535,0"
    51165118)
    5117 xt "31250,73625,32000,74375"
     5119xt "27250,71625,28000,72375"
    51185120)
    51195121tg (CPTG
     
    51265128font "arial,8,0"
    51275129)
    5128 xt "33000,73500,38300,74500"
     5130xt "29000,71500,34300,72500"
    51295131st "ram_write_ea"
    5130 blo "33000,74300"
     5132blo "29000,72300"
    51315133)
    51325134)
     
    51535155fg "0,65535,0"
    51545156)
    5155 xt "31250,74625,32000,75375"
     5157xt "27250,72625,28000,73375"
    51565158)
    51575159tg (CPTG
     
    51645166font "arial,8,0"
    51655167)
    5166 xt "33000,74500,39300,75500"
     5168xt "29000,72500,35300,73500"
    51675169st "ram_write_ready"
    5168 blo "33000,75300"
     5170blo "29000,73300"
    51695171)
    51705172)
     
    51905192fg "0,65535,0"
    51915193)
    5192 xt "31250,80625,32000,81375"
     5194xt "27250,78625,28000,79375"
    51935195)
    51945196tg (CPTG
     
    52015203font "arial,8,0"
    52025204)
    5203 xt "33000,80500,36000,81500"
     5205xt "29000,78500,32000,79500"
    52045206st "roi_max"
    5205 blo "33000,81300"
     5207blo "29000,79300"
    52065208)
    52075209)
     
    52295231fg "0,65535,0"
    52305232)
    5231 xt "63000,70625,63750,71375"
     5233xt "59000,70625,59750,71375"
    52325234)
    52335235tg (CPTG
     
    52405242font "arial,8,0"
    52415243)
    5242 xt "58600,70500,62000,71500"
     5244xt "54600,70500,58000,71500"
    52435245st "wiz_busy"
    52445246ju 2
    5245 blo "62000,71300"
     5247blo "58000,71300"
    52465248)
    52475249)
     
    52665268fg "0,65535,0"
    52675269)
    5268 xt "63000,74625,63750,75375"
     5270xt "59000,74625,59750,75375"
    52695271)
    52705272tg (CPTG
     
    52775279font "arial,8,0"
    52785280)
    5279 xt "50200,74500,62000,75500"
     5281xt "46200,74500,58000,75500"
    52805282st "wiz_number_of_channels : (3:0)"
    52815283ju 2
    5282 blo "62000,75300"
     5284blo "58000,75300"
    52835285)
    52845286)
     
    53065308fg "0,65535,0"
    53075309)
    5308 xt "63000,73625,63750,74375"
     5310xt "59000,73625,59750,74375"
    53095311)
    53105312tg (CPTG
     
    53175319font "arial,8,0"
    53185320)
    5319 xt "42100,73500,62000,74500"
     5321xt "38100,73500,58000,74500"
    53205322st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
    53215323ju 2
    5322 blo "62000,74300"
     5324blo "58000,74300"
    53235325)
    53245326)
     
    53475349fg "0,65535,0"
    53485350)
    5349 xt "63000,71625,63750,72375"
     5351xt "59000,71625,59750,72375"
    53505352)
    53515353tg (CPTG
     
    53585360font "arial,8,0"
    53595361)
    5360 xt "56900,71500,62000,72500"
     5362xt "52900,71500,58000,72500"
    53615363st "wiz_write_ea"
    53625364ju 2
    5363 blo "62000,72300"
     5365blo "58000,72300"
    53645366)
    53655367)
     
    53865388fg "0,65535,0"
    53875389)
    5388 xt "63000,75625,63750,76375"
     5390xt "59000,75625,59750,76375"
    53895391)
    53905392tg (CPTG
     
    53975399font "arial,8,0"
    53985400)
    5399 xt "56500,75500,62000,76500"
     5401xt "52500,75500,58000,76500"
    54005402st "wiz_write_end"
    54015403ju 2
    5402 blo "62000,76300"
     5404blo "58000,76300"
    54035405)
    54045406)
     
    54255427fg "0,65535,0"
    54265428)
    5427 xt "63000,76625,63750,77375"
     5429xt "59000,76625,59750,77375"
    54285430)
    54295431tg (CPTG
     
    54365438font "arial,8,0"
    54375439)
    5438 xt "55400,76500,62000,77500"
     5440xt "51400,76500,58000,77500"
    54395441st "wiz_write_header"
    54405442ju 2
    5441 blo "62000,77300"
     5443blo "58000,77300"
    54425444)
    54435445)
     
    54645466fg "0,65535,0"
    54655467)
    5466 xt "63000,72625,63750,73375"
     5468xt "59000,72625,59750,73375"
    54675469)
    54685470tg (CPTG
     
    54755477font "arial,8,0"
    54765478)
    5477 xt "52600,72500,62000,73500"
     5479xt "48600,72500,58000,73500"
    54785480st "wiz_write_length : (16:0)"
    54795481ju 2
    5480 blo "62000,73300"
     5482blo "58000,73300"
    54815483)
    54825484)
     
    55045506fg "0,65535,0"
    55055507)
    5506 xt "31250,87625,32000,88375"
     5508xt "27250,85625,28000,86375"
    55075509)
    55085510tg (CPTG
     
    55155517font "arial,8,0"
    55165518)
    5517 xt "33000,87500,36400,88500"
     5519xt "29000,85500,32400,86500"
    55185520st "roi_array"
    5519 blo "33000,88300"
     5521blo "29000,86300"
    55205522)
    55215523)
     
    55425544fg "0,65535,0"
    55435545)
    5544 xt "31250,81625,32000,82375"
     5546xt "27250,79625,28000,80375"
    55455547)
    55465548tg (CPTG
     
    55535555font "arial,8,0"
    55545556)
    5555 xt "33000,81500,42100,82500"
     5557xt "29000,79500,38100,80500"
    55565558st "package_length : (15:0)"
    5557 blo "33000,82300"
     5559blo "29000,80300"
    55585560)
    55595561)
     
    55815583fg "0,65535,0"
    55825584)
    5583 xt "31250,78625,32000,79375"
     5585xt "27250,76625,28000,77375"
    55845586)
    55855587tg (CPTG
     
    55925594font "arial,8,0"
    55935595)
    5594 xt "33000,78500,38600,79500"
     5596xt "29000,76500,34600,77500"
    55955597st "config_started"
    5596 blo "33000,79300"
     5598blo "29000,77300"
    55975599)
    55985600)
     
    56195621fg "0,65535,0"
    56205622)
    5621 xt "63000,77625,63750,78375"
     5623xt "59000,77625,59750,78375"
    56225624)
    56235625tg (CPTG
     
    56305632font "arial,8,0"
    56315633)
    5632 xt "59000,77500,62000,78500"
     5634xt "55000,77500,58000,78500"
    56335635st "wiz_ack"
    56345636ju 2
    5635 blo "62000,78300"
     5637blo "58000,78300"
    56365638)
    56375639)
     
    56565658fg "0,65535,0"
    56575659)
    5658 xt "31250,75625,32000,76375"
     5660xt "27250,73625,28000,74375"
    56595661)
    56605662tg (CPTG
     
    56675669font "arial,8,0"
    56685670)
    5669 xt "33000,75500,40800,76500"
     5671xt "29000,73500,36800,74500"
    56705672st "ram_write_ready_ack"
    5671 blo "33000,76300"
     5673blo "29000,74300"
    56725674)
    56735675)
     
    56965698lineWidth 2
    56975699)
    5698 xt "32000,70000,63000,90000"
     5700xt "28000,68000,59000,88000"
    56995701)
    57005702oxt "15000,6000,23000,16000"
     
    57095711font "arial,8,1"
    57105712)
    5711 xt "32350,90000,38550,91000"
     5713xt "28350,88000,34550,89000"
    57125714st "FACT_FAD_lib"
    5713 blo "32350,90800"
     5715blo "28350,88800"
    57145716tm "BdLibraryNameMgr"
    57155717)
     
    57195721font "arial,8,1"
    57205722)
    5721 xt "32350,91000,39650,92000"
     5723xt "28350,89000,35650,90000"
    57225724st "memory_manager"
    5723 blo "32350,91800"
     5725blo "28350,89800"
    57245726tm "CptNameMgr"
    57255727)
     
    57295731font "arial,8,1"
    57305732)
    5731 xt "32350,92000,42850,93000"
     5733xt "28350,90000,38850,91000"
    57325734st "I_main_memory_manager"
    5733 blo "32350,92800"
     5735blo "28350,90800"
    57345736tm "InstanceNameMgr"
    57355737)
     
    57465748font "Courier New,8,0"
    57475749)
    5748 xt "32000,68400,61500,70000"
     5750xt "31000,66400,60500,68000"
    57495751st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer ) 
    57505752RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
     
    57725774fg "49152,49152,49152"
    57735775)
    5774 xt "32250,88250,33750,89750"
     5776xt "28250,86250,29750,87750"
    57755777iconName "VhdlFileViewIcon.png"
    57765778iconMaskName "VhdlFileViewIcon.msk"
     
    57975799font "Courier New,8,0"
    57985800)
    5799 xt "-172000,101200,-149500,102000"
     5801xt "-172000,100400,-149500,101200"
    58005802st "SIGNAL wiz_busy               : std_logic
    58015803"
     
    58175819font "Courier New,8,0"
    58185820)
    5819 xt "-172000,103600,-128500,104400"
     5821xt "-172000,102800,-128500,103600"
    58205822st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
    58215823"
     
    58385840font "Courier New,8,0"
    58395841)
    5840 xt "-172000,106000,-122500,106800"
     5842xt "-172000,105200,-122500,106000"
    58415843st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
    58425844"
     
    58605862font "Courier New,8,0"
    58615863)
    5862 xt "-172000,102800,-122500,103600"
     5864xt "-172000,102000,-122500,102800"
    58635865st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
    58645866"
     
    58815883font "Courier New,8,0"
    58825884)
    5883 xt "-172000,102000,-122500,102800"
     5885xt "-172000,101200,-122500,102000"
    58845886st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
    58855887"
     
    59015903font "Courier New,8,0"
    59025904)
    5903 xt "-172000,104400,-128500,105200"
     5905xt "-172000,103600,-128500,104400"
    59045906st "SIGNAL wiz_write_end          : std_logic                                    := '0'
    59055907"
     
    59215923font "Courier New,8,0"
    59225924)
    5923 xt "-172000,105200,-128500,106000"
     5925xt "-172000,104400,-128500,105200"
    59245926st "SIGNAL wiz_write_header       : std_logic                                    := '0'
    59255927"
     
    69326934sl 0
    69336935ro 90
    6934 xt "-29000,65625,-27500,66375"
     6936xt "-28000,66625,-26500,67375"
    69356937)
    69366938(Line
     
    69386940sl 0
    69396941ro 90
    6940 xt "-27500,66000,-27000,66000"
    6941 pts [
    6942 "-27000,66000"
    6943 "-27500,66000"
     6942xt "-26500,67000,-26000,67000"
     6943pts [
     6944"-26000,67000"
     6945"-26500,67000"
    69446946]
    69456947)
     
    69566958va (VaSet
    69576959)
    6958 xt "-35900,65500,-30000,66500"
     6960xt "-34900,66500,-29000,67500"
    69596961st "drs_channel_id"
    69606962ju 2
    6961 blo "-30000,66300"
     6963blo "-29000,67300"
    69626964tm "WireNameMgr"
    69636965)
     
    1097210974font "Courier New,8,0"
    1097310975)
    10974 xt "-172000,100400,-149500,101200"
     10976xt "-172000,99600,-149500,100400"
    1097510977st "SIGNAL wiz_ack                : std_logic
    1097610978"
     
    1295912961)
    1296012962*431 (Net
    12961 uid 10449,0
    12962 decl (Decl
    12963 n "trigger_out"
    12964 t "std_logic"
    12965 preAdd 0
    12966 posAdd 0
    12967 o 120
    12968 suid 240,0
    12969 )
    12970 declText (MLText
    12971 uid 10450,0
    12972 va (VaSet
    12973 font "Courier New,8,0"
    12974 )
    12975 xt "-172000,99600,-149500,100400"
    12976 st "SIGNAL trigger_out            : std_logic
    12977 "
    12978 )
    12979 )
    12980 *432 (Net
    1298112963uid 10465,0
    1298212964lang 2
     
    1300212984)
    1300312985)
    13004 *433 (Net
     12986*432 (Net
    1300512987uid 10627,0
    1300612988decl (Decl
     
    1302013002)
    1302113003)
    13022 *434 (Net
     13004*433 (Net
    1302313005uid 10635,0
    1302413006decl (Decl
     
    1303813020)
    1303913021)
    13040 *435 (Net
     13022*434 (Net
    1304113023uid 10721,0
    1304213024decl (Decl
     
    1305613038)
    1305713039)
    13058 *436 (PortIoOut
     13040*435 (PortIoOut
    1305913041uid 10729,0
    1306013042shape (CompositeShape
     
    1310013082)
    1310113083)
    13102 *437 (Net
     13084*436 (Net
    1310313085uid 10735,0
    1310413086decl (Decl
     
    1311813100)
    1311913101)
    13120 *438 (PortIoOut
     13102*437 (PortIoOut
    1312113103uid 10743,0
    1312213104shape (CompositeShape
     
    1316213144)
    1316313145)
    13164 *439 (Net
     13146*438 (Net
    1316513147uid 10749,0
    1316613148decl (Decl
     
    1318013162)
    1318113163)
    13182 *440 (PortIoOut
     13164*439 (PortIoOut
    1318313165uid 10757,0
    1318413166shape (CompositeShape
     
    1322413206)
    1322513207)
    13226 *441 (SaComponent
     13208*440 (SaComponent
    1322713209uid 11209,0
    1322813210optionalChildren [
    13229 *442 (CptPort
     13211*441 (CptPort
    1323013212uid 11181,0
    1323113213ps "OnEdgeStrategy"
     
    1326013242)
    1326113243)
    13262 *443 (CptPort
     13244*442 (CptPort
    1326313245uid 11185,0
    1326413246ps "OnEdgeStrategy"
     
    1329513277)
    1329613278)
    13297 *444 (CptPort
     13279*443 (CptPort
    1329813280uid 11189,0
    1329913281ps "OnEdgeStrategy"
     
    1333013312)
    1333113313)
    13332 *445 (CptPort
     13314*444 (CptPort
    1333313315uid 11193,0
    1333413316ps "OnEdgeStrategy"
     
    1336513347)
    1336613348)
    13367 *446 (CptPort
     13349*445 (CptPort
    1336813350uid 11197,0
    1336913351ps "OnEdgeStrategy"
     
    1339813380)
    1339913381)
    13400 *447 (CptPort
     13382*446 (CptPort
    1340113383uid 11201,0
    1340213384ps "OnEdgeStrategy"
     
    1343113413)
    1343213414)
    13433 *448 (CptPort
     13415*447 (CptPort
    1343413416uid 11205,0
    1343513417ps "OnEdgeStrategy"
     
    1346413446)
    1346513447)
    13466 *449 (CptPort
     13448*448 (CptPort
    1346713449uid 12693,0
    1346813450ps "OnEdgeStrategy"
     
    1351613498stg "VerticalLayoutStrategy"
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    1447714459)
     
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     14525blo "71000,64300"
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    1454514527)
     
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    1455414536)
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    1457914561)
     
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     14604st "continous_pulser"
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    1480214784)
    1480314785)
     
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    1481214794)
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     14897blo "219435,60094"
    1491614898)
    1491714899)
     
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    1492614908)
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    17759 xt "63750,72000,87250,79000"
    17760 pts [
    17761 "63750,73000"
    17762 "67000,73000"
    17763 "67000,79000"
    17764 "85000,79000"
    17765 "85000,72000"
    17766 "87250,72000"
     17735xt "59750,73000,87250,73000"
     17736pts [
     17737"59750,73000"
     17738"87250,73000"
    1776717739]
    1776817740)
     
    1778317755va (VaSet
    1778417756)
    17785 xt "64000,72000,73400,73000"
     17757xt "60000,72000,69400,73000"
    1778617758st "wiz_write_length : (16:0)"
    17787 blo "64000,72800"
     17759blo "60000,72800"
    1778817760tm "WireNameMgr"
    1778917761)
     
    1779117763on &157
    1779217764)
    17793 *619 (Wire
     17765*618 (Wire
    1779417766uid 2488,0
    1779517767shape (OrthoPolyLine
     
    1779917771lineWidth 2
    1780017772)
    17801 xt "63750,73000,87250,74000"
    17802 pts [
    17803 "63750,74000"
    17804 "84000,74000"
    17805 "84000,73000"
    17806 "87250,73000"
     17773xt "59750,74000,87250,74000"
     17774pts [
     17775"59750,74000"
     17776"87250,74000"
    1780717777]
    1780817778)
     
    1782317793va (VaSet
    1782417794)
    17825 xt "64000,73000,82800,74000"
     17795xt "60000,73000,78800,74000"
    1782617796st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
    17827 blo "64000,73800"
     17797blo "60000,73800"
    1782817798tm "WireNameMgr"
    1782917799)
     
    1783117801on &158
    1783217802)
    17833 *620 (Wire
     17803*619 (Wire
    1783417804uid 2494,0
    1783517805shape (OrthoPolyLine
     
    1783917809lineWidth 2
    1784017810)
    17841 xt "63750,74000,87250,80000"
    17842 pts [
    17843 "63750,75000"
    17844 "66000,75000"
    17845 "66000,80000"
    17846 "86000,80000"
    17847 "86000,74000"
    17848 "87250,74000"
     17811xt "59750,75000,87250,75000"
     17812pts [
     17813"59750,75000"
     17814"87250,75000"
    1784917815]
    1785017816)
     
    1786517831va (VaSet
    1786617832)
    17867 xt "64000,74000,75800,75000"
     17833xt "60000,74000,71800,75000"
    1786817834st "wiz_number_of_channels : (3:0)"
    17869 blo "64000,74800"
     17835blo "60000,74800"
    1787017836tm "WireNameMgr"
    1787117837)
     
    1787317839on &159
    1787417840)
    17875 *621 (Wire
     17841*620 (Wire
    1787617842uid 2500,0
    1787717843shape (OrthoPolyLine
     
    1788017846vasetType 3
    1788117847)
    17882 xt "63750,75000,87250,76000"
    17883 pts [
    17884 "63750,76000"
    17885 "84000,76000"
    17886 "84000,75000"
    17887 "87250,75000"
     17848xt "59750,76000,87250,76000"
     17849pts [
     17850"59750,76000"
     17851"87250,76000"
    1788817852]
    1788917853)
     
    1790317867va (VaSet
    1790417868)
    17905 xt "64000,75000,69500,76000"
     17869xt "60000,75000,65500,76000"
    1790617870st "wiz_write_end"
    17907 blo "64000,75800"
     17871blo "60000,75800"
    1790817872tm "WireNameMgr"
    1790917873)
     
    1791117875on &160
    1791217876)
    17913 *622 (Wire
     17877*621 (Wire
    1791417878uid 2506,0
    1791517879shape (OrthoPolyLine
     
    1791817882vasetType 3
    1791917883)
    17920 xt "63750,76000,87250,77000"
    17921 pts [
    17922 "63750,77000"
    17923 "71000,77000"
    17924 "71000,76000"
    17925 "87250,76000"
     17884xt "59750,77000,87250,77000"
     17885pts [
     17886"59750,77000"
     17887"87250,77000"
    1792617888]
    1792717889)
     
    1794117903va (VaSet
    1794217904)
    17943 xt "64000,76000,70600,77000"
     17905xt "60000,76000,66600,77000"
    1794417906st "wiz_write_header"
    17945 blo "64000,76800"
     17907blo "60000,76800"
    1794617908tm "WireNameMgr"
    1794717909)
     
    1794917911on &161
    1795017912)
    17951 *623 (Wire
     17913*622 (Wire
    1795217914uid 2576,0
    1795317915shape (OrthoPolyLine
     
    1795617918vasetType 3
    1795717919)
    17958 xt "750,67000,31250,74000"
    17959 pts [
    17960 "750,67000"
    17961 "26000,67000"
    17962 "26000,74000"
    17963 "31250,74000"
     17920xt "750,72000,27250,72000"
     17921pts [
     17922"750,72000"
     17923"27250,72000"
    1796417924]
    1796517925)
     
    1797917939va (VaSet
    1798017940)
    17981 xt "2000,66000,7300,67000"
     17941xt "1000,71000,6300,72000"
    1798217942st "ram_write_ea"
    17983 blo "2000,66800"
     17943blo "1000,71800"
    1798417944tm "WireNameMgr"
    1798517945)
     
    1798717947on &162
    1798817948)
    17989 *624 (Wire
     17949*623 (Wire
    1799017950uid 2582,0
    1799117951shape (OrthoPolyLine
     
    1799417954vasetType 3
    1799517955)
    17996 xt "750,68000,31250,75000"
    17997 pts [
    17998 "750,68000"
    17999 "25000,68000"
    18000 "25000,75000"
    18001 "31250,75000"
     17956xt "750,73000,27250,73000"
     17957pts [
     17958"750,73000"
     17959"27250,73000"
    1800217960]
    1800317961)
     
    1801717975va (VaSet
    1801817976)
    18019 xt "2000,67000,8300,68000"
     17977xt "1000,72000,7300,73000"
    1802017978st "ram_write_ready"
    18021 blo "2000,67800"
     17979blo "1000,72800"
    1802217980tm "WireNameMgr"
    1802317981)
     
    1802517983on &163
    1802617984)
    18027 *625 (Wire
     17985*624 (Wire
    1802817986uid 2588,0
    1802917987shape (OrthoPolyLine
     
    1803217990vasetType 3
    1803317991)
    18034 xt "750,73000,31250,78000"
    18035 pts [
    18036 "750,73000"
    18037 "23000,73000"
    18038 "23000,78000"
    18039 "31250,78000"
     17992xt "750,76000,27250,76000"
     17993pts [
     17994"750,76000"
     17995"27250,76000"
    1804017996]
    1804117997)
     
    1805618012va (VaSet
    1805718013)
    18058 xt "1000,72000,5800,73000"
     18014xt "1000,75000,5800,76000"
    1805918015st "config_start"
    18060 blo "1000,72800"
     18016blo "1000,75800"
    1806118017tm "WireNameMgr"
    1806218018)
     
    1806418020on &164
    1806518021)
    18066 *626 (Wire
     18022*625 (Wire
    1806718023uid 2594,0
    1806818024shape (OrthoPolyLine
     
    1807118027vasetType 3
    1807218028)
    18073 xt "750,75000,31250,80000"
    18074 pts [
    18075 "750,75000"
    18076 "21000,75000"
    18077 "21000,80000"
    18078 "31250,80000"
     18029xt "750,78000,27250,78000"
     18030pts [
     18031"750,78000"
     18032"27250,78000"
    1807918033]
    1808018034)
     
    1809418048va (VaSet
    1809518049)
    18096 xt "1000,74000,6100,75000"
     18050xt "1000,77000,6100,78000"
    1809718051st "config_ready"
    18098 blo "1000,74800"
     18052blo "1000,77800"
    1809918053tm "WireNameMgr"
    1810018054)
     
    1810218056on &165
    1810318057)
    18104 *627 (Wire
     18058*626 (Wire
    1810518059uid 2600,0
    1810618060shape (OrthoPolyLine
     
    1810918063vasetType 3
    1811018064)
    18111 xt "750,77000,31250,81000"
    18112 pts [
    18113 "750,77000"
    18114 "20000,77000"
    18115 "20000,81000"
    18116 "31250,81000"
     18065xt "750,79000,27250,79000"
     18066pts [
     18067"750,79000"
     18068"27250,79000"
    1811718069]
    1811818070)
     
    1813218084va (VaSet
    1813318085)
    18134 xt "1000,76000,4000,77000"
     18086xt "1000,78000,4000,79000"
    1813518087st "roi_max"
    18136 blo "1000,76800"
     18088blo "1000,78800"
    1813718089tm "WireNameMgr"
    1813818090)
     
    1814018092on &166
    1814118093)
    18142 *628 (Wire
     18094*627 (Wire
    1814318095uid 2642,0
    1814418096shape (OrthoPolyLine
     
    1814818100lineWidth 2
    1814918101)
    18150 xt "750,78000,31250,82000"
    18151 pts [
    18152 "750,78000"
    18153 "19000,78000"
    18154 "19000,82000"
    18155 "31250,82000"
     18102xt "750,80000,27250,80000"
     18103pts [
     18104"750,80000"
     18105"27250,80000"
    1815618106]
    1815718107)
     
    1817218122va (VaSet
    1817318123)
    18174 xt "1000,77000,10100,78000"
     18124xt "1000,79000,10100,80000"
    1817518125st "package_length : (15:0)"
    18176 blo "1000,77800"
     18126blo "1000,79800"
    1817718127tm "WireNameMgr"
    1817818128)
     
    1818018130on &167
    1818118131)
    18182 *629 (Wire
     18132*628 (Wire
    1818318133uid 2778,0
    1818418134shape (OrthoPolyLine
     
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    1821918169)
    18220 *630 (Wire
     18170*629 (Wire
    1822118171uid 2786,0
    1822218172shape (OrthoPolyLine
     
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    1825918209)
    18260 *631 (Wire
     18210*630 (Wire
    1826118211uid 3888,0
    1826218212optionalChildren [
    18263 *632 (BdJunction
     18213*631 (BdJunction
    1826418214uid 4230,0
    1826518215ps "OnConnectorStrategy"
     
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    1827418224)
    18275 *633 (BdJunction
     18225*632 (BdJunction
    1827618226uid 4244,0
    1827718227ps "OnConnectorStrategy"
     
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    1832518275)
    18326 *634 (Wire
     18276*633 (Wire
    1832718277uid 3984,0
    1832818278shape (OrthoPolyLine
     
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    1836618316)
    18367 *635 (Wire
     18317*634 (Wire
    1836818318uid 4042,0
    1836918319shape (OrthoPolyLine
     
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    1840418354)
    18405 *636 (Wire
     18355*635 (Wire
    1840618356uid 4226,0
    1840718357shape (OrthoPolyLine
     
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    1842018370start &189
    18421 end &632
     18371end &631
    1842218372sat 32
    1842318373eat 32
     
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    1844418394)
    18445 *637 (Wire
     18395*636 (Wire
    1844618396uid 4240,0
    1844718397shape (OrthoPolyLine
     
    1845918409)
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    18461 end &633
     18411end &632
    1846218412sat 32
    1846318413eat 32
     
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    1848318433)
    18484 *638 (Wire
     18434*637 (Wire
    1848518435uid 4272,0
    1848618436shape (OrthoPolyLine
     
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    1852118471)
    18522 *639 (Wire
     18472*638 (Wire
    1852318473uid 4401,0
    1852418474shape (OrthoPolyLine
     
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    1855918509)
    18560 *640 (Wire
     18510*639 (Wire
    1856118511uid 4407,0
    1856218512shape (OrthoPolyLine
     
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    1859718547)
    18598 *641 (Wire
     18548*640 (Wire
    1859918549uid 4419,0
    1860018550shape (OrthoPolyLine
     
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    1863518585)
    18636 *642 (Wire
     18586*641 (Wire
    1863718587uid 4537,0
    1863818588shape (OrthoPolyLine
     
    1864218592lineWidth 2
    1864318593)
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     18594xt "-26000,67000,-21750,67000"
    1864518595pts [
    1864618596"-21750,67000"
    18647 "-25000,67000"
    18648 "-25000,66000"
    18649 "-27000,66000"
     18597"-26000,67000"
    1865018598]
    1865118599)
     
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    1867718625)
    18678 *643 (Wire
     18626*642 (Wire
    1867918627uid 4545,0
    1868018628shape (OrthoPolyLine
     
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    1871418662)
    18715 *644 (Wire
     18663*643 (Wire
    1871618664uid 4671,0
    1871718665shape (OrthoPolyLine
     
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    1875218700)
    18753 *645 (Wire
     18701*644 (Wire
    1875418702uid 4679,0
    1875518703shape (OrthoPolyLine
     
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    1879018738)
    18791 *646 (Wire
     18739*645 (Wire
    1879218740uid 4687,0
    1879318741shape (OrthoPolyLine
     
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    1882818776)
    18829 *647 (Wire
     18777*646 (Wire
    1883018778uid 4695,0
    1883118779shape (OrthoPolyLine
     
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    1886618814)
    18867 *648 (Wire
     18815*647 (Wire
    1886818816uid 4743,0
    1886918817shape (OrthoPolyLine
     
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    1890418852)
    18905 *649 (Wire
     18853*648 (Wire
    1890618854uid 4757,0
    1890718855optionalChildren [
    18908 *650 (BdJunction
     18856*649 (BdJunction
    1890918857uid 6076,0
    1891018858ps "OnConnectorStrategy"
     
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     18884end *650 (BdJunction
    1893718885uid 6080,0
    1893818886ps "OnConnectorStrategy"
     
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    1896918917)
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     18918*651 (Wire
    1897118919uid 4948,0
    1897218920shape (OrthoPolyLine
     
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    1900718955)
    19008 *653 (Wire
     18956*652 (Wire
    1900918957uid 4962,0
    1901018958shape (OrthoPolyLine
     
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    1904518993)
    19046 *654 (Wire
     18994*653 (Wire
    1904718995uid 5090,0
    1904818996shape (OrthoPolyLine
     
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    1908419032)
    19085 *655 (Wire
     19033*654 (Wire
    1908619034uid 5098,0
    1908719035shape (OrthoPolyLine
     
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    1911819066)
    19119 *656 (Wire
     19067*655 (Wire
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    1912119069shape (OrthoPolyLine
     
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    1915519103)
    19156 *657 (Wire
     19104*656 (Wire
    1915719105uid 5114,0
    1915819106shape (OrthoPolyLine
     
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    1919419142)
    19195 *658 (Wire
     19143*657 (Wire
    1919619144uid 5122,0
    1919719145shape (OrthoPolyLine
     
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    1923119179)
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     19180*658 (Wire
    1923319181uid 5130,0
    1923419182shape (OrthoPolyLine
     
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    1926819216)
    19269 *660 (Wire
     19217*659 (Wire
    1927019218uid 5138,0
    1927119219optionalChildren [
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     19220*660 (BdJunction
    1927319221uid 5400,0
    1927419222ps "OnConnectorStrategy"
     
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    1932119269)
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     19270*661 (Wire
    1932319271uid 5146,0
    1932419272shape (OrthoPolyLine
     
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    1935719305)
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     19306*662 (Wire
    1935919307uid 5168,0
    1936019308shape (OrthoPolyLine
     
    1936319311vasetType 3
    1936419312)
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     19313xt "18000,86000,27250,88000"
    1936619314pts [
    1936719315"18000,88000"
    19368 "31250,88000"
    19369 ]
    19370 )
    19371 start &661
     19316"24000,88000"
     19317"24000,86000"
     19318"27250,86000"
     19319]
     19320)
     19321start &660
    1937219322end &147
    1937319323sat 32
     
    1938419334va (VaSet
    1938519335)
    19386 xt "28000,87000,31400,88000"
     19336xt "24000,85000,27400,86000"
    1938719337st "roi_array"
    19388 blo "28000,87800"
     19338blo "24000,85800"
    1938919339tm "WireNameMgr"
    1939019340)
     
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    1939319343)
    19394 *664 (Wire
     19344*663 (Wire
    1939519345uid 5184,0
    1939619346shape (OrthoPolyLine
     
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    1943019380)
    19431 *665 (Wire
     19381*664 (Wire
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    1943319383shape (OrthoPolyLine
     
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    1946719417)
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     19418*665 (Wire
    1946919419uid 5222,0
    1947019420shape (OrthoPolyLine
     
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    1950719457)
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     19458*666 (Wire
    1950919459uid 5404,0
    1951019460shape (OrthoPolyLine
     
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    1954419494)
    19545 *668 (Wire
     19495*667 (Wire
    1954619496uid 5474,0
    1954719497shape (OrthoPolyLine
     
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    1958119531)
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     19532*668 (Wire
    1958319533uid 5480,0
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    1961819568)
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     19569*669 (Wire
    1962019570uid 5582,0
    1962119571shape (OrthoPolyLine
     
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    1965319603)
    19654 *671 (Wire
     19604*670 (Wire
    1965519605uid 5602,0
    1965619606optionalChildren [
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    19658 *672 (BdJunction
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    19660 ps "OnConnectorStrategy"
    19661 shape (Circle
    19662 uid 6087,0
    19663 va (VaSet
    19664 vasetType 1
    19665 )
    19666 xt "27600,46600,28400,47400"
    19667 radius 400
    19668 )
    19669 )
     19607&650
    1967019608]
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     19649*671 (Wire
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    1974619684)
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     19685*672 (Wire
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    1978419722)
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    1978719725shape (OrthoPolyLine
     
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    1982019758)
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    1985819796)
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    1989219830)
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    2000619944)
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    2004619984)
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    2019820136)
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    20208 "750,74000"
    20209 "22000,74000"
    20210 "22000,79000"
    20211 "31250,79000"
     20144xt "750,77000,27250,77000"
     20145pts [
     20146"750,77000"
     20147"27250,77000"
    2021220148]
    2021320149)
     
    2022720163va (VaSet
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     20165xt "1000,76000,8200,77000"
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    20322 "28000,71000"
    20323 "28000,47000"
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    20340 va (VaSet
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    20398 "-52750,67000"
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     20293pts [
     20294"-61000,68000"
     20295"-52750,68000"
    2039920296]
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    20580 "63750,78000"
    20581 "84000,78000"
    20582 "84000,77000"
    20583 "87250,77000"
     20475xt "59750,78000,87250,78000"
     20476pts [
     20477"59750,78000"
     20478"87250,78000"
    2058420479]
    2058520480)
     
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    2060520500)
     
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    2129221187)
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     21226*714 (Wire
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     21264*715 (Wire
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    21420 )
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    21428 pts [
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    21430 "-54000,72000"
    21431 "-54000,68000"
    21432 "-52750,68000"
    21433 ]
    21434 )
    21435 start &30
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    21452 blo "-25750,71800"
    21453 tm "WireNameMgr"
    21454 )
    21455 )
    21456 on &431
    21457 )
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     21301*716 (Wire
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    21466 pts [
    21467 "31250,76000"
    21468 "24000,76000"
    21469 "24000,69000"
    21470 "750,69000"
     21308xt "750,74000,27250,74000"
     21309pts [
     21310"27250,74000"
     21311"750,74000"
    2147121312]
    2147221313)
     
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     21330xt "1000,73000,8800,74000"
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     21332blo "1000,73800"
    2149221333tm "WireNameMgr"
    2149321334)
    2149421335)
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    21496 )
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     21337)
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     21372)
     21373*718 (Wire
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    2156421405)
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     21407)
     21408*719 (Wire
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    2157921420)
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     21421end &446
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    2159921440)
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     21442)
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     21477)
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    2174321584)
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     21586)
     21587*724 (Wire
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    2175821599)
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     21623on &436
     21624)
     21625*725 (Wire
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    2179621637)
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     21638start &444
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    2181921660)
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    21822 *731 (Wire
     21661on &438
     21662)
     21663*726 (Wire
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    21857 )
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     21698)
     21699*727 (Wire
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    21928 )
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     21770*729 (Wire
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     21784end &458
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    2196421805)
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    21975 pts [
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    21977 "-55250,72000"
    21978 ]
    21979 )
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    21997 st "trigger_out"
    21998 blo "-54000,71800"
    21999 tm "WireNameMgr"
    22000 )
    22001 )
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    22003 )
    22004 *736 (Wire
     21806on &472
     21807)
     21808*730 (Wire
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    2201821822)
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     21823start &455
     21824end &474
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    2204121845)
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    22043 )
    22044 *737 (Wire
     21846on &483
     21847)
     21848*731 (Wire
    2204521849uid 12649,0
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    2205221856pts [
    2205321857"-21750,74000"
    22054 "-38000,74000"
    2205521858"-55250,74000"
    2205621859]
    2205721860)
    2205821861start &66
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     21862end &477
    2206021863sat 32
    2206121864eat 32
     
    2207721880)
    2207821881)
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    22080 )
    22081 *738 (Wire
     21882on &484
     21883)
     21884*732 (Wire
    2208221885uid 12655,0
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    2209421897)
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     21899end &478
    2209721900sat 32
    2209821901eat 32
     
    2211421917)
    2211521918)
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    22117 )
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     21919on &485
     21920)
     21921*733 (Wire
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    2213221935]
    2213321936)
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     21937end &479
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    2215521958)
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     21959*734 (Wire
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    2216721970]
    2216821971)
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     21972start &448
     21973end &487
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    2219121994)
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    22194 *741 (Wire
     21995on &486
     21996)
     21997*735 (Wire
    2219521998uid 13143,0
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    22204 "63750,62000"
    22205 ]
    22206 )
    22207 end &490
     22004xt "72750,62000,78000,62000"
     22005pts [
     22006"78000,62000"
     22007"72750,62000"
     22008]
     22009)
     22010end &489
    2220822011sat 16
    2220922012eat 32
     
    2221922022va (VaSet
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    2222222025st "CLK_25"
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     22026blo "74000,61800"
    2222422027tm "WireNameMgr"
    2222522028)
     
    2222722030on &188
    2222822031)
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     22032*736 (Wire
    2223022033uid 13159,0
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     22039xt "72750,63000,87250,67000"
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    2223822041"87250,67000"
    22239 "79000,67000"
    22240 "79000,63000"
    22241 "63750,63000"
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     22043"77000,63000"
     22044"72750,63000"
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     22048end &490
    2224622049sat 32
    2224722050eat 32
     
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    2226422067)
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     22069)
     22070*737 (Wire
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    2227322076lineWidth 2
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     22078xt "72750,64000,87250,68000"
    2227622079pts [
    2227722080"87250,68000"
    22278 "78000,68000"
    22279 "78000,64000"
    22280 "63750,64000"
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     22082"76000,64000"
     22083"72750,64000"
    2228122084]
    2228222085)
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     22087end &491
    2228522088sat 32
    2228622089eat 32
     
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    2230422107)
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    22306 )
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     22108on &497
     22109)
     22110*738 (Wire
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    22317 "42000,62000"
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     22120"54000,62000"
     22121]
     22122)
     22123start &492
     22124end &501
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    2232322126eat 32
     
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     22138xt "53250,61000,56450,62000"
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     22140blo "53250,61800"
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     22146*739 (Wire
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     22156"54000,60000"
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     22159end &506
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     22173)
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     22176blo "54000,59800"
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     22182*740 (Wire
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     22192"45000,61000"
     22193]
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    2239522197eat 16
     
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     22419end &530
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     22455end &539
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     22478)
     22479*748 (Wire
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    22692 end &542
     22492start &534
     22493end &541
    2269322494sat 32
    2269422495eat 32
     
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    2271322514)
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     22516)
     22517*749 (Wire
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    22731 end &544
     22531start &532
     22532end &543
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    2273322534eat 32
     
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    2275322554)
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    22755 )
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     22556)
     22557*750 (Wire
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     22571end &548
    2277122572sat 32
    2277222573eat 32
     
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    2278922590)
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     22592)
     22593*751 (Wire
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     22606start &550
     22607end &588
    2280722608sat 32
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    2282722628)
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     22630)
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    2284322644)
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     22646end &563
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    2284722648eat 32
     
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    22867 )
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     22669*753 (Wire
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     22682end &578
    2288222683es 0
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    2290322704)
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    2291822719)
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     22720end &580
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    2292122722sat 16
     
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     22743on &538
     22744)
     22745*755 (Wire
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     22749va (VaSet
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     22753pts [
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     22755"29000,67250"
     22756]
     22757)
     22758end &134
     22759sat 16
     22760eat 32
     22761st 0
     22762sf 1
     22763si 0
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     22766ps "ConnStartEndStrategy"
     22767stg "STSignalDisplayStrategy"
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     22770va (VaSet
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     22773st "CLK_25"
     22774blo "29000,64800"
     22775tm "WireNameMgr"
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     22777)
     22778on &188
    2294322779)
    2294422780]
     
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    2322223058va (VaSet
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    2328723123va (VaSet
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    2389723733va (VaSet
    2389823734)
     
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    2395723793va (VaSet
    2395823794)
     
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    2409523931ldm (LogicalDM
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     23932suid 300,0
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    24107 )
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     23938*788 (RefLabelRowHdr
     23939)
     23940*789 (TitleRowHdr
     23941)
     23942*790 (FilterRowHdr
     23943)
     23944*791 (RefLabelColHdr
    2410923945tm "RefLabelColHdrMgr"
    2411023946)
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    2411223948tm "RowExpandColHdrMgr"
    2411323949)
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    2411523951tm "GroupColHdrMgr"
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    2411823954tm "BlockDiagramNameColHdrMgr"
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    2412123957tm "BlockDiagramModeColHdrMgr"
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    2412423960tm "BlockDiagramTypeColHdrMgr"
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    2412723963tm "BlockDiagramBoundsColHdrMgr"
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    2413023966tm "BlockDiagramInitColHdrMgr"
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    2413323969tm "BlockDiagramEolColHdrMgr"
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    2425224088)
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    2426524101)
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    2427824114)
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    2428124117decl (Decl
     
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    2428924125)
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    2429224128decl (Decl
     
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    2430124137)
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    2431424150)
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    2431724153decl (Decl
     
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    2432624162)
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    2434224178)
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    2434524181m 4
     
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    2435724193)
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    2437024206)
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    2438424220)
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    2439924235)
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     24236*820 (LeafLogPort
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    2441524251)
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    2443024266)
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    2444424280)
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    2445824294)
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    2447024306)
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    2448324319)
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    2448624322m 4
     
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    2449624332)
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    2450824344)
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    2452024356)
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    2453324369)
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    2454624382)
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    2455824394)
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    2457024406)
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    2458224418)
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    2459424430)
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    2459724433decl (Decl
     
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    2460524441)
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    2460824444decl (Decl
     
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    2461724453)
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    2462024456decl (Decl
     
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    2462824464)
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    2464124477)
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    2465324489)
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    2466624502)
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    2466924505m 1
     
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    2468024516)
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    2469324529)
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    2469624532decl (Decl
     
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    2470424540)
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    2470724543decl (Decl
     
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    2471524551)
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    2471824554decl (Decl
     
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    2472624562)
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    2472924565decl (Decl
     
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    2473724573)
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    2474924585)
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    2475224588m 1
     
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    2476224598)
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    2476524601m 1
     
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    2477524611)
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     24612*850 (LeafLogPort
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    2477824614m 4
     
    2478724623uid 5198,0
    2478824624)
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    2479024626port (LogicalPort
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    2480024636)
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    2480224638port (LogicalPort
    2480324639m 4
     
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    2481224648)
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    2481424650port (LogicalPort
    2481524651m 4
     
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    2482524661)
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    2482724663port (LogicalPort
    2482824664m 4
     
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    2483724673)
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     24674*855 (LeafLogPort
    2483924675port (LogicalPort
    2484024676m 4
     
    2484824684uid 5208,0
    2484924685)
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     24686*856 (LeafLogPort
    2485124687port (LogicalPort
    2485224688m 4
     
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    2486124697)
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     24698*857 (LeafLogPort
    2486324699port (LogicalPort
    2486424700m 4
     
    2487224708uid 5212,0
    2487324709)
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     24710*858 (LeafLogPort
    2487524711port (LogicalPort
    2487624712m 4
     
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    2488524721)
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     24722*859 (LeafLogPort
    2488724723port (LogicalPort
    2488824724m 1
     
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    2490024736)
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     24737*860 (LeafLogPort
    2490224738port (LogicalPort
    2490324739m 4
     
    2491124747uid 5502,0
    2491224748)
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     24749*861 (LeafLogPort
    2491424750port (LogicalPort
    2491524751m 4
     
    2492324759uid 5504,0
    2492424760)
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     24761*862 (LeafLogPort
    2492624762port (LogicalPort
    2492724763m 4
     
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    2493624772)
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    2495024786)
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     24787*864 (LeafLogPort
    2495224788port (LogicalPort
    2495324789m 4
     
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    2496224798)
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     24799*865 (LeafLogPort
    2496424800port (LogicalPort
    2496524801m 4
     
    2497424810uid 5751,0
    2497524811)
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     24812*866 (LeafLogPort
    2497724813port (LogicalPort
    2497824814m 1
     
    2498624822uid 5867,0
    2498724823)
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    2498924825port (LogicalPort
    2499024826m 2
     
    2500024836uid 5869,0
    2500124837)
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    2500324839port (LogicalPort
    2500424840m 1
     
    2501224848uid 5871,0
    2501324849)
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    2501524851port (LogicalPort
    2501624852m 1
     
    2502524861uid 5873,0
    2502624862)
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     24863*870 (LeafLogPort
    2502824864port (LogicalPort
    2502924865m 4
     
    2503824874uid 5966,0
    2503924875)
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     24876*871 (LeafLogPort
    2504124877port (LogicalPort
    2504224878m 4
     
    2505024886uid 5968,0
    2505124887)
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     24888*872 (LeafLogPort
    2505324889port (LogicalPort
    2505424890m 4
     
    2506324899uid 6022,0
    2506424900)
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     24901*873 (LeafLogPort
    2506624902port (LogicalPort
    2506724903m 4
     
    2507624912uid 6024,0
    2507724913)
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    2507924915port (LogicalPort
    2508024916m 4
     
    2508824924uid 6026,0
    2508924925)
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     24926*875 (LeafLogPort
    2509124927port (LogicalPort
    2509224928m 1
     
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    2510224938)
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    2510524941m 1
     
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    2511724953)
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    2512024956m 4
     
    2512924965uid 6464,0
    2513024966)
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    2513224968port (LogicalPort
    2513324969m 4
     
    2514224978uid 6554,0
    2514324979)
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    2514624982lang 2
     
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    2515624992)
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    2515824994port (LogicalPort
    2515924995m 4
     
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    2516825004)
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     25005*881 (LeafLogPort
    2517025006port (LogicalPort
    2517125007m 4
     
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    2518025016)
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     25017*882 (LeafLogPort
    2518225018port (LogicalPort
    2518325019m 1
     
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    2519325029)
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     25030*883 (LeafLogPort
    2519525031port (LogicalPort
    2519625032m 4
     
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    2520825044)
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     25045*884 (LeafLogPort
    2521025046port (LogicalPort
    2521125047m 4
     
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    2522425060)
    25225 *890 (LeafLogPort
     25061*885 (LeafLogPort
    2522625062port (LogicalPort
    2522725063m 4
     
    2523825074uid 10024,0
    2523925075)
    25240 *891 (LeafLogPort
     25076*886 (LeafLogPort
    2524125077port (LogicalPort
    2524225078m 4
     
    2525125087uid 10026,0
    2525225088)
    25253 *892 (LeafLogPort
     25089*887 (LeafLogPort
    2525425090port (LogicalPort
    2525525091m 4
     
    2526425100uid 10028,0
    2526525101)
    25266 *893 (LeafLogPort
     25102*888 (LeafLogPort
    2526725103port (LogicalPort
    2526825104m 4
     
    2528025116uid 10208,0
    2528125117)
    25282 *894 (LeafLogPort
     25118*889 (LeafLogPort
    2528325119port (LogicalPort
    2528425120m 4
     
    2529625132uid 10210,0
    2529725133)
    25298 *895 (LeafLogPort
     25134*890 (LeafLogPort
    2529925135port (LogicalPort
    2530025136m 4
     
    2530825144uid 10294,0
    2530925145)
    25310 *896 (LeafLogPort
     25146*891 (LeafLogPort
    2531125147port (LogicalPort
    2531225148m 4
     
    2532025156uid 10334,0
    2532125157)
    25322 *897 (LeafLogPort
     25158*892 (LeafLogPort
    2532325159port (LogicalPort
    2532425160m 4
     
    2533325169uid 10336,0
    2533425170)
    25335 *898 (LeafLogPort
     25171*893 (LeafLogPort
    2533625172port (LogicalPort
    2533725173m 4
     
    2534625182uid 10338,0
    2534725183)
    25348 *899 (LeafLogPort
     25184*894 (LeafLogPort
    2534925185port (LogicalPort
    2535025186m 4
     
    2536025196uid 10340,0
    2536125197)
    25362 *900 (LeafLogPort
     25198*895 (LeafLogPort
    2536325199port (LogicalPort
    2536425200m 1
     
    2537325209uid 10342,0
    2537425210)
    25375 *901 (LeafLogPort
    25376 port (LogicalPort
    25377 m 4
    25378 decl (Decl
    25379 n "trigger_out"
    25380 t "std_logic"
    25381 preAdd 0
    25382 posAdd 0
    25383 o 120
    25384 suid 240,0
    25385 )
    25386 )
    25387 uid 10473,0
    25388 )
    25389 *902 (LeafLogPort
     25211*896 (LeafLogPort
    2539025212port (LogicalPort
    2539125213lang 2
     
    2540425226uid 10475,0
    2540525227)
     25228*897 (LeafLogPort
     25229port (LogicalPort
     25230m 4
     25231decl (Decl
     25232n "socks_connected"
     25233t "std_logic"
     25234o 111
     25235suid 243,0
     25236)
     25237)
     25238uid 10763,0
     25239)
     25240*898 (LeafLogPort
     25241port (LogicalPort
     25242m 4
     25243decl (Decl
     25244n "socks_waiting"
     25245t "std_logic"
     25246o 112
     25247suid 244,0
     25248)
     25249)
     25250uid 10765,0
     25251)
     25252*899 (LeafLogPort
     25253port (LogicalPort
     25254m 1
     25255decl (Decl
     25256n "green"
     25257t "std_logic"
     25258o 34
     25259suid 248,0
     25260)
     25261)
     25262uid 10767,0
     25263)
     25264*900 (LeafLogPort
     25265port (LogicalPort
     25266m 1
     25267decl (Decl
     25268n "amber"
     25269t "std_logic"
     25270o 29
     25271suid 249,0
     25272)
     25273)
     25274uid 10769,0
     25275)
     25276*901 (LeafLogPort
     25277port (LogicalPort
     25278m 1
     25279decl (Decl
     25280n "red"
     25281t "std_logic"
     25282o 39
     25283suid 250,0
     25284)
     25285)
     25286uid 10771,0
     25287)
     25288*902 (LeafLogPort
     25289port (LogicalPort
     25290m 4
     25291decl (Decl
     25292n "drs_readout_started"
     25293t "std_logic"
     25294o 87
     25295suid 252,0
     25296)
     25297)
     25298uid 11411,0
     25299)
    2540625300*903 (LeafLogPort
    2540725301port (LogicalPort
    2540825302m 4
    2540925303decl (Decl
    25410 n "socks_connected"
    25411 t "std_logic"
    25412 o 111
    25413 suid 243,0
    25414 )
    25415 )
    25416 uid 10763,0
    25417 )
    25418 *904 (LeafLogPort
    25419 port (LogicalPort
    25420 m 4
    25421 decl (Decl
    25422 n "socks_waiting"
    25423 t "std_logic"
    25424 o 112
    25425 suid 244,0
    25426 )
    25427 )
    25428 uid 10765,0
    25429 )
    25430 *905 (LeafLogPort
    25431 port (LogicalPort
    25432 m 1
    25433 decl (Decl
    25434 n "green"
    25435 t "std_logic"
    25436 o 34
    25437 suid 248,0
    25438 )
    25439 )
    25440 uid 10767,0
    25441 )
    25442 *906 (LeafLogPort
    25443 port (LogicalPort
    25444 m 1
    25445 decl (Decl
    25446 n "amber"
    25447 t "std_logic"
    25448 o 29
    25449 suid 249,0
    25450 )
    25451 )
    25452 uid 10769,0
    25453 )
    25454 *907 (LeafLogPort
    25455 port (LogicalPort
    25456 m 1
    25457 decl (Decl
    25458 n "red"
    25459 t "std_logic"
    25460 o 39
    25461 suid 250,0
    25462 )
    25463 )
    25464 uid 10771,0
    25465 )
    25466 *908 (LeafLogPort
    25467 port (LogicalPort
    25468 m 4
    25469 decl (Decl
    25470 n "drs_readout_started"
    25471 t "std_logic"
    25472 o 87
    25473 suid 252,0
    25474 )
    25475 )
    25476 uid 11411,0
    25477 )
    25478 *909 (LeafLogPort
    25479 port (LogicalPort
    25480 m 4
    25481 decl (Decl
    2548225304n "trigger_enable"
    2548325305t "std_logic"
     
    2548825310uid 11966,0
    2548925311)
    25490 *910 (LeafLogPort
     25312*904 (LeafLogPort
    2549125313port (LogicalPort
    2549225314m 4
     
    2550225324uid 12310,0
    2550325325)
    25504 *911 (LeafLogPort
     25326*905 (LeafLogPort
    2550525327port (LogicalPort
    2550625328m 4
     
    2551625338uid 12659,0
    2551725339)
    25518 *912 (LeafLogPort
     25340*906 (LeafLogPort
    2551925341port (LogicalPort
    2552025342m 4
     
    2553325355uid 12661,0
    2553425356)
    25535 *913 (LeafLogPort
     25357*907 (LeafLogPort
    2553625358port (LogicalPort
    2553725359m 4
     
    2554525367uid 12663,0
    2554625368)
    25547 *914 (LeafLogPort
     25369*908 (LeafLogPort
    2554825370port (LogicalPort
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    2660126417genericsCommonDM (CommonDM
    2660226418ldm (LogicalDM
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     26419emptyRow *1057 (LEmptyRow
    2660426420)
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    26608 )
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    26613 *1068 (RefLabelColHdr
     26423*1058 (RefLabelRowHdr
     26424)
     26425*1059 (TitleRowHdr
     26426)
     26427*1060 (FilterRowHdr
     26428)
     26429*1061 (RefLabelColHdr
    2661426430tm "RefLabelColHdrMgr"
    2661526431)
    26616 *1069 (RowExpandColHdr
     26432*1062 (RowExpandColHdr
    2661726433tm "RowExpandColHdrMgr"
    2661826434)
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     26435*1063 (GroupColHdr
    2662026436tm "GroupColHdrMgr"
    2662126437)
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     26438*1064 (NameColHdr
    2662326439tm "GenericNameColHdrMgr"
    2662426440)
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     26441*1065 (TypeColHdr
    2662626442tm "GenericTypeColHdrMgr"
    2662726443)
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     26444*1066 (InitColHdr
    2662926445tm "GenericValueColHdrMgr"
    2663026446)
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     26447*1067 (PragmaColHdr
    2663226448tm "GenericPragmaColHdrMgr"
    2663326449)
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     26450*1068 (EolColHdr
    2663526451tm "GenericEolColHdrMgr"
    2663626452)
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     26453*1069 (LogGeneric
    2663826454generic (GiElement
    2663926455name "RAMADDRWIDTH64b"
     
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    2665326469sheetRow (SheetRow
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb

    r10129 r10138  
    11991199(vvPair
    12001200variable "date"
    1201 value "04.02.2011"
     1201value "08.02.2011"
    12021202)
    12031203(vvPair
    12041204variable "day"
    1205 value "Fr"
     1205value "Di"
    12061206)
    12071207(vvPair
    12081208variable "day_long"
    1209 value "Freitag"
     1209value "Dienstag"
    12101210)
    12111211(vvPair
    12121212variable "dd"
    1213 value "04"
     1213value "08"
    12141214)
    12151215(vvPair
     
    13511351(vvPair
    13521352variable "time"
    1353 value "12:56:44"
     1353value "11:06:22"
    13541354)
    13551355(vvPair
     
    40004000)
    40014001)
    4002 lastUid 5873,0
     4002lastUid 5942,0
    40034003okToSyncOnLoad 1
    40044004OkToSyncGenericsOnLoad 1
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/w5300_modul/symbol.sb

    r10123 r10138  
    347347t "std_logic_vector"
    348348b "(7 downto 0)"
     349prec "-- read/write configRAM"
     350preAdd 0
    349351o 25
    350352suid 24,0
     
    358360n "config_busy"
    359361t "std_logic"
    360 prec "-- --"
    361 preAdd 0
     362preAdd 0
     363posAdd 0
    362364o 31
    363365suid 25,0
     
    385387n "config_started"
    386388t "std_logic"
     389posAdd 0
    387390o 24
    388391suid 27,0
     
    410413n "new_config"
    411414t "std_logic"
    412 prec "--"
     415prec "-- FAD configuration signals:
     416------------------------------------------------------------------------------
     417-- start entire configuration chain"
    413418preAdd 0
    414419o 23
     
    441446eolc "-- default domino wave off"
    442447posAdd 0
    443 o 35
     448o 36
    444449suid 31,0
    445450i "'0'"
     
    457462preAdd 0
    458463posAdd 0
    459 o 36
     464o 37
    460465suid 32,0
    461466i "'0'"
     
    485490eolc "-- default DWRITE HIGH."
    486491posAdd 0
    487 o 37
     492o 38
    488493suid 35,0
    489494i "'1'"
     
    498503n "ps_direction"
    499504t "std_logic"
     505prec "------------------------------------------------------------------------------
     506
     507-- ADC CLK generator, is able to shift phase with respect to X_50M
     508-- these signals control the behavior of the digital clock manager (DCM)
     509------------------------------------------------------------------------------"
    500510eolc "-- default phase shift upwards"
    501 posAdd 0
    502 o 38
     511preAdd 0
     512posAdd 0
     513o 40
    503514suid 36,0
    504515i "'1'"
     
    516527preAdd 0
    517528posAdd 0
    518 o 39
     529o 41
    519530suid 37,0
    520531i "'0'"
     
    531542eolc "-- pulse this to reset the variable phase shift"
    532543posAdd 0
    533 o 40
     544o 42
    534545suid 38,0
    535546i "'0'"
     
    546557eolc "-- default SRCLK on."
    547558posAdd 0
    548 o 41
     559o 39
    549560suid 39,0
    550561i "'1'"
     
    558569n "config_rw_ack"
    559570t "std_logic"
    560 prec "-- --"
    561571preAdd 0
    562572posAdd 0
     
    572582n "config_rw_ready"
    573583t "std_logic"
    574 prec "-- --"
    575584preAdd 0
    576585posAdd 0
     
    587596n "socks_connected"
    588597t "std_logic"
     598posc "------------------------------------------------------------------------------"
     599posAdd 0
    589600o 44
    590601suid 42,0
     
    599610n "socks_waiting"
    600611t "std_logic"
     612prec "------------------------------------------------------------------------------
     613
     614-- signals used to control FAD LED bahavior:
     615-- one of the three LEDs is used for com-status info
     616------------------------------------------------------------------------------"
    601617preAdd 0
    602618o 43
     
    612628n "trigger_enable"
    613629t "std_logic"
     630prec "------------------------------------------------------------------------------
     631
     632-- user controllable enable signals
     633------------------------------------------------------------------------------"
    614634eolc "-- default triggers are NOT accepted"
    615 posAdd 0
    616 o 42
     635preAdd 0
     636posAdd 0
     637o 35
    617638suid 44,0
    618639i "'0'"
     
    656677t "std_logic_vector"
    657678b "(1 downto 0)"
     679prec "------------------------------------------------------------------------------
     680
     681-- MAC/IP calculation signals:
     682------------------------------------------------------------------------------"
     683preAdd 0
    658684o 32
    659685suid 48,0
     
    680706t "std_logic_vector"
    681707b "(1 downto 0)"
     708posAdd 0
    682709o 34
    683710suid 50,0
     
    11141141value "14"
    11151142)
    1116 uid 1329,0
     1143uid 1354,0
    11171144)
    11181145]
     
    11701197pos 0
    11711198dimension 20
    1172 uid 1330,0
     1199uid 1355,0
    11731200)
    11741201]
     
    12831310(vvPair
    12841311variable "date"
    1285 value "27.01.2011"
     1312value "08.02.2011"
    12861313)
    12871314(vvPair
    12881315variable "day"
    1289 value "Do"
     1316value "Di"
    12901317)
    12911318(vvPair
    12921319variable "day_long"
    1293 value "Donnerstag"
     1320value "Dienstag"
    12941321)
    12951322(vvPair
    12961323variable "dd"
    1297 value "27"
     1324value "08"
    12981325)
    12991326(vvPair
     
    13591386(vvPair
    13601387variable "mm"
    1361 value "01"
     1388value "02"
    13621389)
    13631390(vvPair
     
    13671394(vvPair
    13681395variable "month"
    1369 value "Jan"
     1396value "Feb"
    13701397)
    13711398(vvPair
    13721399variable "month_long"
    1373 value "Januar"
     1400value "Februar"
    13741401)
    13751402(vvPair
     
    14031430(vvPair
    14041431variable "task_ModelSimPath"
    1405 value "<TBD>"
     1432value "C:\\modeltech_6.6a\\win32"
    14061433)
    14071434(vvPair
     
    14351462(vvPair
    14361463variable "time"
    1437 value "15:14:14"
     1464value "10:18:42"
    14381465)
    14391466(vvPair
     
    21612188xt "200,31000,13900,35000"
    21622189st "
    2163 ---- Uncomment the following library declaration if instantiating
    2164 ---- any Xilinx primitives in this code.
    2165 --library UNISIM;
    2166 --use UNISIM.VComponents.all;
     2190
    21672191"
    21682192tm "CommentText"
     
    24392463font "Courier New,8,0"
    24402464)
    2441 xt "2000,36800,33000,37600"
    2442 st "config_addr       : OUT    std_logic_vector (7 downto 0) ;
     2465xt "2000,38400,33000,40000"
     2466st "-- read/write configRAM
     2467config_addr       : OUT    std_logic_vector (7 downto 0) ;
    24432468"
    24442469)
     
    24492474t "std_logic_vector"
    24502475b "(7 downto 0)"
     2476prec "-- read/write configRAM"
     2477preAdd 0
    24512478o 25
    24522479suid 24,0
     
    24852512font "Courier New,8,0"
    24862513)
    2487 xt "2000,43200,23000,44800"
    2488 st "-- --
    2489 config_busy       : IN     std_logic  ;
     2514xt "2000,44000,23000,44800"
     2515st "config_busy       : IN     std_logic  ;
    24902516"
    24912517)
     
    24942520n "config_busy"
    24952521t "std_logic"
    2496 prec "-- --"
    2497 preAdd 0
     2522preAdd 0
     2523posAdd 0
    24982524o 31
    24992525suid 25,0
     
    25332559font "Courier New,8,0"
    25342560)
    2535 xt "2000,37600,43000,38400"
     2561xt "2000,40000,43000,40800"
    25362562st "config_data       : INOUT  std_logic_vector (15 downto 0) := (others => 'Z') ;
    25372563"
     
    25802606font "Courier New,8,0"
    25812607)
    2582 xt "2000,36000,23000,36800"
     2608xt "2000,37600,23000,38400"
    25832609st "config_started    : IN     std_logic  ;
    25842610"
     
    25882614n "config_started"
    25892615t "std_logic"
     2616posAdd 0
    25902617o 24
    25912618suid 27,0
     
    26252652font "Courier New,8,0"
    26262653)
    2627 xt "2000,38400,37000,39200"
     2654xt "2000,40800,37000,41600"
    26282655st "config_wr_en      : OUT    std_logic                      := '0' ;
    26292656"
     
    26722699font "Courier New,8,0"
    26732700)
    2674 xt "2000,34400,37000,36000"
    2675 st "--
     2701xt "2000,34400,43000,37600"
     2702st "-- FAD configuration signals:
     2703------------------------------------------------------------------------------
     2704-- start entire configuration chain
    26762705new_config        : OUT    std_logic                      := '0' ;
    26772706"
     
    26822711n "new_config"
    26832712t "std_logic"
    2684 prec "--"
     2713prec "-- FAD configuration signals:
     2714------------------------------------------------------------------------------
     2715-- start entire configuration chain"
    26852716preAdd 0
    26862717o 23
     
    27222753font "Courier New,8,0"
    27232754)
    2724 xt "2000,39200,37000,40000"
     2755xt "2000,41600,37000,42400"
    27252756st "config_rd_en      : OUT    std_logic                      := '0' ;
    27262757"
     
    27702801font "Courier New,8,0"
    27712802)
    2772 xt "2000,47200,50500,48000"
     2803xt "2000,54400,50500,55200"
    27732804st "denable           : OUT    std_logic                      := '0' ; -- default domino wave off
    27742805"
     
    27812812eolc "-- default domino wave off"
    27822813posAdd 0
    2783 o 35
     2814o 36
    27842815suid 31,0
    27852816i "'0'"
     
    28192850font "Courier New,8,0"
    28202851)
    2821 xt "2000,48000,48500,48800"
     2852xt "2000,55200,48500,56000"
    28222853st "dwrite_enable     : OUT    std_logic                      := '0' ; -- default DWRITE low.
    28232854"
     
    28312862preAdd 0
    28322863posAdd 0
    2833 o 36
     2864o 37
    28342865suid 32,0
    28352866i "'0'"
     
    29162947font "Courier New,8,0"
    29172948)
    2918 xt "2000,48800,49000,49600"
     2949xt "2000,56000,49000,56800"
    29192950st "sclk_enable       : OUT    std_logic                      := '1' ; -- default DWRITE HIGH.
    29202951"
     
    29272958eolc "-- default DWRITE HIGH."
    29282959posAdd 0
    2929 o 37
     2960o 38
    29302961suid 35,0
    29312962i "'1'"
     
    29652996font "Courier New,8,0"
    29662997)
    2967 xt "2000,49600,52500,50400"
    2968 st "ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
     2998xt "2000,57600,52500,62400"
     2999st "------------------------------------------------------------------------------
     3000
     3001-- ADC CLK generator, is able to shift phase with respect to X_50M
     3002-- these signals control the behavior of the digital clock manager (DCM)
     3003------------------------------------------------------------------------------
     3004ps_direction      : OUT    std_logic                      := '1' ; -- default phase shift upwards
    29693005"
    29703006)
     
    29743010n "ps_direction"
    29753011t "std_logic"
     3012prec "------------------------------------------------------------------------------
     3013
     3014-- ADC CLK generator, is able to shift phase with respect to X_50M
     3015-- these signals control the behavior of the digital clock manager (DCM)
     3016------------------------------------------------------------------------------"
    29763017eolc "-- default phase shift upwards"
    2977 posAdd 0
    2978 o 38
     3018preAdd 0
     3019posAdd 0
     3020o 40
    29793021suid 36,0
    29803022i "'1'"
     
    30143056font "Courier New,8,0"
    30153057)
    3016 xt "2000,50400,53500,51200"
     3058xt "2000,62400,53500,63200"
    30173059st "ps_do_phase_shift : OUT    std_logic                      := '0' ; --pulse this to phase shift once
    30183060"
     
    30263068preAdd 0
    30273069posAdd 0
    3028 o 39
     3070o 41
    30293071suid 37,0
    30303072i "'0'"
     
    30643106font "Courier New,8,0"
    30653107)
    3066 xt "2000,51200,61000,52000"
     3108xt "2000,63200,61000,64000"
    30673109st "ps_reset          : OUT    std_logic                      := '0' ; -- pulse this to reset the variable phase shift
    30683110"
     
    30753117eolc "-- pulse this to reset the variable phase shift"
    30763118posAdd 0
    3077 o 40
     3119o 42
    30783120suid 38,0
    30793121i "'0'"
     
    31133155font "Courier New,8,0"
    31143156)
    3115 xt "2000,52000,47500,52800"
     3157xt "2000,56800,47500,57600"
    31163158st "srclk_enable      : OUT    std_logic                      := '1' ; -- default SRCLK on.
    31173159"
     
    31243166eolc "-- default SRCLK on."
    31253167posAdd 0
    3126 o 41
     3168o 39
    31273169suid 39,0
    31283170i "'1'"
     
    31613203font "Courier New,8,0"
    31623204)
    3163 xt "2000,40000,23000,41600"
    3164 st "-- --
    3165 config_rw_ack     : IN     std_logic  ;
     3205xt "2000,42400,23000,43200"
     3206st "config_rw_ack     : IN     std_logic  ;
    31663207"
    31673208)
     
    31703211n "config_rw_ack"
    31713212t "std_logic"
    3172 prec "-- --"
    31733213preAdd 0
    31743214posAdd 0
     
    32093249font "Courier New,8,0"
    32103250)
    3211 xt "2000,41600,23000,43200"
    3212 st "-- --
    3213 config_rw_ready   : IN     std_logic  ;
     3251xt "2000,43200,23000,44000"
     3252st "config_rw_ready   : IN     std_logic  ;
    32143253"
    32153254)
     
    32183257n "config_rw_ready"
    32193258t "std_logic"
    3220 prec "-- --"
    32213259preAdd 0
    32223260posAdd 0
     
    32583296font "Courier New,8,0"
    32593297)
    3260 xt "2000,54400,22000,55200"
     3298xt "2000,68800,43000,70400"
    32613299st "socks_connected   : OUT    std_logic
     3300------------------------------------------------------------------------------
    32623301"
    32633302)
     
    32673306n "socks_connected"
    32683307t "std_logic"
     3308posc "------------------------------------------------------------------------------"
     3309posAdd 0
    32693310o 44
    32703311suid 42,0
     
    33043345font "Courier New,8,0"
    33053346)
    3306 xt "2000,53600,23000,54400"
    3307 st "socks_waiting     : OUT    std_logic  ;
     3347xt "2000,64000,43000,68800"
     3348st "------------------------------------------------------------------------------
     3349
     3350-- signals used to control FAD LED bahavior:
     3351-- one of the three LEDs is used for com-status info
     3352------------------------------------------------------------------------------
     3353socks_waiting     : OUT    std_logic  ;
    33083354"
    33093355)
     
    33133359n "socks_waiting"
    33143360t "std_logic"
     3361prec "------------------------------------------------------------------------------
     3362
     3363-- signals used to control FAD LED bahavior:
     3364-- one of the three LEDs is used for com-status info
     3365------------------------------------------------------------------------------"
    33153366preAdd 0
    33163367o 43
     
    33513402font "Courier New,8,0"
    33523403)
    3353 xt "2000,52800,55500,53600"
    3354 st "trigger_enable    : OUT    std_logic                      := '0' ; -- default triggers are NOT accepted
     3404xt "2000,50400,55500,54400"
     3405st "------------------------------------------------------------------------------
     3406
     3407-- user controllable enable signals
     3408------------------------------------------------------------------------------
     3409trigger_enable    : OUT    std_logic                      := '0' ; -- default triggers are NOT accepted
    33553410"
    33563411)
     
    33603415n "trigger_enable"
    33613416t "std_logic"
     3417prec "------------------------------------------------------------------------------
     3418
     3419-- user controllable enable signals
     3420------------------------------------------------------------------------------"
    33623421eolc "-- default triggers are NOT accepted"
    3363 posAdd 0
    3364 o 42
     3422preAdd 0
     3423posAdd 0
     3424o 35
    33653425suid 44,0
    33663426i "'0'"
     
    34963556font "Courier New,8,0"
    34973557)
    3498 xt "2000,44800,33000,45600"
    3499 st "MAC_jumper        : IN     std_logic_vector (1 downto 0) ;
     3558xt "2000,44800,43000,48800"
     3559st "------------------------------------------------------------------------------
     3560
     3561-- MAC/IP calculation signals:
     3562------------------------------------------------------------------------------
     3563MAC_jumper        : IN     std_logic_vector (1 downto 0) ;
    35003564"
    35013565)
     
    35053569t "std_logic_vector"
    35063570b "(1 downto 0)"
     3571prec "------------------------------------------------------------------------------
     3572
     3573-- MAC/IP calculation signals:
     3574------------------------------------------------------------------------------"
     3575preAdd 0
    35073576o 32
    35083577suid 48,0
     
    35413610font "Courier New,8,0"
    35423611)
    3543 xt "2000,45600,33000,46400"
     3612xt "2000,48800,33000,49600"
    35443613st "BoardID           : IN     std_logic_vector (3 downto 0) ;
    35453614"
     
    35863655font "Courier New,8,0"
    35873656)
    3588 xt "2000,46400,33000,47200"
     3657xt "2000,49600,33000,50400"
    35893658st "CrateID           : IN     std_logic_vector (1 downto 0) ;
    35903659"
     
    35953664t "std_logic_vector"
    35963665b "(1 downto 0)"
     3666posAdd 0
    35973667o 34
    35983668suid 50,0
     
    42764346font "Arial,8,1"
    42774347)
    4278 xt "0,55200,2400,56200"
     4348xt "0,70400,2400,71400"
    42794349st "User:"
    4280 blo "0,56000"
     4350blo "0,71200"
    42814351)
    42824352internalLabel (Text
     
    42954365font "Courier New,8,0"
    42964366)
    4297 xt "2000,56200,2000,56200"
     4367xt "2000,71400,2000,71400"
    42984368tm "SyDeclarativeTextMgr"
    42994369)
     
    43084378)
    43094379)
    4310 lastUid 1330,0
     4380lastUid 1355,0
    43114381activeModelName "Symbol:CDM"
    43124382)
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