Changeset 10144
- Timestamp:
- 02/08/11 16:29:54 (14 years ago)
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firmware/FAD/doc/memory_manager.tex (modified) (7 diffs)
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firmware/FAD/doc/memory_manager.tex
r10142 r10144 6 6 7 7 \setlength{\textwidth}{16cm} 8 \setlength{\textheight}{25cm} 9 8 10 9 11 \setlength{\headheight}{0mm} … … 18 20 \restylefloat{table} 19 21 22 \usepackage{arydshln} 23 20 24 \title{FAD Data Generation} 21 25 \author{D. Neise} … … 37 41 Assume the Event Start-Address beeing {\tt 0x2000} and each package of ChannelData consists 100 samples. 38 42 \\ \\ 39 \emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.}43 %\emph{Erklaeren, dass auch wenn nur ein channel kleiner ist, die selbe Anzahl Daten versendet wird.} 40 44 41 45 42 46 \begin{table}[htbp] 43 44 \begin{tabular}{||l||l|l|l|l||l||} %6 linkbuendige spalten 45 \hline 46 address & word 3 & word 2 & word 1 & word 0 & mnemonic \\ 47 \hline 48 0x2000 & 0x0000 & Version & 0xLLLL & 0xFB01 & Header \\ 49 0x2001 & 0x0000 & TRG-ID 4,5 & TRG-ID 1,0 & TRG-ID 3,2 & Externl trigger ID \\ 50 0x2002 & 0x0000 & TRG-ID 4,5 & TRG-ID 1,0 & TRG-ID 3,2 & Internal trigger ID (now just a copy\\ 47 \begin{tabular}{||l||l|l|l|l||l||} 48 \hline 49 address & word 3 & word 2 & word 1 & word 0 & description \\ 50 \hline 51 0x2000 & 0x0000 & version & length & 0xFB01 & Header \\ 52 0x2001 & 0x0000 & TRG ID 45 & EVT cntr 10 & EVT cntr 32 & Externl trigger ID\\ 53 0x2002 & 0x0000 & TRG ID 45 & EVT cntr 10 & EVT cntr 32 & Internal trigger ID\\ 51 54 0x2003 & 0x0000 & 0x0000 & 0x0000 & 0x0(cid)8(bid) & Board ID \\ 52 55 0x2004 & Temp 3 & Temp 2 & Temp 1 & Temp 0 & Temperatures \\ … … 54 57 0x2006 & DAC 7 & DAC 6 & DAC 5 & DAC 4 & DAC values part 2 \\ 55 58 \hline 56 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 & chip-n-channel ID ( channelgroup 0) \\59 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 & chip-n-channel ID (group 0) \\ 57 60 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ 58 61 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ … … 61 64 0x206D & data adc3 & data adc2 & data adc1 & data adc0 & ADC Data end of ROI \\ 62 65 \hline 63 0x206E & 0x0031 & 0x0021 & 0x0011 & 0x0001 & chip-n-channel ID ( channelgroup 1) \\66 0x206E & 0x0031 & 0x0021 & 0x0011 & 0x0001 & chip-n-channel ID (group 1) \\ 64 67 0x206F & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ 65 68 0x2070 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ … … 70 73 0x20.. &&&&& ... \\ 71 74 \hline 72 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 & chip-n-channel ID ( channelgroup 9) \\75 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 & chip-n-channel ID (group 9) \\ 73 76 0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 & DRS stop positions \\ 74 77 0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 & width of region of interest \\ … … 92 95 Then the EventFooter is added and the Readout is finished. 93 96 97 \newpage 98 \section{data order in 16bit address space} 99 100 After an Event is stored in data RAM, is is ready to be read out by {\tt w5300 modul.vhd}. 101 Since the FIFOs of FADs W5300 ethernet controller are of 16bit width, data is read out of the dataRAM 102 as 16bit words. Empty 16bit words are left out. 103 104 The following table shows how the data is ordered inside data RAM, when accessed in 16bit address space 105 106 \begin{table}[htbp] 107 \begin{tabular}{|l|l|l|} 108 \hline 109 address & 16bit word & description \\ 110 \hline 111 0x8000 & 0xFB01 & Start Flag - fix value \\ 112 0x8001 & 0xllll & package length in 16bit words \\ 113 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ 114 0x8004 & EVT cntr 32 & trigger ID upper word \\ 115 0x8005 & EVT cntr 10 & trigger ID lower word \\ 116 0x8006 & 0xAA55 & trigger type and CRC-fake \\ 117 0x8008 & EVT cntr 32 & trigger ID upper word \\ 118 0x8009 & EVT cntr 10 & trigger ID lower word \\ 119 0x800A & 0xAA55 & trigger type and CRC-fake \\ 120 0x800C & 0x0(cid)8(bid) & Board ID \\ 121 0x8010 & 0xttt0 & temperature sensor next to DRS 0 \\ 122 0x8011 & 0xttt1 & temperature sensor next to DRS 1 \\ 123 0x8012 & 0xttt2 & temperature sensor next to DRS 2 \\ 124 0x8013 & 0xttt3 & temperature sensor next to DRS 3 \\ 125 0x8014 & 0xdac0 & setting of DAC channel A \\ 126 0x8015 & 0xdac1 & setting of DAC channel B \\ 127 0x8016 & 0xdac2 & setting of DAC channel C \\ 128 0x8017 & 0xdac3 & setting of DAC channel D \\ 129 0x8018 & 0xdac4 & setting of DAC channel E \\ 130 0x8019 & 0xdac5 & setting of DAC channel F \\ 131 0x801A & 0xdac6 & setting of DAC channel G \\ 132 0x801B & 0xdac7 & setting of DAC channel H \\ 133 \hline 134 0x801C & 0x0000 & DRS 0 - channel 0 \\ 135 0x8020 & trg pos 0 & DRS 0 stop position \\ 136 0x8024 & ROI 00 & ROI width of this channel \\ 137 0x8028 & adc data 0& ADC data start \\ 138 0x8... & ... & ...data ... \\ 139 0x81B4 & adc data ROI-1 & ADC data stop\\ 140 \hline 141 0x801D & 0x0010 & DRS 1 - channel 0 \\ 142 0x8021 & trg pos 1 & DRS 1 stop position \\ 143 0x8025 & ROI 10 & ROI width of this channel \\ 144 0x8029 & adc data 0& ADC data start \\ 145 0x8... & ... & ...data ... \\ 146 0x81B5 & adc data ROI-1 & ADC data stop\\ 147 \hline 148 0x8... & ... & ...data ... \\ 149 \hline 150 0x8CFC & 0x0039 & DRS 3 - channel 9 \\ 151 0x8D03 & trg pos 3 & DRS 3 stop position \\ 152 0x8D07 & ROI 39 & ROI width of this channel \\ 153 0x8D0B & adc data 0& ADC data start \\ 154 0x8... & ... & ...data ... \\ 155 0x8E97 & adc data ROI-1 & ADC data stop\\ 156 \hline 157 0x8E98 & 0x4242 & packet CRC-fake \\ 158 0x8E99 & 0x04FE & End Flag \\ 159 \hline 160 \end {tabular} 161 162 \caption{word order of event in Data RAM. 16bit addressing. As of 08.02.2011} 163 \label{16bitRAM} 164 \end{table} 165 166 As one can see, the way of reading out of the RAM changes, from header to data section and again when data section ends. 167 When reading the header, the addresses are increased by 1 usually and only jumps, when empty words show up in the RAM. 168 One can picture it as if reading the words in each line from right to left, sometimes jumping over zeroes. 169 When reading out the data sections, the words are read out as columns, i.e. addresses are incremented by 4 usually. One column is read until the data of a channel is completely read out, then either the next DRS chip is read out, which means to decrease the address or, if one group of channels was finished, the next group starts, which means address is increased by 1 only. 170 The footer consisting of the CRC-16 (when finally implemented) and the end package flag is again read out by reading each word from right to left. 171 172 173 \newpage 174 \section{NEW data order} 175 176 Some data is going to be added to the Event header changing the data order like this. 177 178 \begin{table}[htbp] 179 \begin{tabular}{||l||l|l|l|l||} 180 \hline 181 address & word 3 & word 2 & word 1 & word 0 \\ 182 \hline 183 0x2000 & 12bit status + PLLLOCK & version & length & 0xFB01 \\ 184 0x2001 & 0xT1T0 & 0xT3T2 & 0xT5T4 & 0x00T6 \\ 185 0x2002 & REFCLK cntr 10 & REFCLK cntr 32 & EVT cntr 10 & EVT cntr 32 \\ 186 0x2003 & TRG-GEN-DIV & TRG-GEN-No & DCM-PS-STATUS & 0x0(cid)8(bid) \\ 187 0x2004 & more status & more status & time10 & time32 \\ 188 0x2005 & Temp 3 & Temp 2 & Temp 1 & Temp 0 \\ 189 0x2006 & DAC 3 & DAC 2 & DAC 1 & DAC 0 \\ 190 0x2007 & DAC 7 & DAC 6 & DAC 5 & DAC 4 \\ 191 \hline 192 0x2007 & 0x0030 & 0x0020 & 0x0010 & 0x0000 \\ 193 0x2008 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 194 0x2009 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 195 0x200A & data adc3 & data adc2 & data adc1 & data adc0 \\ 196 0x20.. &&&& ... \\ 197 0x206D & data adc3 & data adc2 & data adc1 & data adc0 \\ 198 \hline 199 0x20.. &&&& ... \\ 200 \hline 201 0x233F & 0x0039 & 0x0029 & 0x0019 & 0x0009 \\ 202 0x2340 & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 203 0x2341 & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ 204 0x2342 & data adc3 & data adc2 & data adc1 & data adc0 \\ 205 0x23.. &&&& ... \\ 206 0x23A5 & data adc3 & data adc2 & data adc1 & data adc0 \\ 207 \hline 208 0x23A6 & 0x0000 & 0x0000 & 0x04FE & 0x4242\\ 209 \hline 210 \end {tabular} 211 212 \caption{NEW word order of event in Data RAM. 64bit addressing. As of > 08.02.2011} 213 \label{new64bitRAM} 214 \end{table} 215 216 \newpage 217 Which in turn changes the the word order in the 16bit address space like this 218 \begin{table}[htbp] 219 \begin{tabular}{|l|l|l|} 220 \hline 221 address & 16bit word & description \\ 222 \hline 223 0x8000 & 0xFB01 & Start Flag - fix value \\ 224 0x8001 & 0xllll & package length in 16bit words \\ 225 0x8002 & 0xvvvv & version - deduced from SVN revision number \\ 226 0x8003 & 0xsssP & 12 bits for status - TBD - 4 bit showing PLLLCK status \\ \hdashline 227 0x8004 & 0x00T6 & FTM trigger ID byte 6 : CRC \\ 228 0x8005 & 0xT5T4 & ... bytes 5 and 4 : Type 2 and Type 1\\ 229 0x8006 & 0xT3T2 & ... bytes 3 and 2 : TRG number high word \\ 230 0x8007 & 0xT1T0 & ... bytes 1 and 0 : TRG number low word \\ \hdashline 231 0x8008 & 0xev32 & FAD event counter high word \\ 232 0x8009 & 0xev10 & FAD event counter low word -- should be equal to T3T2T1T0\\ 233 0x800A & 0xRC32 & REFCLK counter high word \\ 234 0x800B & 0xRC10 & REFCLK counter low word \\ \hdashline 235 0x800C & 0x0(cid)8(bid) & Board ID \\ 236 0x800D & DCM-PS & status of ADC clock phase shifter , value and locked-bit\\ 237 0x800E & TRG-GEN-No& Number of Triggers to generare, when 'trigger continous' issued \\ 238 0x800F & TRG-GEN-DIV& continous trigger generator clock prescaler \\ \hdashline 239 0x8010 & timer32 & timer high word \\ 240 0x8011 & timer10 & timer low word \\ 241 0x8012 & more status1 & reserved for status info; high word \\ 242 0x8013 & more status0 & reserved for status info; low word \\ \hdashline 243 0x8014 & 0xttt0 & temperature sensor next to DRS 0 \\ 244 0x8015 & 0xttt1 & temperature sensor next to DRS 1 \\ 245 0x8016 & 0xttt2 & temperature sensor next to DRS 2 \\ 246 0x8017 & 0xttt3 & temperature sensor next to DRS 3 \\ \hdashline 247 0x8018 & 0xdac0 & setting of DAC channel A \\ 248 0x8019 & 0xdac1 & setting of DAC channel B \\ 249 0x801A & 0xdac2 & setting of DAC channel C \\ 250 0x801B & 0xdac3 & setting of DAC channel D \\ \hdashline 251 0x801C & 0xdac4 & setting of DAC channel E \\ 252 0x801D & 0xdac5 & setting of DAC channel F \\ 253 0x801E & 0xdac6 & setting of DAC channel G \\ 254 0x801F & 0xdac7 & setting of DAC channel H \\ 255 \hline 256 0x8... & ... & ...data ... \\ 257 \hline 258 259 \end {tabular} 260 \caption{word order of event in Data RAM. 16bit addressing. As of > 08.02.2011} 261 \label{16bitRAM} 262 \end{table} 263 264 This new order has several advantages apart from the additional information included. 265 All data may be treated as 64bit aligned. And the data readout process does not have to jump over word during data sending. 266 267 \newpage 268 \subsection{new {\tt FADFormat.h}} 269 270 \begin{verbatim} 271 typedef struct { 272 // ------------------------------ 273 unsigned short start_package_flag; 274 unsigned short package_length; 275 unsigned short version_no; 276 unsinged short PLLLCK; 277 // ------------------------------ 278 unsigned short trigger_crc; 279 unsigned short tigger_type; 280 unsigned long trigger_id; 281 // ------------------------------ 282 unsigned long fad_evt_counter; 283 unsigned long REFCLK_frequency; 284 // ------------------------------ 285 unsigned short board_id; 286 unsigned short adc_clock_phase_shift; 287 unsgined short number_of_triggers_to_generate; 288 unsigned short trigger_generator_prescaler; 289 // ------------------------------ 290 unsigned long time; 291 unsigned long fad_status; 292 // ------------------------------ 293 short drs_temperature[NTemp]; 294 // ------------------------------ 295 unsigned short dac[NDAC]; 296 // ------------------------------ 297 } __attribute__((__packed__)) PEVNT_HEADER; 298 299 typedef struct { 300 unsigned short id; 301 unsigned short start_cell; 302 unsigned short roi; 303 unsigned short adc_data[]; 304 } __attribute__((__packed__)) PCHANNEL; 305 306 typedef struct { 307 unsigned short package_crc; 308 unsigned short end_package_flag; 309 } __attribute__((__packed__)) PEVNT_FOOTER; 310 \end{verbatim} 311 94 312 95 313 \end{document}
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