Changeset 10155 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 02/15/11 12:07:05 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 1 added
- 10 edited
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clock_generator_var_ps_struct.vhd (modified) (8 diffs)
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control_unit_struct.vhd (modified) (2 diffs)
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data_generator.vhd (modified) (7 diffs)
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dna_gen.vhd (added)
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fad_board_struct.vhd (modified) (2 diffs)
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fad_definitions.vhd (modified) (1 diff)
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fad_main_struct.vhd (modified) (4 diffs)
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memory_manager_beha.vhd (modified) (2 diffs)
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phase_shifter.vhd (modified) (3 diffs)
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spi_interface_struct.vhd (modified) (2 diffs)
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trigger_counter_beha.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:49 04.02.20115 -- at - 13:26:27 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 32 32 -- Created: 33 33 -- by - dneise.UNKNOWN (E5B-LABOR6) 34 -- at - 1 5:27:49 04.02.201134 -- at - 13:26:27 14.02.2011 35 35 -- 36 36 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 42 42 LIBRARY UNISIM; 43 43 --USE UNISIM.Vcomponents.all; 44 LIBRARY FACT_FAD_lib; 45 USE FACT_FAD_lib.fad_definitions.all; 44 46 45 47 LIBRARY FACT_FAD_lib; … … 56 58 SIGNAL PSEN_IN : std_logic; 57 59 SIGNAL PSINCDEC_IN : std_logic; 60 SIGNAL rst : std_logic := '0'; --asynch in of DCM 58 61 59 62 -- Implicit buffer signal declarations … … 91 94 PORT ( 92 95 CLK : IN std_logic ; 93 rst : IN std_logic ;--asynch in of DCM96 rst : OUT std_logic := '0'; --asynch in of DCM 94 97 -- interface to: clock_generator_variable_PS_struct.vhd 95 98 PSCLK : OUT std_logic ; 96 99 PSEN : OUT std_logic := '0'; 97 PSINCDEC : OUT std_logic := '1'; 98 PSDONE : IN std_logic ; 99 LOCKED : IN std_logic ; 100 PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' 101 PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done. 102 LOCKED : IN std_logic ; -- when is this going high? 100 103 -- interface to: w5300_modul.vhd 101 104 shift_phase : IN std_logic ; 102 direction : IN std_logic ; -- corresponds TO 'PSINCDEC' 105 direction : IN std_logic ; -- corresponds TO 'PSINCDEC' 106 reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM 103 107 -- status: 104 108 shifting : OUT std_logic := '0'; 105 109 ready : OUT std_logic := '0'; 106 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 107 DCM_locked : OUT std_logic 110 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 108 111 ); 109 112 END COMPONENT; … … 139 142 PSEN_IN => PSEN_IN, 140 143 PSINCDEC_IN => PSINCDEC_IN, 141 RST_IN => RST_IN,144 RST_IN => rst, 142 145 CLK0_OUT => CLK_25_PS, 143 146 LOCKED_OUT => LOCKED_OUT, … … 147 150 PORT MAP ( 148 151 CLK => CLK0_OUT, 149 rst => RST_IN,152 rst => rst, 150 153 PSCLK => PSCLK_IN, 151 154 PSEN => PSEN_IN, … … 155 158 shift_phase => do_shift, 156 159 direction => direction, 160 reset_DCM => RST_IN, 157 161 shifting => OPEN, 158 162 ready => OPEN, 159 offset => offset, 160 DCM_locked => OPEN 163 offset => offset 161 164 ); 162 165 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 1:39:13 04.02.20115 -- at - 13:10:37 12.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 42 42 -- Created: 43 43 -- by - dneise.UNKNOWN (E5B-LABOR6) 44 -- at - 1 1:39:13 04.02.201144 -- at - 13:10:37 12.02.2011 45 45 -- 46 46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10138 r10155 45 45 sensor_ready : in std_logic; 46 46 dac_array : in dac_array_type; 47 48 -- EVT HEADER - part 1 47 49 package_length : in std_logic_vector (15 downto 0); 50 pll_lock : in std_logic_vector ( 3 downto 0); 51 -- 52 53 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 54 -- during EVT header wrinting, this field is left out ... and only written into event header, 55 -- when the DRS chip were read out already. 56 FTM_RS485_ready : in std_logic; 57 FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte 58 -- 59 60 -- EVT HEADER - part 3 61 fad_event_counter : in std_logic_vector (31 downto 0); 62 refclk_counter : in std_logic_vector (11 downto 0); 63 refclk_too_high: in std_logic; 64 refclk_too_low : in std_logic; 65 -- 66 67 -- EVT HEADER - part 4 48 68 board_id : in std_logic_vector (3 downto 0); 49 69 crate_id : in std_logic_vector (1 downto 0); 50 trigger_id : in std_logic_vector (47 downto 0); 70 DCM_PS_status : in std_logic_vector (7 downto 0); 71 TRG_GEN_no : in std_logic_vector (15 downto 0); 72 TRG_GEN_div : in std_logic_vector (15 downto 0); 73 -- 74 75 -- EVT HEADER - part 5 76 dna : in std_logic_vector (63 downto 0); 77 -- 78 79 -- EVT HEADER - part 6 80 timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us 81 -- 82 51 83 trigger : in std_logic; 52 84 -- s_trigger : in std_logic; … … 79 111 architecture Behavioral of data_generator is 80 112 81 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, 82 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, 83 WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1, 84 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); 113 type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, 114 WRITE_DATA_IDLE, 115 WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID, 116 WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES, 117 WRITE_DAC1, WRITE_DAC2, 118 WAIT_FOR_STOP_CELL, 119 START_DRS_READING, 120 WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING, 121 WAIT_FOR_ADC, WRITE_ADC_DATA, 122 WRITE_EXTERNAL_TRIGGER, 123 WRITE_END_FLAG, 124 WRITE_DATA_END, WRITE_DATA_END_WAIT, 125 WRITE_DATA_STOP, WRITE_DATA_STOP1); 85 126 86 127 signal state_generate : state_generate_type := INIT; … … 199 240 when WRITE_HEADER => 200 241 write_ea <= "1"; 201 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; 202 addr_cntr <= addr_cntr + 3; 203 state_generate <= WRITE_BOARD_ID; 204 when WRITE_BOARD_ID => -- crate ID & board ID 205 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; 206 addr_cntr <= addr_cntr + 1; 207 state_generate <= WRITE_TEMPERATURES; 242 data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; 243 addr_cntr <= addr_cntr + 1; 244 state_generate <= WRITE_FTM_INFO; 245 246 when WRITE_FTM_INFO => 247 -- here we do not write the FTM info ... just jump over it. 248 addr_cntr <= addr_cntr + 1; 249 state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER; 250 251 when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER => 252 data_out <= X"0000" & 253 refclk_too_high & refclk_too_low & "00" & refclk_counter & 254 fad_event_counter(15 downto 0) & 255 fad_event_counter(31 downto 16) ; 256 addr_cntr <= addr_cntr + 1; 257 state_generate <= WRITE_BOARD_ID; 258 -- crate ID & board ID 259 -- and a lot more... 260 -- info about the phase shifter 261 -- status of the trigger generator 262 when WRITE_BOARD_ID => 263 data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; 264 addr_cntr <= addr_cntr + 1; 265 state_generate <= WRITE_DNA; 266 267 when WRITE_DNA => 268 data_out <= X"00" & dna(55 downto 0); 269 addr_cntr <= addr_cntr + 1; 270 state_generate <= WRITE_TIMER; 271 272 when WRITE_TIMER => 273 data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info 274 addr_cntr <= addr_cntr + 1; 275 state_generate <= WRITE_TEMPERATURES; 276 208 277 when WRITE_TEMPERATURES => -- temperatures 209 278 if (sensor_ready = '1') then … … 248 317 249 318 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs 250 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)251 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)252 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)253 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);319 data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) 320 & conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) 321 & conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) 322 & conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4); 254 323 addr_cntr <= addr_cntr + 1; 255 324 state_generate <= WRITE_START_CELL; … … 267 336 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); 268 337 addr_cntr <= addr_cntr + 1; 269 state_generate <= WAIT_FOR_ADC; 338 state_generate <= WRITE_FILLING; 339 340 when WRITE_FILLING => -- write FILLING 341 data_out <= conv_std_logic_vector(0,64); -- filling 342 addr_cntr <= addr_cntr + 1; 343 state_generate <= WAIT_FOR_ADC; 344 270 345 when WAIT_FOR_ADC => 271 346 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! … … 281 356 & "000" & adc_otr(1) & adc_data_array(1) 282 357 & "000" & adc_otr(0) & adc_data_array(0); 283 358 -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) 284 359 -- & "00010" & conv_std_logic_vector (data_cntr, 11) 285 360 -- & "00100" & conv_std_logic_vector (data_cntr, 11) … … 303 378 end if; 304 379 305 306 380 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID 307 381 addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); 308 -- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); 309 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 310 state_generate <= WRITE_INTERNAL_TRIGGER; 311 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID 312 addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); 313 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); 382 data_out <= FTM_trigger_info(15 downto 0) 383 & FTM_trigger_info(31 downto 16) 384 & FTM_trigger_info(47 downto 32) 385 & X"00" & FTM_trigger_info(55 downto 48); 314 386 state_generate <= WRITE_END_FLAG; 387 315 388 when WRITE_END_FLAG => 316 389 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:51 04.02.20115 -- at - 13:26:28 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 5:27:51 04.02.201178 -- at - 13:26:28 14.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10138 r10155 56 56 constant PACKAGE_HEADER_LENGTH : integer := 22; 57 57 constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag 58 constant CHANNEL_HEADER_SIZE : integer := 3; 58 59 59 60 constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 5:27:49 04.02.20115 -- at - 13:26:27 14.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 72 72 -- Created: 73 73 -- by - dneise.UNKNOWN (E5B-LABOR6) 74 -- at - 1 5:27:50 04.02.201174 -- at - 13:26:28 14.02.2011 75 75 -- 76 76 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 171 171 SIGNAL trigger_enable : std_logic; 172 172 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); 173 SIGNAL trigger_out : std_logic ;173 SIGNAL trigger_out : std_logic := '0'; 174 174 SIGNAL wiz_ack : std_logic; 175 175 SIGNAL wiz_busy : std_logic; … … 451 451 c_trigger_enable : OUT std_logic := '0'; 452 452 c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes 453 -- 453 -- FAD configuration signals: 454 ------------------------------------------------------------------------------ 455 -- start entire configuration chain 454 456 new_config : OUT std_logic := '0'; 455 457 config_started : IN std_logic ; 458 -- read/write configRAM 456 459 config_addr : OUT std_logic_vector (7 DOWNTO 0); 457 460 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 458 461 config_wr_en : OUT std_logic := '0'; 459 462 config_rd_en : OUT std_logic := '0'; 460 -- --461 463 config_rw_ack : IN std_logic ; 462 -- --463 464 config_rw_ready : IN std_logic ; 464 -- --465 465 config_busy : IN std_logic ; 466 ------------------------------------------------------------------------------ 467 468 -- MAC/IP calculation signals: 469 ------------------------------------------------------------------------------ 466 470 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 467 471 BoardID : IN std_logic_vector (3 DOWNTO 0); 468 472 CrateID : IN std_logic_vector (1 DOWNTO 0); 473 ------------------------------------------------------------------------------ 474 475 -- user controllable enable signals 476 ------------------------------------------------------------------------------ 477 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 469 478 denable : OUT std_logic := '0'; -- default domino wave off 470 479 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 471 480 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 481 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 482 ------------------------------------------------------------------------------ 483 484 -- ADC CLK generator, is able to shift phase with respect to X_50M 485 -- these signals control the behavior of the digital clock manager (DCM) 486 ------------------------------------------------------------------------------ 472 487 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 473 488 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 474 489 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 475 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 476 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 490 ------------------------------------------------------------------------------ 491 492 -- signals used to control FAD LED bahavior: 493 -- one of the three LEDs is used for com-status info 494 ------------------------------------------------------------------------------ 477 495 socks_waiting : OUT std_logic ; 478 496 socks_connected : OUT std_logic 497 ------------------------------------------------------------------------------ 479 498 ); 480 499 END COMPONENT; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10072 r10155 51 51 wiz_write_end : OUT std_logic := '0'; 52 52 wiz_busy : IN std_logic; 53 wiz_ack : IN std_logic;53 wiz_ack : IN std_logic; 54 54 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 55 55 ); … … 134 134 roi_max_array (channel_id) <= temp_roi; 135 135 end if; 136 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3;136 channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE; 137 137 drs_id <= drs_id + 1; 138 138 state_mm <= MAX_ROI; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
r10154 r10155 35 35 shifting : OUT std_logic := '0'; 36 36 ready : OUT std_logic := '0'; 37 37 38 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 38 39 … … 93 94 94 95 -- MAIN FSM 95 FSM: process( state, PSDONE, LOCKED, shift_phase, direction, local_direction)96 FSM: process(CLK) 96 97 begin 97 98 … … 144 145 end if; 145 146 146 if (reset_dcm_sr = "01") then 147 if (reset_dcm_sr = "01") then 147 148 state <= RESET_STATE; 148 149 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd
r10129 r10155 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 6:13:08 03.02.20115 -- at - 13:10:37 12.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 38 38 -- Created: 39 39 -- by - dneise.UNKNOWN (E5B-LABOR6) 40 -- at - 1 6:13:08 03.02.201140 -- at - 13:10:37 12.02.2011 41 41 -- 42 42 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd
r9912 r10155 16 16 entity trigger_counter is 17 17 port( 18 trigger_id : out std_logic_vector( 47downto 0);18 trigger_id : out std_logic_vector(31 downto 0); 19 19 trigger : in std_logic; 20 20 clk : in std_logic … … 29 29 begin 30 30 31 trigger_id <= X"AA55" &conv_std_logic_vector(temp_id, 32);31 trigger_id <= conv_std_logic_vector(temp_id, 32); 32 32 33 33 trigger_incr_proc: process(clk)
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