Changeset 10155 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds
- Timestamp:
- 02/15/11 12:07:05 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds
- Files:
-
- 4 added
- 12 edited
-
.cache.dat (modified) ( previous)
-
.xrf/clock_generator_var_ps_struct.xrf (modified) (1 diff)
-
.xrf/fad_main_struct.xrf (modified) (4 diffs)
-
@f@a@d_main/struct.bd (modified) (526 diffs)
-
@f@a@d_main/struct.bd.bak (modified) (449 diffs)
-
@f@a@d_main/symbol.sb (modified) (4 diffs)
-
_dna_gen._epf (added)
-
clock_generator_var_ps/struct.bd (modified) (86 diffs)
-
clock_generator_var_ps/struct.bd.bak (modified) (29 diffs)
-
clock_generator_var_ps/symbol.sb (modified) (3 diffs)
-
data_generator/symbol.sb (modified) (184 diffs)
-
dna_gen (added)
-
dna_gen/@behavioral.bd (added)
-
dna_gen/symbol.sb (added)
-
phase_shifter/symbol.sb (modified) (36 diffs)
-
trigger_counter/symbol.sb (modified) (17 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf
r10129 r10155 43 43 DESIGN clock_generator_var_ps 44 44 VIEW struct.bd 45 NO_GRAPHIC 43 46 DESIGN clock_generator_var_ps 47 VIEW struct.bd 48 GRAPHIC 0,0 46 2 49 DESIGN clock_generator_var_ps 50 VIEW struct.bd 51 GRAPHIC 524,0 51 0 52 DESIGN clock_generator_var_ps 53 VIEW struct.bd 54 GRAPHIC 600,0 52 0 55 DESIGN clock_generator_var_ps 56 VIEW struct.bd 57 GRAPHIC 530,0 53 0 58 DESIGN clock_generator_var_ps 59 VIEW struct.bd 60 GRAPHIC 586,0 54 0 61 DESIGN clock_generator_var_ps 62 VIEW struct.bd 63 GRAPHIC 544,0 55 0 64 DESIGN clock_generator_var_ps 65 VIEW struct.bd 66 GRAPHIC 558,0 56 0 67 DESIGN clock_generator_var_ps 68 VIEW struct.bd 69 NO_GRAPHIC 57 70 DESIGN clock_generator_var_ps 71 VIEW struct.bd 72 GRAPHIC 229,0 59 0 73 DESIGN clock_generator_var_ps 74 VIEW struct.bd 75 NO_GRAPHIC 61 45 NO_GRAPHIC 45 46 DESIGN clock_generator_var_ps 47 VIEW struct.bd 48 GRAPHIC 0,0 48 2 49 DESIGN clock_generator_var_ps 50 VIEW struct.bd 51 GRAPHIC 524,0 53 0 52 DESIGN clock_generator_var_ps 53 VIEW struct.bd 54 GRAPHIC 600,0 54 0 55 DESIGN clock_generator_var_ps 56 VIEW struct.bd 57 GRAPHIC 530,0 55 0 58 DESIGN clock_generator_var_ps 59 VIEW struct.bd 60 GRAPHIC 586,0 56 0 61 DESIGN clock_generator_var_ps 62 VIEW struct.bd 63 GRAPHIC 544,0 57 0 64 DESIGN clock_generator_var_ps 65 VIEW struct.bd 66 GRAPHIC 558,0 58 0 67 DESIGN clock_generator_var_ps 68 VIEW struct.bd 69 GRAPHIC 1979,0 59 0 70 DESIGN clock_generator_var_ps 71 VIEW struct.bd 72 NO_GRAPHIC 60 73 DESIGN clock_generator_var_ps 74 VIEW struct.bd 75 GRAPHIC 229,0 62 0 76 DESIGN clock_generator_var_ps 77 VIEW struct.bd 78 NO_GRAPHIC 64 76 79 LIBRARY FACT_FAD_lib 77 80 DESIGN dcm_50_to_25 78 81 VIEW @b@e@h@a@v@i@o@r@a@l 79 GRAPHIC 403,0 6 3080 DESIGN clock_generator_var_ps 81 VIEW struct.bd 82 NO_GRAPHIC 6983 DESIGN clock_generator_var_ps 84 VIEW struct.bd 85 GRAPHIC 354,0 7 1086 DESIGN clock_generator_var_ps 87 VIEW struct.bd 88 NO_GRAPHIC 7 589 DESIGN clock_generator_var_ps 90 VIEW struct.bd 91 GRAPHIC 514,0 77092 DESIGN clock_generator_var_ps 93 VIEW struct.bd 94 NO_GRAPHIC 8795 DESIGN clock_generator_var_ps 96 VIEW struct.bd 97 GRAPHIC 826,0 89098 DESIGN phase_shifter 99 VIEW first_behave 100 GRAPHIC 48,0 9 10101 DESIGN phase_shifter 102 VIEW first_behave 103 GRAPHIC 281,0 9 20104 DESIGN phase_shifter 105 VIEW first_behave 106 GRAPHIC 53,0 9 30107 DESIGN phase_shifter 108 VIEW first_behave 109 GRAPHIC 58,0 9 50110 DESIGN phase_shifter 111 VIEW first_behave 112 GRAPHIC 63,0 9 60113 DESIGN phase_shifter 114 VIEW first_behave 115 GRAPHIC 68,0 970116 DESIGN phase_shifter 117 VIEW first_behave 118 GRAPHIC 73,0 980119 DESIGN phase_shifter 120 VIEW first_behave 121 GRAPHIC 83,0 990122 DESIGN phase_shifter 123 VIEW first_behave 124 GRAPHIC 88,0 10 10125 DESIGN phase_shifter 126 VIEW first_behave 127 GRAPHIC 93,0 1020128 DESIGN phase_shifter 129 VIEW first_behave 130 GRAPHIC 9 8,0 1040131 DESIGN phase_shifter 132 VIEW first_behave 133 GRAPHIC 103,0 1050134 DESIGN phase_shifter 135 VIEW first_behave 136 GRAPHIC 10 8,0 106082 GRAPHIC 403,0 66 0 83 DESIGN clock_generator_var_ps 84 VIEW struct.bd 85 NO_GRAPHIC 72 86 DESIGN clock_generator_var_ps 87 VIEW struct.bd 88 GRAPHIC 354,0 74 0 89 DESIGN clock_generator_var_ps 90 VIEW struct.bd 91 NO_GRAPHIC 78 92 DESIGN clock_generator_var_ps 93 VIEW struct.bd 94 GRAPHIC 514,0 80 0 95 DESIGN clock_generator_var_ps 96 VIEW struct.bd 97 NO_GRAPHIC 90 98 DESIGN clock_generator_var_ps 99 VIEW struct.bd 100 GRAPHIC 826,0 92 0 101 DESIGN phase_shifter 102 VIEW first_behave 103 GRAPHIC 48,0 94 0 104 DESIGN phase_shifter 105 VIEW first_behave 106 GRAPHIC 281,0 95 0 107 DESIGN phase_shifter 108 VIEW first_behave 109 GRAPHIC 53,0 96 0 110 DESIGN phase_shifter 111 VIEW first_behave 112 GRAPHIC 58,0 98 0 113 DESIGN phase_shifter 114 VIEW first_behave 115 GRAPHIC 63,0 99 0 116 DESIGN phase_shifter 117 VIEW first_behave 118 GRAPHIC 68,0 100 0 119 DESIGN phase_shifter 120 VIEW first_behave 121 GRAPHIC 73,0 101 0 122 DESIGN phase_shifter 123 VIEW first_behave 124 GRAPHIC 83,0 102 0 125 DESIGN phase_shifter 126 VIEW first_behave 127 GRAPHIC 88,0 104 0 128 DESIGN phase_shifter 129 VIEW first_behave 130 GRAPHIC 362,0 105 0 131 DESIGN phase_shifter 132 VIEW first_behave 133 GRAPHIC 93,0 106 0 134 DESIGN phase_shifter 135 VIEW first_behave 136 GRAPHIC 98,0 108 0 137 DESIGN phase_shifter 138 VIEW first_behave 139 GRAPHIC 103,0 109 0 137 140 LIBRARY FACT_FAD_lib 138 141 DESIGN clock_generator_var_ps 139 142 VIEW struct.bd 140 NO_GRAPHIC 109 141 DESIGN clock_generator_var_ps 142 VIEW struct.bd 143 GRAPHIC 403,0 112 0 144 DESIGN clock_generator_var_ps 145 VIEW struct.bd 146 GRAPHIC 354,0 113 0 147 DESIGN clock_generator_var_ps 148 VIEW struct.bd 149 GRAPHIC 514,0 114 0 150 DESIGN clock_generator_var_ps 151 VIEW struct.bd 152 GRAPHIC 826,0 115 0 153 DESIGN clock_generator_var_ps 154 VIEW struct.bd 155 NO_GRAPHIC 118 156 DESIGN clock_generator_var_ps 157 VIEW struct.bd 158 NO_GRAPHIC 120 159 DESIGN clock_generator_var_ps 160 VIEW struct.bd 161 GRAPHIC 403,0 122 0 162 DESIGN clock_generator_var_ps 163 VIEW struct.bd 164 GRAPHIC 163,0 124 0 165 DESIGN clock_generator_var_ps 166 VIEW struct.bd 167 GRAPHIC 209,0 125 0 168 DESIGN clock_generator_var_ps 169 VIEW struct.bd 170 GRAPHIC 191,0 127 0 171 DESIGN clock_generator_var_ps 172 VIEW struct.bd 173 GRAPHIC 354,0 129 0 174 DESIGN clock_generator_var_ps 175 VIEW struct.bd 176 GRAPHIC 229,0 131 0 177 DESIGN clock_generator_var_ps 178 VIEW struct.bd 179 GRAPHIC 526,0 132 0 180 DESIGN clock_generator_var_ps 181 VIEW struct.bd 182 GRAPHIC 514,0 134 0 183 DESIGN clock_generator_var_ps 184 VIEW struct.bd 185 GRAPHIC 526,0 136 0 186 DESIGN clock_generator_var_ps 187 VIEW struct.bd 188 GRAPHIC 532,0 137 0 189 DESIGN clock_generator_var_ps 190 VIEW struct.bd 191 GRAPHIC 546,0 138 0 192 DESIGN clock_generator_var_ps 193 VIEW struct.bd 194 GRAPHIC 841,0 139 0 195 DESIGN clock_generator_var_ps 196 VIEW struct.bd 197 GRAPHIC 1493,0 140 0 198 DESIGN clock_generator_var_ps 199 VIEW struct.bd 200 GRAPHIC 1254,0 141 0 201 DESIGN clock_generator_var_ps 202 VIEW struct.bd 203 GRAPHIC 602,0 142 0 204 DESIGN clock_generator_var_ps 205 VIEW struct.bd 206 GRAPHIC 588,0 143 0 207 DESIGN clock_generator_var_ps 208 VIEW struct.bd 209 GRAPHIC 826,0 145 0 210 DESIGN clock_generator_var_ps 211 VIEW struct.bd 212 GRAPHIC 1458,0 147 0 213 DESIGN clock_generator_var_ps 214 VIEW struct.bd 215 GRAPHIC 1625,0 148 0 216 DESIGN clock_generator_var_ps 217 VIEW struct.bd 218 GRAPHIC 532,0 149 0 219 DESIGN clock_generator_var_ps 220 VIEW struct.bd 221 GRAPHIC 546,0 150 0 222 DESIGN clock_generator_var_ps 223 VIEW struct.bd 224 GRAPHIC 841,0 151 0 225 DESIGN clock_generator_var_ps 226 VIEW struct.bd 227 GRAPHIC 588,0 152 0 228 DESIGN clock_generator_var_ps 229 VIEW struct.bd 230 GRAPHIC 602,0 153 0 231 DESIGN clock_generator_var_ps 232 VIEW struct.bd 233 GRAPHIC 1272,0 154 0 234 DESIGN clock_generator_var_ps 235 VIEW struct.bd 236 GRAPHIC 1286,0 155 0 237 DESIGN clock_generator_var_ps 238 VIEW struct.bd 239 GRAPHIC 1609,0 158 0 240 DESIGN clock_generator_var_ps 241 VIEW struct.bd 242 GRAPHIC 229,0 163 0 243 DESIGN clock_generator_var_ps 244 VIEW struct.bd 245 NO_GRAPHIC 165 143 NO_GRAPHIC 112 144 DESIGN clock_generator_var_ps 145 VIEW struct.bd 146 GRAPHIC 403,0 115 0 147 DESIGN clock_generator_var_ps 148 VIEW struct.bd 149 GRAPHIC 354,0 116 0 150 DESIGN clock_generator_var_ps 151 VIEW struct.bd 152 GRAPHIC 514,0 117 0 153 DESIGN clock_generator_var_ps 154 VIEW struct.bd 155 GRAPHIC 826,0 118 0 156 DESIGN clock_generator_var_ps 157 VIEW struct.bd 158 NO_GRAPHIC 121 159 DESIGN clock_generator_var_ps 160 VIEW struct.bd 161 NO_GRAPHIC 123 162 DESIGN clock_generator_var_ps 163 VIEW struct.bd 164 GRAPHIC 403,0 125 0 165 DESIGN clock_generator_var_ps 166 VIEW struct.bd 167 GRAPHIC 163,0 127 0 168 DESIGN clock_generator_var_ps 169 VIEW struct.bd 170 GRAPHIC 209,0 128 0 171 DESIGN clock_generator_var_ps 172 VIEW struct.bd 173 GRAPHIC 191,0 130 0 174 DESIGN clock_generator_var_ps 175 VIEW struct.bd 176 GRAPHIC 354,0 132 0 177 DESIGN clock_generator_var_ps 178 VIEW struct.bd 179 GRAPHIC 229,0 134 0 180 DESIGN clock_generator_var_ps 181 VIEW struct.bd 182 GRAPHIC 526,0 135 0 183 DESIGN clock_generator_var_ps 184 VIEW struct.bd 185 GRAPHIC 514,0 137 0 186 DESIGN clock_generator_var_ps 187 VIEW struct.bd 188 GRAPHIC 526,0 139 0 189 DESIGN clock_generator_var_ps 190 VIEW struct.bd 191 GRAPHIC 532,0 140 0 192 DESIGN clock_generator_var_ps 193 VIEW struct.bd 194 GRAPHIC 546,0 141 0 195 DESIGN clock_generator_var_ps 196 VIEW struct.bd 197 GRAPHIC 841,0 142 0 198 DESIGN clock_generator_var_ps 199 VIEW struct.bd 200 GRAPHIC 1981,0 143 0 201 DESIGN clock_generator_var_ps 202 VIEW struct.bd 203 GRAPHIC 1254,0 144 0 204 DESIGN clock_generator_var_ps 205 VIEW struct.bd 206 GRAPHIC 602,0 145 0 207 DESIGN clock_generator_var_ps 208 VIEW struct.bd 209 GRAPHIC 588,0 146 0 210 DESIGN clock_generator_var_ps 211 VIEW struct.bd 212 GRAPHIC 826,0 148 0 213 DESIGN clock_generator_var_ps 214 VIEW struct.bd 215 GRAPHIC 1458,0 150 0 216 DESIGN clock_generator_var_ps 217 VIEW struct.bd 218 GRAPHIC 1981,0 151 0 219 DESIGN clock_generator_var_ps 220 VIEW struct.bd 221 GRAPHIC 532,0 152 0 222 DESIGN clock_generator_var_ps 223 VIEW struct.bd 224 GRAPHIC 546,0 153 0 225 DESIGN clock_generator_var_ps 226 VIEW struct.bd 227 GRAPHIC 841,0 154 0 228 DESIGN clock_generator_var_ps 229 VIEW struct.bd 230 GRAPHIC 588,0 155 0 231 DESIGN clock_generator_var_ps 232 VIEW struct.bd 233 GRAPHIC 602,0 156 0 234 DESIGN clock_generator_var_ps 235 VIEW struct.bd 236 GRAPHIC 1272,0 157 0 237 DESIGN clock_generator_var_ps 238 VIEW struct.bd 239 GRAPHIC 1286,0 158 0 240 DESIGN clock_generator_var_ps 241 VIEW struct.bd 242 GRAPHIC 1493,0 159 0 243 DESIGN clock_generator_var_ps 244 VIEW struct.bd 245 GRAPHIC 1609,0 162 0 246 DESIGN clock_generator_var_ps 247 VIEW struct.bd 248 GRAPHIC 229,0 166 0 249 DESIGN clock_generator_var_ps 250 VIEW struct.bd 251 NO_GRAPHIC 168 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r10129 r10155 367 367 DESIGN @f@a@d_main 368 368 VIEW struct.bd 369 GRAPHIC 1 0449,0 172 0369 GRAPHIC 15492,0 172 0 370 370 DESIGN @f@a@d_main 371 371 VIEW struct.bd … … 884 884 DESIGN w5300_modul 885 885 VIEW @behavioral 886 GRAPHIC 566,0 45 40887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 551,0 45 50890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 561,0 45 60893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 571,0 4 570896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 640,0 4 580899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 1052,0 4 590902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1057,0 46 10905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 556,0 46 30886 GRAPHIC 566,0 456 0 887 DESIGN w5300_modul 888 VIEW @behavioral 889 GRAPHIC 551,0 457 0 890 DESIGN w5300_modul 891 VIEW @behavioral 892 GRAPHIC 561,0 459 0 893 DESIGN w5300_modul 894 VIEW @behavioral 895 GRAPHIC 571,0 460 0 896 DESIGN w5300_modul 897 VIEW @behavioral 898 GRAPHIC 640,0 461 0 899 DESIGN w5300_modul 900 VIEW @behavioral 901 GRAPHIC 1052,0 462 0 902 DESIGN w5300_modul 903 VIEW @behavioral 904 GRAPHIC 1057,0 463 0 905 DESIGN w5300_modul 906 VIEW @behavioral 907 GRAPHIC 556,0 464 0 908 908 DESIGN w5300_modul 909 909 VIEW @behavioral … … 911 911 DESIGN w5300_modul 912 912 VIEW @behavioral 913 GRAPHIC 1315,0 4 660914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 1320,0 4 670917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 670,0 4680920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 723,0 4690923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 917,0 4700926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 9 49,0 4710929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 954,0 4720932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 9 88,0 4730935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 1020,0 4740938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 1130,0 4750941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 1096,0 4 760944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 1091,0 4 770913 GRAPHIC 1315,0 470 0 914 DESIGN w5300_modul 915 VIEW @behavioral 916 GRAPHIC 1320,0 471 0 917 DESIGN w5300_modul 918 VIEW @behavioral 919 GRAPHIC 1130,0 472 0 920 DESIGN w5300_modul 921 VIEW @behavioral 922 GRAPHIC 670,0 477 0 923 DESIGN w5300_modul 924 VIEW @behavioral 925 GRAPHIC 723,0 478 0 926 DESIGN w5300_modul 927 VIEW @behavioral 928 GRAPHIC 917,0 479 0 929 DESIGN w5300_modul 930 VIEW @behavioral 931 GRAPHIC 1020,0 480 0 932 DESIGN w5300_modul 933 VIEW @behavioral 934 GRAPHIC 949,0 481 0 935 DESIGN w5300_modul 936 VIEW @behavioral 937 GRAPHIC 954,0 487 0 938 DESIGN w5300_modul 939 VIEW @behavioral 940 GRAPHIC 988,0 488 0 941 DESIGN w5300_modul 942 VIEW @behavioral 943 GRAPHIC 1096,0 489 0 944 DESIGN w5300_modul 945 VIEW @behavioral 946 GRAPHIC 1091,0 495 0 947 947 LIBRARY FACT_FAD_lib 948 948 DESIGN @f@a@d_main 949 949 VIEW struct.bd 950 NO_GRAPHIC 480951 DESIGN @f@a@d_main952 VIEW struct.bd953 GRAPHIC 14417,0 483 0954 DESIGN @f@a@d_main955 VIEW struct.bd956 GRAPHIC 5678,0 484 0957 DESIGN @f@a@d_main958 VIEW struct.bd959 GRAPHIC 9175,0 485 0960 DESIGN @f@a@d_main961 VIEW struct.bd962 GRAPHIC 13117,0 486 0963 DESIGN @f@a@d_main964 VIEW struct.bd965 GRAPHIC 5072,0 487 0966 DESIGN @f@a@d_main967 VIEW struct.bd968 GRAPHIC 8277,0 488 0969 DESIGN @f@a@d_main970 VIEW struct.bd971 GRAPHIC 1399,0 489 0972 DESIGN @f@a@d_main973 VIEW struct.bd974 GRAPHIC 4903,0 490 0975 DESIGN @f@a@d_main976 VIEW struct.bd977 GRAPHIC 11209,0 491 0978 DESIGN @f@a@d_main979 VIEW struct.bd980 GRAPHIC 2311,0 492 0981 DESIGN @f@a@d_main982 VIEW struct.bd983 GRAPHIC 5793,0 493 0984 DESIGN @f@a@d_main985 VIEW struct.bd986 GRAPHIC 1768,0 494 0987 DESIGN @f@a@d_main988 VIEW struct.bd989 GRAPHIC 12625,0 495 0990 DESIGN @f@a@d_main991 VIEW struct.bd992 GRAPHIC 1606,0 496 0993 DESIGN @f@a@d_main994 VIEW struct.bd995 950 NO_GRAPHIC 499 996 951 DESIGN @f@a@d_main 997 952 VIEW struct.bd 998 GRAPHIC 6529,0 501 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 9957,0 504 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 8721,0 507 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 14991,0 510 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 12295,0 513 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 15058,0 516 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 15036,0 519 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 10380,0 523 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 13266,0 526 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 NO_GRAPHIC 529 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 14417,0 531 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 14427,0 533 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 14048,0 534 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 14622,0 535 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 14479,0 536 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 14493,0 537 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 5678,0 539 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 5646,0 541 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 4272,0 542 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 2786,0 543 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5626,0 544 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5634,0 545 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 9175,0 547 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 4042,0 549 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 10036,0 550 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 9253,0 551 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 9261,0 552 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 6072,0 553 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 3984,0 554 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 3888,0 555 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 13117,0 558 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 13124,0 559 1 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 13143,0 563 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 13159,0 564 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 13165,0 565 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 13210,0 566 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5072,0 568 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5582,0 570 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5090,0 571 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5130,0 572 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 5184,0 573 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 5122,0 574 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 5106,0 575 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 5098,0 576 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5190,0 577 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 10194,0 578 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 10202,0 579 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 6002,0 580 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 5146,0 581 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 5138,0 582 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 5114,0 583 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 8277,0 585 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5602,0 587 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 334,0 588 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 328,0 589 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 322,0 590 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 4240,0 591 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 364,0 592 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 370,0 593 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 1399,0 595 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 1406,0 596 1 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5602,0 600 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 334,0 601 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 328,0 602 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 322,0 603 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 2299,0 604 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2576,0 605 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2582,0 606 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 10467,0 607 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 2588,0 608 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5184,0 609 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5745,0 610 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 2594,0 611 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5190,0 612 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5404,0 613 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6018,0 614 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 6002,0 615 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 6008,0 616 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 5138,0 617 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2600,0 618 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 5480,0 619 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 5474,0 620 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 6064,0 621 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 2642,0 622 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 GRAPHIC 1411,0 623 0 1251 DESIGN @f@a@d_main 1252 VIEW struct.bd 1253 GRAPHIC 1682,0 624 0 1254 DESIGN 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VIEW struct.bd 1298 GRAPHIC 10304,0 639 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10316,0 640 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 10310,0 641 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 4743,0 642 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 4407,0 643 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 11405,0 644 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 4903,0 646 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 4757,0 648 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 4401,0 649 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 4419,0 650 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 4671,0 651 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 4679,0 652 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 4687,0 653 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 4695,0 654 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 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DESIGN @f@a@d_main 994 VIEW struct.bd 995 NO_GRAPHIC 518 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 6529,0 520 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 9957,0 523 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 8721,0 526 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 14991,0 529 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 12295,0 532 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 15058,0 535 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 15036,0 538 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 10380,0 542 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 13266,0 545 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 NO_GRAPHIC 548 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 14417,0 550 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 14427,0 552 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 14048,0 553 0 1035 DESIGN @f@a@d_main 1036 VIEW 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GRAPHIC 6072,0 572 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 3984,0 573 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 3888,0 574 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 13117,0 577 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 13124,0 578 1 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 13143,0 582 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 13159,0 583 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 13165,0 584 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 13210,0 585 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5072,0 587 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5582,0 589 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5090,0 590 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5130,0 591 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 5184,0 592 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 5122,0 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@f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 4240,0 610 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 364,0 611 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 370,0 612 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 1399,0 614 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 1406,0 615 1 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5602,0 619 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 334,0 620 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 328,0 621 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 322,0 622 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 2299,0 623 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 2576,0 624 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 2582,0 625 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 10467,0 626 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 2588,0 627 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5184,0 628 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5745,0 629 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 2594,0 630 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 5190,0 631 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 5404,0 632 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6018,0 633 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 6002,0 634 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 GRAPHIC 6008,0 635 0 1230 DESIGN @f@a@d_main 1231 VIEW struct.bd 1232 GRAPHIC 5138,0 636 0 1233 DESIGN @f@a@d_main 1234 VIEW struct.bd 1235 GRAPHIC 2600,0 637 0 1236 DESIGN @f@a@d_main 1237 VIEW struct.bd 1238 GRAPHIC 5480,0 638 0 1239 DESIGN @f@a@d_main 1240 VIEW struct.bd 1241 GRAPHIC 5474,0 639 0 1242 DESIGN @f@a@d_main 1243 VIEW struct.bd 1244 GRAPHIC 6064,0 640 0 1245 DESIGN @f@a@d_main 1246 VIEW struct.bd 1247 GRAPHIC 2642,0 641 0 1248 DESIGN @f@a@d_main 1249 VIEW struct.bd 1250 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656 0 1344 1293 DESIGN @f@a@d_main 1345 1294 VIEW struct.bd … … 1347 1296 DESIGN @f@a@d_main 1348 1297 VIEW struct.bd 1349 GRAPHIC 10310,0 658 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10304,0 659 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 10316,0 660 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 10322,0 661 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4948,0 662 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 10010,0 663 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 11209,0 665 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 11216,0 666 1 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 10699,0 672 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 10723,0 673 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 10737,0 674 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 10751,0 675 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 12707,0 676 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 10707,0 677 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10685,0 678 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 10691,0 679 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2311,0 681 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 2318,0 682 1 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 6082,0 687 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 2588,0 688 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 2582,0 689 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 10467,0 690 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 5168,0 691 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 2576,0 692 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 2594,0 693 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 6018,0 694 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2600,0 695 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 2642,0 696 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 2488,0 697 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2482,0 698 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 2494,0 699 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 2476,0 700 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2506,0 701 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2500,0 702 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 2470,0 703 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 8416,0 704 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2299,0 705 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 5793,0 707 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 5805,0 709 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 5745,0 710 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 5146,0 711 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 5404,0 712 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 6008,0 713 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 5829,0 714 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 6160,0 715 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 8732,0 716 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 5480,0 717 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 5837,0 718 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 5474,0 719 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 5821,0 720 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 1768,0 722 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 1983,0 724 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 10439,0 725 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 6276,0 726 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 12625,0 728 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 12687,0 730 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 12643,0 731 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 12635,0 732 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 6540,0 733 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 12649,0 734 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 12655,0 735 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 1606,0 737 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 1613,0 738 1 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 3888,0 742 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 376,0 743 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 384,0 744 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 392,0 745 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 400,0 746 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 408,0 747 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 5222,0 748 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 424,0 749 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 432,0 750 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 2482,0 751 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 2488,0 752 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 370,0 753 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 364,0 754 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 2476,0 755 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 8416,0 756 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 2470,0 757 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 2506,0 758 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 2500,0 759 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 2494,0 760 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 10266,0 761 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 13159,0 762 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 13165,0 763 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 5950,0 764 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 5962,0 765 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 5090,0 766 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 5114,0 767 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 5122,0 768 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 5130,0 769 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 10194,0 770 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 10202,0 771 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 5106,0 772 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 13695,0 773 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 13921,0 774 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 13929,0 775 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 15071,0 776 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 6452,0 777 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 8752,0 778 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 9233,0 779 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 9241,0 780 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 9943,0 781 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 9951,0 782 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 11858,0 783 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 10637,0 784 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 10629,0 785 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 6276,0 789 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 3888,0 790 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 15138,0 791 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 15130,0 792 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 NO_GRAPHIC 794 1298 GRAPHIC 10304,0 658 0 1299 DESIGN @f@a@d_main 1300 VIEW struct.bd 1301 GRAPHIC 10316,0 659 0 1302 DESIGN @f@a@d_main 1303 VIEW struct.bd 1304 GRAPHIC 10310,0 660 0 1305 DESIGN @f@a@d_main 1306 VIEW struct.bd 1307 GRAPHIC 4743,0 661 0 1308 DESIGN @f@a@d_main 1309 VIEW struct.bd 1310 GRAPHIC 4407,0 662 0 1311 DESIGN @f@a@d_main 1312 VIEW struct.bd 1313 GRAPHIC 11405,0 663 0 1314 DESIGN @f@a@d_main 1315 VIEW struct.bd 1316 GRAPHIC 4903,0 665 0 1317 DESIGN @f@a@d_main 1318 VIEW struct.bd 1319 GRAPHIC 4757,0 667 0 1320 DESIGN @f@a@d_main 1321 VIEW struct.bd 1322 GRAPHIC 4401,0 668 0 1323 DESIGN @f@a@d_main 1324 VIEW struct.bd 1325 GRAPHIC 4419,0 669 0 1326 DESIGN @f@a@d_main 1327 VIEW struct.bd 1328 GRAPHIC 4671,0 670 0 1329 DESIGN @f@a@d_main 1330 VIEW struct.bd 1331 GRAPHIC 4679,0 671 0 1332 DESIGN @f@a@d_main 1333 VIEW struct.bd 1334 GRAPHIC 4687,0 672 0 1335 DESIGN @f@a@d_main 1336 VIEW struct.bd 1337 GRAPHIC 4695,0 673 0 1338 DESIGN @f@a@d_main 1339 VIEW struct.bd 1340 GRAPHIC 4407,0 674 0 1341 DESIGN @f@a@d_main 1342 VIEW struct.bd 1343 GRAPHIC 4743,0 675 0 1344 DESIGN @f@a@d_main 1345 VIEW struct.bd 1346 GRAPHIC 10298,0 676 0 1347 DESIGN @f@a@d_main 1348 VIEW struct.bd 1349 GRAPHIC 10310,0 677 0 1350 DESIGN @f@a@d_main 1351 VIEW struct.bd 1352 GRAPHIC 10304,0 678 0 1353 DESIGN @f@a@d_main 1354 VIEW struct.bd 1355 GRAPHIC 10316,0 679 0 1356 DESIGN @f@a@d_main 1357 VIEW struct.bd 1358 GRAPHIC 10322,0 680 0 1359 DESIGN @f@a@d_main 1360 VIEW struct.bd 1361 GRAPHIC 4948,0 681 0 1362 DESIGN @f@a@d_main 1363 VIEW struct.bd 1364 GRAPHIC 10010,0 682 0 1365 DESIGN @f@a@d_main 1366 VIEW struct.bd 1367 GRAPHIC 11209,0 684 0 1368 DESIGN @f@a@d_main 1369 VIEW struct.bd 1370 GRAPHIC 11216,0 685 1 1371 DESIGN @f@a@d_main 1372 VIEW struct.bd 1373 GRAPHIC 10699,0 691 0 1374 DESIGN @f@a@d_main 1375 VIEW struct.bd 1376 GRAPHIC 10723,0 692 0 1377 DESIGN @f@a@d_main 1378 VIEW struct.bd 1379 GRAPHIC 10737,0 693 0 1380 DESIGN @f@a@d_main 1381 VIEW struct.bd 1382 GRAPHIC 10751,0 694 0 1383 DESIGN @f@a@d_main 1384 VIEW struct.bd 1385 GRAPHIC 12707,0 695 0 1386 DESIGN @f@a@d_main 1387 VIEW struct.bd 1388 GRAPHIC 10707,0 696 0 1389 DESIGN @f@a@d_main 1390 VIEW struct.bd 1391 GRAPHIC 10685,0 697 0 1392 DESIGN @f@a@d_main 1393 VIEW struct.bd 1394 GRAPHIC 10691,0 698 0 1395 DESIGN @f@a@d_main 1396 VIEW struct.bd 1397 GRAPHIC 2311,0 700 0 1398 DESIGN @f@a@d_main 1399 VIEW struct.bd 1400 GRAPHIC 2318,0 701 1 1401 DESIGN @f@a@d_main 1402 VIEW struct.bd 1403 GRAPHIC 15379,0 706 0 1404 DESIGN @f@a@d_main 1405 VIEW struct.bd 1406 GRAPHIC 2588,0 707 0 1407 DESIGN @f@a@d_main 1408 VIEW struct.bd 1409 GRAPHIC 2582,0 708 0 1410 DESIGN @f@a@d_main 1411 VIEW struct.bd 1412 GRAPHIC 10467,0 709 0 1413 DESIGN @f@a@d_main 1414 VIEW struct.bd 1415 GRAPHIC 5168,0 710 0 1416 DESIGN @f@a@d_main 1417 VIEW struct.bd 1418 GRAPHIC 2576,0 711 0 1419 DESIGN @f@a@d_main 1420 VIEW struct.bd 1421 GRAPHIC 2594,0 712 0 1422 DESIGN @f@a@d_main 1423 VIEW struct.bd 1424 GRAPHIC 6018,0 713 0 1425 DESIGN @f@a@d_main 1426 VIEW struct.bd 1427 GRAPHIC 2600,0 714 0 1428 DESIGN @f@a@d_main 1429 VIEW struct.bd 1430 GRAPHIC 2642,0 715 0 1431 DESIGN @f@a@d_main 1432 VIEW struct.bd 1433 GRAPHIC 2488,0 716 0 1434 DESIGN @f@a@d_main 1435 VIEW struct.bd 1436 GRAPHIC 2482,0 717 0 1437 DESIGN @f@a@d_main 1438 VIEW struct.bd 1439 GRAPHIC 2494,0 718 0 1440 DESIGN @f@a@d_main 1441 VIEW struct.bd 1442 GRAPHIC 2476,0 719 0 1443 DESIGN @f@a@d_main 1444 VIEW struct.bd 1445 GRAPHIC 2506,0 720 0 1446 DESIGN @f@a@d_main 1447 VIEW struct.bd 1448 GRAPHIC 2500,0 721 0 1449 DESIGN @f@a@d_main 1450 VIEW struct.bd 1451 GRAPHIC 2470,0 722 0 1452 DESIGN @f@a@d_main 1453 VIEW struct.bd 1454 GRAPHIC 8416,0 723 0 1455 DESIGN @f@a@d_main 1456 VIEW struct.bd 1457 GRAPHIC 2299,0 724 0 1458 DESIGN @f@a@d_main 1459 VIEW struct.bd 1460 GRAPHIC 5793,0 726 0 1461 DESIGN @f@a@d_main 1462 VIEW struct.bd 1463 GRAPHIC 5805,0 728 0 1464 DESIGN @f@a@d_main 1465 VIEW struct.bd 1466 GRAPHIC 5745,0 729 0 1467 DESIGN @f@a@d_main 1468 VIEW struct.bd 1469 GRAPHIC 5146,0 730 0 1470 DESIGN @f@a@d_main 1471 VIEW struct.bd 1472 GRAPHIC 5404,0 731 0 1473 DESIGN @f@a@d_main 1474 VIEW struct.bd 1475 GRAPHIC 6008,0 732 0 1476 DESIGN @f@a@d_main 1477 VIEW struct.bd 1478 GRAPHIC 5829,0 733 0 1479 DESIGN @f@a@d_main 1480 VIEW struct.bd 1481 GRAPHIC 6160,0 734 0 1482 DESIGN @f@a@d_main 1483 VIEW struct.bd 1484 GRAPHIC 8732,0 735 0 1485 DESIGN @f@a@d_main 1486 VIEW struct.bd 1487 GRAPHIC 5480,0 736 0 1488 DESIGN @f@a@d_main 1489 VIEW struct.bd 1490 GRAPHIC 5837,0 737 0 1491 DESIGN @f@a@d_main 1492 VIEW struct.bd 1493 GRAPHIC 5474,0 738 0 1494 DESIGN @f@a@d_main 1495 VIEW struct.bd 1496 GRAPHIC 5821,0 739 0 1497 DESIGN @f@a@d_main 1498 VIEW struct.bd 1499 GRAPHIC 1768,0 741 0 1500 DESIGN @f@a@d_main 1501 VIEW struct.bd 1502 GRAPHIC 1983,0 743 0 1503 DESIGN @f@a@d_main 1504 VIEW struct.bd 1505 GRAPHIC 15498,0 744 0 1506 DESIGN @f@a@d_main 1507 VIEW struct.bd 1508 GRAPHIC 6276,0 745 0 1509 DESIGN @f@a@d_main 1510 VIEW struct.bd 1511 GRAPHIC 12625,0 747 0 1512 DESIGN @f@a@d_main 1513 VIEW struct.bd 1514 GRAPHIC 12687,0 749 0 1515 DESIGN @f@a@d_main 1516 VIEW struct.bd 1517 GRAPHIC 12643,0 750 0 1518 DESIGN @f@a@d_main 1519 VIEW struct.bd 1520 GRAPHIC 15494,0 751 0 1521 DESIGN @f@a@d_main 1522 VIEW struct.bd 1523 GRAPHIC 6540,0 752 0 1524 DESIGN @f@a@d_main 1525 VIEW struct.bd 1526 GRAPHIC 12649,0 753 0 1527 DESIGN @f@a@d_main 1528 VIEW struct.bd 1529 GRAPHIC 12655,0 754 0 1530 DESIGN @f@a@d_main 1531 VIEW struct.bd 1532 GRAPHIC 1606,0 756 0 1533 DESIGN @f@a@d_main 1534 VIEW struct.bd 1535 GRAPHIC 1613,0 757 1 1536 DESIGN @f@a@d_main 1537 VIEW struct.bd 1538 GRAPHIC 3888,0 761 0 1539 DESIGN @f@a@d_main 1540 VIEW struct.bd 1541 GRAPHIC 376,0 762 0 1542 DESIGN @f@a@d_main 1543 VIEW struct.bd 1544 GRAPHIC 384,0 763 0 1545 DESIGN @f@a@d_main 1546 VIEW struct.bd 1547 GRAPHIC 392,0 764 0 1548 DESIGN @f@a@d_main 1549 VIEW struct.bd 1550 GRAPHIC 400,0 765 0 1551 DESIGN @f@a@d_main 1552 VIEW struct.bd 1553 GRAPHIC 408,0 766 0 1554 DESIGN @f@a@d_main 1555 VIEW struct.bd 1556 GRAPHIC 5222,0 767 0 1557 DESIGN @f@a@d_main 1558 VIEW struct.bd 1559 GRAPHIC 424,0 768 0 1560 DESIGN @f@a@d_main 1561 VIEW struct.bd 1562 GRAPHIC 432,0 769 0 1563 DESIGN @f@a@d_main 1564 VIEW struct.bd 1565 GRAPHIC 2482,0 770 0 1566 DESIGN @f@a@d_main 1567 VIEW struct.bd 1568 GRAPHIC 2488,0 771 0 1569 DESIGN @f@a@d_main 1570 VIEW struct.bd 1571 GRAPHIC 370,0 772 0 1572 DESIGN @f@a@d_main 1573 VIEW struct.bd 1574 GRAPHIC 364,0 773 0 1575 DESIGN @f@a@d_main 1576 VIEW struct.bd 1577 GRAPHIC 2476,0 774 0 1578 DESIGN @f@a@d_main 1579 VIEW struct.bd 1580 GRAPHIC 8416,0 775 0 1581 DESIGN @f@a@d_main 1582 VIEW struct.bd 1583 GRAPHIC 2470,0 776 0 1584 DESIGN @f@a@d_main 1585 VIEW struct.bd 1586 GRAPHIC 2506,0 777 0 1587 DESIGN @f@a@d_main 1588 VIEW struct.bd 1589 GRAPHIC 2500,0 778 0 1590 DESIGN @f@a@d_main 1591 VIEW struct.bd 1592 GRAPHIC 2494,0 779 0 1593 DESIGN @f@a@d_main 1594 VIEW struct.bd 1595 GRAPHIC 10266,0 780 0 1596 DESIGN @f@a@d_main 1597 VIEW struct.bd 1598 GRAPHIC 13159,0 781 0 1599 DESIGN @f@a@d_main 1600 VIEW struct.bd 1601 GRAPHIC 13165,0 782 0 1602 DESIGN @f@a@d_main 1603 VIEW struct.bd 1604 GRAPHIC 5950,0 783 0 1605 DESIGN @f@a@d_main 1606 VIEW struct.bd 1607 GRAPHIC 5962,0 784 0 1608 DESIGN @f@a@d_main 1609 VIEW struct.bd 1610 GRAPHIC 5090,0 785 0 1611 DESIGN @f@a@d_main 1612 VIEW struct.bd 1613 GRAPHIC 5114,0 786 0 1614 DESIGN @f@a@d_main 1615 VIEW struct.bd 1616 GRAPHIC 5122,0 787 0 1617 DESIGN @f@a@d_main 1618 VIEW struct.bd 1619 GRAPHIC 5130,0 788 0 1620 DESIGN @f@a@d_main 1621 VIEW struct.bd 1622 GRAPHIC 10194,0 789 0 1623 DESIGN @f@a@d_main 1624 VIEW struct.bd 1625 GRAPHIC 10202,0 790 0 1626 DESIGN @f@a@d_main 1627 VIEW struct.bd 1628 GRAPHIC 5106,0 791 0 1629 DESIGN @f@a@d_main 1630 VIEW struct.bd 1631 GRAPHIC 13695,0 792 0 1632 DESIGN @f@a@d_main 1633 VIEW struct.bd 1634 GRAPHIC 13921,0 793 0 1635 DESIGN @f@a@d_main 1636 VIEW struct.bd 1637 GRAPHIC 13929,0 794 0 1638 DESIGN @f@a@d_main 1639 VIEW struct.bd 1640 GRAPHIC 15071,0 795 0 1641 DESIGN @f@a@d_main 1642 VIEW struct.bd 1643 GRAPHIC 6452,0 796 0 1644 DESIGN @f@a@d_main 1645 VIEW struct.bd 1646 GRAPHIC 8752,0 797 0 1647 DESIGN @f@a@d_main 1648 VIEW struct.bd 1649 GRAPHIC 9233,0 798 0 1650 DESIGN @f@a@d_main 1651 VIEW struct.bd 1652 GRAPHIC 9241,0 799 0 1653 DESIGN @f@a@d_main 1654 VIEW struct.bd 1655 GRAPHIC 9943,0 800 0 1656 DESIGN @f@a@d_main 1657 VIEW struct.bd 1658 GRAPHIC 9951,0 801 0 1659 DESIGN @f@a@d_main 1660 VIEW struct.bd 1661 GRAPHIC 11858,0 802 0 1662 DESIGN @f@a@d_main 1663 VIEW struct.bd 1664 GRAPHIC 10637,0 803 0 1665 DESIGN @f@a@d_main 1666 VIEW struct.bd 1667 GRAPHIC 10629,0 804 0 1668 DESIGN @f@a@d_main 1669 VIEW struct.bd 1670 GRAPHIC 6276,0 808 0 1671 DESIGN @f@a@d_main 1672 VIEW struct.bd 1673 GRAPHIC 3888,0 809 0 1674 DESIGN @f@a@d_main 1675 VIEW struct.bd 1676 GRAPHIC 15138,0 810 0 1677 DESIGN @f@a@d_main 1678 VIEW struct.bd 1679 GRAPHIC 15130,0 811 0 1680 DESIGN @f@a@d_main 1681 VIEW struct.bd 1682 NO_GRAPHIC 813 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r10138 r10155 26 26 library "IEEE" 27 27 unitName "std_logic_signed" 28 ) 29 (DmPackageRef 30 library "UNISIM" 31 unitName "VComponents" 28 32 ) 29 33 ] … … 278 282 uid 15058,0 279 283 ) 284 (Instance 285 name "U_0" 286 duLibraryName "FACT_FAD_lib" 287 duName "dna_gen" 288 elements [ 289 ] 290 mwi 0 291 uid 15728,0 292 ) 280 293 ] 281 294 libraryRefs [ … … 333 346 (vvPair 334 347 variable "date" 335 value " 08.02.2011"348 value "15.02.2011" 336 349 ) 337 350 (vvPair … … 345 358 (vvPair 346 359 variable "dd" 347 value " 08"360 value "15" 348 361 ) 349 362 (vvPair … … 485 498 (vvPair 486 499 variable "time" 487 value " 11:06:22"500 value "09:27:14" 488 501 ) 489 502 (vvPair … … 1363 1376 preAdd 0 1364 1377 posAdd 0 1365 o 2 41378 o 25 1366 1379 suid 9,0 1367 1380 ) … … 1369 1382 ) 1370 1383 *29 (CptPort 1371 uid 1388,01372 ps "OnEdgeStrategy"1373 shape (Triangle1374 uid 1389,01375 ro 901376 va (VaSet1377 vasetType 11378 fg "0,65535,0"1379 )1380 xt "-21750,69625,-21000,70375"1381 )1382 tg (CPTG1383 uid 1390,01384 ps "CptPortTextPlaceStrategy"1385 stg "VerticalLayoutStrategy"1386 f (Text1387 uid 1391,01388 va (VaSet1389 )1390 xt "-20000,69500,-13200,70500"1391 st "trigger_id : (47:0)"1392 blo "-20000,70300"1393 )1394 )1395 thePort (LogicalPort1396 decl (Decl1397 n "trigger_id"1398 t "std_logic_vector"1399 b "(47 downto 0)"1400 preAdd 01401 posAdd 01402 o 261403 suid 10,01404 )1405 )1406 )1407 *30 (CptPort1408 1384 uid 1392,0 1409 1385 ps "OnEdgeStrategy" … … 1436 1412 preAdd 0 1437 1413 posAdd 0 1438 o 2 71414 o 28 1439 1415 suid 11,0 1440 1416 ) 1441 1417 ) 1442 1418 ) 1443 *3 1(CptPort1419 *30 (CptPort 1444 1420 uid 1676,0 1445 1421 ps "OnEdgeStrategy" … … 1471 1447 t "std_logic_vector" 1472 1448 b "(1 downto 0)" 1473 o 2 51449 o 26 1474 1450 suid 12,0 1475 1451 ) 1476 1452 ) 1477 1453 ) 1478 *3 2(CptPort1454 *31 (CptPort 1479 1455 uid 2562,0 1480 1456 ps "OnEdgeStrategy" … … 1511 1487 ) 1512 1488 ) 1513 *3 3(CptPort1489 *32 (CptPort 1514 1490 uid 2566,0 1515 1491 ps "OnEdgeStrategy" … … 1549 1525 ) 1550 1526 ) 1551 *3 4(CptPort1527 *33 (CptPort 1552 1528 uid 2570,0 1553 1529 ps "OnEdgeStrategy" … … 1584 1560 ) 1585 1561 ) 1586 *3 5(CptPort1562 *34 (CptPort 1587 1563 uid 2614,0 1588 1564 ps "OnEdgeStrategy" … … 1619 1595 ) 1620 1596 ) 1621 *3 6(CptPort1597 *35 (CptPort 1622 1598 uid 2624,0 1623 1599 ps "OnEdgeStrategy" … … 1655 1631 ) 1656 1632 ) 1657 *3 7(CptPort1633 *36 (CptPort 1658 1634 uid 2760,0 1659 1635 ps "OnEdgeStrategy" … … 1685 1661 n "adc_oeb" 1686 1662 t "std_logic" 1687 o 3 11663 o 32 1688 1664 suid 23,0 1689 1665 i "'1'" … … 1691 1667 ) 1692 1668 ) 1693 *3 8(CptPort1669 *37 (CptPort 1694 1670 uid 2764,0 1695 1671 ps "OnEdgeStrategy" … … 1721 1697 t "std_logic_vector" 1722 1698 b "(3 downto 0)" 1723 o 3 31699 o 34 1724 1700 suid 24,0 1725 1701 ) 1726 1702 ) 1727 1703 ) 1728 *3 9(CptPort1704 *38 (CptPort 1729 1705 uid 3918,0 1730 1706 ps "OnEdgeStrategy" … … 1758 1734 b "(3 downto 0)" 1759 1735 posAdd 0 1760 o 3 41736 o 35 1761 1737 suid 25,0 1762 1738 i "(others => '0')" … … 1764 1740 ) 1765 1741 ) 1766 * 40(CptPort1742 *39 (CptPort 1767 1743 uid 3922,0 1768 1744 ps "OnEdgeStrategy" … … 1797 1773 preAdd 0 1798 1774 posAdd 0 1799 o 3 71775 o 38 1800 1776 suid 26,0 1801 1777 i "'0'" … … 1803 1779 ) 1804 1780 ) 1805 *4 1(CptPort1781 *40 (CptPort 1806 1782 uid 3930,0 1807 1783 ps "OnEdgeStrategy" … … 1835 1811 prec "-- --" 1836 1812 preAdd 0 1837 o 3 81813 o 39 1838 1814 suid 33,0 1839 1815 i "'0'" … … 1841 1817 ) 1842 1818 ) 1843 *4 2(CptPort1819 *41 (CptPort 1844 1820 uid 3934,0 1845 1821 ps "OnEdgeStrategy" … … 1870 1846 n "drs_read_s_cell_ready" 1871 1847 t "std_logic" 1872 o 4 31848 o 44 1873 1849 suid 34,0 1874 1850 ) 1875 1851 ) 1876 1852 ) 1877 *4 3(CptPort1853 *42 (CptPort 1878 1854 uid 3938,0 1879 1855 ps "OnEdgeStrategy" … … 1904 1880 n "drs_s_cell_array" 1905 1881 t "drs_s_cell_array_type" 1906 o 4 41882 o 45 1907 1883 suid 35,0 1908 1884 ) 1909 1885 ) 1910 1886 ) 1911 *4 4(CptPort1887 *43 (CptPort 1912 1888 uid 4246,0 1913 1889 ps "OnEdgeStrategy" … … 1938 1914 n "adc_data_array" 1939 1915 t "adc_data_array_type" 1940 o 3 01916 o 31 1941 1917 suid 37,0 1942 1918 ) 1943 1919 ) 1944 1920 ) 1945 *4 5(CptPort1921 *44 (CptPort 1946 1922 uid 5174,0 1947 1923 ps "OnEdgeStrategy" … … 1978 1954 ) 1979 1955 ) 1980 *4 6(CptPort1956 *45 (CptPort 1981 1957 uid 5178,0 1982 1958 ps "OnEdgeStrategy" … … 2018 1994 ) 2019 1995 ) 2020 *4 7(CptPort1996 *46 (CptPort 2021 1997 uid 5392,0 2022 1998 ps "OnEdgeStrategy" … … 2053 2029 ) 2054 2030 ) 2055 *4 8(CptPort2031 *47 (CptPort 2056 2032 uid 5396,0 2057 2033 ps "OnEdgeStrategy" … … 2088 2064 ) 2089 2065 ) 2090 *4 9(CptPort2066 *48 (CptPort 2091 2067 uid 5464,0 2092 2068 ps "OnEdgeStrategy" … … 2123 2099 ) 2124 2100 ) 2125 * 50(CptPort2101 *49 (CptPort 2126 2102 uid 5468,0 2127 2103 ps "OnEdgeStrategy" … … 2158 2134 ) 2159 2135 ) 2160 *5 1(CptPort2136 *50 (CptPort 2161 2137 uid 5735,0 2162 2138 ps "OnEdgeStrategy" … … 2198 2174 ) 2199 2175 ) 2200 *5 2(CptPort2176 *51 (CptPort 2201 2177 uid 5739,0 2202 2178 ps "OnEdgeStrategy" … … 2237 2213 ) 2238 2214 ) 2239 *5 3(CptPort2215 *52 (CptPort 2240 2216 uid 5916,0 2241 2217 ps "OnEdgeStrategy" … … 2268 2244 n "config_started" 2269 2245 t "std_logic" 2270 o 292246 o 30 2271 2247 suid 48,0 2272 2248 i "'0'" … … 2274 2250 ) 2275 2251 ) 2276 *5 4(CptPort2252 *53 (CptPort 2277 2253 uid 5920,0 2278 2254 ps "OnEdgeStrategy" … … 2306 2282 prec "-- s_trigger : in std_logic;" 2307 2283 preAdd 0 2308 o 2 82284 o 29 2309 2285 suid 49,0 2310 2286 ) 2311 2287 ) 2312 2288 ) 2313 *5 5(CptPort2289 *54 (CptPort 2314 2290 uid 5974,0 2315 2291 ps "OnEdgeStrategy" … … 2346 2322 ) 2347 2323 ) 2348 *5 6(CptPort2324 *55 (CptPort 2349 2325 uid 5978,0 2350 2326 ps "OnEdgeStrategy" … … 2381 2357 ) 2382 2358 ) 2383 *5 7(CptPort2359 *56 (CptPort 2384 2360 uid 5982,0 2385 2361 ps "OnEdgeStrategy" … … 2416 2392 ) 2417 2393 ) 2418 *5 8(CptPort2394 *57 (CptPort 2419 2395 uid 6060,0 2420 2396 ps "OnEdgeStrategy" … … 2451 2427 ) 2452 2428 ) 2453 *5 9(CptPort2429 *58 (CptPort 2454 2430 uid 9000,0 2455 2431 ps "OnEdgeStrategy" … … 2481 2457 n "adc_clk_en" 2482 2458 t "std_logic" 2483 o 3 22459 o 33 2484 2460 suid 54,0 2485 2461 i "'0'" … … 2487 2463 ) 2488 2464 ) 2489 * 60(CptPort2465 *59 (CptPort 2490 2466 uid 10244,0 2491 2467 ps "OnEdgeStrategy" … … 2518 2494 t "std_logic_vector" 2519 2495 b "(7 downto 0)" 2520 o 4 12496 o 42 2521 2497 suid 56,0 2522 2498 i "(others => '0')" … … 2524 2500 ) 2525 2501 ) 2526 *6 1(CptPort2502 *60 (CptPort 2527 2503 uid 10248,0 2528 2504 ps "OnEdgeStrategy" … … 2554 2530 n "drs_srin_write_8b" 2555 2531 t "std_logic" 2556 o 392532 o 40 2557 2533 suid 57,0 2558 2534 i "'0'" … … 2560 2536 ) 2561 2537 ) 2562 *6 2(CptPort2538 *61 (CptPort 2563 2539 uid 10252,0 2564 2540 ps "OnEdgeStrategy" … … 2589 2565 n "drs_srin_write_ack" 2590 2566 t "std_logic" 2591 o 4 02567 o 41 2592 2568 suid 58,0 2593 2569 ) 2594 2570 ) 2595 2571 ) 2596 *6 3(CptPort2572 *62 (CptPort 2597 2573 uid 10256,0 2598 2574 ps "OnEdgeStrategy" … … 2623 2599 n "drs_srin_write_ready" 2624 2600 t "std_logic" 2625 o 4 22601 o 43 2626 2602 suid 59,0 2627 2603 ) 2628 2604 ) 2629 2605 ) 2630 *6 4(CptPort2606 *63 (CptPort 2631 2607 uid 10260,0 2632 2608 ps "OnEdgeStrategy" … … 2666 2642 ) 2667 2643 ) 2668 *6 5(CptPort2644 *64 (CptPort 2669 2645 uid 11385,0 2670 2646 ps "OnEdgeStrategy" … … 2697 2673 n "drs_readout_started" 2698 2674 t "std_logic" 2699 o 4 52675 o 46 2700 2676 suid 61,0 2701 2677 i "'0'" … … 2703 2679 ) 2704 2680 ) 2705 *6 6(CptPort2681 *65 (CptPort 2706 2682 uid 12597,0 2707 2683 ps "OnEdgeStrategy" … … 2737 2713 preAdd 0 2738 2714 posAdd 0 2739 o 3 52715 o 36 2740 2716 suid 62,0 2741 2717 i "'0'" … … 2743 2719 ) 2744 2720 ) 2745 *6 7(CptPort2721 *66 (CptPort 2746 2722 uid 12601,0 2747 2723 ps "OnEdgeStrategy" … … 2772 2748 n "drs_readout_ready_ack" 2773 2749 t "std_logic" 2774 o 3 62750 o 37 2775 2751 suid 63,0 2752 ) 2753 ) 2754 ) 2755 *67 (CptPort 2756 uid 15740,0 2757 ps "OnEdgeStrategy" 2758 shape (Triangle 2759 uid 15741,0 2760 ro 90 2761 va (VaSet 2762 vasetType 1 2763 fg "0,65535,0" 2764 ) 2765 xt "-21750,69625,-21000,70375" 2766 ) 2767 tg (CPTG 2768 uid 15742,0 2769 ps "CptPortTextPlaceStrategy" 2770 stg "VerticalLayoutStrategy" 2771 f (Text 2772 uid 15743,0 2773 va (VaSet 2774 ) 2775 xt "-20000,69500,-10200,70500" 2776 st "fad_event_counter : (31:0)" 2777 blo "-20000,70300" 2778 ) 2779 ) 2780 thePort (LogicalPort 2781 decl (Decl 2782 n "fad_event_counter" 2783 t "std_logic_vector" 2784 b "(31 downto 0)" 2785 o 27 2786 suid 65,0 2787 ) 2788 ) 2789 ) 2790 *68 (CptPort 2791 uid 15744,0 2792 ps "OnEdgeStrategy" 2793 shape (Triangle 2794 uid 15745,0 2795 ro 90 2796 va (VaSet 2797 vasetType 1 2798 fg "0,65535,0" 2799 ) 2800 xt "-21750,95625,-21000,96375" 2801 ) 2802 tg (CPTG 2803 uid 15746,0 2804 ps "CptPortTextPlaceStrategy" 2805 stg "VerticalLayoutStrategy" 2806 f (Text 2807 uid 15747,0 2808 va (VaSet 2809 ) 2810 xt "-20000,95500,-14500,96500" 2811 st "pll_lock : (3:0)" 2812 blo "-20000,96300" 2813 ) 2814 ) 2815 thePort (LogicalPort 2816 decl (Decl 2817 n "pll_lock" 2818 t "std_logic_vector" 2819 b "( 3 downto 0)" 2820 o 24 2821 suid 64,0 2776 2822 ) 2777 2823 ) … … 2794 2840 stg "VerticalLayoutStrategy" 2795 2841 textVec [ 2796 *6 8(Text2842 *69 (Text 2797 2843 uid 1402,0 2798 2844 va (VaSet … … 2804 2850 tm "BdLibraryNameMgr" 2805 2851 ) 2806 * 69(Text2852 *70 (Text 2807 2853 uid 1403,0 2808 2854 va (VaSet … … 2814 2860 tm "CptNameMgr" 2815 2861 ) 2816 *7 0(Text2862 *71 (Text 2817 2863 uid 1404,0 2818 2864 va (VaSet … … 2867 2913 archFileType "UNKNOWN" 2868 2914 ) 2869 *7 1(Net2915 *72 (Net 2870 2916 uid 1409,0 2871 2917 decl (Decl … … 2886 2932 ) 2887 2933 ) 2888 *7 2(Net2934 *73 (Net 2889 2935 uid 1423,0 2890 2936 decl (Decl … … 2906 2952 ) 2907 2953 ) 2908 *7 3(PortIoIn2954 *74 (PortIoIn 2909 2955 uid 1443,0 2910 2956 shape (CompositeShape … … 2951 2997 ) 2952 2998 ) 2953 *7 4(SaComponent2999 *75 (SaComponent 2954 3000 uid 1606,0 2955 3001 optionalChildren [ 2956 *7 5(CptPort3002 *76 (CptPort 2957 3003 uid 1542,0 2958 3004 ps "OnEdgeStrategy" … … 2990 3036 ) 2991 3037 ) 2992 *7 6(CptPort3038 *77 (CptPort 2993 3039 uid 1546,0 2994 3040 ps "OnEdgeStrategy" … … 3029 3075 ) 3030 3076 ) 3031 *7 7(CptPort3077 *78 (CptPort 3032 3078 uid 1550,0 3033 3079 ps "OnEdgeStrategy" … … 3068 3114 ) 3069 3115 ) 3070 *7 8(CptPort3116 *79 (CptPort 3071 3117 uid 1554,0 3072 3118 ps "OnEdgeStrategy" … … 3107 3153 ) 3108 3154 ) 3109 * 79(CptPort3155 *80 (CptPort 3110 3156 uid 1558,0 3111 3157 ps "OnEdgeStrategy" … … 3146 3192 ) 3147 3193 ) 3148 *8 0(CptPort3194 *81 (CptPort 3149 3195 uid 1562,0 3150 3196 ps "OnEdgeStrategy" … … 3185 3231 ) 3186 3232 ) 3187 *8 1(CptPort3233 *82 (CptPort 3188 3234 uid 1570,0 3189 3235 ps "OnEdgeStrategy" … … 3224 3270 ) 3225 3271 ) 3226 *8 2(CptPort3272 *83 (CptPort 3227 3273 uid 1574,0 3228 3274 ps "OnEdgeStrategy" … … 3261 3307 ) 3262 3308 ) 3263 *8 3(CptPort3309 *84 (CptPort 3264 3310 uid 1578,0 3265 3311 ps "OnEdgeStrategy" … … 3298 3344 ) 3299 3345 ) 3300 *8 4(CptPort3346 *85 (CptPort 3301 3347 uid 1582,0 3302 3348 ps "OnEdgeStrategy" … … 3335 3381 ) 3336 3382 ) 3337 *8 5(CptPort3383 *86 (CptPort 3338 3384 uid 1586,0 3339 3385 ps "OnEdgeStrategy" … … 3372 3418 ) 3373 3419 ) 3374 *8 6(CptPort3420 *87 (CptPort 3375 3421 uid 1590,0 3376 3422 ps "OnEdgeStrategy" … … 3410 3456 ) 3411 3457 ) 3412 *8 7(CptPort3458 *88 (CptPort 3413 3459 uid 1594,0 3414 3460 ps "OnEdgeStrategy" … … 3446 3492 ) 3447 3493 ) 3448 *8 8(CptPort3494 *89 (CptPort 3449 3495 uid 1598,0 3450 3496 ps "OnEdgeStrategy" … … 3484 3530 ) 3485 3531 ) 3486 * 89(CptPort3532 *90 (CptPort 3487 3533 uid 2218,0 3488 3534 ps "OnEdgeStrategy" … … 3520 3566 ) 3521 3567 ) 3522 *9 0(CptPort3568 *91 (CptPort 3523 3569 uid 2222,0 3524 3570 ps "OnEdgeStrategy" … … 3554 3600 ) 3555 3601 ) 3556 *9 1(CptPort3602 *92 (CptPort 3557 3603 uid 2226,0 3558 3604 ps "OnEdgeStrategy" … … 3588 3634 ) 3589 3635 ) 3590 *9 2(CptPort3636 *93 (CptPort 3591 3637 uid 5216,0 3592 3638 ps "OnEdgeStrategy" … … 3627 3673 ) 3628 3674 ) 3629 *9 3(CptPort3675 *94 (CptPort 3630 3676 uid 5275,0 3631 3677 ps "OnEdgeStrategy" … … 3665 3711 ) 3666 3712 ) 3667 *9 4(CptPort3713 *95 (CptPort 3668 3714 uid 5924,0 3669 3715 ps "OnEdgeStrategy" … … 3701 3747 ) 3702 3748 ) 3703 *9 5(CptPort3749 *96 (CptPort 3704 3750 uid 5928,0 3705 3751 ps "OnEdgeStrategy" … … 3737 3783 ) 3738 3784 ) 3739 *9 6(CptPort3785 *97 (CptPort 3740 3786 uid 5932,0 3741 3787 ps "OnEdgeStrategy" … … 3774 3820 ) 3775 3821 ) 3776 *9 7(CptPort3822 *98 (CptPort 3777 3823 uid 5936,0 3778 3824 ps "OnEdgeStrategy" … … 3808 3854 ) 3809 3855 ) 3810 *9 8(CptPort3856 *99 (CptPort 3811 3857 uid 5940,0 3812 3858 ps "OnEdgeStrategy" … … 3844 3890 ) 3845 3891 ) 3846 * 99(CptPort3892 *100 (CptPort 3847 3893 uid 5944,0 3848 3894 ps "OnEdgeStrategy" … … 3882 3928 ) 3883 3929 ) 3884 *10 0(CptPort3930 *101 (CptPort 3885 3931 uid 5970,0 3886 3932 ps "OnEdgeStrategy" … … 3919 3965 ) 3920 3966 ) 3921 *10 1(CptPort3967 *102 (CptPort 3922 3968 uid 6356,0 3923 3969 ps "OnEdgeStrategy" … … 3958 4004 ) 3959 4005 ) 3960 *10 2(CptPort4006 *103 (CptPort 3961 4007 uid 6446,0 3962 4008 ps "OnEdgeStrategy" … … 3998 4044 ) 3999 4045 ) 4000 *10 3(CptPort4046 *104 (CptPort 4001 4047 uid 8406,0 4002 4048 ps "OnEdgeStrategy" … … 4034 4080 ) 4035 4081 ) 4036 *10 4(CptPort4082 *105 (CptPort 4037 4083 uid 8748,0 4038 4084 ps "OnEdgeStrategy" … … 4073 4119 ) 4074 4120 ) 4075 *10 5(CptPort4121 *106 (CptPort 4076 4122 uid 9223,0 4077 4123 ps "OnEdgeStrategy" … … 4112 4158 ) 4113 4159 ) 4114 *10 6(CptPort4160 *107 (CptPort 4115 4161 uid 9227,0 4116 4162 ps "OnEdgeStrategy" … … 4152 4198 ) 4153 4199 ) 4154 *10 7(CptPort4200 *108 (CptPort 4155 4201 uid 9933,0 4156 4202 ps "OnEdgeStrategy" … … 4191 4237 ) 4192 4238 ) 4193 *10 8(CptPort4239 *109 (CptPort 4194 4240 uid 9937,0 4195 4241 ps "OnEdgeStrategy" … … 4230 4276 ) 4231 4277 ) 4232 *1 09(CptPort4278 *110 (CptPort 4233 4279 uid 10212,0 4234 4280 ps "OnEdgeStrategy" … … 4267 4313 ) 4268 4314 ) 4269 *11 0(CptPort4315 *111 (CptPort 4270 4316 uid 10216,0 4271 4317 ps "OnEdgeStrategy" … … 4304 4350 ) 4305 4351 ) 4306 *11 1(CptPort4352 *112 (CptPort 4307 4353 uid 10619,0 4308 4354 ps "OnEdgeStrategy" … … 4340 4386 ) 4341 4387 ) 4342 *11 2(CptPort4388 *113 (CptPort 4343 4389 uid 10623,0 4344 4390 ps "OnEdgeStrategy" … … 4377 4423 ) 4378 4424 ) 4379 *11 3(CptPort4425 *114 (CptPort 4380 4426 uid 11838,0 4381 4427 ps "OnEdgeStrategy" … … 4416 4462 ) 4417 4463 ) 4418 *11 4(CptPort4464 *115 (CptPort 4419 4465 uid 13149,0 4420 4466 ps "OnEdgeStrategy" … … 4452 4498 ) 4453 4499 ) 4454 *11 5(CptPort4500 *116 (CptPort 4455 4501 uid 13153,0 4456 4502 ps "OnEdgeStrategy" … … 4491 4537 ) 4492 4538 ) 4493 *11 6(CptPort4539 *117 (CptPort 4494 4540 uid 13806,0 4495 4541 ps "OnEdgeStrategy" … … 4526 4572 ) 4527 4573 ) 4528 *11 7(CptPort4574 *118 (CptPort 4529 4575 uid 13911,0 4530 4576 ps "OnEdgeStrategy" … … 4561 4607 ) 4562 4608 ) 4563 *11 8(CptPort4609 *119 (CptPort 4564 4610 uid 13915,0 4565 4611 ps "OnEdgeStrategy" … … 4613 4659 stg "VerticalLayoutStrategy" 4614 4660 textVec [ 4615 *1 19(Text4661 *120 (Text 4616 4662 uid 1609,0 4617 4663 va (VaSet … … 4623 4669 tm "BdLibraryNameMgr" 4624 4670 ) 4625 *12 0(Text4671 *121 (Text 4626 4672 uid 1610,0 4627 4673 va (VaSet … … 4633 4679 tm "CptNameMgr" 4634 4680 ) 4635 *12 1(Text4681 *122 (Text 4636 4682 uid 1611,0 4637 4683 va (VaSet … … 4686 4732 archFileType "UNKNOWN" 4687 4733 ) 4688 *12 2(Net4734 *123 (Net 4689 4735 uid 1680,0 4690 4736 decl (Decl … … 4705 4751 ) 4706 4752 ) 4707 *12 3(SaComponent4753 *124 (SaComponent 4708 4754 uid 1768,0 4709 4755 optionalChildren [ 4710 *12 4(CptPort4756 *125 (CptPort 4711 4757 uid 1760,0 4712 4758 ps "OnEdgeStrategy" … … 4729 4775 ) 4730 4776 xt "-48800,68500,-42000,69500" 4731 st "trigger_id : ( 47:0)"4777 st "trigger_id : (31:0)" 4732 4778 ju 2 4733 4779 blo "-42000,69300" … … 4740 4786 n "trigger_id" 4741 4787 t "std_logic_vector" 4742 b "( 47downto 0)"4788 b "(31 downto 0)" 4743 4789 preAdd 0 4744 4790 posAdd 0 … … 4748 4794 ) 4749 4795 ) 4750 *12 5(CptPort4796 *126 (CptPort 4751 4797 uid 1764,0 4752 4798 ps "OnEdgeStrategy" … … 4785 4831 ) 4786 4832 ) 4787 *12 6(CptPort4833 *127 (CptPort 4788 4834 uid 6207,0 4789 4835 ps "OnEdgeStrategy" … … 4837 4883 stg "VerticalLayoutStrategy" 4838 4884 textVec [ 4839 *12 7(Text4885 *128 (Text 4840 4886 uid 1771,0 4841 4887 va (VaSet … … 4848 4894 tm "BdLibraryNameMgr" 4849 4895 ) 4850 *12 8(Text4896 *129 (Text 4851 4897 uid 1772,0 4852 4898 va (VaSet … … 4859 4905 tm "CptNameMgr" 4860 4906 ) 4861 *1 29(Text4907 *130 (Text 4862 4908 uid 1773,0 4863 4909 va (VaSet … … 4907 4953 ) 4908 4954 archFileType "UNKNOWN" 4909 )4910 *130 (Net4911 uid 1981,04912 lang 24913 decl (Decl4914 n "trigger_id"4915 t "std_logic_vector"4916 b "(47 downto 0)"4917 preAdd 04918 posAdd 04919 o 1194920 suid 34,04921 )4922 declText (MLText4923 uid 1982,04924 va (VaSet4925 font "Courier New,8,0"4926 )4927 xt "-172000,98800,-139500,99600"4928 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)4929 "4930 )4931 4955 ) 4932 4956 *131 (Net … … 17011 17035 ) 17012 17036 ) 17013 *599 (Wire 17037 *599 (SaComponent 17038 uid 15728,0 17039 optionalChildren [ 17040 *600 (CptPort 17041 uid 15712,0 17042 ps "OnEdgeStrategy" 17043 shape (Triangle 17044 uid 15713,0 17045 ro 90 17046 va (VaSet 17047 vasetType 1 17048 fg "0,65535,0" 17049 ) 17050 xt "-83750,113625,-83000,114375" 17051 ) 17052 tg (CPTG 17053 uid 15714,0 17054 ps "CptPortTextPlaceStrategy" 17055 stg "VerticalLayoutStrategy" 17056 f (Text 17057 uid 15715,0 17058 va (VaSet 17059 ) 17060 xt "-82000,113500,-80700,114500" 17061 st "clk" 17062 blo "-82000,114300" 17063 ) 17064 ) 17065 thePort (LogicalPort 17066 decl (Decl 17067 n "clk" 17068 t "STD_LOGIC" 17069 preAdd 0 17070 posAdd 0 17071 o 1 17072 suid 1,0 17073 ) 17074 ) 17075 ) 17076 *601 (CptPort 17077 uid 15716,0 17078 ps "OnEdgeStrategy" 17079 shape (Triangle 17080 uid 15717,0 17081 ro 90 17082 va (VaSet 17083 vasetType 1 17084 fg "0,65535,0" 17085 ) 17086 xt "-83750,115625,-83000,116375" 17087 ) 17088 tg (CPTG 17089 uid 15718,0 17090 ps "CptPortTextPlaceStrategy" 17091 stg "VerticalLayoutStrategy" 17092 f (Text 17093 uid 15719,0 17094 va (VaSet 17095 ) 17096 xt "-82000,115500,-80100,116500" 17097 st "start" 17098 blo "-82000,116300" 17099 ) 17100 ) 17101 thePort (LogicalPort 17102 decl (Decl 17103 n "start" 17104 t "STD_LOGIC" 17105 preAdd 0 17106 posAdd 0 17107 o 2 17108 suid 2,0 17109 ) 17110 ) 17111 ) 17112 *602 (CptPort 17113 uid 15720,0 17114 ps "OnEdgeStrategy" 17115 shape (Triangle 17116 uid 15721,0 17117 ro 90 17118 va (VaSet 17119 vasetType 1 17120 fg "0,65535,0" 17121 ) 17122 xt "-73000,113625,-72250,114375" 17123 ) 17124 tg (CPTG 17125 uid 15722,0 17126 ps "CptPortTextPlaceStrategy" 17127 stg "RightVerticalLayoutStrategy" 17128 f (Text 17129 uid 15723,0 17130 va (VaSet 17131 ) 17132 xt "-78600,113500,-74000,114500" 17133 st "dna : (63:0)" 17134 ju 2 17135 blo "-74000,114300" 17136 ) 17137 t (Text 17138 uid 15738,0 17139 va (VaSet 17140 ) 17141 xt "-79700,114500,-74000,115500" 17142 st "(others => '0')" 17143 ju 2 17144 blo "-74000,115300" 17145 ) 17146 ) 17147 thePort (LogicalPort 17148 m 1 17149 decl (Decl 17150 n "dna" 17151 t "STD_LOGIC_VECTOR" 17152 b "(63 downto 0)" 17153 preAdd 0 17154 posAdd 0 17155 o 3 17156 suid 3,0 17157 i "(others => '0')" 17158 ) 17159 ) 17160 ) 17161 *603 (CptPort 17162 uid 15724,0 17163 ps "OnEdgeStrategy" 17164 shape (Triangle 17165 uid 15725,0 17166 ro 90 17167 va (VaSet 17168 vasetType 1 17169 fg "0,65535,0" 17170 ) 17171 xt "-73000,115625,-72250,116375" 17172 ) 17173 tg (CPTG 17174 uid 15726,0 17175 ps "CptPortTextPlaceStrategy" 17176 stg "RightVerticalLayoutStrategy" 17177 f (Text 17178 uid 15727,0 17179 va (VaSet 17180 ) 17181 xt "-76200,115500,-74000,116500" 17182 st "ready" 17183 ju 2 17184 blo "-74000,116300" 17185 ) 17186 t (Text 17187 uid 15739,0 17188 va (VaSet 17189 ) 17190 xt "-75200,116500,-74000,117500" 17191 st "'0'" 17192 ju 2 17193 blo "-74000,117300" 17194 ) 17195 ) 17196 thePort (LogicalPort 17197 m 1 17198 decl (Decl 17199 n "ready" 17200 t "STD_LOGIC" 17201 preAdd 0 17202 posAdd 0 17203 o 4 17204 suid 4,0 17205 i "'0'" 17206 ) 17207 ) 17208 ) 17209 ] 17210 shape (Rectangle 17211 uid 15729,0 17212 va (VaSet 17213 vasetType 1 17214 fg "0,65535,0" 17215 lineColor "0,32896,0" 17216 lineWidth 2 17217 ) 17218 xt "-83000,112000,-73000,118000" 17219 ) 17220 oxt "39000,2000,49000,12000" 17221 ttg (MlTextGroup 17222 uid 15730,0 17223 ps "CenterOffsetStrategy" 17224 stg "VerticalLayoutStrategy" 17225 textVec [ 17226 *604 (Text 17227 uid 15731,0 17228 va (VaSet 17229 font "Arial,8,1" 17230 ) 17231 xt "-80800,118000,-74600,119000" 17232 st "FACT_FAD_lib" 17233 blo "-80800,118800" 17234 tm "BdLibraryNameMgr" 17235 ) 17236 *605 (Text 17237 uid 15732,0 17238 va (VaSet 17239 font "Arial,8,1" 17240 ) 17241 xt "-80800,119000,-77200,120000" 17242 st "dna_gen" 17243 blo "-80800,119800" 17244 tm "CptNameMgr" 17245 ) 17246 *606 (Text 17247 uid 15733,0 17248 va (VaSet 17249 font "Arial,8,1" 17250 ) 17251 xt "-80800,120000,-79000,121000" 17252 st "U_0" 17253 blo "-80800,120800" 17254 tm "InstanceNameMgr" 17255 ) 17256 ] 17257 ) 17258 ga (GenericAssociation 17259 uid 15734,0 17260 ps "EdgeToEdgeStrategy" 17261 matrix (Matrix 17262 uid 15735,0 17263 text (MLText 17264 uid 15736,0 17265 va (VaSet 17266 font "Courier New,8,0" 17267 ) 17268 xt "-83000,111000,-83000,111000" 17269 ) 17270 header "" 17271 ) 17272 elements [ 17273 ] 17274 ) 17275 viewicon (ZoomableIcon 17276 uid 15737,0 17277 sl 0 17278 va (VaSet 17279 vasetType 1 17280 fg "49152,49152,49152" 17281 ) 17282 xt "-82750,116250,-81250,117750" 17283 iconName "VhdlFileViewIcon.png" 17284 iconMaskName "VhdlFileViewIcon.msk" 17285 ftype 10 17286 ) 17287 ordering 1 17288 viewiconposition 0 17289 portVis (PortSigDisplay 17290 sIVOD 1 17291 ) 17292 archFileType "UNKNOWN" 17293 ) 17294 *607 (Net 17295 uid 15748,0 17296 lang 2 17297 decl (Decl 17298 n "trigger_id" 17299 t "std_logic_vector" 17300 b "(31 downto 0)" 17301 preAdd 0 17302 posAdd 0 17303 o 123 17304 suid 302,0 17305 ) 17306 declText (MLText 17307 uid 15749,0 17308 va (VaSet 17309 font "Courier New,8,0" 17310 ) 17311 xt "-172000,98800,-139500,99600" 17312 st "SIGNAL trigger_id : std_logic_vector(31 downto 0) 17313 " 17314 ) 17315 ) 17316 *608 (Wire 17014 17317 uid 322,0 17015 17318 shape (OrthoPolyLine … … 17050 17353 on &2 17051 17354 ) 17052 *60 0(Wire17355 *609 (Wire 17053 17356 uid 328,0 17054 17357 shape (OrthoPolyLine … … 17089 17392 on &3 17090 17393 ) 17091 *6 01(Wire17394 *610 (Wire 17092 17395 uid 334,0 17093 17396 shape (OrthoPolyLine … … 17128 17431 on &4 17129 17432 ) 17130 *6 02(Wire17433 *611 (Wire 17131 17434 uid 364,0 17132 17435 shape (OrthoPolyLine … … 17144 17447 ] 17145 17448 ) 17146 start &8 617449 start &87 17147 17450 end &336 17148 17451 sat 32 … … 17168 17471 on &5 17169 17472 ) 17170 *6 03(Wire17473 *612 (Wire 17171 17474 uid 370,0 17172 17475 shape (OrthoPolyLine … … 17184 17487 ] 17185 17488 ) 17186 start &8 517489 start &86 17187 17490 end &337 17188 17491 sat 32 … … 17208 17511 on &6 17209 17512 ) 17210 *6 04(Wire17513 *613 (Wire 17211 17514 uid 376,0 17212 17515 shape (OrthoPolyLine … … 17221 17524 ] 17222 17525 ) 17223 start &7 617526 start &77 17224 17527 end &14 17225 17528 sat 32 … … 17246 17549 on &7 17247 17550 ) 17248 *6 05(Wire17551 *614 (Wire 17249 17552 uid 384,0 17250 17553 shape (OrthoPolyLine … … 17260 17563 ] 17261 17564 ) 17262 start &7 717565 start &78 17263 17566 end &15 17264 17567 sat 32 … … 17286 17589 on &8 17287 17590 ) 17288 *6 06(Wire17591 *615 (Wire 17289 17592 uid 392,0 17290 17593 shape (OrthoPolyLine … … 17300 17603 ] 17301 17604 ) 17302 start &7 817605 start &79 17303 17606 end &16 17304 17607 sat 32 … … 17326 17629 on &9 17327 17630 ) 17328 *6 07(Wire17631 *616 (Wire 17329 17632 uid 400,0 17330 17633 shape (OrthoPolyLine … … 17339 17642 ] 17340 17643 ) 17341 start & 7917644 start &80 17342 17645 end &17 17343 17646 sat 32 … … 17364 17667 on &10 17365 17668 ) 17366 *6 08(Wire17669 *617 (Wire 17367 17670 uid 408,0 17368 17671 shape (OrthoPolyLine … … 17377 17680 ] 17378 17681 ) 17379 start &8 017682 start &81 17380 17683 end &18 17381 17684 sat 32 … … 17402 17705 on &11 17403 17706 ) 17404 *6 09(Wire17707 *618 (Wire 17405 17708 uid 424,0 17406 17709 shape (OrthoPolyLine … … 17415 17718 ] 17416 17719 ) 17417 start &8 117720 start &82 17418 17721 end &20 17419 17722 sat 32 … … 17440 17743 on &12 17441 17744 ) 17442 *61 0(Wire17745 *619 (Wire 17443 17746 uid 432,0 17444 17747 shape (OrthoPolyLine … … 17454 17757 ) 17455 17758 start &21 17456 end &8 217759 end &83 17457 17760 sat 32 17458 17761 eat 32 … … 17478 17781 on &13 17479 17782 ) 17480 *6 11(Wire17783 *620 (Wire 17481 17784 uid 1411,0 17482 17785 shape (OrthoPolyLine … … 17515 17818 ) 17516 17819 ) 17517 on &7 117518 ) 17519 *6 12(Wire17820 on &72 17821 ) 17822 *621 (Wire 17520 17823 uid 1425,0 17521 17824 shape (OrthoPolyLine … … 17530 17833 ] 17531 17834 ) 17532 start &7 317835 start &74 17533 17836 end &409 17534 17837 es 0 … … 17554 17857 ) 17555 17858 ) 17556 on &7 217557 ) 17558 *6 13(Wire17859 on &73 17860 ) 17861 *622 (Wire 17559 17862 uid 1682,0 17560 17863 shape (OrthoPolyLine … … 17571 17874 ) 17572 17875 start &173 17573 end &3 117876 end &30 17574 17877 sat 32 17575 17878 eat 32 … … 17593 17896 ) 17594 17897 ) 17595 on &122 17596 ) 17597 *614 (Wire 17598 uid 1983,0 17599 shape (OrthoPolyLine 17600 uid 1984,0 17601 va (VaSet 17602 vasetType 3 17603 lineWidth 2 17604 ) 17605 xt "-40250,69000,-21750,70000" 17606 pts [ 17607 "-40250,69000" 17608 "-36000,69000" 17609 "-36000,70000" 17610 "-21750,70000" 17611 ] 17612 ) 17613 start &124 17614 end &29 17615 sat 32 17616 eat 32 17617 sty 1 17618 st 0 17619 sf 1 17620 tg (WTG 17621 uid 1985,0 17622 ps "ConnStartEndStrategy" 17623 stg "STSignalDisplayStrategy" 17624 f (Text 17625 uid 1986,0 17626 va (VaSet 17627 ) 17628 xt "-29000,70000,-22200,71000" 17629 st "trigger_id : (47:0)" 17630 blo "-29000,70800" 17631 tm "WireNameMgr" 17632 ) 17633 ) 17634 on &130 17635 ) 17636 *615 (Wire 17898 on &123 17899 ) 17900 *623 (Wire 17637 17901 uid 2299,0 17638 17902 shape (OrthoPolyLine … … 17672 17936 on &131 17673 17937 ) 17674 *6 16(Wire17938 *624 (Wire 17675 17939 uid 2470,0 17676 17940 shape (OrthoPolyLine … … 17686 17950 ) 17687 17951 start &140 17688 end &8 817952 end &89 17689 17953 sat 32 17690 17954 eat 32 … … 17708 17972 on &155 17709 17973 ) 17710 *6 17(Wire17974 *625 (Wire 17711 17975 uid 2476,0 17712 17976 shape (OrthoPolyLine … … 17722 17986 ) 17723 17987 start &143 17724 end &8 717988 end &88 17725 17989 sat 32 17726 17990 eat 32 … … 17744 18008 on &156 17745 18009 ) 17746 *6 18(Wire18010 *626 (Wire 17747 18011 uid 2482,0 17748 18012 shape (OrthoPolyLine … … 17759 18023 ) 17760 18024 start &146 17761 end &8 318025 end &84 17762 18026 sat 32 17763 18027 eat 32 … … 17782 18046 on &157 17783 18047 ) 17784 *6 19(Wire18048 *627 (Wire 17785 18049 uid 2488,0 17786 18050 shape (OrthoPolyLine … … 17797 18061 ) 17798 18062 start &142 17799 end &8 418063 end &85 17800 18064 sat 32 17801 18065 eat 32 … … 17820 18084 on &158 17821 18085 ) 17822 *62 0(Wire18086 *628 (Wire 17823 18087 uid 2494,0 17824 18088 shape (OrthoPolyLine … … 17835 18099 ) 17836 18100 start &141 17837 end & 8918101 end &90 17838 18102 sat 32 17839 18103 eat 32 … … 17858 18122 on &159 17859 18123 ) 17860 *62 1(Wire18124 *629 (Wire 17861 18125 uid 2500,0 17862 18126 shape (OrthoPolyLine … … 17872 18136 ) 17873 18137 start &144 17874 end &9 018138 end &91 17875 18139 sat 32 17876 18140 eat 32 … … 17894 18158 on &160 17895 18159 ) 17896 *6 22(Wire18160 *630 (Wire 17897 18161 uid 2506,0 17898 18162 shape (OrthoPolyLine … … 17908 18172 ) 17909 18173 start &145 17910 end &9 118174 end &92 17911 18175 sat 32 17912 18176 eat 32 … … 17930 18194 on &161 17931 18195 ) 17932 *6 23(Wire18196 *631 (Wire 17933 18197 uid 2576,0 17934 18198 shape (OrthoPolyLine … … 17943 18207 ] 17944 18208 ) 17945 start &3 218209 start &31 17946 18210 end &137 17947 18211 sat 32 … … 17966 18230 on &162 17967 18231 ) 17968 *6 24(Wire18232 *632 (Wire 17969 18233 uid 2582,0 17970 18234 shape (OrthoPolyLine … … 17979 18243 ] 17980 18244 ) 17981 start &3 318245 start &32 17982 18246 end &138 17983 18247 sat 32 … … 18002 18266 on &163 18003 18267 ) 18004 *6 25(Wire18268 *633 (Wire 18005 18269 uid 2588,0 18006 18270 shape (OrthoPolyLine … … 18015 18279 ] 18016 18280 ) 18017 start &5 118281 start &50 18018 18282 end &136 18019 18283 ss 0 … … 18039 18303 on &164 18040 18304 ) 18041 *6 26(Wire18305 *634 (Wire 18042 18306 uid 2594,0 18043 18307 shape (OrthoPolyLine … … 18052 18316 ] 18053 18317 ) 18054 start &4 718318 start &46 18055 18319 end &135 18056 18320 sat 32 … … 18075 18339 on &165 18076 18340 ) 18077 *6 27(Wire18341 *635 (Wire 18078 18342 uid 2600,0 18079 18343 shape (OrthoPolyLine … … 18088 18352 ] 18089 18353 ) 18090 start &3 418354 start &33 18091 18355 end &139 18092 18356 sat 32 … … 18111 18375 on &166 18112 18376 ) 18113 *6 28(Wire18377 *636 (Wire 18114 18378 uid 2642,0 18115 18379 shape (OrthoPolyLine … … 18125 18389 ] 18126 18390 ) 18127 start &3 618391 start &35 18128 18392 end &148 18129 18393 sat 32 … … 18149 18413 on &167 18150 18414 ) 18151 *6 29(Wire18415 *637 (Wire 18152 18416 uid 2778,0 18153 18417 shape (OrthoPolyLine … … 18162 18426 ] 18163 18427 ) 18164 start &3 718428 start &36 18165 18429 end &169 18166 18430 sat 32 … … 18187 18451 on &168 18188 18452 ) 18189 *63 0(Wire18453 *638 (Wire 18190 18454 uid 2786,0 18191 18455 shape (OrthoPolyLine … … 18227 18491 on &191 18228 18492 ) 18229 *63 1(Wire18493 *639 (Wire 18230 18494 uid 3888,0 18231 18495 optionalChildren [ 18232 *6 32(BdJunction18496 *640 (BdJunction 18233 18497 uid 4230,0 18234 18498 ps "OnConnectorStrategy" … … 18242 18506 ) 18243 18507 ) 18244 *6 33(BdJunction18508 *641 (BdJunction 18245 18509 uid 4244,0 18246 18510 ps "OnConnectorStrategy" … … 18270 18534 ) 18271 18535 start &365 18272 end &7 518536 end &76 18273 18537 sat 32 18274 18538 eat 32 … … 18293 18557 on &187 18294 18558 ) 18295 *6 34(Wire18559 *642 (Wire 18296 18560 uid 3984,0 18297 18561 shape (OrthoPolyLine … … 18334 18598 on &185 18335 18599 ) 18336 *6 35(Wire18600 *643 (Wire 18337 18601 uid 4042,0 18338 18602 shape (OrthoPolyLine … … 18372 18636 on &190 18373 18637 ) 18374 *6 36(Wire18638 *644 (Wire 18375 18639 uid 4226,0 18376 18640 shape (OrthoPolyLine … … 18388 18652 ) 18389 18653 start &189 18390 end &6 3218654 end &640 18391 18655 sat 32 18392 18656 eat 32 … … 18412 18676 on &187 18413 18677 ) 18414 *6 37(Wire18678 *645 (Wire 18415 18679 uid 4240,0 18416 18680 shape (OrthoPolyLine … … 18428 18692 ) 18429 18693 start &335 18430 end &6 3318694 end &641 18431 18695 sat 32 18432 18696 eat 32 … … 18451 18715 on &187 18452 18716 ) 18453 *6 38(Wire18717 *646 (Wire 18454 18718 uid 4272,0 18455 18719 shape (OrthoPolyLine … … 18489 18753 on &192 18490 18754 ) 18491 *6 39(Wire18755 *647 (Wire 18492 18756 uid 4401,0 18493 18757 shape (OrthoPolyLine … … 18504 18768 ] 18505 18769 ) 18506 start & 4018770 start &39 18507 18771 end &212 18508 18772 sat 32 … … 18527 18791 on &194 18528 18792 ) 18529 *64 0(Wire18793 *648 (Wire 18530 18794 uid 4407,0 18531 18795 shape (OrthoPolyLine … … 18542 18806 ] 18543 18807 ) 18544 start &4 318808 start &42 18545 18809 end &218 18546 18810 sat 32 … … 18565 18829 on &195 18566 18830 ) 18567 *64 1(Wire18831 *649 (Wire 18568 18832 uid 4419,0 18569 18833 shape (OrthoPolyLine … … 18580 18844 ] 18581 18845 ) 18582 start &4 118846 start &40 18583 18847 end &213 18584 18848 sat 32 … … 18603 18867 on &196 18604 18868 ) 18605 *6 42(Wire18869 *650 (Wire 18606 18870 uid 4537,0 18607 18871 shape (OrthoPolyLine … … 18617 18881 ] 18618 18882 ) 18619 start &3 918883 start &38 18620 18884 end &199 18621 18885 sat 32 … … 18643 18907 on &197 18644 18908 ) 18645 *6 43(Wire18909 *651 (Wire 18646 18910 uid 4545,0 18647 18911 shape (OrthoPolyLine … … 18680 18944 on &198 18681 18945 ) 18682 *6 44(Wire18946 *652 (Wire 18683 18947 uid 4671,0 18684 18948 shape (OrthoPolyLine … … 18718 18982 on &201 18719 18983 ) 18720 *6 45(Wire18984 *653 (Wire 18721 18985 uid 4679,0 18722 18986 shape (OrthoPolyLine … … 18756 19020 on &202 18757 19021 ) 18758 *6 46(Wire19022 *654 (Wire 18759 19023 uid 4687,0 18760 19024 shape (OrthoPolyLine … … 18794 19058 on &203 18795 19059 ) 18796 *6 47(Wire19060 *655 (Wire 18797 19061 uid 4695,0 18798 19062 shape (OrthoPolyLine … … 18832 19096 on &204 18833 19097 ) 18834 *6 48(Wire19098 *656 (Wire 18835 19099 uid 4743,0 18836 19100 shape (OrthoPolyLine … … 18848 19112 ) 18849 19113 start &219 18850 end &4 219114 end &41 18851 19115 sat 32 18852 19116 eat 32 … … 18870 19134 on &209 18871 19135 ) 18872 *6 49(Wire19136 *657 (Wire 18873 19137 uid 4757,0 18874 19138 optionalChildren [ 18875 *65 0(BdJunction19139 *658 (BdJunction 18876 19140 uid 6076,0 18877 19141 ps "OnConnectorStrategy" … … 18881 19145 vasetType 1 18882 19146 ) 18883 xt "-2 5400,40600,-24600,41400"19147 xt "-26400,40600,-25600,41400" 18884 19148 radius 400 18885 19149 ) … … 18892 19156 lineColor "0,32896,0" 18893 19157 ) 18894 xt "-6 2000,41000,-25000,48000"19158 xt "-64000,41000,-26000,48000" 18895 19159 pts [ 18896 19160 "-58750,48000" 18897 "-6 2000,48000"18898 "-6 2000,41000"18899 "-2 5000,41000"19161 "-64000,48000" 19162 "-64000,41000" 19163 "-26000,41000" 18900 19164 ] 18901 19165 ) 18902 19166 start &211 18903 end *65 1(BdJunction19167 end *659 (BdJunction 18904 19168 uid 6080,0 18905 19169 ps "OnConnectorStrategy" … … 18909 19173 vasetType 1 18910 19174 ) 18911 xt "-2 5400,40600,-24600,41400"19175 xt "-26400,40600,-25600,41400" 18912 19176 radius 400 18913 19177 ) … … 18935 19199 on &188 18936 19200 ) 18937 *6 52(Wire19201 *660 (Wire 18938 19202 uid 4948,0 18939 19203 shape (OrthoPolyLine … … 18973 19237 on &230 18974 19238 ) 18975 *6 53(Wire19239 *661 (Wire 18976 19240 uid 4962,0 18977 19241 shape (OrthoPolyLine … … 19011 19275 on &232 19012 19276 ) 19013 *6 54(Wire19277 *662 (Wire 19014 19278 uid 5090,0 19015 19279 shape (OrthoPolyLine … … 19027 19291 ] 19028 19292 ) 19029 start &9 419293 start &95 19030 19294 end &236 19031 19295 sat 32 … … 19050 19314 on &252 19051 19315 ) 19052 *6 55(Wire19316 *663 (Wire 19053 19317 uid 5098,0 19054 19318 shape (OrthoPolyLine … … 19084 19348 on &253 19085 19349 ) 19086 *6 56(Wire19350 *664 (Wire 19087 19351 uid 5106,0 19088 19352 shape (OrthoPolyLine … … 19100 19364 ) 19101 19365 start &238 19102 end &9 519366 end &96 19103 19367 sat 32 19104 19368 eat 32 … … 19121 19385 on &254 19122 19386 ) 19123 *6 57(Wire19387 *665 (Wire 19124 19388 uid 5114,0 19125 19389 shape (OrthoPolyLine … … 19138 19402 ) 19139 19403 start &239 19140 end &9 619404 end &97 19141 19405 sat 32 19142 19406 eat 32 … … 19160 19424 on &255 19161 19425 ) 19162 *6 58(Wire19426 *666 (Wire 19163 19427 uid 5122,0 19164 19428 shape (OrthoPolyLine … … 19175 19439 ] 19176 19440 ) 19177 start &9 819441 start &99 19178 19442 end &241 19179 19443 sat 32 … … 19197 19461 on &256 19198 19462 ) 19199 *6 59(Wire19463 *667 (Wire 19200 19464 uid 5130,0 19201 19465 shape (OrthoPolyLine … … 19212 19476 ] 19213 19477 ) 19214 start &10 019478 start &101 19215 19479 end &243 19216 19480 sat 32 … … 19234 19498 on &257 19235 19499 ) 19236 *66 0(Wire19500 *668 (Wire 19237 19501 uid 5138,0 19238 19502 optionalChildren [ 19239 *66 1(BdJunction19503 *669 (BdJunction 19240 19504 uid 5400,0 19241 19505 ps "OnConnectorStrategy" … … 19264 19528 ) 19265 19529 start &240 19266 end &3 519530 end &34 19267 19531 ss 0 19268 19532 es 0 … … 19287 19551 on &171 19288 19552 ) 19289 *6 62(Wire19553 *670 (Wire 19290 19554 uid 5146,0 19291 19555 shape (OrthoPolyLine … … 19323 19587 on &258 19324 19588 ) 19325 *6 63(Wire19589 *671 (Wire 19326 19590 uid 5168,0 19327 19591 shape (OrthoPolyLine … … 19338 19602 ] 19339 19603 ) 19340 start &66 119604 start &669 19341 19605 end &147 19342 19606 sat 32 … … 19361 19625 on &171 19362 19626 ) 19363 *6 64(Wire19627 *672 (Wire 19364 19628 uid 5184,0 19365 19629 shape (OrthoPolyLine … … 19377 19641 ) 19378 19642 start &244 19379 end &4 619643 end &45 19380 19644 sat 32 19381 19645 eat 32 … … 19398 19662 on &259 19399 19663 ) 19400 *6 65(Wire19664 *673 (Wire 19401 19665 uid 5190,0 19402 19666 shape (OrthoPolyLine … … 19414 19678 ) 19415 19679 start &245 19416 end &4 519680 end &44 19417 19681 sat 32 19418 19682 eat 32 … … 19435 19699 on &260 19436 19700 ) 19437 *6 66(Wire19701 *674 (Wire 19438 19702 uid 5222,0 19439 19703 shape (OrthoPolyLine … … 19449 19713 ] 19450 19714 ) 19451 start &9 219715 start &93 19452 19716 end &19 19453 19717 sat 32 … … 19475 19739 on &261 19476 19740 ) 19477 *6 67(Wire19741 *675 (Wire 19478 19742 uid 5404,0 19479 19743 shape (OrthoPolyLine … … 19491 19755 ) 19492 19756 start &280 19493 end &4 819757 end &47 19494 19758 sat 32 19495 19759 eat 32 … … 19512 19776 on &264 19513 19777 ) 19514 *6 68(Wire19778 *676 (Wire 19515 19779 uid 5474,0 19516 19780 shape (OrthoPolyLine … … 19528 19792 ) 19529 19793 start &283 19530 end & 5019794 end &49 19531 19795 sat 32 19532 19796 eat 32 … … 19549 19813 on &262 19550 19814 ) 19551 *6 69(Wire19815 *677 (Wire 19552 19816 uid 5480,0 19553 19817 shape (OrthoPolyLine … … 19565 19829 ) 19566 19830 start &282 19567 end &4 919831 end &48 19568 19832 sat 32 19569 19833 eat 32 … … 19586 19850 on &263 19587 19851 ) 19588 *67 0(Wire19852 *678 (Wire 19589 19853 uid 5582,0 19590 19854 shape (OrthoPolyLine … … 19621 19885 on &187 19622 19886 ) 19623 *67 1(Wire19887 *679 (Wire 19624 19888 uid 5602,0 19625 19889 optionalChildren [ 19626 &65 119890 &659 19627 19891 ] 19628 19892 shape (OrthoPolyLine … … 19632 19896 lineColor "0,32896,0" 19633 19897 ) 19634 xt "-2 5000,41000,36250,51000"19898 xt "-26000,41000,36250,51000" 19635 19899 pts [ 19636 19900 "-21750,51000" 19637 "-2 5000,51000"19638 "-2 5000,41000"19901 "-26000,51000" 19902 "-26000,41000" 19639 19903 "28000,41000" 19640 19904 "28000,47000" … … 19666 19930 on &188 19667 19931 ) 19668 *6 72(Wire19932 *680 (Wire 19669 19933 uid 5626,0 19670 19934 shape (OrthoPolyLine … … 19679 19943 ] 19680 19944 ) 19681 start &4 419945 start &43 19682 19946 end &269 19683 19947 sat 32 … … 19702 19966 on &266 19703 19967 ) 19704 *6 73(Wire19968 *681 (Wire 19705 19969 uid 5634,0 19706 19970 shape (OrthoPolyLine … … 19716 19980 ] 19717 19981 ) 19718 start &3 819982 start &37 19719 19983 end &270 19720 19984 sat 32 … … 19740 20004 on &265 19741 20005 ) 19742 *6 74(Wire20006 *682 (Wire 19743 20007 uid 5646,0 19744 20008 shape (OrthoPolyLine … … 19776 20040 on &185 19777 20041 ) 19778 *6 75(Wire20042 *683 (Wire 19779 20043 uid 5745,0 19780 20044 shape (OrthoPolyLine … … 19791 20055 ] 19792 20056 ) 19793 start &5 220057 start &51 19794 20058 end &281 19795 20059 sat 32 … … 19814 20078 on &276 19815 20079 ) 19816 *6 76(Wire20080 *684 (Wire 19817 20081 uid 5805,0 19818 20082 shape (OrthoPolyLine … … 19848 20112 on &187 19849 20113 ) 19850 *6 77(Wire20114 *685 (Wire 19851 20115 uid 5813,0 19852 20116 shape (OrthoPolyLine … … 19886 20150 on &293 19887 20151 ) 19888 *6 78(Wire20152 *686 (Wire 19889 20153 uid 5821,0 19890 20154 shape (OrthoPolyLine … … 19924 20188 on &294 19925 20189 ) 19926 *6 79(Wire20190 *687 (Wire 19927 20191 uid 5829,0 19928 20192 shape (OrthoPolyLine … … 19962 20226 on &295 19963 20227 ) 19964 *68 0(Wire20228 *688 (Wire 19965 20229 uid 5837,0 19966 20230 shape (OrthoPolyLine … … 20002 20266 on &296 20003 20267 ) 20004 *68 1(Wire20268 *689 (Wire 20005 20269 uid 5950,0 20006 20270 shape (OrthoPolyLine … … 20017 20281 ] 20018 20282 ) 20019 start & 9920020 end &5 420283 start &100 20284 end &53 20021 20285 sat 32 20022 20286 eat 32 … … 20040 20304 on &301 20041 20305 ) 20042 *6 82(Wire20306 *690 (Wire 20043 20307 uid 5962,0 20044 20308 shape (OrthoPolyLine … … 20055 20319 ] 20056 20320 ) 20057 start &9 720058 end &5 320321 start &98 20322 end &52 20059 20323 sat 32 20060 20324 eat 32 … … 20078 20342 on &302 20079 20343 ) 20080 *6 83(Wire20344 *691 (Wire 20081 20345 uid 6002,0 20082 20346 shape (OrthoPolyLine … … 20094 20358 ) 20095 20359 start &246 20096 end &5 520360 end &54 20097 20361 sat 32 20098 20362 eat 32 … … 20116 20380 on &304 20117 20381 ) 20118 *6 84(Wire20382 *692 (Wire 20119 20383 uid 6008,0 20120 20384 shape (OrthoPolyLine … … 20132 20396 ) 20133 20397 start &287 20134 end &5 720398 end &56 20135 20399 sat 32 20136 20400 eat 32 … … 20154 20418 on &303 20155 20419 ) 20156 *6 85(Wire20420 *693 (Wire 20157 20421 uid 6018,0 20158 20422 shape (OrthoPolyLine … … 20167 20431 ] 20168 20432 ) 20169 start &5 620433 start &55 20170 20434 end &149 20171 20435 sat 32 … … 20190 20454 on &305 20191 20455 ) 20192 *6 86(Wire20456 *694 (Wire 20193 20457 uid 6064,0 20194 20458 shape (OrthoPolyLine … … 20203 20467 ] 20204 20468 ) 20205 end &5 820469 end &57 20206 20470 sat 16 20207 20471 eat 32 … … 20225 20489 on &258 20226 20490 ) 20227 *6 87(Wire20491 *695 (Wire 20228 20492 uid 6072,0 20229 20493 shape (OrthoPolyLine … … 20233 20497 lineColor "0,32896,0" 20234 20498 ) 20235 xt "-41250,23000,-2 5000,41000"20499 xt "-41250,23000,-26000,41000" 20236 20500 pts [ 20237 20501 "-41250,23000" 20238 "-2 5000,23000"20239 "-2 5000,41000"20502 "-26000,23000" 20503 "-26000,41000" 20240 20504 ] 20241 20505 ) 20242 20506 start &366 20243 end &65 020507 end &658 20244 20508 sat 32 20245 20509 eat 32 … … 20264 20528 on &188 20265 20529 ) 20266 *6 88(Wire20530 *696 (Wire 20267 20531 uid 6160,0 20268 20532 shape (OrthoPolyLine … … 20302 20566 on &306 20303 20567 ) 20304 *6 89(Wire20568 *697 (Wire 20305 20569 uid 6276,0 20306 20570 shape (OrthoPolyLine … … 20315 20579 ] 20316 20580 ) 20317 end &12 620581 end &127 20318 20582 sat 16 20319 20583 eat 32 … … 20336 20600 on &185 20337 20601 ) 20338 *69 0(Wire20602 *698 (Wire 20339 20603 uid 6362,0 20340 20604 shape (OrthoPolyLine … … 20375 20639 on &308 20376 20640 ) 20377 *69 1(Wire20641 *699 (Wire 20378 20642 uid 6452,0 20379 20643 shape (OrthoPolyLine … … 20388 20652 ] 20389 20653 ) 20390 start &10 220654 start &103 20391 20655 sat 32 20392 20656 eat 16 … … 20411 20675 on &310 20412 20676 ) 20413 * 692(Wire20677 *700 (Wire 20414 20678 uid 6540,0 20415 20679 shape (OrthoPolyLine … … 20448 20712 on &329 20449 20713 ) 20450 * 693(Wire20714 *701 (Wire 20451 20715 uid 6548,0 20452 20716 shape (OrthoPolyLine … … 20485 20749 on &310 20486 20750 ) 20487 * 694(Wire20751 *702 (Wire 20488 20752 uid 8416,0 20489 20753 shape (OrthoPolyLine … … 20499 20763 ) 20500 20764 start &150 20501 end &10 320765 end &104 20502 20766 sat 32 20503 20767 eat 32 … … 20521 20785 on &341 20522 20786 ) 20523 * 695(Wire20787 *703 (Wire 20524 20788 uid 8732,0 20525 20789 shape (OrthoPolyLine … … 20559 20823 on &360 20560 20824 ) 20561 * 696(Wire20825 *704 (Wire 20562 20826 uid 8738,0 20563 20827 shape (OrthoPolyLine … … 20595 20859 on &361 20596 20860 ) 20597 * 697(Wire20861 *705 (Wire 20598 20862 uid 8752,0 20599 20863 shape (OrthoPolyLine … … 20608 20872 ] 20609 20873 ) 20610 start &10 420874 start &105 20611 20875 sat 32 20612 20876 eat 16 … … 20630 20894 on &361 20631 20895 ) 20632 * 698(Wire20896 *706 (Wire 20633 20897 uid 9006,0 20634 20898 shape (OrthoPolyLine … … 20643 20907 ] 20644 20908 ) 20645 start &5 920909 start &58 20646 20910 end &363 20647 20911 sat 32 … … 20668 20932 on &362 20669 20933 ) 20670 * 699(Wire20934 *707 (Wire 20671 20935 uid 9233,0 20672 20936 shape (OrthoPolyLine … … 20681 20945 ] 20682 20946 ) 20683 start &10 520947 start &106 20684 20948 sat 32 20685 20949 eat 16 … … 20703 20967 on &376 20704 20968 ) 20705 *70 0(Wire20969 *708 (Wire 20706 20970 uid 9241,0 20707 20971 shape (OrthoPolyLine … … 20716 20980 ] 20717 20981 ) 20718 start &10 620982 start &107 20719 20983 sat 32 20720 20984 eat 16 … … 20738 21002 on &377 20739 21003 ) 20740 *70 1(Wire21004 *709 (Wire 20741 21005 uid 9253,0 20742 21006 shape (OrthoPolyLine … … 20772 21036 on &376 20773 21037 ) 20774 *7 02(Wire21038 *710 (Wire 20775 21039 uid 9261,0 20776 21040 shape (OrthoPolyLine … … 20806 21070 on &377 20807 21071 ) 20808 *7 03(Wire21072 *711 (Wire 20809 21073 uid 9943,0 20810 21074 shape (OrthoPolyLine … … 20819 21083 ] 20820 21084 ) 20821 start &10 721085 start &108 20822 21086 sat 32 20823 21087 eat 16 … … 20841 21105 on &378 20842 21106 ) 20843 *7 04(Wire21107 *712 (Wire 20844 21108 uid 9951,0 20845 21109 shape (OrthoPolyLine … … 20854 21118 ] 20855 21119 ) 20856 start &10 821120 start &109 20857 21121 sat 32 20858 21122 eat 16 … … 20876 21140 on &379 20877 21141 ) 20878 *7 05(Wire21142 *713 (Wire 20879 21143 uid 10010,0 20880 21144 shape (OrthoPolyLine … … 20914 21178 on &398 20915 21179 ) 20916 *7 06(Wire21180 *714 (Wire 20917 21181 uid 10018,0 20918 21182 shape (OrthoPolyLine … … 20950 21214 on &379 20951 21215 ) 20952 *7 07(Wire21216 *715 (Wire 20953 21217 uid 10036,0 20954 21218 shape (OrthoPolyLine … … 20984 21248 on &378 20985 21249 ) 20986 *7 08(Wire21250 *716 (Wire 20987 21251 uid 10194,0 20988 21252 shape (OrthoPolyLine … … 21000 21264 ) 21001 21265 start &247 21002 end &1 0921266 end &110 21003 21267 ss 0 21004 21268 es 0 … … 21024 21288 on &399 21025 21289 ) 21026 *7 09(Wire21290 *717 (Wire 21027 21291 uid 10202,0 21028 21292 shape (OrthoPolyLine … … 21040 21304 ) 21041 21305 start &248 21042 end &11 021306 end &111 21043 21307 sat 32 21044 21308 eat 32 … … 21062 21326 on &400 21063 21327 ) 21064 *71 0(Wire21328 *718 (Wire 21065 21329 uid 10266,0 21066 21330 shape (OrthoPolyLine … … 21075 21339 ] 21076 21340 ) 21077 start &9 321341 start &94 21078 21342 sat 32 21079 21343 eat 16 … … 21097 21361 on &498 21098 21362 ) 21099 *71 1(Wire21363 *719 (Wire 21100 21364 uid 10298,0 21101 21365 shape (OrthoPolyLine … … 21111 21375 ) 21112 21376 start &226 21113 end &6 121377 end &60 21114 21378 sat 32 21115 21379 eat 32 … … 21133 21397 on &402 21134 21398 ) 21135 *7 12(Wire21399 *720 (Wire 21136 21400 uid 10304,0 21137 21401 shape (OrthoPolyLine … … 21147 21411 ) 21148 21412 start &224 21149 end &6 221413 end &61 21150 21414 sat 32 21151 21415 eat 32 … … 21169 21433 on &403 21170 21434 ) 21171 *7 13(Wire21435 *721 (Wire 21172 21436 uid 10310,0 21173 21437 shape (OrthoPolyLine … … 21183 21447 ) 21184 21448 start &225 21185 end &6 321449 end &62 21186 21450 sat 32 21187 21451 eat 32 … … 21205 21469 on &404 21206 21470 ) 21207 *7 14(Wire21471 *722 (Wire 21208 21472 uid 10316,0 21209 21473 shape (OrthoPolyLine … … 21219 21483 ] 21220 21484 ) 21221 start & 6021485 start &59 21222 21486 end &222 21223 21487 sat 32 … … 21243 21507 on &405 21244 21508 ) 21245 *7 15(Wire21509 *723 (Wire 21246 21510 uid 10322,0 21247 21511 shape (OrthoPolyLine … … 21281 21545 on &406 21282 21546 ) 21283 *7 16(Wire21547 *724 (Wire 21284 21548 uid 10431,0 21285 21549 shape (OrthoPolyLine … … 21318 21582 on &401 21319 21583 ) 21320 *7 17(Wire21584 *725 (Wire 21321 21585 uid 10467,0 21322 21586 shape (OrthoPolyLine … … 21332 21596 ) 21333 21597 start &151 21334 end &6 421598 end &63 21335 21599 es 0 21336 21600 sat 32 … … 21355 21619 on &431 21356 21620 ) 21357 *7 18(Wire21621 *726 (Wire 21358 21622 uid 10629,0 21359 21623 shape (OrthoPolyLine … … 21368 21632 ] 21369 21633 ) 21370 start &11 121634 start &112 21371 21635 sat 32 21372 21636 eat 16 … … 21390 21654 on &432 21391 21655 ) 21392 *7 19(Wire21656 *727 (Wire 21393 21657 uid 10637,0 21394 21658 shape (OrthoPolyLine … … 21403 21667 ] 21404 21668 ) 21405 start &11 221669 start &113 21406 21670 sat 32 21407 21671 eat 16 … … 21425 21689 on &433 21426 21690 ) 21427 *72 0(Wire21691 *728 (Wire 21428 21692 uid 10685,0 21429 21693 shape (OrthoPolyLine … … 21460 21724 on &433 21461 21725 ) 21462 *72 1(Wire21726 *729 (Wire 21463 21727 uid 10691,0 21464 21728 shape (OrthoPolyLine … … 21495 21759 on &432 21496 21760 ) 21497 *7 22(Wire21761 *730 (Wire 21498 21762 uid 10699,0 21499 21763 shape (OrthoPolyLine … … 21531 21795 on &187 21532 21796 ) 21533 *7 23(Wire21797 *731 (Wire 21534 21798 uid 10707,0 21535 21799 shape (OrthoPolyLine … … 21566 21830 on &452 21567 21831 ) 21568 *7 24(Wire21832 *732 (Wire 21569 21833 uid 10723,0 21570 21834 shape (OrthoPolyLine … … 21604 21868 on &434 21605 21869 ) 21606 *7 25(Wire21870 *733 (Wire 21607 21871 uid 10737,0 21608 21872 shape (OrthoPolyLine … … 21642 21906 on &436 21643 21907 ) 21644 *7 26(Wire21908 *734 (Wire 21645 21909 uid 10751,0 21646 21910 shape (OrthoPolyLine … … 21680 21944 on &438 21681 21945 ) 21682 *7 27(Wire21946 *735 (Wire 21683 21947 uid 11405,0 21684 21948 shape (OrthoPolyLine … … 21694 21958 ] 21695 21959 ) 21696 start &6 521960 start &64 21697 21961 sat 32 21698 21962 eat 16 … … 21716 21980 on &452 21717 21981 ) 21718 *7 28(Wire21982 *736 (Wire 21719 21983 uid 11858,0 21720 21984 shape (OrthoPolyLine … … 21729 21993 ] 21730 21994 ) 21731 start &11 321995 start &114 21732 21996 sat 32 21733 21997 eat 16 … … 21751 22015 on &453 21752 22016 ) 21753 *7 29(Wire22017 *737 (Wire 21754 22018 uid 11952,0 21755 22019 shape (OrthoPolyLine … … 21787 22051 on &453 21788 22052 ) 21789 *73 0(Wire22053 *738 (Wire 21790 22054 uid 12306,0 21791 22055 shape (OrthoPolyLine … … 21825 22089 on &472 21826 22090 ) 21827 *73 1(Wire22091 *739 (Wire 21828 22092 uid 12643,0 21829 22093 shape (OrthoPolyLine … … 21865 22129 on &483 21866 22130 ) 21867 *7 32(Wire22131 *740 (Wire 21868 22132 uid 12649,0 21869 22133 shape (OrthoPolyLine … … 21878 22142 ] 21879 22143 ) 21880 start &6 622144 start &65 21881 22145 end &477 21882 22146 sat 32 … … 21901 22165 on &484 21902 22166 ) 21903 *7 33(Wire22167 *741 (Wire 21904 22168 uid 12655,0 21905 22169 shape (OrthoPolyLine … … 21915 22179 ] 21916 22180 ) 21917 start &6 722181 start &66 21918 22182 end &478 21919 22183 sat 32 … … 21938 22202 on &485 21939 22203 ) 21940 *7 34(Wire22204 *742 (Wire 21941 22205 uid 12687,0 21942 22206 shape (OrthoPolyLine … … 21976 22240 on &188 21977 22241 ) 21978 *7 35(Wire22242 *743 (Wire 21979 22243 uid 12707,0 21980 22244 shape (OrthoPolyLine … … 22014 22278 on &486 22015 22279 ) 22016 *7 36(Wire22280 *744 (Wire 22017 22281 uid 13143,0 22018 22282 shape (OrthoPolyLine … … 22049 22313 on &188 22050 22314 ) 22051 *7 37(Wire22315 *745 (Wire 22052 22316 uid 13159,0 22053 22317 shape (OrthoPolyLine … … 22064 22328 ] 22065 22329 ) 22066 start &11 422330 start &115 22067 22331 end &490 22068 22332 sat 32 … … 22087 22351 on &496 22088 22352 ) 22089 *7 38(Wire22353 *746 (Wire 22090 22354 uid 13165,0 22091 22355 shape (OrthoPolyLine … … 22103 22367 ] 22104 22368 ) 22105 start &11 522369 start &116 22106 22370 end &491 22107 22371 sat 32 … … 22127 22391 on &497 22128 22392 ) 22129 *7 39(Wire22393 *747 (Wire 22130 22394 uid 13210,0 22131 22395 shape (OrthoPolyLine … … 22163 22427 on &499 22164 22428 ) 22165 *74 0(Wire22429 *748 (Wire 22166 22430 uid 13216,0 22167 22431 shape (OrthoPolyLine … … 22199 22463 on &498 22200 22464 ) 22201 *74 1(Wire22465 *749 (Wire 22202 22466 uid 13224,0 22203 22467 shape (OrthoPolyLine … … 22235 22499 on &401 22236 22500 ) 22237 *7 42(Wire22501 *750 (Wire 22238 22502 uid 13695,0 22239 22503 shape (OrthoPolyLine … … 22250 22514 ) 22251 22515 start &523 22252 end &11 622516 end &117 22253 22517 sat 32 22254 22518 eat 32 … … 22274 22538 on &524 22275 22539 ) 22276 *7 43(Wire22540 *751 (Wire 22277 22541 uid 13921,0 22278 22542 shape (OrthoPolyLine … … 22288 22552 ] 22289 22553 ) 22290 end &11 722554 end &118 22291 22555 sat 16 22292 22556 eat 32 … … 22309 22573 ) 22310 22574 ) 22311 on &7 122312 ) 22313 *7 44(Wire22575 on &72 22576 ) 22577 *752 (Wire 22314 22578 uid 13929,0 22315 22579 shape (OrthoPolyLine … … 22325 22589 ] 22326 22590 ) 22327 end &11 822591 end &119 22328 22592 sat 16 22329 22593 eat 32 … … 22346 22610 ) 22347 22611 ) 22348 on &12 222349 ) 22350 *7 45(Wire22612 on &123 22613 ) 22614 *753 (Wire 22351 22615 uid 14048,0 22352 22616 shape (OrthoPolyLine … … 22385 22649 on &526 22386 22650 ) 22387 *7 46(Wire22651 *754 (Wire 22388 22652 uid 14171,0 22389 22653 shape (OrthoPolyLine … … 22423 22687 on &528 22424 22688 ) 22425 *7 47(Wire22689 *755 (Wire 22426 22690 uid 14427,0 22427 22691 shape (OrthoPolyLine … … 22458 22722 on &187 22459 22723 ) 22460 *7 48(Wire22724 *756 (Wire 22461 22725 uid 14479,0 22462 22726 shape (OrthoPolyLine … … 22496 22760 on &538 22497 22761 ) 22498 *7 49(Wire22762 *757 (Wire 22499 22763 uid 14493,0 22500 22764 shape (OrthoPolyLine … … 22534 22798 on &540 22535 22799 ) 22536 *75 0(Wire22800 *758 (Wire 22537 22801 uid 14622,0 22538 22802 shape (OrthoPolyLine … … 22574 22838 on &542 22575 22839 ) 22576 *75 1(Wire22840 *759 (Wire 22577 22841 uid 15071,0 22578 22842 shape (OrthoPolyLine … … 22587 22851 ] 22588 22852 ) 22589 start &10 122853 start &102 22590 22854 end &548 22591 22855 sat 32 … … 22610 22874 on &595 22611 22875 ) 22612 *7 52(Wire22876 *760 (Wire 22613 22877 uid 15081,0 22614 22878 shape (OrthoPolyLine … … 22648 22912 on &596 22649 22913 ) 22650 *7 53(Wire22914 *761 (Wire 22651 22915 uid 15122,0 22652 22916 shape (OrthoPolyLine … … 22686 22950 on &597 22687 22951 ) 22688 *7 54(Wire22952 *762 (Wire 22689 22953 uid 15130,0 22690 22954 shape (OrthoPolyLine … … 22724 22988 on &540 22725 22989 ) 22726 *7 55(Wire22990 *763 (Wire 22727 22991 uid 15138,0 22728 22992 shape (OrthoPolyLine … … 22762 23026 on &538 22763 23027 ) 22764 *7 56(Wire23028 *764 (Wire 22765 23029 uid 15379,0 22766 23030 shape (OrthoPolyLine … … 22797 23061 on &188 22798 23062 ) 22799 *7 57(Wire23063 *765 (Wire 22800 23064 uid 15494,0 22801 23065 optionalChildren [ 22802 *7 58(BdJunction23066 *766 (BdJunction 22803 23067 uid 15502,0 22804 23068 ps "OnConnectorStrategy" … … 22825 23089 ) 22826 23090 start &475 22827 end & 3023091 end &29 22828 23092 sat 32 22829 23093 eat 32 … … 22847 23111 on &598 22848 23112 ) 22849 *7 59(Wire23113 *767 (Wire 22850 23114 uid 15498,0 22851 23115 shape (OrthoPolyLine … … 22861 23125 ] 22862 23126 ) 22863 start &12 522864 end &7 5823127 start &126 23128 end &766 22865 23129 sat 32 22866 23130 eat 32 … … 22885 23149 on &598 22886 23150 ) 23151 *768 (Wire 23152 uid 15750,0 23153 shape (OrthoPolyLine 23154 uid 15751,0 23155 va (VaSet 23156 vasetType 3 23157 lineWidth 2 23158 ) 23159 xt "-40250,69000,-21750,70000" 23160 pts [ 23161 "-40250,69000" 23162 "-28000,69000" 23163 "-28000,70000" 23164 "-21750,70000" 23165 ] 23166 ) 23167 start &125 23168 end &67 23169 sat 32 23170 eat 32 23171 sty 1 23172 st 0 23173 sf 1 23174 tg (WTG 23175 uid 15752,0 23176 ps "ConnStartEndStrategy" 23177 stg "STSignalDisplayStrategy" 23178 f (Text 23179 uid 15753,0 23180 va (VaSet 23181 ) 23182 xt "-38250,68000,-31450,69000" 23183 st "trigger_id : (31:0)" 23184 blo "-38250,68800" 23185 tm "WireNameMgr" 23186 ) 23187 ) 23188 on &607 23189 ) 22887 23190 ] 22888 23191 bg "65535,65535,65535" … … 22897 23200 color "26368,26368,26368" 22898 23201 ) 22899 packageList *76 0(PackageList23202 packageList *769 (PackageList 22900 23203 uid 41,0 22901 23204 stg "VerticalLayoutStrategy" 22902 23205 textVec [ 22903 *7 61(Text23206 *770 (Text 22904 23207 uid 42,0 22905 23208 va (VaSet … … 22910 23213 blo "-163000,-15200" 22911 23214 ) 22912 *7 62(MLText23215 *771 (MLText 22913 23216 uid 43,0 22914 23217 va (VaSet 22915 23218 ) 22916 xt "-163000,-15000,-148600,- 3000"23219 xt "-163000,-15000,-148600,-2000" 22917 23220 st "library ieee; 22918 23221 use ieee.std_logic_1164.all; … … 22926 23229 --use UNISIM.VComponents.all; 22927 23230 USE IEEE.NUMERIC_STD.all; 22928 USE IEEE.std_logic_signed.all;" 23231 USE IEEE.std_logic_signed.all; 23232 USE UNISIM.VComponents.all;" 22929 23233 tm "PackageList" 22930 23234 ) … … 22935 23239 stg "VerticalLayoutStrategy" 22936 23240 textVec [ 22937 *7 63(Text23241 *772 (Text 22938 23242 uid 45,0 22939 23243 va (VaSet … … 22945 23249 blo "20000,800" 22946 23250 ) 22947 *7 64(Text23251 *773 (Text 22948 23252 uid 46,0 22949 23253 va (VaSet … … 22955 23259 blo "20000,1800" 22956 23260 ) 22957 *7 65(MLText23261 *774 (MLText 22958 23262 uid 47,0 22959 23263 va (VaSet … … 22965 23269 tm "BdCompilerDirectivesTextMgr" 22966 23270 ) 22967 *7 66(Text23271 *775 (Text 22968 23272 uid 48,0 22969 23273 va (VaSet … … 22975 23279 blo "20000,4800" 22976 23280 ) 22977 *7 67(MLText23281 *776 (MLText 22978 23282 uid 49,0 22979 23283 va (VaSet … … 22983 23287 tm "BdCompilerDirectivesTextMgr" 22984 23288 ) 22985 *7 68(Text23289 *777 (Text 22986 23290 uid 50,0 22987 23291 va (VaSet … … 22993 23297 blo "20000,5800" 22994 23298 ) 22995 *7 69(MLText23299 *778 (MLText 22996 23300 uid 51,0 22997 23301 va (VaSet … … 23005 23309 ) 23006 23310 windowSize "0,0,1281,1024" 23007 viewArea "- 65700,47500,1143,102625"23311 viewArea "-70475,46416,-3930,101296" 23008 23312 cachedDiagramExtent "-174000,-25425,428157,346294" 23009 23313 pageSetupInfo (PageSetupInfo … … 23031 23335 hasePageBreakOrigin 1 23032 23336 pageBreakOrigin "-73000,0" 23033 lastUid 15 505,023337 lastUid 15755,0 23034 23338 defaultCommentText (CommentText 23035 23339 shape (Rectangle … … 23093 23397 stg "VerticalLayoutStrategy" 23094 23398 textVec [ 23095 *77 0(Text23399 *779 (Text 23096 23400 va (VaSet 23097 23401 font "Arial,8,1" … … 23102 23406 tm "BdLibraryNameMgr" 23103 23407 ) 23104 *7 71(Text23408 *780 (Text 23105 23409 va (VaSet 23106 23410 font "Arial,8,1" … … 23111 23415 tm "BlkNameMgr" 23112 23416 ) 23113 *7 72(Text23417 *781 (Text 23114 23418 va (VaSet 23115 23419 font "Arial,8,1" … … 23157 23461 ) 23158 23462 xt "0,0,8000,10000" 23159 )23160 ttg (MlTextGroup23161 ps "CenterOffsetStrategy"23162 stg "VerticalLayoutStrategy"23163 textVec [23164 *773 (Text23165 va (VaSet23166 font "Arial,8,1"23167 )23168 xt "550,3500,3450,4500"23169 st "Library"23170 blo "550,4300"23171 )23172 *774 (Text23173 va (VaSet23174 font "Arial,8,1"23175 )23176 xt "550,4500,7450,5500"23177 st "MWComponent"23178 blo "550,5300"23179 )23180 *775 (Text23181 va (VaSet23182 font "Arial,8,1"23183 )23184 xt "550,5500,2350,6500"23185 st "U_0"23186 blo "550,6300"23187 tm "InstanceNameMgr"23188 )23189 ]23190 )23191 ga (GenericAssociation23192 ps "EdgeToEdgeStrategy"23193 matrix (Matrix23194 text (MLText23195 va (VaSet23196 font "Courier New,8,0"23197 )23198 xt "-6450,1500,-6450,1500"23199 )23200 header ""23201 )23202 elements [23203 ]23204 )23205 portVis (PortSigDisplay23206 )23207 prms (Property23208 pclass "params"23209 pname "params"23210 ptn "String"23211 )23212 visOptions (mwParamsVisibilityOptions23213 )23214 )23215 defaultSaComponent (SaComponent23216 shape (Rectangle23217 va (VaSet23218 vasetType 123219 fg "0,65535,0"23220 lineColor "0,32896,0"23221 lineWidth 223222 )23223 xt "0,0,8000,10000"23224 )23225 ttg (MlTextGroup23226 ps "CenterOffsetStrategy"23227 stg "VerticalLayoutStrategy"23228 textVec [23229 *776 (Text23230 va (VaSet23231 font "Arial,8,1"23232 )23233 xt "900,3500,3800,4500"23234 st "Library"23235 blo "900,4300"23236 tm "BdLibraryNameMgr"23237 )23238 *777 (Text23239 va (VaSet23240 font "Arial,8,1"23241 )23242 xt "900,4500,7100,5500"23243 st "SaComponent"23244 blo "900,5300"23245 tm "CptNameMgr"23246 )23247 *778 (Text23248 va (VaSet23249 font "Arial,8,1"23250 )23251 xt "900,5500,2700,6500"23252 st "U_0"23253 blo "900,6300"23254 tm "InstanceNameMgr"23255 )23256 ]23257 )23258 ga (GenericAssociation23259 ps "EdgeToEdgeStrategy"23260 matrix (Matrix23261 text (MLText23262 va (VaSet23263 font "Courier New,8,0"23264 )23265 xt "-6100,1500,-6100,1500"23266 )23267 header ""23268 )23269 elements [23270 ]23271 )23272 viewicon (ZoomableIcon23273 sl 023274 va (VaSet23275 vasetType 123276 fg "49152,49152,49152"23277 )23278 xt "0,0,1500,1500"23279 iconName "UnknownFile.png"23280 iconMaskName "UnknownFile.msk"23281 )23282 viewiconposition 023283 portVis (PortSigDisplay23284 )23285 archFileType "UNKNOWN"23286 )23287 defaultVhdlComponent (VhdlComponent23288 shape (Rectangle23289 va (VaSet23290 vasetType 123291 fg "0,65535,0"23292 lineColor "0,32896,0"23293 lineWidth 223294 )23295 xt "0,0,8000,10000"23296 )23297 ttg (MlTextGroup23298 ps "CenterOffsetStrategy"23299 stg "VerticalLayoutStrategy"23300 textVec [23301 *779 (Text23302 va (VaSet23303 font "Arial,8,1"23304 )23305 xt "500,3500,3400,4500"23306 st "Library"23307 blo "500,4300"23308 )23309 *780 (Text23310 va (VaSet23311 font "Arial,8,1"23312 )23313 xt "500,4500,7500,5500"23314 st "VhdlComponent"23315 blo "500,5300"23316 )23317 *781 (Text23318 va (VaSet23319 font "Arial,8,1"23320 )23321 xt "500,5500,2300,6500"23322 st "U_0"23323 blo "500,6300"23324 tm "InstanceNameMgr"23325 )23326 ]23327 )23328 ga (GenericAssociation23329 ps "EdgeToEdgeStrategy"23330 matrix (Matrix23331 text (MLText23332 va (VaSet23333 font "Courier New,8,0"23334 )23335 xt "-6500,1500,-6500,1500"23336 )23337 header ""23338 )23339 elements [23340 ]23341 )23342 portVis (PortSigDisplay23343 )23344 entityPath ""23345 archName ""23346 archPath ""23347 )23348 defaultVerilogComponent (VerilogComponent23349 shape (Rectangle23350 va (VaSet23351 vasetType 123352 fg "0,65535,0"23353 lineColor "0,32896,0"23354 lineWidth 223355 )23356 xt "-450,0,8450,10000"23357 23463 ) 23358 23464 ttg (MlTextGroup … … 23364 23470 font "Arial,8,1" 23365 23471 ) 23366 xt "5 0,3500,2950,4500"23472 xt "550,3500,3450,4500" 23367 23473 st "Library" 23368 blo "5 0,4300"23474 blo "550,4300" 23369 23475 ) 23370 23476 *783 (Text … … 23372 23478 font "Arial,8,1" 23373 23479 ) 23374 xt "5 0,4500,7950,5500"23375 st " VerilogComponent"23376 blo "5 0,5300"23480 xt "550,4500,7450,5500" 23481 st "MWComponent" 23482 blo "550,5300" 23377 23483 ) 23378 23484 *784 (Text … … 23380 23486 font "Arial,8,1" 23381 23487 ) 23382 xt "5 0,5500,1850,6500"23488 xt "550,5500,2350,6500" 23383 23489 st "U_0" 23384 blo "5 0,6300"23490 blo "550,6300" 23385 23491 tm "InstanceNameMgr" 23386 23492 ) … … 23394 23500 font "Courier New,8,0" 23395 23501 ) 23396 xt "-6 950,1500,-6950,1500"23502 xt "-6450,1500,-6450,1500" 23397 23503 ) 23398 23504 header "" … … 23401 23507 ] 23402 23508 ) 23403 entityPath "" 23404 ) 23405 defaultHdlText (HdlText 23509 portVis (PortSigDisplay 23510 ) 23511 prms (Property 23512 pclass "params" 23513 pname "params" 23514 ptn "String" 23515 ) 23516 visOptions (mwParamsVisibilityOptions 23517 ) 23518 ) 23519 defaultSaComponent (SaComponent 23406 23520 shape (Rectangle 23407 23521 va (VaSet 23408 23522 vasetType 1 23409 fg " 65535,65535,37120"23410 lineColor "0, 0,32768"23523 fg "0,65535,0" 23524 lineColor "0,32896,0" 23411 23525 lineWidth 2 23412 23526 ) … … 23421 23535 font "Arial,8,1" 23422 23536 ) 23537 xt "900,3500,3800,4500" 23538 st "Library" 23539 blo "900,4300" 23540 tm "BdLibraryNameMgr" 23541 ) 23542 *786 (Text 23543 va (VaSet 23544 font "Arial,8,1" 23545 ) 23546 xt "900,4500,7100,5500" 23547 st "SaComponent" 23548 blo "900,5300" 23549 tm "CptNameMgr" 23550 ) 23551 *787 (Text 23552 va (VaSet 23553 font "Arial,8,1" 23554 ) 23555 xt "900,5500,2700,6500" 23556 st "U_0" 23557 blo "900,6300" 23558 tm "InstanceNameMgr" 23559 ) 23560 ] 23561 ) 23562 ga (GenericAssociation 23563 ps "EdgeToEdgeStrategy" 23564 matrix (Matrix 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23616 ) 23617 xt "500,4500,7500,5500" 23618 st "VhdlComponent" 23619 blo "500,5300" 23620 ) 23621 *790 (Text 23622 va (VaSet 23623 font "Arial,8,1" 23624 ) 23625 xt "500,5500,2300,6500" 23626 st "U_0" 23627 blo "500,6300" 23628 tm "InstanceNameMgr" 23629 ) 23630 ] 23631 ) 23632 ga (GenericAssociation 23633 ps "EdgeToEdgeStrategy" 23634 matrix (Matrix 23635 text (MLText 23636 va (VaSet 23637 font "Courier New,8,0" 23638 ) 23639 xt "-6500,1500,-6500,1500" 23640 ) 23641 header "" 23642 ) 23643 elements [ 23644 ] 23645 ) 23646 portVis (PortSigDisplay 23647 ) 23648 entityPath "" 23649 archName "" 23650 archPath "" 23651 ) 23652 defaultVerilogComponent (VerilogComponent 23653 shape (Rectangle 23654 va (VaSet 23655 vasetType 1 23656 fg "0,65535,0" 23657 lineColor "0,32896,0" 23658 lineWidth 2 23659 ) 23660 xt "-450,0,8450,10000" 23661 ) 23662 ttg (MlTextGroup 23663 ps "CenterOffsetStrategy" 23664 stg "VerticalLayoutStrategy" 23665 textVec [ 23666 *791 (Text 23667 va (VaSet 23668 font "Arial,8,1" 23669 ) 23670 xt "50,3500,2950,4500" 23671 st "Library" 23672 blo "50,4300" 23673 ) 23674 *792 (Text 23675 va (VaSet 23676 font "Arial,8,1" 23677 ) 23678 xt "50,4500,7950,5500" 23679 st "VerilogComponent" 23680 blo "50,5300" 23681 ) 23682 *793 (Text 23683 va (VaSet 23684 font "Arial,8,1" 23685 ) 23686 xt "50,5500,1850,6500" 23687 st "U_0" 23688 blo "50,6300" 23689 tm "InstanceNameMgr" 23690 ) 23691 ] 23692 ) 23693 ga (GenericAssociation 23694 ps "EdgeToEdgeStrategy" 23695 matrix (Matrix 23696 text (MLText 23697 va (VaSet 23698 font "Courier New,8,0" 23699 ) 23700 xt "-6950,1500,-6950,1500" 23701 ) 23702 header "" 23703 ) 23704 elements [ 23705 ] 23706 ) 23707 entityPath "" 23708 ) 23709 defaultHdlText (HdlText 23710 shape (Rectangle 23711 va (VaSet 23712 vasetType 1 23713 fg "65535,65535,37120" 23714 lineColor "0,0,32768" 23715 lineWidth 2 23716 ) 23717 xt "0,0,8000,10000" 23718 ) 23719 ttg (MlTextGroup 23720 ps "CenterOffsetStrategy" 23721 stg "VerticalLayoutStrategy" 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26459 *10 53(MRCItem26460 litem &9 2526761 uid 15149,0 26762 ) 26763 *1062 (MRCItem 26764 litem &934 26461 26765 pos 121 26462 26766 dimension 20 26463 uid 15 149,026464 ) 26465 *10 54(MRCItem26466 litem &9 2626767 uid 15505,0 26768 ) 26769 *1063 (MRCItem 26770 litem &935 26467 26771 pos 122 26468 26772 dimension 20 26469 uid 15 505,026773 uid 15755,0 26470 26774 ) 26471 26775 ] … … 26480 26784 uid 73,0 26481 26785 optionalChildren [ 26482 *10 55(MRCItem26483 litem & 79526786 *1064 (MRCItem 26787 litem &804 26484 26788 pos 0 26485 26789 dimension 20 26486 26790 uid 74,0 26487 26791 ) 26488 *10 56(MRCItem26489 litem & 79726792 *1065 (MRCItem 26793 litem &806 26490 26794 pos 1 26491 26795 dimension 50 26492 26796 uid 75,0 26493 26797 ) 26494 *10 57(MRCItem26495 litem & 79826798 *1066 (MRCItem 26799 litem &807 26496 26800 pos 2 26497 26801 dimension 100 26498 26802 uid 76,0 26499 26803 ) 26500 *10 58(MRCItem26501 litem & 79926804 *1067 (MRCItem 26805 litem &808 26502 26806 pos 3 26503 26807 dimension 50 26504 26808 uid 77,0 26505 26809 ) 26506 *10 59(MRCItem26507 litem &80 026810 *1068 (MRCItem 26811 litem &809 26508 26812 pos 4 26509 26813 dimension 100 26510 26814 uid 78,0 26511 26815 ) 26512 *106 0(MRCItem26513 litem &8 0126816 *1069 (MRCItem 26817 litem &810 26514 26818 pos 5 26515 26819 dimension 100 26516 26820 uid 79,0 26517 26821 ) 26518 *10 61(MRCItem26519 litem &8 0226822 *1070 (MRCItem 26823 litem &811 26520 26824 pos 6 26521 26825 dimension 50 26522 26826 uid 80,0 26523 26827 ) 26524 *10 62(MRCItem26525 litem &8 0326828 *1071 (MRCItem 26829 litem &812 26526 26830 pos 7 26527 26831 dimension 290 … … 26543 26847 genericsCommonDM (CommonDM 26544 26848 ldm (LogicalDM 26545 emptyRow *10 63(LEmptyRow26849 emptyRow *1072 (LEmptyRow 26546 26850 ) 26547 26851 uid 83,0 26548 26852 optionalChildren [ 26549 *10 64(RefLabelRowHdr26550 ) 26551 *10 65(TitleRowHdr26552 ) 26553 *10 66(FilterRowHdr26554 ) 26555 *10 67(RefLabelColHdr26853 *1073 (RefLabelRowHdr 26854 ) 26855 *1074 (TitleRowHdr 26856 ) 26857 *1075 (FilterRowHdr 26858 ) 26859 *1076 (RefLabelColHdr 26556 26860 tm "RefLabelColHdrMgr" 26557 26861 ) 26558 *10 68(RowExpandColHdr26862 *1077 (RowExpandColHdr 26559 26863 tm "RowExpandColHdrMgr" 26560 26864 ) 26561 *10 69(GroupColHdr26865 *1078 (GroupColHdr 26562 26866 tm "GroupColHdrMgr" 26563 26867 ) 26564 *107 0(NameColHdr26868 *1079 (NameColHdr 26565 26869 tm "GenericNameColHdrMgr" 26566 26870 ) 26567 *10 71(TypeColHdr26871 *1080 (TypeColHdr 26568 26872 tm "GenericTypeColHdrMgr" 26569 26873 ) 26570 *10 72(InitColHdr26874 *1081 (InitColHdr 26571 26875 tm "GenericValueColHdrMgr" 26572 26876 ) 26573 *10 73(PragmaColHdr26877 *1082 (PragmaColHdr 26574 26878 tm "GenericPragmaColHdrMgr" 26575 26879 ) 26576 *10 74(EolColHdr26880 *1083 (EolColHdr 26577 26881 tm "GenericEolColHdrMgr" 26578 26882 ) 26579 *10 75(LogGeneric26883 *1084 (LogGeneric 26580 26884 generic (GiElement 26581 26885 name "RAMADDRWIDTH64b" … … 26592 26896 uid 95,0 26593 26897 optionalChildren [ 26594 *10 76(Sheet26898 *1085 (Sheet 26595 26899 sheetRow (SheetRow 26596 26900 headerVa (MVa … … 26609 26913 font "Tahoma,10,0" 26610 26914 ) 26611 emptyMRCItem *10 77(MRCItem26612 litem &10 6326915 emptyMRCItem *1086 (MRCItem 26916 litem &1072 26613 26917 pos 1 26614 26918 dimension 20 … … 26616 26920 uid 97,0 26617 26921 optionalChildren [ 26618 *10 78(MRCItem26619 litem &10 6426922 *1087 (MRCItem 26923 litem &1073 26620 26924 pos 0 26621 26925 dimension 20 26622 26926 uid 98,0 26623 26927 ) 26624 *10 79(MRCItem26625 litem &10 6526928 *1088 (MRCItem 26929 litem &1074 26626 26930 pos 1 26627 26931 dimension 23 26628 26932 uid 99,0 26629 26933 ) 26630 *108 0(MRCItem26631 litem &10 6626934 *1089 (MRCItem 26935 litem &1075 26632 26936 pos 2 26633 26937 hidden 1 … … 26635 26939 uid 100,0 26636 26940 ) 26637 *10 81(MRCItem26638 litem &10 7526941 *1090 (MRCItem 26942 litem &1084 26639 26943 pos 0 26640 26944 dimension 20 … … 26652 26956 uid 101,0 26653 26957 optionalChildren [ 26654 *10 82(MRCItem26655 litem &10 6726958 *1091 (MRCItem 26959 litem &1076 26656 26960 pos 0 26657 26961 dimension 20 26658 26962 uid 102,0 26659 26963 ) 26660 *10 83(MRCItem26661 litem &10 6926964 *1092 (MRCItem 26965 litem &1078 26662 26966 pos 1 26663 26967 dimension 50 26664 26968 uid 103,0 26665 26969 ) 26666 *10 84(MRCItem26667 litem &107 026970 *1093 (MRCItem 26971 litem &1079 26668 26972 pos 2 26669 26973 dimension 186 26670 26974 uid 104,0 26671 26975 ) 26672 *10 85(MRCItem26673 litem &10 7126976 *1094 (MRCItem 26977 litem &1080 26674 26978 pos 3 26675 26979 dimension 96 26676 26980 uid 105,0 26677 26981 ) 26678 *10 86(MRCItem26679 litem &10 7226982 *1095 (MRCItem 26983 litem &1081 26680 26984 pos 4 26681 26985 dimension 50 26682 26986 uid 106,0 26683 26987 ) 26684 *10 87(MRCItem26685 litem &10 7326988 *1096 (MRCItem 26989 litem &1082 26686 26990 pos 5 26687 26991 dimension 50 26688 26992 uid 107,0 26689 26993 ) 26690 *10 88(MRCItem26691 litem &10 7426994 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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r10138 r10155 333 333 (vvPair 334 334 variable "date" 335 value " 08.02.2011"335 value "14.02.2011" 336 336 ) 337 337 (vvPair 338 338 variable "day" 339 value " Di"339 value "Mo" 340 340 ) 341 341 (vvPair 342 342 variable "day_long" 343 value " Dienstag"343 value "Montag" 344 344 ) 345 345 (vvPair 346 346 variable "dd" 347 value " 08"347 value "14" 348 348 ) 349 349 (vvPair … … 485 485 (vvPair 486 486 variable "time" 487 value "1 1:05:26"487 value "17:05:04" 488 488 ) 489 489 (vvPair … … 576 576 font "Courier New,8,0" 577 577 ) 578 xt "-172000,106000,-128500,106800" 579 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 580 " 578 xt "-172000,106800,-128500,107600" 579 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 581 580 ) 582 581 ) … … 596 595 ) 597 596 xt "-172000,42800,-132000,43600" 598 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 599 " 597 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 600 598 ) 601 599 ) … … 615 613 ) 616 614 xt "-172000,62000,-139500,62800" 617 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 618 " 615 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 619 616 ) 620 617 ) … … 634 631 ) 635 632 xt "-172000,80400,-132000,81200" 636 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 637 " 633 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 638 634 ) 639 635 ) … … 653 649 ) 654 650 xt "-172000,81200,-139500,82000" 655 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 656 " 651 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 657 652 ) 658 653 ) … … 672 667 ) 673 668 xt "-172000,34400,-132000,35200" 674 st "wiz_reset : std_logic := '1' 675 " 669 st "wiz_reset : std_logic := '1'" 676 670 ) 677 671 ) … … 691 685 ) 692 686 xt "-172000,32000,-143500,32800" 693 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 694 " 687 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 695 688 ) 696 689 ) … … 710 703 ) 711 704 xt "-172000,36800,-143000,37600" 712 st "wiz_data : std_logic_vector(15 DOWNTO 0) 713 " 705 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 714 706 ) 715 707 ) … … 729 721 ) 730 722 xt "-172000,32800,-132000,33600" 731 st "wiz_cs : std_logic := '1' 732 " 723 st "wiz_cs : std_logic := '1'" 733 724 ) 734 725 ) … … 748 739 ) 749 740 xt "-172000,35200,-132000,36000" 750 st "wiz_wr : std_logic := '1' 751 " 741 st "wiz_wr : std_logic := '1'" 752 742 ) 753 743 ) … … 767 757 ) 768 758 xt "-172000,33600,-132000,34400" 769 st "wiz_rd : std_logic := '1' 770 " 759 st "wiz_rd : std_logic := '1'" 771 760 ) 772 761 ) … … 785 774 ) 786 775 xt "-172000,13600,-153500,14400" 787 st "wiz_int : std_logic 788 " 776 st "wiz_int : std_logic" 789 777 ) 790 778 ) … … 2882 2870 ) 2883 2871 xt "-172000,9600,-143500,10400" 2884 st "board_id : std_logic_vector(3 DOWNTO 0) 2885 " 2872 st "board_id : std_logic_vector(3 DOWNTO 0)" 2886 2873 ) 2887 2874 ) … … 2902 2889 ) 2903 2890 xt "-172000,12800,-153500,13600" 2904 st "trigger : std_logic 2905 " 2891 st "trigger : std_logic" 2906 2892 ) 2907 2893 ) … … 4701 4687 ) 4702 4688 xt "-172000,10400,-143500,11200" 4703 st "crate_id : std_logic_vector(1 DOWNTO 0) 4704 " 4689 st "crate_id : std_logic_vector(1 DOWNTO 0)" 4705 4690 ) 4706 4691 ) … … 4926 4911 ) 4927 4912 xt "-172000,98800,-139500,99600" 4928 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 4929 " 4913 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 4930 4914 ) 4931 4915 ) … … 4947 4931 ) 4948 4932 xt "-172000,82000,-132000,82800" 4949 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 4950 " 4933 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 4951 4934 ) 4952 4935 ) … … 5799 5782 font "Courier New,8,0" 5800 5783 ) 5801 xt "-172000,100400,-149500,101200" 5802 st "SIGNAL wiz_busy : std_logic 5803 " 5784 xt "-172000,101200,-149500,102000" 5785 st "SIGNAL wiz_busy : std_logic" 5804 5786 ) 5805 5787 ) … … 5819 5801 font "Courier New,8,0" 5820 5802 ) 5821 xt "-172000,102800,-128500,103600" 5822 st "SIGNAL wiz_write_ea : std_logic := '0' 5823 " 5803 xt "-172000,103600,-128500,104400" 5804 st "SIGNAL wiz_write_ea : std_logic := '0'" 5824 5805 ) 5825 5806 ) … … 5840 5821 font "Courier New,8,0" 5841 5822 ) 5842 xt "-172000,105200,-122500,106000" 5843 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 5844 " 5823 xt "-172000,106000,-122500,106800" 5824 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 5845 5825 ) 5846 5826 ) … … 5862 5842 font "Courier New,8,0" 5863 5843 ) 5864 xt "-172000,102000,-122500,102800" 5865 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 5866 " 5844 xt "-172000,102800,-122500,103600" 5845 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 5867 5846 ) 5868 5847 ) … … 5883 5862 font "Courier New,8,0" 5884 5863 ) 5885 xt "-172000,101200,-122500,102000" 5886 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 5887 " 5864 xt "-172000,102000,-122500,102800" 5865 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 5888 5866 ) 5889 5867 ) … … 5903 5881 font "Courier New,8,0" 5904 5882 ) 5905 xt "-172000,103600,-128500,104400" 5906 st "SIGNAL wiz_write_end : std_logic := '0' 5907 " 5883 xt "-172000,104400,-128500,105200" 5884 st "SIGNAL wiz_write_end : std_logic := '0'" 5908 5885 ) 5909 5886 ) … … 5923 5900 font "Courier New,8,0" 5924 5901 ) 5925 xt "-172000,104400,-128500,105200" 5926 st "SIGNAL wiz_write_header : std_logic := '0' 5927 " 5902 xt "-172000,105200,-128500,106000" 5903 st "SIGNAL wiz_write_header : std_logic := '0'" 5928 5904 ) 5929 5905 ) … … 5942 5918 ) 5943 5919 xt "-172000,82800,-149500,83600" 5944 st "SIGNAL ram_write_ea : std_logic 5945 " 5920 st "SIGNAL ram_write_ea : std_logic" 5946 5921 ) 5947 5922 ) … … 5961 5936 ) 5962 5937 xt "-172000,83600,-128500,84400" 5963 st "SIGNAL ram_write_ready : std_logic := '0' 5964 " 5938 st "SIGNAL ram_write_ready : std_logic := '0'" 5965 5939 ) 5966 5940 ) … … 5980 5954 ) 5981 5955 xt "-172000,54800,-128500,55600" 5982 st "SIGNAL config_start : std_logic := '0' 5983 " 5956 st "SIGNAL config_start : std_logic := '0'" 5984 5957 ) 5985 5958 ) … … 5998 5971 ) 5999 5972 xt "-172000,49200,-149500,50000" 6000 st "SIGNAL config_ready : std_logic 6001 " 5973 st "SIGNAL config_ready : std_logic" 6002 5974 ) 6003 5975 ) … … 6016 5988 ) 6017 5989 xt "-172000,86800,-148000,87600" 6018 st "SIGNAL roi_max : roi_max_type 6019 " 5990 st "SIGNAL roi_max : roi_max_type" 6020 5991 ) 6021 5992 ) … … 6035 6006 ) 6036 6007 xt "-172000,77200,-139500,78000" 6037 st "SIGNAL package_length : std_logic_vector(15 downto 0) 6038 " 6008 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 6039 6009 ) 6040 6010 ) … … 6054 6024 ) 6055 6025 xt "-172000,19200,-132000,20000" 6056 st "adc_oeb : std_logic := '1' 6057 " 6026 st "adc_oeb : std_logic := '1'" 6058 6027 ) 6059 6028 ) … … 6162 6131 ) 6163 6132 xt "-172000,86000,-147000,86800" 6164 st "SIGNAL roi_array : roi_array_type 6165 " 6133 st "SIGNAL roi_array : roi_array_type" 6166 6134 ) 6167 6135 ) … … 6596 6564 ) 6597 6565 xt "-172000,14400,-153500,15200" 6598 st "CLK_25_PS : std_logic 6599 " 6566 st "CLK_25_PS : std_logic" 6600 6567 ) 6601 6568 ) … … 6659 6626 ) 6660 6627 xt "-172000,15200,-153500,16000" 6661 st "CLK_50 : std_logic 6662 " 6628 st "CLK_50 : std_logic" 6663 6629 ) 6664 6630 ) … … 6677 6643 ) 6678 6644 xt "-172000,39600,-149500,40400" 6679 st "SIGNAL CLK_25 : std_logic 6680 " 6645 st "SIGNAL CLK_25 : std_logic" 6681 6646 ) 6682 6647 ) … … 6740 6705 ) 6741 6706 xt "-172000,3200,-153500,4000" 6742 st "CLK : std_logic 6743 " 6707 st "CLK : std_logic" 6744 6708 ) 6745 6709 ) … … 6759 6723 ) 6760 6724 xt "-172000,8800,-143500,9600" 6761 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 6762 " 6725 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 6763 6726 ) 6764 6727 ) … … 6777 6740 ) 6778 6741 xt "-172000,8000,-148000,8800" 6779 st "adc_data_array : adc_data_array_type 6780 " 6742 st "adc_data_array : adc_data_array_type" 6781 6743 ) 6782 6744 ) … … 6841 6803 ) 6842 6804 xt "-172000,66800,-128500,67600" 6843 st "SIGNAL drs_clk_en : std_logic := '0' 6844 " 6805 st "SIGNAL drs_clk_en : std_logic := '0'" 6845 6806 ) 6846 6807 ) … … 6859 6820 ) 6860 6821 xt "-172000,73200,-143500,74000" 6861 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6862 " 6822 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6863 6823 ) 6864 6824 ) … … 6878 6838 ) 6879 6839 xt "-172000,67600,-128500,68400" 6880 st "SIGNAL drs_read_s_cell : std_logic := '0' 6881 " 6840 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6882 6841 ) 6883 6842 ) … … 6898 6857 ) 6899 6858 xt "-172000,25600,-126000,26400" 6900 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6901 " 6859 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6902 6860 ) 6903 6861 ) … … 6917 6875 ) 6918 6876 xt "-172000,26400,-132000,27200" 6919 st "drs_dwrite : std_logic := '1' 6920 " 6877 st "drs_dwrite : std_logic := '1'" 6921 6878 ) 6922 6879 ) … … 7025 6982 ) 7026 6983 xt "-172000,4800,-153500,5600" 7027 st "SROUT_in_0 : std_logic 7028 " 6984 st "SROUT_in_0 : std_logic" 7029 6985 ) 7030 6986 ) … … 7043 6999 ) 7044 7000 xt "-172000,5600,-153500,6400" 7045 st "SROUT_in_1 : std_logic 7046 " 7001 st "SROUT_in_1 : std_logic" 7047 7002 ) 7048 7003 ) … … 7061 7016 ) 7062 7017 xt "-172000,6400,-153500,7200" 7063 st "SROUT_in_2 : std_logic 7064 " 7018 st "SROUT_in_2 : std_logic" 7065 7019 ) 7066 7020 ) … … 7079 7033 ) 7080 7034 xt "-172000,7200,-153500,8000" 7081 st "SROUT_in_3 : std_logic 7082 " 7035 st "SROUT_in_3 : std_logic" 7083 7036 ) 7084 7037 ) … … 7277 7230 ) 7278 7231 xt "-172000,68400,-149500,69200" 7279 st "SIGNAL drs_read_s_cell_ready : std_logic 7280 " 7232 st "SIGNAL drs_read_s_cell_ready : std_logic" 7281 7233 ) 7282 7234 ) … … 7933 7885 ) 7934 7886 xt "-172000,16000,-132000,16800" 7935 st "RSRLOAD : std_logic := '0' 7936 " 7887 st "RSRLOAD : std_logic := '0'" 7937 7888 ) 7938 7889 ) … … 7997 7948 ) 7998 7949 xt "-172000,16800,-132000,17600" 7999 st "SRCLK : std_logic := '0' 8000 " 7950 st "SRCLK : std_logic := '0'" 8001 7951 ) 8002 7952 ) … … 8651 8601 ) 8652 8602 xt "-172000,45200,-140000,46000" 8653 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 8654 " 8603 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 8655 8604 ) 8656 8605 ) … … 8669 8618 ) 8670 8619 xt "-172000,47600,-149500,48400" 8671 st "SIGNAL config_data_valid : std_logic 8672 " 8620 st "SIGNAL config_data_valid : std_logic" 8673 8621 ) 8674 8622 ) … … 8687 8635 ) 8688 8636 xt "-172000,46000,-149500,46800" 8689 st "SIGNAL config_busy : std_logic 8690 " 8637 st "SIGNAL config_busy : std_logic" 8691 8638 ) 8692 8639 ) … … 8706 8653 ) 8707 8654 xt "-172000,46800,-139500,47600" 8708 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 8709 " 8655 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 8710 8656 ) 8711 8657 ) … … 8724 8670 ) 8725 8671 xt "-172000,60400,-149500,61200" 8726 st "SIGNAL config_wr_en : std_logic 8727 " 8672 st "SIGNAL config_wr_en : std_logic" 8728 8673 ) 8729 8674 ) … … 8742 8687 ) 8743 8688 xt "-172000,48400,-149500,49200" 8744 st "SIGNAL config_rd_en : std_logic 8745 " 8689 st "SIGNAL config_rd_en : std_logic" 8746 8690 ) 8747 8691 ) … … 8760 8704 ) 8761 8705 xt "-172000,61200,-147000,62000" 8762 st "SIGNAL dac_array : dac_array_type 8763 " 8706 st "SIGNAL dac_array : dac_array_type" 8764 8707 ) 8765 8708 ) … … 8778 8721 ) 8779 8722 xt "-172000,55600,-149500,56400" 8780 st "SIGNAL config_start_cm : std_logic 8781 " 8723 st "SIGNAL config_start_cm : std_logic" 8782 8724 ) 8783 8725 ) … … 8796 8738 ) 8797 8739 xt "-172000,50000,-149500,50800" 8798 st "SIGNAL config_ready_cm : std_logic 8799 " 8740 st "SIGNAL config_ready_cm : std_logic" 8800 8741 ) 8801 8742 ) … … 8817 8758 ) 8818 8759 xt "-172000,28000,-126000,28800" 8819 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 8820 " 8760 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 8821 8761 ) 8822 8762 ) … … 8835 8775 ) 8836 8776 xt "-172000,91600,-149500,92400" 8837 st "SIGNAL sensor_ready : std_logic 8838 " 8777 st "SIGNAL sensor_ready : std_logic" 8839 8778 ) 8840 8779 ) … … 8853 8792 ) 8854 8793 xt "-172000,90800,-145500,91600" 8855 st "SIGNAL sensor_array : sensor_array_type 8856 " 8794 st "SIGNAL sensor_array : sensor_array_type" 8857 8795 ) 8858 8796 ) … … 8871 8809 ) 8872 8810 xt "-172000,50800,-149500,51600" 8873 st "SIGNAL config_ready_spi : std_logic 8874 " 8811 st "SIGNAL config_ready_spi : std_logic" 8875 8812 ) 8876 8813 ) … … 8891 8828 ) 8892 8829 xt "-172000,42000,-140000,42800" 8893 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 8894 " 8830 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 8895 8831 ) 8896 8832 ) … … 8909 8845 ) 8910 8846 xt "-172000,41200,-144500,42000" 8911 st "SIGNAL adc_data_array_int : adc_data_array_type 8912 " 8847 st "SIGNAL adc_data_array_int : adc_data_array_type" 8913 8848 ) 8914 8849 ) … … 9200 9135 ) 9201 9136 xt "-172000,56400,-128500,57200" 9202 st "SIGNAL config_start_spi : std_logic := '0' 9203 " 9137 st "SIGNAL config_start_spi : std_logic := '0'" 9204 9138 ) 9205 9139 ) … … 9734 9668 ) 9735 9669 xt "-172000,30400,-153500,31200" 9736 st "sclk : std_logic 9737 " 9670 st "sclk : std_logic" 9738 9671 ) 9739 9672 ) … … 9754 9687 ) 9755 9688 xt "-172000,36000,-153500,36800" 9756 st "sio : std_logic 9757 " 9689 st "sio : std_logic" 9758 9690 ) 9759 9691 ) … … 9772 9704 ) 9773 9705 xt "-172000,24000,-153500,24800" 9774 st "dac_cs : std_logic 9775 " 9706 st "dac_cs : std_logic" 9776 9707 ) 9777 9708 ) … … 9791 9722 ) 9792 9723 xt "-172000,31200,-143500,32000" 9793 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 9794 " 9724 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 9795 9725 ) 9796 9726 ) … … 9990 9920 ) 9991 9921 xt "-172000,76400,-128500,77200" 9992 st "SIGNAL new_config : std_logic := '0' 9993 " 9922 st "SIGNAL new_config : std_logic := '0'" 9994 9923 ) 9995 9924 ) … … 10008 9937 ) 10009 9938 xt "-172000,57200,-149500,58000" 10010 st "SIGNAL config_started : std_logic 10011 " 9939 st "SIGNAL config_started : std_logic" 10012 9940 ) 10013 9941 ) … … 10027 9955 ) 10028 9956 xt "-172000,59600,-128500,60400" 10029 st "SIGNAL config_started_spi : std_logic := '0' 10030 " 9957 st "SIGNAL config_started_spi : std_logic := '0'" 10031 9958 ) 10032 9959 ) … … 10046 9973 ) 10047 9974 xt "-172000,58000,-128500,58800" 10048 st "SIGNAL config_started_cu : std_logic := '0' 10049 " 9975 st "SIGNAL config_started_cu : std_logic := '0'" 10050 9976 ) 10051 9977 ) … … 10064 9990 ) 10065 9991 xt "-172000,58800,-149500,59600" 10066 st "SIGNAL config_started_mm : std_logic 10067 " 9992 st "SIGNAL config_started_mm : std_logic" 10068 9993 ) 10069 9994 ) … … 10083 10008 ) 10084 10009 xt "-172000,28800,-132000,29600" 10085 st "mosi : std_logic := '0' 10086 " 10010 st "mosi : std_logic := '0'" 10087 10011 ) 10088 10012 ) … … 10149 10073 ) 10150 10074 xt "-172000,24800,-118500,25600" 10151 st "denable : std_logic := '0' -- default domino wave off 10152 " 10075 st "denable : std_logic := '0' -- default domino wave off" 10153 10076 ) 10154 10077 ) … … 10212 10135 ) 10213 10136 xt "-172000,75600,-128500,76400" 10214 st "SIGNAL dwrite_enable : std_logic := '1' 10215 " 10137 st "SIGNAL dwrite_enable : std_logic := '1'" 10216 10138 ) 10217 10139 ) … … 10600 10522 ) 10601 10523 xt "-172000,74800,-128500,75600" 10602 st "SIGNAL dwrite : std_logic := '1' 10603 " 10524 st "SIGNAL dwrite : std_logic := '1'" 10604 10525 ) 10605 10526 ) … … 10974 10895 font "Courier New,8,0" 10975 10896 ) 10976 xt "-172000,99600,-149500,100400" 10977 st "SIGNAL wiz_ack : std_logic 10978 " 10897 xt "-172000,100400,-149500,101200" 10898 st "SIGNAL wiz_ack : std_logic" 10979 10899 ) 10980 10900 ) … … 11359 11279 ) 11360 11280 xt "-172000,89200,-149500,90000" 11361 st "SIGNAL sclk1 : std_logic 11362 " 11281 st "SIGNAL sclk1 : std_logic" 11363 11282 ) 11364 11283 ) … … 11377 11296 ) 11378 11297 xt "-172000,90000,-149500,90800" 11379 st "SIGNAL sclk_enable : std_logic 11380 " 11298 st "SIGNAL sclk_enable : std_logic" 11381 11299 ) 11382 11300 ) … … 11396 11314 ) 11397 11315 xt "-172000,18400,-132000,19200" 11398 st "adc_clk_en : std_logic := '0' 11399 " 11316 st "adc_clk_en : std_logic := '0'" 11400 11317 ) 11401 11318 ) … … 11851 11768 ) 11852 11769 xt "-172000,78000,-113000,78800" 11853 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards 11854 " 11770 st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" 11855 11771 ) 11856 11772 ) … … 11873 11789 ) 11874 11790 xt "-172000,78800,-112000,79600" 11875 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once 11876 " 11791 st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" 11877 11792 ) 11878 11793 ) … … 11894 11809 ) 11895 11810 xt "-172000,79600,-104500,80400" 11896 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift 11897 " 11811 st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" 11898 11812 ) 11899 11813 ) … … 11913 11827 ) 11914 11828 xt "-172000,94000,-128500,94800" 11915 st "SIGNAL srclk_enable : std_logic := '0' 11916 " 11829 st "SIGNAL srclk_enable : std_logic := '0'" 11917 11830 ) 11918 11831 ) … … 12298 12211 ) 12299 12212 xt "-172000,40400,-128500,41200" 12300 st "SIGNAL SRCLK1 : std_logic := '0' 12301 " 12213 st "SIGNAL SRCLK1 : std_logic := '0'" 12302 12214 ) 12303 12215 ) … … 12321 12233 xt "-172000,51600,-128500,53200" 12322 12234 st "-- -- 12323 SIGNAL config_rw_ack : std_logic := '0' 12324 " 12235 SIGNAL config_rw_ack : std_logic := '0'" 12325 12236 ) 12326 12237 ) … … 12344 12255 xt "-172000,53200,-128500,54800" 12345 12256 st "-- -- 12346 SIGNAL config_rw_ready : std_logic := '0' 12347 " 12257 SIGNAL config_rw_ready : std_logic := '0'" 12348 12258 ) 12349 12259 ) … … 12362 12272 ) 12363 12273 xt "-172000,87600,-149500,88400" 12364 st "SIGNAL s_trigger : std_logic 12365 " 12274 st "SIGNAL s_trigger : std_logic" 12366 12275 ) 12367 12276 ) … … 12380 12289 ) 12381 12290 xt "-172000,96400,-149500,97200" 12382 st "SIGNAL start_srin_write_8b : std_logic 12383 " 12291 st "SIGNAL start_srin_write_8b : std_logic" 12384 12292 ) 12385 12293 ) … … 12399 12307 ) 12400 12308 xt "-172000,94800,-128500,95600" 12401 st "SIGNAL srin_write_ack : std_logic := '0' 12402 " 12309 st "SIGNAL srin_write_ack : std_logic := '0'" 12403 12310 ) 12404 12311 ) … … 12418 12325 ) 12419 12326 xt "-172000,95600,-128500,96400" 12420 st "SIGNAL srin_write_ready : std_logic := '0' 12421 " 12327 st "SIGNAL srin_write_ready : std_logic := '0'" 12422 12328 ) 12423 12329 ) … … 12438 12344 ) 12439 12345 xt "-172000,74000,-122500,74800" 12440 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') 12441 " 12346 st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" 12442 12347 ) 12443 12348 ) … … 12457 12362 ) 12458 12363 xt "-172000,17600,-132000,18400" 12459 st "SRIN_out : std_logic := '0' 12460 " 12364 st "SRIN_out : std_logic := '0'" 12461 12365 ) 12462 12366 ) … … 12980 12884 xt "-172000,84400,-128500,86000" 12981 12885 st "-- -- 12982 SIGNAL ram_write_ready_ack : std_logic := '0' 12983 " 12886 SIGNAL ram_write_ready_ack : std_logic := '0'" 12984 12887 ) 12985 12888 ) … … 12998 12901 ) 12999 12902 xt "-172000,92400,-149500,93200" 13000 st "SIGNAL socks_connected : std_logic 13001 " 12903 st "SIGNAL socks_connected : std_logic" 13002 12904 ) 13003 12905 ) … … 13016 12918 ) 13017 12919 xt "-172000,93200,-149500,94000" 13018 st "SIGNAL socks_waiting : std_logic 13019 " 12920 st "SIGNAL socks_waiting : std_logic" 13020 12921 ) 13021 12922 ) … … 13034 12935 ) 13035 12936 xt "-172000,27200,-153500,28000" 13036 st "green : std_logic 13037 " 12937 st "green : std_logic" 13038 12938 ) 13039 12939 ) … … 13096 12996 ) 13097 12997 xt "-172000,22400,-153500,23200" 13098 st "amber : std_logic 13099 " 12998 st "amber : std_logic" 13100 12999 ) 13101 13000 ) … … 13158 13057 ) 13159 13058 xt "-172000,29600,-153500,30400" 13160 st "red : std_logic 13161 " 13059 st "red : std_logic" 13162 13060 ) 13163 13061 ) … … 13599 13497 ) 13600 13498 xt "-172000,72400,-149500,73200" 13601 st "SIGNAL drs_readout_started : std_logic 13602 " 13499 st "SIGNAL drs_readout_started : std_logic" 13603 13500 ) 13604 13501 ) … … 13617 13514 ) 13618 13515 xt "-172000,98000,-149500,98800" 13619 st "SIGNAL trigger_enable : std_logic 13620 " 13516 st "SIGNAL trigger_enable : std_logic" 13621 13517 ) 13622 13518 ) … … 14006 13902 ) 14007 13903 xt "-172000,65200,-149500,66000" 14008 st "SIGNAL dout : std_logic 14009 " 13904 st "SIGNAL dout : std_logic" 14010 13905 ) 14011 13906 ) … … 14320 14215 ) 14321 14216 xt "-172000,66000,-149500,66800" 14322 st "SIGNAL dout1 : std_logic 14323 " 14217 st "SIGNAL dout1 : std_logic" 14324 14218 ) 14325 14219 ) … … 14345 14239 st "-- -- 14346 14240 -- drs_dwrite : out std_logic := '1'; 14347 SIGNAL drs_readout_ready : std_logic := '0' 14348 " 14241 SIGNAL drs_readout_ready : std_logic := '0'" 14349 14242 ) 14350 14243 ) … … 14363 14256 ) 14364 14257 xt "-172000,71600,-149500,72400" 14365 st "SIGNAL drs_readout_ready_ack : std_logic 14366 " 14258 st "SIGNAL drs_readout_ready_ack : std_logic" 14367 14259 ) 14368 14260 ) … … 14381 14273 ) 14382 14274 xt "-172000,20000,-153500,20800" 14383 st "additional_flasher_out : std_logic 14384 " 14275 st "additional_flasher_out : std_logic" 14385 14276 ) 14386 14277 ) … … 14674 14565 ) 14675 14566 xt "-172000,43600,-128500,44400" 14676 st "SIGNAL c_trigger_enable : std_logic := '0' 14677 " 14567 st "SIGNAL c_trigger_enable : std_logic := '0'" 14678 14568 ) 14679 14569 ) … … 14696 14586 ) 14697 14587 xt "-172000,44400,-112000,45200" 14698 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes 14699 " 14588 st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes" 14700 14589 ) 14701 14590 ) … … 14714 14603 ) 14715 14604 xt "-172000,88400,-149500,89200" 14716 st "SIGNAL s_trigger_0 : std_logic 14717 " 14605 st "SIGNAL s_trigger_0 : std_logic" 14718 14606 ) 14719 14607 ) … … 14732 14620 ) 14733 14621 xt "-172000,97200,-149500,98000" 14734 st "SIGNAL trigger1 : std_logic 14735 " 14622 st "SIGNAL trigger1 : std_logic" 14736 14623 ) 14737 14624 ) … … 15247 15134 ) 15248 15135 xt "-172000,4000,-143500,4800" 15249 st "D_T_in : std_logic_vector(1 DOWNTO 0) 15250 " 15136 st "D_T_in : std_logic_vector(1 DOWNTO 0)" 15251 15137 ) 15252 15138 ) … … 15311 15197 ) 15312 15198 xt "-172000,11200,-121500,12000" 15313 st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit 15314 " 15199 st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 15315 15200 ) 15316 15201 ) … … 15376 15261 ) 15377 15262 xt "-172000,12000,-114000,12800" 15378 st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked 15379 " 15263 st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" 15380 15264 ) 15381 15265 ) … … 15660 15544 ) 15661 15545 xt "-172000,20800,-118500,21600" 15662 st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off 15663 " 15546 st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off" 15664 15547 ) 15665 15548 ) … … 15725 15608 ) 15726 15609 xt "-172000,21600,-118500,22400" 15727 st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off 15728 " 15610 st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off" 15729 15611 ) 15730 15612 ) … … 15789 15671 ) 15790 15672 xt "-172000,23200,-126000,24000" 15791 st "counter_result : std_logic_vector(11 downto 0) := (others => '0') 15792 " 15673 st "counter_result : std_logic_vector(11 downto 0) := (others => '0')" 15793 15674 ) 15794 15675 ) … … 16946 16827 ) 16947 16828 xt "-172000,63600,-115000,64400" 16948 st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off 16949 " 16829 st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off" 16950 16830 ) 16951 16831 ) … … 16967 16847 ) 16968 16848 xt "-172000,64400,-115000,65200" 16969 st "SIGNAL din1 : std_logic := '0' -- default domino wave off 16970 " 16849 st "SIGNAL din1 : std_logic := '0' -- default domino wave off" 16971 16850 ) 16972 16851 ) … … 16988 16867 ) 16989 16868 xt "-172000,62800,-115000,63600" 16990 st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off 16991 " 16992 ) 16993 ) 16994 *598 (Wire 16869 st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off" 16870 ) 16871 ) 16872 *598 (Net 16873 uid 15492,0 16874 decl (Decl 16875 n "trigger_out" 16876 t "std_logic" 16877 o 123 16878 suid 301,0 16879 i "'0'" 16880 ) 16881 declText (MLText 16882 uid 15493,0 16883 va (VaSet 16884 font "Courier New,8,0" 16885 ) 16886 xt "-172000,99600,-128500,100400" 16887 st "SIGNAL trigger_out : std_logic := '0'" 16888 ) 16889 ) 16890 *599 (Wire 16995 16891 uid 322,0 16996 16892 shape (OrthoPolyLine … … 17031 16927 on &2 17032 16928 ) 17033 * 599(Wire16929 *600 (Wire 17034 16930 uid 328,0 17035 16931 shape (OrthoPolyLine … … 17070 16966 on &3 17071 16967 ) 17072 *60 0(Wire16968 *601 (Wire 17073 16969 uid 334,0 17074 16970 shape (OrthoPolyLine … … 17109 17005 on &4 17110 17006 ) 17111 *60 1(Wire17007 *602 (Wire 17112 17008 uid 364,0 17113 17009 shape (OrthoPolyLine … … 17149 17045 on &5 17150 17046 ) 17151 *60 2(Wire17047 *603 (Wire 17152 17048 uid 370,0 17153 17049 shape (OrthoPolyLine … … 17189 17085 on &6 17190 17086 ) 17191 *60 3(Wire17087 *604 (Wire 17192 17088 uid 376,0 17193 17089 shape (OrthoPolyLine … … 17227 17123 on &7 17228 17124 ) 17229 *60 4(Wire17125 *605 (Wire 17230 17126 uid 384,0 17231 17127 shape (OrthoPolyLine … … 17267 17163 on &8 17268 17164 ) 17269 *60 5(Wire17165 *606 (Wire 17270 17166 uid 392,0 17271 17167 shape (OrthoPolyLine … … 17307 17203 on &9 17308 17204 ) 17309 *60 6(Wire17205 *607 (Wire 17310 17206 uid 400,0 17311 17207 shape (OrthoPolyLine … … 17345 17241 on &10 17346 17242 ) 17347 *60 7(Wire17243 *608 (Wire 17348 17244 uid 408,0 17349 17245 shape (OrthoPolyLine … … 17383 17279 on &11 17384 17280 ) 17385 *60 8(Wire17281 *609 (Wire 17386 17282 uid 424,0 17387 17283 shape (OrthoPolyLine … … 17421 17317 on &12 17422 17318 ) 17423 *6 09(Wire17319 *610 (Wire 17424 17320 uid 432,0 17425 17321 shape (OrthoPolyLine … … 17459 17355 on &13 17460 17356 ) 17461 *61 0(Wire17357 *611 (Wire 17462 17358 uid 1411,0 17463 17359 shape (OrthoPolyLine … … 17498 17394 on &71 17499 17395 ) 17500 *61 1(Wire17396 *612 (Wire 17501 17397 uid 1425,0 17502 17398 shape (OrthoPolyLine … … 17537 17433 on &72 17538 17434 ) 17539 *61 2(Wire17435 *613 (Wire 17540 17436 uid 1682,0 17541 17437 shape (OrthoPolyLine … … 17576 17472 on &122 17577 17473 ) 17578 *61 3(Wire17474 *614 (Wire 17579 17475 uid 1983,0 17580 17476 shape (OrthoPolyLine … … 17615 17511 on &130 17616 17512 ) 17617 *61 4(Wire17513 *615 (Wire 17618 17514 uid 2299,0 17619 17515 shape (OrthoPolyLine … … 17653 17549 on &131 17654 17550 ) 17655 *61 5(Wire17551 *616 (Wire 17656 17552 uid 2470,0 17657 17553 shape (OrthoPolyLine … … 17689 17585 on &155 17690 17586 ) 17691 *61 6(Wire17587 *617 (Wire 17692 17588 uid 2476,0 17693 17589 shape (OrthoPolyLine … … 17725 17621 on &156 17726 17622 ) 17727 *61 7(Wire17623 *618 (Wire 17728 17624 uid 2482,0 17729 17625 shape (OrthoPolyLine … … 17763 17659 on &157 17764 17660 ) 17765 *61 8(Wire17661 *619 (Wire 17766 17662 uid 2488,0 17767 17663 shape (OrthoPolyLine … … 17801 17697 on &158 17802 17698 ) 17803 *6 19(Wire17699 *620 (Wire 17804 17700 uid 2494,0 17805 17701 shape (OrthoPolyLine … … 17839 17735 on &159 17840 17736 ) 17841 *62 0(Wire17737 *621 (Wire 17842 17738 uid 2500,0 17843 17739 shape (OrthoPolyLine … … 17875 17771 on &160 17876 17772 ) 17877 *62 1(Wire17773 *622 (Wire 17878 17774 uid 2506,0 17879 17775 shape (OrthoPolyLine … … 17911 17807 on &161 17912 17808 ) 17913 *62 2(Wire17809 *623 (Wire 17914 17810 uid 2576,0 17915 17811 shape (OrthoPolyLine … … 17947 17843 on &162 17948 17844 ) 17949 *62 3(Wire17845 *624 (Wire 17950 17846 uid 2582,0 17951 17847 shape (OrthoPolyLine … … 17983 17879 on &163 17984 17880 ) 17985 *62 4(Wire17881 *625 (Wire 17986 17882 uid 2588,0 17987 17883 shape (OrthoPolyLine … … 18020 17916 on &164 18021 17917 ) 18022 *62 5(Wire17918 *626 (Wire 18023 17919 uid 2594,0 18024 17920 shape (OrthoPolyLine … … 18056 17952 on &165 18057 17953 ) 18058 *62 6(Wire17954 *627 (Wire 18059 17955 uid 2600,0 18060 17956 shape (OrthoPolyLine … … 18092 17988 on &166 18093 17989 ) 18094 *62 7(Wire17990 *628 (Wire 18095 17991 uid 2642,0 18096 17992 shape (OrthoPolyLine … … 18130 18026 on &167 18131 18027 ) 18132 *62 8(Wire18028 *629 (Wire 18133 18029 uid 2778,0 18134 18030 shape (OrthoPolyLine … … 18168 18064 on &168 18169 18065 ) 18170 *6 29(Wire18066 *630 (Wire 18171 18067 uid 2786,0 18172 18068 shape (OrthoPolyLine … … 18208 18104 on &191 18209 18105 ) 18210 *63 0(Wire18106 *631 (Wire 18211 18107 uid 3888,0 18212 18108 optionalChildren [ 18213 *63 1(BdJunction18109 *632 (BdJunction 18214 18110 uid 4230,0 18215 18111 ps "OnConnectorStrategy" … … 18223 18119 ) 18224 18120 ) 18225 *63 2(BdJunction18121 *633 (BdJunction 18226 18122 uid 4244,0 18227 18123 ps "OnConnectorStrategy" … … 18274 18170 on &187 18275 18171 ) 18276 *63 3(Wire18172 *634 (Wire 18277 18173 uid 3984,0 18278 18174 shape (OrthoPolyLine … … 18315 18211 on &185 18316 18212 ) 18317 *63 4(Wire18213 *635 (Wire 18318 18214 uid 4042,0 18319 18215 shape (OrthoPolyLine … … 18353 18249 on &190 18354 18250 ) 18355 *63 5(Wire18251 *636 (Wire 18356 18252 uid 4226,0 18357 18253 shape (OrthoPolyLine … … 18369 18265 ) 18370 18266 start &189 18371 end &63 118267 end &632 18372 18268 sat 32 18373 18269 eat 32 … … 18393 18289 on &187 18394 18290 ) 18395 *63 6(Wire18291 *637 (Wire 18396 18292 uid 4240,0 18397 18293 shape (OrthoPolyLine … … 18409 18305 ) 18410 18306 start &335 18411 end &63 218307 end &633 18412 18308 sat 32 18413 18309 eat 32 … … 18432 18328 on &187 18433 18329 ) 18434 *63 7(Wire18330 *638 (Wire 18435 18331 uid 4272,0 18436 18332 shape (OrthoPolyLine … … 18470 18366 on &192 18471 18367 ) 18472 *63 8(Wire18368 *639 (Wire 18473 18369 uid 4401,0 18474 18370 shape (OrthoPolyLine … … 18508 18404 on &194 18509 18405 ) 18510 *6 39(Wire18406 *640 (Wire 18511 18407 uid 4407,0 18512 18408 shape (OrthoPolyLine … … 18546 18442 on &195 18547 18443 ) 18548 *64 0(Wire18444 *641 (Wire 18549 18445 uid 4419,0 18550 18446 shape (OrthoPolyLine … … 18584 18480 on &196 18585 18481 ) 18586 *64 1(Wire18482 *642 (Wire 18587 18483 uid 4537,0 18588 18484 shape (OrthoPolyLine … … 18624 18520 on &197 18625 18521 ) 18626 *64 2(Wire18522 *643 (Wire 18627 18523 uid 4545,0 18628 18524 shape (OrthoPolyLine … … 18661 18557 on &198 18662 18558 ) 18663 *64 3(Wire18559 *644 (Wire 18664 18560 uid 4671,0 18665 18561 shape (OrthoPolyLine … … 18699 18595 on &201 18700 18596 ) 18701 *64 4(Wire18597 *645 (Wire 18702 18598 uid 4679,0 18703 18599 shape (OrthoPolyLine … … 18737 18633 on &202 18738 18634 ) 18739 *64 5(Wire18635 *646 (Wire 18740 18636 uid 4687,0 18741 18637 shape (OrthoPolyLine … … 18775 18671 on &203 18776 18672 ) 18777 *64 6(Wire18673 *647 (Wire 18778 18674 uid 4695,0 18779 18675 shape (OrthoPolyLine … … 18813 18709 on &204 18814 18710 ) 18815 *64 7(Wire18711 *648 (Wire 18816 18712 uid 4743,0 18817 18713 shape (OrthoPolyLine … … 18851 18747 on &209 18852 18748 ) 18853 *64 8(Wire18749 *649 (Wire 18854 18750 uid 4757,0 18855 18751 optionalChildren [ 18856 *6 49(BdJunction18752 *650 (BdJunction 18857 18753 uid 6076,0 18858 18754 ps "OnConnectorStrategy" … … 18862 18758 vasetType 1 18863 18759 ) 18864 xt "-2 5400,40600,-24600,41400"18760 xt "-26400,40600,-25600,41400" 18865 18761 radius 400 18866 18762 ) … … 18873 18769 lineColor "0,32896,0" 18874 18770 ) 18875 xt "-6 2000,41000,-25000,48000"18771 xt "-64000,41000,-26000,48000" 18876 18772 pts [ 18877 18773 "-58750,48000" 18878 "-6 2000,48000"18879 "-6 2000,41000"18880 "-2 5000,41000"18774 "-64000,48000" 18775 "-64000,41000" 18776 "-26000,41000" 18881 18777 ] 18882 18778 ) 18883 18779 start &211 18884 end *65 0(BdJunction18780 end *651 (BdJunction 18885 18781 uid 6080,0 18886 18782 ps "OnConnectorStrategy" … … 18890 18786 vasetType 1 18891 18787 ) 18892 xt "-2 5400,40600,-24600,41400"18788 xt "-26400,40600,-25600,41400" 18893 18789 radius 400 18894 18790 ) … … 18916 18812 on &188 18917 18813 ) 18918 *65 1(Wire18814 *652 (Wire 18919 18815 uid 4948,0 18920 18816 shape (OrthoPolyLine … … 18954 18850 on &230 18955 18851 ) 18956 *65 2(Wire18852 *653 (Wire 18957 18853 uid 4962,0 18958 18854 shape (OrthoPolyLine … … 18992 18888 on &232 18993 18889 ) 18994 *65 3(Wire18890 *654 (Wire 18995 18891 uid 5090,0 18996 18892 shape (OrthoPolyLine … … 19031 18927 on &252 19032 18928 ) 19033 *65 4(Wire18929 *655 (Wire 19034 18930 uid 5098,0 19035 18931 shape (OrthoPolyLine … … 19065 18961 on &253 19066 18962 ) 19067 *65 5(Wire18963 *656 (Wire 19068 18964 uid 5106,0 19069 18965 shape (OrthoPolyLine … … 19102 18998 on &254 19103 18999 ) 19104 *65 6(Wire19000 *657 (Wire 19105 19001 uid 5114,0 19106 19002 shape (OrthoPolyLine … … 19141 19037 on &255 19142 19038 ) 19143 *65 7(Wire19039 *658 (Wire 19144 19040 uid 5122,0 19145 19041 shape (OrthoPolyLine … … 19178 19074 on &256 19179 19075 ) 19180 *65 8(Wire19076 *659 (Wire 19181 19077 uid 5130,0 19182 19078 shape (OrthoPolyLine … … 19215 19111 on &257 19216 19112 ) 19217 *6 59(Wire19113 *660 (Wire 19218 19114 uid 5138,0 19219 19115 optionalChildren [ 19220 *66 0(BdJunction19116 *661 (BdJunction 19221 19117 uid 5400,0 19222 19118 ps "OnConnectorStrategy" … … 19268 19164 on &171 19269 19165 ) 19270 *66 1(Wire19166 *662 (Wire 19271 19167 uid 5146,0 19272 19168 shape (OrthoPolyLine … … 19304 19200 on &258 19305 19201 ) 19306 *66 2(Wire19202 *663 (Wire 19307 19203 uid 5168,0 19308 19204 shape (OrthoPolyLine … … 19319 19215 ] 19320 19216 ) 19321 start &66 019217 start &661 19322 19218 end &147 19323 19219 sat 32 … … 19342 19238 on &171 19343 19239 ) 19344 *66 3(Wire19240 *664 (Wire 19345 19241 uid 5184,0 19346 19242 shape (OrthoPolyLine … … 19379 19275 on &259 19380 19276 ) 19381 *66 4(Wire19277 *665 (Wire 19382 19278 uid 5190,0 19383 19279 shape (OrthoPolyLine … … 19416 19312 on &260 19417 19313 ) 19418 *66 5(Wire19314 *666 (Wire 19419 19315 uid 5222,0 19420 19316 shape (OrthoPolyLine … … 19456 19352 on &261 19457 19353 ) 19458 *66 6(Wire19354 *667 (Wire 19459 19355 uid 5404,0 19460 19356 shape (OrthoPolyLine … … 19493 19389 on &264 19494 19390 ) 19495 *66 7(Wire19391 *668 (Wire 19496 19392 uid 5474,0 19497 19393 shape (OrthoPolyLine … … 19530 19426 on &262 19531 19427 ) 19532 *66 8(Wire19428 *669 (Wire 19533 19429 uid 5480,0 19534 19430 shape (OrthoPolyLine … … 19567 19463 on &263 19568 19464 ) 19569 *6 69(Wire19465 *670 (Wire 19570 19466 uid 5582,0 19571 19467 shape (OrthoPolyLine … … 19602 19498 on &187 19603 19499 ) 19604 *67 0(Wire19500 *671 (Wire 19605 19501 uid 5602,0 19606 19502 optionalChildren [ 19607 &65 019503 &651 19608 19504 ] 19609 19505 shape (OrthoPolyLine … … 19613 19509 lineColor "0,32896,0" 19614 19510 ) 19615 xt "-2 5000,41000,36250,51000"19511 xt "-26000,41000,36250,51000" 19616 19512 pts [ 19617 19513 "-21750,51000" 19618 "-2 5000,51000"19619 "-2 5000,41000"19514 "-26000,51000" 19515 "-26000,41000" 19620 19516 "28000,41000" 19621 19517 "28000,47000" … … 19647 19543 on &188 19648 19544 ) 19649 *67 1(Wire19545 *672 (Wire 19650 19546 uid 5626,0 19651 19547 shape (OrthoPolyLine … … 19683 19579 on &266 19684 19580 ) 19685 *67 2(Wire19581 *673 (Wire 19686 19582 uid 5634,0 19687 19583 shape (OrthoPolyLine … … 19721 19617 on &265 19722 19618 ) 19723 *67 3(Wire19619 *674 (Wire 19724 19620 uid 5646,0 19725 19621 shape (OrthoPolyLine … … 19757 19653 on &185 19758 19654 ) 19759 *67 4(Wire19655 *675 (Wire 19760 19656 uid 5745,0 19761 19657 shape (OrthoPolyLine … … 19795 19691 on &276 19796 19692 ) 19797 *67 5(Wire19693 *676 (Wire 19798 19694 uid 5805,0 19799 19695 shape (OrthoPolyLine … … 19829 19725 on &187 19830 19726 ) 19831 *67 6(Wire19727 *677 (Wire 19832 19728 uid 5813,0 19833 19729 shape (OrthoPolyLine … … 19867 19763 on &293 19868 19764 ) 19869 *67 7(Wire19765 *678 (Wire 19870 19766 uid 5821,0 19871 19767 shape (OrthoPolyLine … … 19905 19801 on &294 19906 19802 ) 19907 *67 8(Wire19803 *679 (Wire 19908 19804 uid 5829,0 19909 19805 shape (OrthoPolyLine … … 19943 19839 on &295 19944 19840 ) 19945 *6 79(Wire19841 *680 (Wire 19946 19842 uid 5837,0 19947 19843 shape (OrthoPolyLine … … 19983 19879 on &296 19984 19880 ) 19985 *68 0(Wire19881 *681 (Wire 19986 19882 uid 5950,0 19987 19883 shape (OrthoPolyLine … … 20021 19917 on &301 20022 19918 ) 20023 *68 1(Wire19919 *682 (Wire 20024 19920 uid 5962,0 20025 19921 shape (OrthoPolyLine … … 20059 19955 on &302 20060 19956 ) 20061 *68 2(Wire19957 *683 (Wire 20062 19958 uid 6002,0 20063 19959 shape (OrthoPolyLine … … 20097 19993 on &304 20098 19994 ) 20099 *68 3(Wire19995 *684 (Wire 20100 19996 uid 6008,0 20101 19997 shape (OrthoPolyLine … … 20135 20031 on &303 20136 20032 ) 20137 *68 4(Wire20033 *685 (Wire 20138 20034 uid 6018,0 20139 20035 shape (OrthoPolyLine … … 20171 20067 on &305 20172 20068 ) 20173 *68 5(Wire20069 *686 (Wire 20174 20070 uid 6064,0 20175 20071 shape (OrthoPolyLine … … 20206 20102 on &258 20207 20103 ) 20208 *68 6(Wire20104 *687 (Wire 20209 20105 uid 6072,0 20210 20106 shape (OrthoPolyLine … … 20214 20110 lineColor "0,32896,0" 20215 20111 ) 20216 xt "-41250,23000,-2 5000,41000"20112 xt "-41250,23000,-26000,41000" 20217 20113 pts [ 20218 20114 "-41250,23000" 20219 "-2 5000,23000"20220 "-2 5000,41000"20115 "-26000,23000" 20116 "-26000,41000" 20221 20117 ] 20222 20118 ) 20223 20119 start &366 20224 end &6 4920120 end &650 20225 20121 sat 32 20226 20122 eat 32 … … 20245 20141 on &188 20246 20142 ) 20247 *68 7(Wire20143 *688 (Wire 20248 20144 uid 6160,0 20249 20145 shape (OrthoPolyLine … … 20283 20179 on &306 20284 20180 ) 20285 *68 8(Wire20181 *689 (Wire 20286 20182 uid 6276,0 20287 20183 shape (OrthoPolyLine … … 20317 20213 on &185 20318 20214 ) 20319 *6 89(Wire20215 *690 (Wire 20320 20216 uid 6362,0 20321 20217 shape (OrthoPolyLine … … 20356 20252 on &308 20357 20253 ) 20358 *69 0(Wire20254 *691 (Wire 20359 20255 uid 6452,0 20360 20256 shape (OrthoPolyLine … … 20392 20288 on &310 20393 20289 ) 20394 *69 1(Wire20290 *692 (Wire 20395 20291 uid 6540,0 20396 20292 shape (OrthoPolyLine … … 20429 20325 on &329 20430 20326 ) 20431 *69 2(Wire20327 *693 (Wire 20432 20328 uid 6548,0 20433 20329 shape (OrthoPolyLine … … 20466 20362 on &310 20467 20363 ) 20468 *69 3(Wire20364 *694 (Wire 20469 20365 uid 8416,0 20470 20366 shape (OrthoPolyLine … … 20502 20398 on &341 20503 20399 ) 20504 *69 4(Wire20400 *695 (Wire 20505 20401 uid 8732,0 20506 20402 shape (OrthoPolyLine … … 20540 20436 on &360 20541 20437 ) 20542 *69 5(Wire20438 *696 (Wire 20543 20439 uid 8738,0 20544 20440 shape (OrthoPolyLine … … 20576 20472 on &361 20577 20473 ) 20578 *69 6(Wire20474 *697 (Wire 20579 20475 uid 8752,0 20580 20476 shape (OrthoPolyLine … … 20611 20507 on &361 20612 20508 ) 20613 *69 7(Wire20509 *698 (Wire 20614 20510 uid 9006,0 20615 20511 shape (OrthoPolyLine … … 20649 20545 on &362 20650 20546 ) 20651 *69 8(Wire20547 *699 (Wire 20652 20548 uid 9233,0 20653 20549 shape (OrthoPolyLine … … 20684 20580 on &376 20685 20581 ) 20686 * 699(Wire20582 *700 (Wire 20687 20583 uid 9241,0 20688 20584 shape (OrthoPolyLine … … 20719 20615 on &377 20720 20616 ) 20721 *70 0(Wire20617 *701 (Wire 20722 20618 uid 9253,0 20723 20619 shape (OrthoPolyLine … … 20753 20649 on &376 20754 20650 ) 20755 *70 1(Wire20651 *702 (Wire 20756 20652 uid 9261,0 20757 20653 shape (OrthoPolyLine … … 20787 20683 on &377 20788 20684 ) 20789 *70 2(Wire20685 *703 (Wire 20790 20686 uid 9943,0 20791 20687 shape (OrthoPolyLine … … 20822 20718 on &378 20823 20719 ) 20824 *70 3(Wire20720 *704 (Wire 20825 20721 uid 9951,0 20826 20722 shape (OrthoPolyLine … … 20857 20753 on &379 20858 20754 ) 20859 *70 4(Wire20755 *705 (Wire 20860 20756 uid 10010,0 20861 20757 shape (OrthoPolyLine … … 20895 20791 on &398 20896 20792 ) 20897 *70 5(Wire20793 *706 (Wire 20898 20794 uid 10018,0 20899 20795 shape (OrthoPolyLine … … 20931 20827 on &379 20932 20828 ) 20933 *70 6(Wire20829 *707 (Wire 20934 20830 uid 10036,0 20935 20831 shape (OrthoPolyLine … … 20965 20861 on &378 20966 20862 ) 20967 *70 7(Wire20863 *708 (Wire 20968 20864 uid 10194,0 20969 20865 shape (OrthoPolyLine … … 21005 20901 on &399 21006 20902 ) 21007 *70 8(Wire20903 *709 (Wire 21008 20904 uid 10202,0 21009 20905 shape (OrthoPolyLine … … 21043 20939 on &400 21044 20940 ) 21045 *7 09(Wire20941 *710 (Wire 21046 20942 uid 10266,0 21047 20943 shape (OrthoPolyLine … … 21078 20974 on &498 21079 20975 ) 21080 *71 0(Wire20976 *711 (Wire 21081 20977 uid 10298,0 21082 20978 shape (OrthoPolyLine … … 21114 21010 on &402 21115 21011 ) 21116 *71 1(Wire21012 *712 (Wire 21117 21013 uid 10304,0 21118 21014 shape (OrthoPolyLine … … 21150 21046 on &403 21151 21047 ) 21152 *71 2(Wire21048 *713 (Wire 21153 21049 uid 10310,0 21154 21050 shape (OrthoPolyLine … … 21186 21082 on &404 21187 21083 ) 21188 *71 3(Wire21084 *714 (Wire 21189 21085 uid 10316,0 21190 21086 shape (OrthoPolyLine … … 21224 21120 on &405 21225 21121 ) 21226 *71 4(Wire21122 *715 (Wire 21227 21123 uid 10322,0 21228 21124 shape (OrthoPolyLine … … 21262 21158 on &406 21263 21159 ) 21264 *71 5(Wire21160 *716 (Wire 21265 21161 uid 10431,0 21266 21162 shape (OrthoPolyLine … … 21299 21195 on &401 21300 21196 ) 21301 *71 6(Wire21197 *717 (Wire 21302 21198 uid 10467,0 21303 21199 shape (OrthoPolyLine … … 21336 21232 on &431 21337 21233 ) 21338 *71 7(Wire21234 *718 (Wire 21339 21235 uid 10629,0 21340 21236 shape (OrthoPolyLine … … 21371 21267 on &432 21372 21268 ) 21373 *71 8(Wire21269 *719 (Wire 21374 21270 uid 10637,0 21375 21271 shape (OrthoPolyLine … … 21406 21302 on &433 21407 21303 ) 21408 *7 19(Wire21304 *720 (Wire 21409 21305 uid 10685,0 21410 21306 shape (OrthoPolyLine … … 21441 21337 on &433 21442 21338 ) 21443 *72 0(Wire21339 *721 (Wire 21444 21340 uid 10691,0 21445 21341 shape (OrthoPolyLine … … 21476 21372 on &432 21477 21373 ) 21478 *72 1(Wire21374 *722 (Wire 21479 21375 uid 10699,0 21480 21376 shape (OrthoPolyLine … … 21512 21408 on &187 21513 21409 ) 21514 *72 2(Wire21410 *723 (Wire 21515 21411 uid 10707,0 21516 21412 shape (OrthoPolyLine … … 21547 21443 on &452 21548 21444 ) 21549 *72 3(Wire21445 *724 (Wire 21550 21446 uid 10723,0 21551 21447 shape (OrthoPolyLine … … 21585 21481 on &434 21586 21482 ) 21587 *72 4(Wire21483 *725 (Wire 21588 21484 uid 10737,0 21589 21485 shape (OrthoPolyLine … … 21623 21519 on &436 21624 21520 ) 21625 *72 5(Wire21521 *726 (Wire 21626 21522 uid 10751,0 21627 21523 shape (OrthoPolyLine … … 21661 21557 on &438 21662 21558 ) 21663 *72 6(Wire21559 *727 (Wire 21664 21560 uid 11405,0 21665 21561 shape (OrthoPolyLine … … 21697 21593 on &452 21698 21594 ) 21699 *72 7(Wire21595 *728 (Wire 21700 21596 uid 11858,0 21701 21597 shape (OrthoPolyLine … … 21732 21628 on &453 21733 21629 ) 21734 *72 8(Wire21630 *729 (Wire 21735 21631 uid 11952,0 21736 21632 shape (OrthoPolyLine … … 21768 21664 on &453 21769 21665 ) 21770 *7 29(Wire21666 *730 (Wire 21771 21667 uid 12306,0 21772 21668 shape (OrthoPolyLine … … 21806 21702 on &472 21807 21703 ) 21808 *73 0(Wire21704 *731 (Wire 21809 21705 uid 12643,0 21810 21706 shape (OrthoPolyLine … … 21846 21742 on &483 21847 21743 ) 21848 *73 1(Wire21744 *732 (Wire 21849 21745 uid 12649,0 21850 21746 shape (OrthoPolyLine … … 21882 21778 on &484 21883 21779 ) 21884 *73 2(Wire21780 *733 (Wire 21885 21781 uid 12655,0 21886 21782 shape (OrthoPolyLine … … 21919 21815 on &485 21920 21816 ) 21921 *73 3(Wire21817 *734 (Wire 21922 21818 uid 12687,0 21923 21819 shape (OrthoPolyLine … … 21957 21853 on &188 21958 21854 ) 21959 *73 4(Wire21855 *735 (Wire 21960 21856 uid 12707,0 21961 21857 shape (OrthoPolyLine … … 21995 21891 on &486 21996 21892 ) 21997 *73 5(Wire21893 *736 (Wire 21998 21894 uid 13143,0 21999 21895 shape (OrthoPolyLine … … 22030 21926 on &188 22031 21927 ) 22032 *73 6(Wire21928 *737 (Wire 22033 21929 uid 13159,0 22034 21930 shape (OrthoPolyLine … … 22068 21964 on &496 22069 21965 ) 22070 *73 7(Wire21966 *738 (Wire 22071 21967 uid 13165,0 22072 21968 shape (OrthoPolyLine … … 22108 22004 on &497 22109 22005 ) 22110 *73 8(Wire22006 *739 (Wire 22111 22007 uid 13210,0 22112 22008 shape (OrthoPolyLine … … 22144 22040 on &499 22145 22041 ) 22146 *7 39(Wire22042 *740 (Wire 22147 22043 uid 13216,0 22148 22044 shape (OrthoPolyLine … … 22180 22076 on &498 22181 22077 ) 22182 *74 0(Wire22078 *741 (Wire 22183 22079 uid 13224,0 22184 22080 shape (OrthoPolyLine … … 22216 22112 on &401 22217 22113 ) 22218 *74 1(Wire22114 *742 (Wire 22219 22115 uid 13695,0 22220 22116 shape (OrthoPolyLine … … 22255 22151 on &524 22256 22152 ) 22257 *74 2(Wire22153 *743 (Wire 22258 22154 uid 13921,0 22259 22155 shape (OrthoPolyLine … … 22292 22188 on &71 22293 22189 ) 22294 *74 3(Wire22190 *744 (Wire 22295 22191 uid 13929,0 22296 22192 shape (OrthoPolyLine … … 22329 22225 on &122 22330 22226 ) 22331 *74 4(Wire22227 *745 (Wire 22332 22228 uid 14048,0 22333 22229 shape (OrthoPolyLine … … 22366 22262 on &526 22367 22263 ) 22368 *74 5(Wire22264 *746 (Wire 22369 22265 uid 14171,0 22370 22266 shape (OrthoPolyLine … … 22404 22300 on &528 22405 22301 ) 22406 *74 6(Wire22302 *747 (Wire 22407 22303 uid 14427,0 22408 22304 shape (OrthoPolyLine … … 22439 22335 on &187 22440 22336 ) 22441 *74 7(Wire22337 *748 (Wire 22442 22338 uid 14479,0 22443 22339 shape (OrthoPolyLine … … 22477 22373 on &538 22478 22374 ) 22479 *74 8(Wire22375 *749 (Wire 22480 22376 uid 14493,0 22481 22377 shape (OrthoPolyLine … … 22515 22411 on &540 22516 22412 ) 22517 *7 49(Wire22413 *750 (Wire 22518 22414 uid 14622,0 22519 22415 shape (OrthoPolyLine … … 22555 22451 on &542 22556 22452 ) 22557 *75 0(Wire22453 *751 (Wire 22558 22454 uid 15071,0 22559 22455 shape (OrthoPolyLine … … 22591 22487 on &595 22592 22488 ) 22593 *75 1(Wire22489 *752 (Wire 22594 22490 uid 15081,0 22595 22491 shape (OrthoPolyLine … … 22629 22525 on &596 22630 22526 ) 22631 *75 2(Wire22527 *753 (Wire 22632 22528 uid 15122,0 22633 22529 shape (OrthoPolyLine … … 22667 22563 on &597 22668 22564 ) 22669 *75 3(Wire22565 *754 (Wire 22670 22566 uid 15130,0 22671 22567 shape (OrthoPolyLine … … 22705 22601 on &540 22706 22602 ) 22707 *75 4(Wire22603 *755 (Wire 22708 22604 uid 15138,0 22709 22605 shape (OrthoPolyLine … … 22743 22639 on &538 22744 22640 ) 22745 *75 5(Wire22641 *756 (Wire 22746 22642 uid 15379,0 22747 22643 shape (OrthoPolyLine … … 22778 22674 on &188 22779 22675 ) 22676 *757 (Wire 22677 uid 15494,0 22678 optionalChildren [ 22679 *758 (BdJunction 22680 uid 15502,0 22681 ps "OnConnectorStrategy" 22682 shape (Circle 22683 uid 15503,0 22684 va (VaSet 22685 vasetType 1 22686 ) 22687 xt "-54400,71600,-53600,72400" 22688 radius 400 22689 ) 22690 ) 22691 ] 22692 shape (OrthoPolyLine 22693 uid 15495,0 22694 va (VaSet 22695 vasetType 3 22696 ) 22697 xt "-55250,72000,-21750,72000" 22698 pts [ 22699 "-55250,72000" 22700 "-21750,72000" 22701 ] 22702 ) 22703 start &475 22704 end &30 22705 sat 32 22706 eat 32 22707 st 0 22708 sf 1 22709 si 0 22710 tg (WTG 22711 uid 15496,0 22712 ps "ConnStartEndStrategy" 22713 stg "STSignalDisplayStrategy" 22714 f (Text 22715 uid 15497,0 22716 va (VaSet 22717 ) 22718 xt "-53250,71000,-48650,72000" 22719 st "trigger_out" 22720 blo "-53250,71800" 22721 tm "WireNameMgr" 22722 ) 22723 ) 22724 on &598 22725 ) 22726 *759 (Wire 22727 uid 15498,0 22728 shape (OrthoPolyLine 22729 uid 15499,0 22730 va (VaSet 22731 vasetType 3 22732 ) 22733 xt "-54000,69000,-52750,72000" 22734 pts [ 22735 "-52750,69000" 22736 "-54000,69000" 22737 "-54000,72000" 22738 ] 22739 ) 22740 start &125 22741 end &758 22742 sat 32 22743 eat 32 22744 stc 0 22745 st 0 22746 sf 1 22747 si 0 22748 tg (WTG 22749 uid 15500,0 22750 ps "ConnStartEndStrategy" 22751 stg "STSignalDisplayStrategy" 22752 f (Text 22753 uid 15501,0 22754 va (VaSet 22755 ) 22756 xt "-58000,69000,-53400,70000" 22757 st "trigger_out" 22758 blo "-58000,69800" 22759 tm "WireNameMgr" 22760 ) 22761 ) 22762 on &598 22763 ) 22780 22764 ] 22781 22765 bg "65535,65535,65535" … … 22790 22774 color "26368,26368,26368" 22791 22775 ) 22792 packageList *7 56(PackageList22776 packageList *760 (PackageList 22793 22777 uid 41,0 22794 22778 stg "VerticalLayoutStrategy" 22795 22779 textVec [ 22796 *7 57(Text22780 *761 (Text 22797 22781 uid 42,0 22798 22782 va (VaSet … … 22803 22787 blo "-163000,-15200" 22804 22788 ) 22805 *7 58(MLText22789 *762 (MLText 22806 22790 uid 43,0 22807 22791 va (VaSet … … 22828 22812 stg "VerticalLayoutStrategy" 22829 22813 textVec [ 22830 *7 59(Text22814 *763 (Text 22831 22815 uid 45,0 22832 22816 va (VaSet … … 22838 22822 blo "20000,800" 22839 22823 ) 22840 *76 0(Text22824 *764 (Text 22841 22825 uid 46,0 22842 22826 va (VaSet … … 22848 22832 blo "20000,1800" 22849 22833 ) 22850 *76 1(MLText22834 *765 (MLText 22851 22835 uid 47,0 22852 22836 va (VaSet … … 22858 22842 tm "BdCompilerDirectivesTextMgr" 22859 22843 ) 22860 *76 2(Text22844 *766 (Text 22861 22845 uid 48,0 22862 22846 va (VaSet … … 22868 22852 blo "20000,4800" 22869 22853 ) 22870 *76 3(MLText22854 *767 (MLText 22871 22855 uid 49,0 22872 22856 va (VaSet … … 22876 22860 tm "BdCompilerDirectivesTextMgr" 22877 22861 ) 22878 *76 4(Text22862 *768 (Text 22879 22863 uid 50,0 22880 22864 va (VaSet … … 22886 22870 blo "20000,5800" 22887 22871 ) 22888 *76 5(MLText22872 *769 (MLText 22889 22873 uid 51,0 22890 22874 va (VaSet … … 22898 22882 ) 22899 22883 windowSize "0,0,1281,1024" 22900 viewArea "- 65668,47481,1175,102606"22884 viewArea "-115714,18689,-11272,104822" 22901 22885 cachedDiagramExtent "-174000,-25425,428157,346294" 22902 22886 pageSetupInfo (PageSetupInfo … … 22924 22908 hasePageBreakOrigin 1 22925 22909 pageBreakOrigin "-73000,0" 22926 lastUid 15 388,022910 lastUid 15608,0 22927 22911 defaultCommentText (CommentText 22928 22912 shape (Rectangle … … 22986 22970 stg "VerticalLayoutStrategy" 22987 22971 textVec [ 22988 *7 66(Text22972 *770 (Text 22989 22973 va (VaSet 22990 22974 font "Arial,8,1" … … 22995 22979 tm "BdLibraryNameMgr" 22996 22980 ) 22997 *7 67(Text22981 *771 (Text 22998 22982 va (VaSet 22999 22983 font "Arial,8,1" … … 23004 22988 tm "BlkNameMgr" 23005 22989 ) 23006 *7 68(Text22990 *772 (Text 23007 22991 va (VaSet 23008 22992 font "Arial,8,1" … … 23055 23039 stg "VerticalLayoutStrategy" 23056 23040 textVec [ 23057 *7 69(Text23041 *773 (Text 23058 23042 va (VaSet 23059 23043 font "Arial,8,1" … … 23063 23047 blo "550,4300" 23064 23048 ) 23065 *77 0(Text23049 *774 (Text 23066 23050 va (VaSet 23067 23051 font "Arial,8,1" … … 23071 23055 blo "550,5300" 23072 23056 ) 23073 *77 1(Text23057 *775 (Text 23074 23058 va (VaSet 23075 23059 font "Arial,8,1" … … 23120 23104 stg "VerticalLayoutStrategy" 23121 23105 textVec [ 23122 *77 2(Text23106 *776 (Text 23123 23107 va (VaSet 23124 23108 font "Arial,8,1" … … 23129 23113 tm "BdLibraryNameMgr" 23130 23114 ) 23131 *77 3(Text23115 *777 (Text 23132 23116 va (VaSet 23133 23117 font "Arial,8,1" … … 23138 23122 tm "CptNameMgr" 23139 23123 ) 23140 *77 4(Text23124 *778 (Text 23141 23125 va (VaSet 23142 23126 font "Arial,8,1" … … 23192 23176 stg "VerticalLayoutStrategy" 23193 23177 textVec [ 23194 *77 5(Text23178 *779 (Text 23195 23179 va (VaSet 23196 23180 font "Arial,8,1" … … 23200 23184 blo "500,4300" 23201 23185 ) 23202 *7 76(Text23186 *780 (Text 23203 23187 va (VaSet 23204 23188 font "Arial,8,1" … … 23208 23192 blo "500,5300" 23209 23193 ) 23210 *7 77(Text23194 *781 (Text 23211 23195 va (VaSet 23212 23196 font "Arial,8,1" … … 23253 23237 stg "VerticalLayoutStrategy" 23254 23238 textVec [ 23255 *7 78(Text23239 *782 (Text 23256 23240 va (VaSet 23257 23241 font "Arial,8,1" … … 23261 23245 blo "50,4300" 23262 23246 ) 23263 *7 79(Text23247 *783 (Text 23264 23248 va (VaSet 23265 23249 font "Arial,8,1" … … 23269 23253 blo "50,5300" 23270 23254 ) 23271 *78 0(Text23255 *784 (Text 23272 23256 va (VaSet 23273 23257 font "Arial,8,1" … … 23310 23294 stg "VerticalLayoutStrategy" 23311 23295 textVec [ 23312 *78 1(Text23296 *785 (Text 23313 23297 va (VaSet 23314 23298 font "Arial,8,1" … … 23319 23303 tm "HdlTextNameMgr" 23320 23304 ) 23321 *78 2(Text23305 *786 (Text 23322 23306 va (VaSet 23323 23307 font "Arial,8,1" … … 23722 23706 stg "VerticalLayoutStrategy" 23723 23707 textVec [ 23724 *78 3(Text23708 *787 (Text 23725 23709 va (VaSet 23726 23710 font "Arial,8,1" … … 23730 23714 blo "14100,20800" 23731 23715 ) 23732 *78 4(MLText23716 *788 (MLText 23733 23717 va (VaSet 23734 23718 ) … … 23782 23766 stg "VerticalLayoutStrategy" 23783 23767 textVec [ 23784 *78 5(Text23768 *789 (Text 23785 23769 va (VaSet 23786 23770 font "Arial,8,1" … … 23790 23774 blo "14100,20800" 23791 23775 ) 23792 *7 86(MLText23776 *790 (MLText 23793 23777 va (VaSet 23794 23778 ) … … 23915 23899 font "Arial,8,1" 23916 23900 ) 23917 xt "-174000,10 6800,-169300,107800"23901 xt "-174000,107600,-169300,108600" 23918 23902 st "Post User:" 23919 blo "-174000,10 7600"23903 blo "-174000,108400" 23920 23904 ) 23921 23905 postUserText (MLText … … 23930 23914 commonDM (CommonDM 23931 23915 ldm (LogicalDM 23932 suid 30 0,023916 suid 301,0 23933 23917 usingSuid 1 23934 emptyRow *7 87(LEmptyRow23918 emptyRow *791 (LEmptyRow 23935 23919 ) 23936 23920 uid 54,0 23937 23921 optionalChildren [ 23938 *7 88(RefLabelRowHdr23939 ) 23940 *7 89(TitleRowHdr23941 ) 23942 *79 0(FilterRowHdr23943 ) 23944 *79 1(RefLabelColHdr23922 *792 (RefLabelRowHdr 23923 ) 23924 *793 (TitleRowHdr 23925 ) 23926 *794 (FilterRowHdr 23927 ) 23928 *795 (RefLabelColHdr 23945 23929 tm "RefLabelColHdrMgr" 23946 23930 ) 23947 *79 2(RowExpandColHdr23931 *796 (RowExpandColHdr 23948 23932 tm "RowExpandColHdrMgr" 23949 23933 ) 23950 *79 3(GroupColHdr23934 *797 (GroupColHdr 23951 23935 tm "GroupColHdrMgr" 23952 23936 ) 23953 *79 4(NameColHdr23937 *798 (NameColHdr 23954 23938 tm "BlockDiagramNameColHdrMgr" 23955 23939 ) 23956 *79 5(ModeColHdr23940 *799 (ModeColHdr 23957 23941 tm "BlockDiagramModeColHdrMgr" 23958 23942 ) 23959 * 796(TypeColHdr23943 *800 (TypeColHdr 23960 23944 tm "BlockDiagramTypeColHdrMgr" 23961 23945 ) 23962 * 797(BoundsColHdr23946 *801 (BoundsColHdr 23963 23947 tm "BlockDiagramBoundsColHdrMgr" 23964 23948 ) 23965 * 798(InitColHdr23949 *802 (InitColHdr 23966 23950 tm "BlockDiagramInitColHdrMgr" 23967 23951 ) 23968 * 799(EolColHdr23952 *803 (EolColHdr 23969 23953 tm "BlockDiagramEolColHdrMgr" 23970 23954 ) 23971 *80 0(LeafLogPort23955 *804 (LeafLogPort 23972 23956 port (LogicalPort 23973 23957 m 4 … … 23983 23967 uid 516,0 23984 23968 ) 23985 *80 1(LeafLogPort23969 *805 (LeafLogPort 23986 23970 port (LogicalPort 23987 23971 m 4 … … 23996 23980 uid 518,0 23997 23981 ) 23998 *80 2(LeafLogPort23982 *806 (LeafLogPort 23999 23983 port (LogicalPort 24000 23984 m 4 … … 24009 23993 uid 520,0 24010 23994 ) 24011 *80 3(LeafLogPort23995 *807 (LeafLogPort 24012 23996 port (LogicalPort 24013 23997 m 4 … … 24022 24006 uid 530,0 24023 24007 ) 24024 *80 4(LeafLogPort24008 *808 (LeafLogPort 24025 24009 port (LogicalPort 24026 24010 m 4 … … 24035 24019 uid 532,0 24036 24020 ) 24037 *80 5(LeafLogPort24021 *809 (LeafLogPort 24038 24022 port (LogicalPort 24039 24023 m 1 … … 24048 24032 uid 534,0 24049 24033 ) 24050 *8 06(LeafLogPort24034 *810 (LeafLogPort 24051 24035 port (LogicalPort 24052 24036 m 1 … … 24061 24045 uid 536,0 24062 24046 ) 24063 *8 07(LeafLogPort24047 *811 (LeafLogPort 24064 24048 port (LogicalPort 24065 24049 m 2 … … 24074 24058 uid 538,0 24075 24059 ) 24076 *8 08(LeafLogPort24060 *812 (LeafLogPort 24077 24061 port (LogicalPort 24078 24062 m 1 … … 24087 24071 uid 540,0 24088 24072 ) 24089 *8 09(LeafLogPort24073 *813 (LeafLogPort 24090 24074 port (LogicalPort 24091 24075 m 1 … … 24100 24084 uid 542,0 24101 24085 ) 24102 *81 0(LeafLogPort24086 *814 (LeafLogPort 24103 24087 port (LogicalPort 24104 24088 m 1 … … 24113 24097 uid 546,0 24114 24098 ) 24115 *81 1(LeafLogPort24099 *815 (LeafLogPort 24116 24100 port (LogicalPort 24117 24101 decl (Decl … … 24124 24108 uid 548,0 24125 24109 ) 24126 *81 2(LeafLogPort24110 *816 (LeafLogPort 24127 24111 port (LogicalPort 24128 24112 decl (Decl … … 24136 24120 uid 1455,0 24137 24121 ) 24138 *81 3(LeafLogPort24122 *817 (LeafLogPort 24139 24123 port (LogicalPort 24140 24124 decl (Decl … … 24149 24133 uid 1457,0 24150 24134 ) 24151 *81 4(LeafLogPort24135 *818 (LeafLogPort 24152 24136 port (LogicalPort 24153 24137 decl (Decl … … 24161 24145 uid 1694,0 24162 24146 ) 24163 *81 5(LeafLogPort24147 *819 (LeafLogPort 24164 24148 port (LogicalPort 24165 24149 lang 2 … … 24177 24161 uid 1993,0 24178 24162 ) 24179 *8 16(LeafLogPort24163 *820 (LeafLogPort 24180 24164 port (LogicalPort 24181 24165 m 4 … … 24192 24176 uid 2305,0 24193 24177 ) 24194 *8 17(LeafLogPort24178 *821 (LeafLogPort 24195 24179 port (LogicalPort 24196 24180 lang 2 … … 24205 24189 uid 2510,0 24206 24190 ) 24207 *8 18(LeafLogPort24191 *822 (LeafLogPort 24208 24192 port (LogicalPort 24209 24193 lang 2 … … 24219 24203 uid 2512,0 24220 24204 ) 24221 *8 19(LeafLogPort24205 *823 (LeafLogPort 24222 24206 port (LogicalPort 24223 24207 lang 2 … … 24234 24218 uid 2514,0 24235 24219 ) 24236 *82 0(LeafLogPort24220 *824 (LeafLogPort 24237 24221 port (LogicalPort 24238 24222 lang 2 … … 24250 24234 uid 2516,0 24251 24235 ) 24252 *82 1(LeafLogPort24236 *825 (LeafLogPort 24253 24237 port (LogicalPort 24254 24238 lang 2 … … 24265 24249 uid 2518,0 24266 24250 ) 24267 *82 2(LeafLogPort24251 *826 (LeafLogPort 24268 24252 port (LogicalPort 24269 24253 lang 2 … … 24279 24263 uid 2520,0 24280 24264 ) 24281 *82 3(LeafLogPort24265 *827 (LeafLogPort 24282 24266 port (LogicalPort 24283 24267 lang 2 … … 24293 24277 uid 2522,0 24294 24278 ) 24295 *82 4(LeafLogPort24279 *828 (LeafLogPort 24296 24280 port (LogicalPort 24297 24281 m 4 … … 24305 24289 uid 2604,0 24306 24290 ) 24307 *82 5(LeafLogPort24291 *829 (LeafLogPort 24308 24292 port (LogicalPort 24309 24293 m 4 … … 24318 24302 uid 2606,0 24319 24303 ) 24320 *8 26(LeafLogPort24304 *830 (LeafLogPort 24321 24305 port (LogicalPort 24322 24306 m 4 … … 24331 24315 uid 2608,0 24332 24316 ) 24333 *8 27(LeafLogPort24317 *831 (LeafLogPort 24334 24318 port (LogicalPort 24335 24319 m 4 … … 24343 24327 uid 2610,0 24344 24328 ) 24345 *8 28(LeafLogPort24329 *832 (LeafLogPort 24346 24330 port (LogicalPort 24347 24331 m 4 … … 24355 24339 uid 2612,0 24356 24340 ) 24357 *8 29(LeafLogPort24341 *833 (LeafLogPort 24358 24342 port (LogicalPort 24359 24343 m 4 … … 24368 24352 uid 2646,0 24369 24353 ) 24370 *83 0(LeafLogPort24354 *834 (LeafLogPort 24371 24355 port (LogicalPort 24372 24356 m 1 … … 24381 24365 uid 2812,0 24382 24366 ) 24383 *83 1(LeafLogPort24367 *835 (LeafLogPort 24384 24368 port (LogicalPort 24385 24369 m 4 … … 24393 24377 uid 2962,0 24394 24378 ) 24395 *83 2(LeafLogPort24379 *836 (LeafLogPort 24396 24380 port (LogicalPort 24397 24381 m 1 … … 24405 24389 uid 3902,0 24406 24390 ) 24407 *83 3(LeafLogPort24391 *837 (LeafLogPort 24408 24392 port (LogicalPort 24409 24393 m 1 … … 24417 24401 uid 4070,0 24418 24402 ) 24419 *83 4(LeafLogPort24403 *838 (LeafLogPort 24420 24404 port (LogicalPort 24421 24405 m 4 … … 24429 24413 uid 4212,0 24430 24414 ) 24431 *83 5(LeafLogPort24415 *839 (LeafLogPort 24432 24416 port (LogicalPort 24433 24417 decl (Decl … … 24440 24424 uid 4234,0 24441 24425 ) 24442 *8 36(LeafLogPort24426 *840 (LeafLogPort 24443 24427 port (LogicalPort 24444 24428 decl (Decl … … 24452 24436 uid 4262,0 24453 24437 ) 24454 *8 37(LeafLogPort24438 *841 (LeafLogPort 24455 24439 port (LogicalPort 24456 24440 decl (Decl … … 24463 24447 uid 4276,0 24464 24448 ) 24465 *8 38(LeafLogPort24449 *842 (LeafLogPort 24466 24450 port (LogicalPort 24467 24451 m 4 … … 24476 24460 uid 4563,0 24477 24461 ) 24478 *8 39(LeafLogPort24462 *843 (LeafLogPort 24479 24463 port (LogicalPort 24480 24464 m 4 … … 24488 24472 uid 4565,0 24489 24473 ) 24490 *84 0(LeafLogPort24474 *844 (LeafLogPort 24491 24475 port (LogicalPort 24492 24476 m 4 … … 24501 24485 uid 4569,0 24502 24486 ) 24503 *84 1(LeafLogPort24487 *845 (LeafLogPort 24504 24488 port (LogicalPort 24505 24489 m 1 … … 24515 24499 uid 4585,0 24516 24500 ) 24517 *84 2(LeafLogPort24501 *846 (LeafLogPort 24518 24502 port (LogicalPort 24519 24503 m 1 … … 24528 24512 uid 4587,0 24529 24513 ) 24530 *84 3(LeafLogPort24514 *847 (LeafLogPort 24531 24515 port (LogicalPort 24532 24516 decl (Decl … … 24539 24523 uid 4733,0 24540 24524 ) 24541 *84 4(LeafLogPort24525 *848 (LeafLogPort 24542 24526 port (LogicalPort 24543 24527 decl (Decl … … 24550 24534 uid 4735,0 24551 24535 ) 24552 *84 5(LeafLogPort24536 *849 (LeafLogPort 24553 24537 port (LogicalPort 24554 24538 decl (Decl … … 24561 24545 uid 4737,0 24562 24546 ) 24563 *8 46(LeafLogPort24547 *850 (LeafLogPort 24564 24548 port (LogicalPort 24565 24549 decl (Decl … … 24572 24556 uid 4739,0 24573 24557 ) 24574 *8 47(LeafLogPort24558 *851 (LeafLogPort 24575 24559 port (LogicalPort 24576 24560 m 4 … … 24584 24568 uid 4749,0 24585 24569 ) 24586 *8 48(LeafLogPort24570 *852 (LeafLogPort 24587 24571 port (LogicalPort 24588 24572 m 1 … … 24597 24581 uid 4974,0 24598 24582 ) 24599 *8 49(LeafLogPort24583 *853 (LeafLogPort 24600 24584 port (LogicalPort 24601 24585 m 1 … … 24610 24594 uid 4976,0 24611 24595 ) 24612 *85 0(LeafLogPort24596 *854 (LeafLogPort 24613 24597 port (LogicalPort 24614 24598 m 4 … … 24623 24607 uid 5198,0 24624 24608 ) 24625 *85 1(LeafLogPort24609 *855 (LeafLogPort 24626 24610 port (LogicalPort 24627 24611 m 4 … … 24635 24619 uid 5200,0 24636 24620 ) 24637 *85 2(LeafLogPort24621 *856 (LeafLogPort 24638 24622 port (LogicalPort 24639 24623 m 4 … … 24647 24631 uid 5202,0 24648 24632 ) 24649 *85 3(LeafLogPort24633 *857 (LeafLogPort 24650 24634 port (LogicalPort 24651 24635 m 4 … … 24660 24644 uid 5204,0 24661 24645 ) 24662 *85 4(LeafLogPort24646 *858 (LeafLogPort 24663 24647 port (LogicalPort 24664 24648 m 4 … … 24672 24656 uid 5206,0 24673 24657 ) 24674 *85 5(LeafLogPort24658 *859 (LeafLogPort 24675 24659 port (LogicalPort 24676 24660 m 4 … … 24684 24668 uid 5208,0 24685 24669 ) 24686 *8 56(LeafLogPort24670 *860 (LeafLogPort 24687 24671 port (LogicalPort 24688 24672 m 4 … … 24696 24680 uid 5210,0 24697 24681 ) 24698 *8 57(LeafLogPort24682 *861 (LeafLogPort 24699 24683 port (LogicalPort 24700 24684 m 4 … … 24708 24692 uid 5212,0 24709 24693 ) 24710 *8 58(LeafLogPort24694 *862 (LeafLogPort 24711 24695 port (LogicalPort 24712 24696 m 4 … … 24720 24704 uid 5214,0 24721 24705 ) 24722 *8 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20 26325 26322 uid 14635,0 26326 26323 ) 26327 *10 46(MRCItem26328 litem &9 1926324 *1051 (MRCItem 26325 litem &923 26329 26326 pos 119 26330 26327 dimension 20 26331 26328 uid 15145,0 26332 26329 ) 26333 *10 47(MRCItem26334 litem &92 026330 *1052 (MRCItem 26331 litem &924 26335 26332 pos 120 26336 26333 dimension 20 26337 26334 uid 15147,0 26338 26335 ) 26339 *10 48(MRCItem26340 litem &92 126336 *1053 (MRCItem 26337 litem &925 26341 26338 pos 121 26342 26339 dimension 20 26343 26340 uid 15149,0 26341 ) 26342 *1054 (MRCItem 26343 litem &926 26344 pos 122 26345 dimension 20 26346 uid 15505,0 26344 26347 ) 26345 26348 ] … … 26354 26357 uid 73,0 26355 26358 optionalChildren [ 26356 *10 49(MRCItem26357 litem &79 126359 *1055 (MRCItem 26360 litem &795 26358 26361 pos 0 26359 26362 dimension 20 26360 26363 uid 74,0 26361 26364 ) 26362 *105 0(MRCItem26363 litem &79 326365 *1056 (MRCItem 26366 litem &797 26364 26367 pos 1 26365 26368 dimension 50 26366 26369 uid 75,0 26367 26370 ) 26368 *105 1(MRCItem26369 litem &79 426371 *1057 (MRCItem 26372 litem &798 26370 26373 pos 2 26371 26374 dimension 100 26372 26375 uid 76,0 26373 26376 ) 26374 *105 2(MRCItem26375 litem &79 526377 *1058 (MRCItem 26378 litem &799 26376 26379 pos 3 26377 26380 dimension 50 26378 26381 uid 77,0 26379 26382 ) 26380 *105 3(MRCItem26381 litem & 79626383 *1059 (MRCItem 26384 litem &800 26382 26385 pos 4 26383 26386 dimension 100 26384 26387 uid 78,0 26385 26388 ) 26386 *10 54(MRCItem26387 litem & 79726389 *1060 (MRCItem 26390 litem &801 26388 26391 pos 5 26389 26392 dimension 100 26390 26393 uid 79,0 26391 26394 ) 26392 *10 55(MRCItem26393 litem & 79826395 *1061 (MRCItem 26396 litem &802 26394 26397 pos 6 26395 26398 dimension 50 26396 26399 uid 80,0 26397 26400 ) 26398 *10 56(MRCItem26399 litem & 79926401 *1062 (MRCItem 26402 litem &803 26400 26403 pos 7 26401 26404 dimension 290 … … 26417 26420 genericsCommonDM (CommonDM 26418 26421 ldm (LogicalDM 26419 emptyRow *10 57(LEmptyRow26422 emptyRow *1063 (LEmptyRow 26420 26423 ) 26421 26424 uid 83,0 26422 26425 optionalChildren [ 26423 *10 58(RefLabelRowHdr26424 ) 26425 *10 59(TitleRowHdr26426 ) 26427 *106 0(FilterRowHdr26428 ) 26429 *106 1(RefLabelColHdr26426 *1064 (RefLabelRowHdr 26427 ) 26428 *1065 (TitleRowHdr 26429 ) 26430 *1066 (FilterRowHdr 26431 ) 26432 *1067 (RefLabelColHdr 26430 26433 tm "RefLabelColHdrMgr" 26431 26434 ) 26432 *106 2(RowExpandColHdr26435 *1068 (RowExpandColHdr 26433 26436 tm "RowExpandColHdrMgr" 26434 26437 ) 26435 *106 3(GroupColHdr26438 *1069 (GroupColHdr 26436 26439 tm "GroupColHdrMgr" 26437 26440 ) 26438 *10 64(NameColHdr26441 *1070 (NameColHdr 26439 26442 tm "GenericNameColHdrMgr" 26440 26443 ) 26441 *10 65(TypeColHdr26444 *1071 (TypeColHdr 26442 26445 tm "GenericTypeColHdrMgr" 26443 26446 ) 26444 *10 66(InitColHdr26447 *1072 (InitColHdr 26445 26448 tm "GenericValueColHdrMgr" 26446 26449 ) 26447 *10 67(PragmaColHdr26450 *1073 (PragmaColHdr 26448 26451 tm "GenericPragmaColHdrMgr" 26449 26452 ) 26450 *10 68(EolColHdr26453 *1074 (EolColHdr 26451 26454 tm "GenericEolColHdrMgr" 26452 26455 ) 26453 *10 69(LogGeneric26456 *1075 (LogGeneric 26454 26457 generic (GiElement 26455 26458 name "RAMADDRWIDTH64b" … … 26466 26469 uid 95,0 26467 26470 optionalChildren [ 26468 *107 0(Sheet26471 *1076 (Sheet 26469 26472 sheetRow (SheetRow 26470 26473 headerVa (MVa … … 26483 26486 font "Tahoma,10,0" 26484 26487 ) 26485 emptyMRCItem *107 1(MRCItem26486 litem &10 5726488 emptyMRCItem *1077 (MRCItem 26489 litem &1063 26487 26490 pos 1 26488 26491 dimension 20 … … 26490 26493 uid 97,0 26491 26494 optionalChildren [ 26492 *107 2(MRCItem26493 litem &10 5826495 *1078 (MRCItem 26496 litem &1064 26494 26497 pos 0 26495 26498 dimension 20 26496 26499 uid 98,0 26497 26500 ) 26498 *107 3(MRCItem26499 litem &10 5926501 *1079 (MRCItem 26502 litem &1065 26500 26503 pos 1 26501 26504 dimension 23 26502 26505 uid 99,0 26503 26506 ) 26504 *10 74(MRCItem26505 litem &106 026507 *1080 (MRCItem 26508 litem &1066 26506 26509 pos 2 26507 26510 hidden 1 … … 26509 26512 uid 100,0 26510 26513 ) 26511 *10 75(MRCItem26512 litem &10 6926514 *1081 (MRCItem 26515 litem &1075 26513 26516 pos 0 26514 26517 dimension 20 … … 26526 26529 uid 101,0 26527 26530 optionalChildren [ 26528 *10 76(MRCItem26529 litem &106 126531 *1082 (MRCItem 26532 litem &1067 26530 26533 pos 0 26531 26534 dimension 20 26532 26535 uid 102,0 26533 26536 ) 26534 *10 77(MRCItem26535 litem &106 326537 *1083 (MRCItem 26538 litem &1069 26536 26539 pos 1 26537 26540 dimension 50 26538 26541 uid 103,0 26539 26542 ) 26540 *10 78(MRCItem26541 litem &10 6426543 *1084 (MRCItem 26544 litem &1070 26542 26545 pos 2 26543 26546 dimension 186 26544 26547 uid 104,0 26545 26548 ) 26546 *10 79(MRCItem26547 litem &10 6526549 *1085 (MRCItem 26550 litem &1071 26548 26551 pos 3 26549 26552 dimension 96 26550 26553 uid 105,0 26551 26554 ) 26552 *108 0(MRCItem26553 litem &10 6626555 *1086 (MRCItem 26556 litem &1072 26554 26557 pos 4 26555 26558 dimension 50 26556 26559 uid 106,0 26557 26560 ) 26558 *108 1(MRCItem26559 litem &10 6726561 *1087 (MRCItem 26562 litem &1073 26560 26563 pos 5 26561 26564 dimension 50 26562 26565 uid 107,0 26563 26566 ) 26564 *108 2(MRCItem26565 litem &10 6826567 *1088 (MRCItem 26568 litem &1074 26566 26569 pos 6 26567 26570 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb
r10138 r10155 1199 1199 (vvPair 1200 1200 variable "date" 1201 value " 08.02.2011"1201 value "15.02.2011" 1202 1202 ) 1203 1203 (vvPair … … 1211 1211 (vvPair 1212 1212 variable "dd" 1213 value " 08"1213 value "15" 1214 1214 ) 1215 1215 (vvPair … … 1351 1351 (vvPair 1352 1352 variable "time" 1353 value " 11:06:22"1353 value "09:27:14" 1354 1354 ) 1355 1355 (vvPair … … 4000 4000 ) 4001 4001 ) 4002 lastUid 59 42,04002 lastUid 5988,0 4003 4003 okToSyncOnLoad 1 4004 4004 OkToSyncGenericsOnLoad 1 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd
r10129 r10155 15 15 unitName "numeric_std" 16 16 ) 17 (DmPackageRef 18 library "FACT_FAD_lib" 19 unitName "fad_definitions" 20 ) 17 21 ] 18 22 instances [ … … 57 61 "ieee" 58 62 "UNISIM" 63 "FACT_FAD_lib" 59 64 ] 60 65 ) … … 107 112 (vvPair 108 113 variable "date" 109 value " 04.02.2011"114 value "12.02.2011" 110 115 ) 111 116 (vvPair 112 117 variable "day" 113 value " Fr"118 value "Sa" 114 119 ) 115 120 (vvPair 116 121 variable "day_long" 117 value " Freitag"122 value "Samstag" 118 123 ) 119 124 (vvPair 120 125 variable "dd" 121 value " 04"126 value "12" 122 127 ) 123 128 (vvPair … … 255 260 (vvPair 256 261 variable "time" 257 value "1 2:52:25"262 value "13:16:51" 258 263 ) 259 264 (vvPair … … 761 766 ) 762 767 xt "11000,-9200,24000,-8400" 763 st "CLK_50 : std_logic" 768 st "CLK_50 : std_logic 769 " 764 770 ) 765 771 ) … … 778 784 ) 779 785 xt "11000,-10800,24000,-10000" 780 st "CLK_25 : std_logic" 786 st "CLK_25 : std_logic 787 " 781 788 ) 782 789 ) … … 795 802 ) 796 803 xt "11000,-14000,24000,-13200" 797 st "CLK : std_logic" 804 st "CLK : std_logic 805 " 798 806 ) 799 807 ) … … 1563 1571 ) 1564 1572 xt "11000,-6600,27500,-5800" 1565 st "SIGNAL CLK0_OUT : std_logic" 1573 st "SIGNAL CLK0_OUT : std_logic 1574 " 1566 1575 ) 1567 1576 ) … … 1580 1589 ) 1581 1590 xt "11000,-5000,27500,-4200" 1582 st "SIGNAL PSCLK_IN : std_logic" 1591 st "SIGNAL PSCLK_IN : std_logic 1592 " 1583 1593 ) 1584 1594 ) … … 1597 1607 ) 1598 1608 xt "11000,-3400,27500,-2600" 1599 st "SIGNAL PSEN_IN : std_logic" 1609 st "SIGNAL PSEN_IN : std_logic 1610 " 1600 1611 ) 1601 1612 ) … … 1614 1625 ) 1615 1626 xt "11000,-2600,27500,-1800" 1616 st "SIGNAL PSINCDEC_IN : std_logic" 1627 st "SIGNAL PSINCDEC_IN : std_logic 1628 " 1617 1629 ) 1618 1630 ) … … 1631 1643 ) 1632 1644 xt "11000,-4200,27500,-3400" 1633 st "SIGNAL PSDONE_OUT : std_logic" 1645 st "SIGNAL PSDONE_OUT : std_logic 1646 " 1634 1647 ) 1635 1648 ) … … 1648 1661 ) 1649 1662 xt "11000,-5800,27500,-5000" 1650 st "SIGNAL LOCKED_OUT : std_logic" 1663 st "SIGNAL LOCKED_OUT : std_logic 1664 " 1651 1665 ) 1652 1666 ) … … 1874 1888 n "LOCKED" 1875 1889 t "std_logic" 1890 eolc "-- when is this going high?" 1876 1891 preAdd 0 1877 1892 posAdd 0 … … 1989 2004 preAdd 0 1990 2005 posAdd 0 1991 o 1 02006 o 11 1992 2007 suid 10,0 1993 2008 i "'0'" … … 2028 2043 preAdd 0 2029 2044 posAdd 0 2030 o 1 12045 o 12 2031 2046 suid 11,0 2032 2047 i "'0'" … … 2068 2083 preAdd 0 2069 2084 posAdd 0 2070 o 1 22085 o 13 2071 2086 suid 12,0 2072 2087 i "(OTHERS => '0')" … … 2075 2090 ) 2076 2091 *62 (CptPort 2077 uid 815,02078 ps "OnEdgeStrategy"2079 shape (Triangle2080 uid 816,02081 ro 902082 va (VaSet2083 vasetType 12084 fg "0,65535,0"2085 )2086 xt "64000,32625,64750,33375"2087 )2088 tg (CPTG2089 uid 817,02090 ps "CptPortTextPlaceStrategy"2091 stg "RightVerticalLayoutStrategy"2092 f (Text2093 uid 818,02094 va (VaSet2095 )2096 xt "57800,32500,63000,33500"2097 st "DCM_locked"2098 ju 22099 blo "63000,33300"2100 )2101 )2102 thePort (LogicalPort2103 m 12104 decl (Decl2105 n "DCM_locked"2106 t "std_logic"2107 preAdd 02108 posAdd 02109 o 132110 suid 13,02111 )2112 )2113 )2114 *63 (CptPort2115 2092 uid 1621,0 2116 2093 ps "OnEdgeStrategy" 2117 2094 shape (Triangle 2118 uid 1622,0 2119 ro 90 2095 ro 270 2120 2096 va (VaSet 2121 2097 vasetType 1 … … 2138 2114 ) 2139 2115 thePort (LogicalPort 2116 m 1 2140 2117 decl (Decl 2141 2118 n "rst" … … 2145 2122 o 2 2146 2123 suid 15,0 2124 i "'0'" 2125 ) 2126 ) 2127 ) 2128 *63 (CptPort 2129 uid 1975,0 2130 ps "OnEdgeStrategy" 2131 shape (Triangle 2132 uid 1976,0 2133 ro 90 2134 va (VaSet 2135 vasetType 1 2136 fg "0,65535,0" 2137 ) 2138 xt "37250,41625,38000,42375" 2139 ) 2140 tg (CPTG 2141 uid 1977,0 2142 ps "CptPortTextPlaceStrategy" 2143 stg "VerticalLayoutStrategy" 2144 f (Text 2145 uid 1978,0 2146 va (VaSet 2147 ) 2148 xt "39000,41500,43400,42500" 2149 st "reset_DCM" 2150 blo "39000,42300" 2151 ) 2152 ) 2153 thePort (LogicalPort 2154 decl (Decl 2155 n "reset_DCM" 2156 t "std_logic" 2157 eolc "-- asynch in: orders us, to reset the DCM" 2158 posAdd 0 2159 o 10 2160 suid 17,0 2147 2161 ) 2148 2162 ) … … 2157 2171 lineWidth 2 2158 2172 ) 2159 xt "38000,28000,64000,4 3000"2173 xt "38000,28000,64000,44000" 2160 2174 ) 2161 2175 oxt "50000,7000,63000,25000" … … 2221 2235 fg "49152,49152,49152" 2222 2236 ) 2223 xt "38250,4 1250,39750,42750"2237 xt "38250,42250,39750,43750" 2224 2238 iconName "VhdlFileViewIcon.png" 2225 2239 iconMaskName "VhdlFileViewIcon.msk" … … 2291 2305 ) 2292 2306 xt "11000,-10000,24000,-9200" 2293 st "CLK_25_PS : std_logic" 2307 st "CLK_25_PS : std_logic 2308 " 2294 2309 ) 2295 2310 ) … … 2354 2369 ) 2355 2370 xt "11000,-11600,24000,-10800" 2356 st "do_shift : std_logic" 2371 st "do_shift : std_logic 2372 " 2357 2373 ) 2358 2374 ) … … 2417 2433 ) 2418 2434 xt "11000,-12400,24000,-11600" 2419 st "direction : std_logic" 2435 st "direction : std_logic 2436 " 2420 2437 ) 2421 2438 ) … … 2434 2451 ) 2435 2452 xt "11000,-13200,24000,-12400" 2436 st "RST_IN : std_logic" 2453 st "RST_IN : std_logic 2454 " 2437 2455 ) 2438 2456 ) … … 2450 2468 sl 0 2451 2469 ro 270 2452 xt " 6000,35625,7500,36375"2470 xt "28000,42625,29500,43375" 2453 2471 ) 2454 2472 (Line … … 2456 2474 sl 0 2457 2475 ro 270 2458 xt " 7500,36000,8000,36000"2476 xt "29500,43000,30000,43000" 2459 2477 pts [ 2460 " 7500,36000"2461 " 8000,36000"2478 "29500,43000" 2479 "30000,43000" 2462 2480 ] 2463 2481 ) … … 2475 2493 font "arial,8,0" 2476 2494 ) 2477 xt " 1800,35500,5000,36500"2495 xt "23800,42500,27000,43500" 2478 2496 st "RST_IN" 2479 2497 ju 2 2480 blo " 5000,36300"2498 blo "27000,43300" 2481 2499 tm "WireNameMgr" 2482 2500 ) … … 2501 2519 ) 2502 2520 xt "11000,-8400,43500,-7600" 2503 st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 2521 st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 2522 " 2504 2523 ) 2505 2524 ) … … 2549 2568 ) 2550 2569 ) 2551 *77 (Wire 2570 *77 (Net 2571 uid 1979,0 2572 decl (Decl 2573 n "rst" 2574 t "std_logic" 2575 eolc "--asynch in of DCM" 2576 posAdd 0 2577 o 15 2578 suid 40,0 2579 i "'0'" 2580 ) 2581 declText (MLText 2582 uid 1980,0 2583 va (VaSet 2584 font "Courier New,8,0" 2585 ) 2586 xt "11000,-1800,50500,-1000" 2587 st "SIGNAL rst : std_logic := '0' --asynch in of DCM 2588 " 2589 ) 2590 ) 2591 *78 (Wire 2552 2592 uid 163,0 2553 2593 shape (OrthoPolyLine … … 2588 2628 on &17 2589 2629 ) 2590 *7 8(Wire2630 *79 (Wire 2591 2631 uid 191,0 2592 2632 shape (OrthoPolyLine … … 2627 2667 on &15 2628 2668 ) 2629 * 79(Wire2669 *80 (Wire 2630 2670 uid 209,0 2631 2671 optionalChildren [ 2632 *8 0(BdJunction2672 *81 (BdJunction 2633 2673 uid 233,0 2634 2674 ps "OnConnectorStrategy" … … 2680 2720 on &16 2681 2721 ) 2682 *8 1(Wire2722 *82 (Wire 2683 2723 uid 229,0 2684 2724 shape (OrthoPolyLine … … 2694 2734 ] 2695 2735 ) 2696 start &8 02736 start &81 2697 2737 end &19 2698 2738 sat 32 … … 2719 2759 on &16 2720 2760 ) 2721 *8 2(Wire2761 *83 (Wire 2722 2762 uid 526,0 2723 2763 shape (OrthoPolyLine … … 2760 2800 on &44 2761 2801 ) 2762 *8 3(Wire2802 *84 (Wire 2763 2803 uid 532,0 2764 2804 shape (OrthoPolyLine … … 2803 2843 on &45 2804 2844 ) 2805 *8 4(Wire2845 *85 (Wire 2806 2846 uid 546,0 2807 2847 shape (OrthoPolyLine … … 2846 2886 on &46 2847 2887 ) 2848 *8 5(Wire2888 *86 (Wire 2849 2889 uid 588,0 2850 2890 shape (OrthoPolyLine … … 2885 2925 on &48 2886 2926 ) 2887 *8 6(Wire2927 *87 (Wire 2888 2928 uid 602,0 2889 2929 shape (OrthoPolyLine … … 2924 2964 on &49 2925 2965 ) 2926 *8 7(Wire2966 *88 (Wire 2927 2967 uid 841,0 2928 2968 shape (OrthoPolyLine … … 2967 3007 on &47 2968 3008 ) 2969 *8 8(Wire3009 *89 (Wire 2970 3010 uid 1254,0 2971 3011 shape (OrthoPolyLine … … 3006 3046 on &68 3007 3047 ) 3008 * 89(Wire3048 *90 (Wire 3009 3049 uid 1272,0 3010 3050 shape (OrthoPolyLine … … 3045 3085 on &70 3046 3086 ) 3047 *9 0(Wire3087 *91 (Wire 3048 3088 uid 1286,0 3049 3089 shape (OrthoPolyLine … … 3084 3124 on &72 3085 3125 ) 3086 *9 1(Wire3126 *92 (Wire 3087 3127 uid 1458,0 3088 3128 shape (OrthoPolyLine … … 3121 3161 on &44 3122 3162 ) 3123 *9 2(Wire3163 *93 (Wire 3124 3164 uid 1493,0 3125 optionalChildren [3126 *93 (BdJunction3127 uid 1629,03128 ps "OnConnectorStrategy"3129 shape (Circle3130 uid 1630,03131 va (VaSet3132 vasetType 13133 )3134 xt "9600,35600,10400,36400"3135 radius 4003136 )3137 )3138 ]3139 3165 shape (OrthoPolyLine 3140 3166 uid 1494,0 … … 3142 3168 vasetType 3 3143 3169 ) 3144 xt " 8000,36000,13250,36000"3170 xt "30000,42000,37250,43000" 3145 3171 pts [ 3146 " 8000,36000"3147 " 13250,36000"3172 "30000,43000" 3173 "37250,42000" 3148 3174 ] 3149 3175 ) 3150 3176 start &74 3151 end &40 3177 end &63 3178 es 0 3152 3179 sat 32 3153 3180 eat 32 … … 3166 3193 font "arial,8,0" 3167 3194 ) 3168 xt " 9000,35000,12200,36000"3195 xt "31000,42000,34200,43000" 3169 3196 st "RST_IN" 3170 blo " 9000,35800"3197 blo "31000,42800" 3171 3198 tm "WireNameMgr" 3172 3199 ) … … 3216 3243 ) 3217 3244 *95 (Wire 3218 uid 1 625,03245 uid 1981,0 3219 3246 shape (OrthoPolyLine 3220 uid 1 626,03247 uid 1982,0 3221 3248 va (VaSet 3222 3249 vasetType 3 3223 3250 ) 3224 xt " 10000,36000,37250,41000"3251 xt "8000,36000,37250,41000" 3225 3252 pts [ 3226 3253 "37250,41000" 3227 "10000,41000" 3228 "10000,36000" 3229 ] 3230 ) 3231 start &63 3232 end &93 3254 "8000,41000" 3255 "8000,36000" 3256 "13250,36000" 3257 ] 3258 ) 3259 start &62 3260 end &40 3233 3261 sat 32 3234 3262 eat 32 3235 stc 03236 3263 st 0 3237 3264 sf 1 3238 3265 si 0 3239 3266 tg (WTG 3240 uid 1 627,03267 uid 1983,0 3241 3268 ps "ConnStartEndStrategy" 3242 3269 stg "STSignalDisplayStrategy" 3243 3270 f (Text 3244 uid 1 628,03245 va (VaSet 3246 font "arial,8,0" 3247 ) 3248 xt "3 3250,40000,36450,41000"3249 st " RST_IN"3250 blo "3 3250,40800"3271 uid 1984,0 3272 va (VaSet 3273 font "arial,8,0" 3274 ) 3275 xt "35250,40000,36550,41000" 3276 st "rst" 3277 blo "35250,40800" 3251 3278 tm "WireNameMgr" 3252 3279 ) 3253 3280 ) 3254 on &7 33281 on &77 3255 3282 ) 3256 3283 ] … … 3284 3311 font "arial,8,0" 3285 3312 ) 3286 xt "0,1000,1 2300,7000"3313 xt "0,1000,14500,9000" 3287 3314 st "LIBRARY ieee; 3288 3315 USE ieee.std_logic_1164.all; … … 3290 3317 USE ieee.numeric_std.all; 3291 3318 LIBRARY UNISIM; 3292 --USE UNISIM.Vcomponents.all;" 3319 --USE UNISIM.Vcomponents.all; 3320 LIBRARY FACT_FAD_lib; 3321 USE FACT_FAD_lib.fad_definitions.all;" 3293 3322 tm "PackageList" 3294 3323 ) … … 3372 3401 ) 3373 3402 windowSize "0,0,1281,1024" 3374 viewArea "-54 15,-5866,75221,60634"3403 viewArea "-5400,-10460,75236,56040" 3375 3404 cachedDiagramExtent "0,-16000,73000,46000" 3376 3405 pageSetupInfo (PageSetupInfo … … 3384 3413 ) 3385 3414 hasePageBreakOrigin 1 3386 pageBreakOrigin "0, 0"3387 lastUid 1 655,03415 pageBreakOrigin "0,-49000" 3416 lastUid 1986,0 3388 3417 defaultCommentText (CommentText 3389 3418 shape (Rectangle … … 4415 4444 commonDM (CommonDM 4416 4445 ldm (LogicalDM 4417 suid 39,04446 suid 40,0 4418 4447 usingSuid 1 4419 4448 emptyRow *127 (LEmptyRow … … 4625 4654 uid 1631,0 4626 4655 ) 4656 *154 (LeafLogPort 4657 port (LogicalPort 4658 m 4 4659 decl (Decl 4660 n "rst" 4661 t "std_logic" 4662 eolc "--asynch in of DCM" 4663 posAdd 0 4664 o 15 4665 suid 40,0 4666 i "'0'" 4667 ) 4668 ) 4669 uid 1985,0 4670 ) 4627 4671 ] 4628 4672 ) … … 4632 4676 uid 67,0 4633 4677 optionalChildren [ 4634 *15 4(Sheet4678 *155 (Sheet 4635 4679 sheetRow (SheetRow 4636 4680 headerVa (MVa … … 4649 4693 font "Tahoma,10,0" 4650 4694 ) 4651 emptyMRCItem *15 5(MRCItem4695 emptyMRCItem *156 (MRCItem 4652 4696 litem &127 4653 pos 1 44697 pos 15 4654 4698 dimension 20 4655 4699 ) 4656 4700 uid 69,0 4657 4701 optionalChildren [ 4658 *15 6(MRCItem4702 *157 (MRCItem 4659 4703 litem &128 4660 4704 pos 0 … … 4662 4706 uid 70,0 4663 4707 ) 4664 *15 7(MRCItem4708 *158 (MRCItem 4665 4709 litem &129 4666 4710 pos 1 … … 4668 4712 uid 71,0 4669 4713 ) 4670 *15 8(MRCItem4714 *159 (MRCItem 4671 4715 litem &130 4672 4716 pos 2 … … 4675 4719 uid 72,0 4676 4720 ) 4677 *1 59(MRCItem4721 *160 (MRCItem 4678 4722 litem &140 4679 4723 pos 0 … … 4681 4725 uid 238,0 4682 4726 ) 4683 *16 0(MRCItem4727 *161 (MRCItem 4684 4728 litem &141 4685 4729 pos 1 … … 4687 4731 uid 240,0 4688 4732 ) 4689 *16 1(MRCItem4733 *162 (MRCItem 4690 4734 litem &142 4691 4735 pos 2 … … 4693 4737 uid 296,0 4694 4738 ) 4695 *16 2(MRCItem4739 *163 (MRCItem 4696 4740 litem &143 4697 4741 pos 8 … … 4699 4743 uid 615,0 4700 4744 ) 4701 *16 3(MRCItem4745 *164 (MRCItem 4702 4746 litem &144 4703 4747 pos 3 … … 4705 4749 uid 617,0 4706 4750 ) 4707 *16 4(MRCItem4751 *165 (MRCItem 4708 4752 litem &145 4709 4753 pos 4 … … 4711 4755 uid 619,0 4712 4756 ) 4713 *16 5(MRCItem4757 *166 (MRCItem 4714 4758 litem &146 4715 4759 pos 5 … … 4717 4761 uid 621,0 4718 4762 ) 4719 *16 6(MRCItem4763 *167 (MRCItem 4720 4764 litem &147 4721 4765 pos 6 … … 4723 4767 uid 625,0 4724 4768 ) 4725 *16 7(MRCItem4769 *168 (MRCItem 4726 4770 litem &148 4727 4771 pos 7 … … 4729 4773 uid 627,0 4730 4774 ) 4731 *16 8(MRCItem4775 *169 (MRCItem 4732 4776 litem &149 4733 4777 pos 9 … … 4735 4779 uid 1247,0 4736 4780 ) 4737 *1 69(MRCItem4781 *170 (MRCItem 4738 4782 litem &150 4739 4783 pos 10 … … 4741 4785 uid 1263,0 4742 4786 ) 4743 *17 0(MRCItem4787 *171 (MRCItem 4744 4788 litem &151 4745 4789 pos 11 … … 4747 4791 uid 1265,0 4748 4792 ) 4749 *17 1(MRCItem4793 *172 (MRCItem 4750 4794 litem &152 4751 4795 pos 12 … … 4753 4797 uid 1506,0 4754 4798 ) 4755 *17 2(MRCItem4799 *173 (MRCItem 4756 4800 litem &153 4757 4801 pos 13 4758 4802 dimension 20 4759 4803 uid 1632,0 4804 ) 4805 *174 (MRCItem 4806 litem &154 4807 pos 14 4808 dimension 20 4809 uid 1986,0 4760 4810 ) 4761 4811 ] … … 4770 4820 uid 73,0 4771 4821 optionalChildren [ 4772 *17 3(MRCItem4822 *175 (MRCItem 4773 4823 litem &131 4774 4824 pos 0 … … 4776 4826 uid 74,0 4777 4827 ) 4778 *17 4(MRCItem4828 *176 (MRCItem 4779 4829 litem &133 4780 4830 pos 1 … … 4782 4832 uid 75,0 4783 4833 ) 4784 *17 5(MRCItem4834 *177 (MRCItem 4785 4835 litem &134 4786 4836 pos 2 … … 4788 4838 uid 76,0 4789 4839 ) 4790 *17 6(MRCItem4840 *178 (MRCItem 4791 4841 litem &135 4792 4842 pos 3 … … 4794 4844 uid 77,0 4795 4845 ) 4796 *17 7(MRCItem4846 *179 (MRCItem 4797 4847 litem &136 4798 4848 pos 4 … … 4800 4850 uid 78,0 4801 4851 ) 4802 *1 78(MRCItem4852 *180 (MRCItem 4803 4853 litem &137 4804 4854 pos 5 … … 4806 4856 uid 79,0 4807 4857 ) 4808 *1 79(MRCItem4858 *181 (MRCItem 4809 4859 litem &138 4810 4860 pos 6 … … 4812 4862 uid 80,0 4813 4863 ) 4814 *18 0(MRCItem4864 *182 (MRCItem 4815 4865 litem &139 4816 4866 pos 7 … … 4833 4883 genericsCommonDM (CommonDM 4834 4884 ldm (LogicalDM 4835 emptyRow *18 1(LEmptyRow4885 emptyRow *183 (LEmptyRow 4836 4886 ) 4837 4887 uid 83,0 4838 4888 optionalChildren [ 4839 *18 2(RefLabelRowHdr4840 ) 4841 *18 3(TitleRowHdr4842 ) 4843 *18 4(FilterRowHdr4844 ) 4845 *18 5(RefLabelColHdr4889 *184 (RefLabelRowHdr 4890 ) 4891 *185 (TitleRowHdr 4892 ) 4893 *186 (FilterRowHdr 4894 ) 4895 *187 (RefLabelColHdr 4846 4896 tm "RefLabelColHdrMgr" 4847 4897 ) 4848 *18 6(RowExpandColHdr4898 *188 (RowExpandColHdr 4849 4899 tm "RowExpandColHdrMgr" 4850 4900 ) 4851 *18 7(GroupColHdr4901 *189 (GroupColHdr 4852 4902 tm "GroupColHdrMgr" 4853 4903 ) 4854 *1 88(NameColHdr4904 *190 (NameColHdr 4855 4905 tm "GenericNameColHdrMgr" 4856 4906 ) 4857 *1 89(TypeColHdr4907 *191 (TypeColHdr 4858 4908 tm "GenericTypeColHdrMgr" 4859 4909 ) 4860 *19 0(InitColHdr4910 *192 (InitColHdr 4861 4911 tm "GenericValueColHdrMgr" 4862 4912 ) 4863 *19 1(PragmaColHdr4913 *193 (PragmaColHdr 4864 4914 tm "GenericPragmaColHdrMgr" 4865 4915 ) 4866 *19 2(EolColHdr4916 *194 (EolColHdr 4867 4917 tm "GenericEolColHdrMgr" 4868 4918 ) … … 4874 4924 uid 95,0 4875 4925 optionalChildren [ 4876 *19 3(Sheet4926 *195 (Sheet 4877 4927 sheetRow (SheetRow 4878 4928 headerVa (MVa … … 4891 4941 font "Tahoma,10,0" 4892 4942 ) 4893 emptyMRCItem *19 4(MRCItem4894 litem &18 14943 emptyMRCItem *196 (MRCItem 4944 litem &183 4895 4945 pos 0 4896 4946 dimension 20 … … 4898 4948 uid 97,0 4899 4949 optionalChildren [ 4900 *19 5(MRCItem4901 litem &18 24950 *197 (MRCItem 4951 litem &184 4902 4952 pos 0 4903 4953 dimension 20 4904 4954 uid 98,0 4905 4955 ) 4906 *19 6(MRCItem4907 litem &18 34956 *198 (MRCItem 4957 litem &185 4908 4958 pos 1 4909 4959 dimension 23 4910 4960 uid 99,0 4911 4961 ) 4912 *19 7(MRCItem4913 litem &18 44962 *199 (MRCItem 4963 litem &186 4914 4964 pos 2 4915 4965 hidden 1 … … 4928 4978 uid 101,0 4929 4979 optionalChildren [ 4930 * 198(MRCItem4931 litem &18 54980 *200 (MRCItem 4981 litem &187 4932 4982 pos 0 4933 4983 dimension 20 4934 4984 uid 102,0 4935 4985 ) 4936 * 199(MRCItem4937 litem &18 74986 *201 (MRCItem 4987 litem &189 4938 4988 pos 1 4939 4989 dimension 50 4940 4990 uid 103,0 4941 4991 ) 4942 *20 0(MRCItem4943 litem &1 884992 *202 (MRCItem 4993 litem &190 4944 4994 pos 2 4945 4995 dimension 100 4946 4996 uid 104,0 4947 4997 ) 4948 *20 1(MRCItem4949 litem &1 894998 *203 (MRCItem 4999 litem &191 4950 5000 pos 3 4951 5001 dimension 100 4952 5002 uid 105,0 4953 5003 ) 4954 *20 2(MRCItem4955 litem &19 05004 *204 (MRCItem 5005 litem &192 4956 5006 pos 4 4957 5007 dimension 50 4958 5008 uid 106,0 4959 5009 ) 4960 *20 3(MRCItem4961 litem &19 15010 *205 (MRCItem 5011 litem &193 4962 5012 pos 5 4963 5013 dimension 50 4964 5014 uid 107,0 4965 5015 ) 4966 *20 4(MRCItem4967 litem &19 25016 *206 (MRCItem 5017 litem &194 4968 5018 pos 6 4969 5019 dimension 80 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak
r10129 r10155 15 15 unitName "numeric_std" 16 16 ) 17 (DmPackageRef 18 library "FACT_FAD_lib" 19 unitName "fad_definitions" 20 ) 17 21 ] 18 22 instances [ … … 57 61 "ieee" 58 62 "UNISIM" 63 "FACT_FAD_lib" 59 64 ] 60 65 ) … … 107 112 (vvPair 108 113 variable "date" 109 value " 04.02.2011"114 value "12.02.2011" 110 115 ) 111 116 (vvPair 112 117 variable "day" 113 value " Fr"118 value "Sa" 114 119 ) 115 120 (vvPair 116 121 variable "day_long" 117 value " Freitag"122 value "Samstag" 118 123 ) 119 124 (vvPair 120 125 variable "dd" 121 value " 04"126 value "12" 122 127 ) 123 128 (vvPair … … 255 260 (vvPair 256 261 variable "time" 257 value "1 2:51:51"262 value "13:14:23" 258 263 ) 259 264 (vvPair … … 760 765 font "Courier New,8,0" 761 766 ) 762 xt "22000,6800,35000,7600" 763 st "CLK_50 : std_logic" 767 xt "11000,-9200,24000,-8400" 768 st "CLK_50 : std_logic 769 " 764 770 ) 765 771 ) … … 777 783 font "Courier New,8,0" 778 784 ) 779 xt "22000,5200,35000,6000" 780 st "CLK_25 : std_logic" 785 xt "11000,-10800,24000,-10000" 786 st "CLK_25 : std_logic 787 " 781 788 ) 782 789 ) … … 794 801 font "Courier New,8,0" 795 802 ) 796 xt "22000,2000,35000,2800" 797 st "CLK : std_logic" 803 xt "11000,-14000,24000,-13200" 804 st "CLK : std_logic 805 " 798 806 ) 799 807 ) … … 1562 1570 font "Courier New,8,0" 1563 1571 ) 1564 xt "22000,9400,38500,10200" 1565 st "SIGNAL CLK0_OUT : std_logic" 1572 xt "11000,-6600,27500,-5800" 1573 st "SIGNAL CLK0_OUT : std_logic 1574 " 1566 1575 ) 1567 1576 ) … … 1579 1588 font "Courier New,8,0" 1580 1589 ) 1581 xt "22000,11000,38500,11800" 1582 st "SIGNAL PSCLK_IN : std_logic" 1590 xt "11000,-5000,27500,-4200" 1591 st "SIGNAL PSCLK_IN : std_logic 1592 " 1583 1593 ) 1584 1594 ) … … 1596 1606 font "Courier New,8,0" 1597 1607 ) 1598 xt "22000,12600,38500,13400" 1599 st "SIGNAL PSEN_IN : std_logic" 1608 xt "11000,-3400,27500,-2600" 1609 st "SIGNAL PSEN_IN : std_logic 1610 " 1600 1611 ) 1601 1612 ) … … 1613 1624 font "Courier New,8,0" 1614 1625 ) 1615 xt "22000,13400,38500,14200" 1616 st "SIGNAL PSINCDEC_IN : std_logic" 1626 xt "11000,-2600,27500,-1800" 1627 st "SIGNAL PSINCDEC_IN : std_logic 1628 " 1617 1629 ) 1618 1630 ) … … 1630 1642 font "Courier New,8,0" 1631 1643 ) 1632 xt "22000,11800,38500,12600" 1633 st "SIGNAL PSDONE_OUT : std_logic" 1644 xt "11000,-4200,27500,-3400" 1645 st "SIGNAL PSDONE_OUT : std_logic 1646 " 1634 1647 ) 1635 1648 ) … … 1647 1660 font "Courier New,8,0" 1648 1661 ) 1649 xt "22000,10200,38500,11000" 1650 st "SIGNAL LOCKED_OUT : std_logic" 1662 xt "11000,-5800,27500,-5000" 1663 st "SIGNAL LOCKED_OUT : std_logic 1664 " 1651 1665 ) 1652 1666 ) … … 2290 2304 font "Courier New,8,0" 2291 2305 ) 2292 xt "22000,6000,35000,6800" 2293 st "CLK_25_PS : std_logic" 2306 xt "11000,-10000,24000,-9200" 2307 st "CLK_25_PS : std_logic 2308 " 2294 2309 ) 2295 2310 ) … … 2353 2368 font "Courier New,8,0" 2354 2369 ) 2355 xt "22000,4400,35000,5200" 2356 st "do_shift : std_logic" 2370 xt "11000,-11600,24000,-10800" 2371 st "do_shift : std_logic 2372 " 2357 2373 ) 2358 2374 ) … … 2416 2432 font "Courier New,8,0" 2417 2433 ) 2418 xt "22000,3600,35000,4400" 2419 st "direction : std_logic" 2434 xt "11000,-12400,24000,-11600" 2435 st "direction : std_logic 2436 " 2420 2437 ) 2421 2438 ) … … 2433 2450 font "Courier New,8,0" 2434 2451 ) 2435 xt "22000,2800,35000,3600" 2436 st "RST_IN : std_logic" 2452 xt "11000,-13200,24000,-12400" 2453 st "RST_IN : std_logic 2454 " 2437 2455 ) 2438 2456 ) … … 2500 2518 font "Courier New,8,0" 2501 2519 ) 2502 xt "22000,7600,54500,8400" 2503 st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 2520 xt "11000,-8400,43500,-7600" 2521 st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 2522 " 2504 2523 ) 2505 2524 ) … … 3284 3303 font "arial,8,0" 3285 3304 ) 3286 xt "0,1000,1 2300,7000"3305 xt "0,1000,14500,9000" 3287 3306 st "LIBRARY ieee; 3288 3307 USE ieee.std_logic_1164.all; … … 3290 3309 USE ieee.numeric_std.all; 3291 3310 LIBRARY UNISIM; 3292 --USE UNISIM.Vcomponents.all;" 3311 --USE UNISIM.Vcomponents.all; 3312 LIBRARY FACT_FAD_lib; 3313 USE FACT_FAD_lib.fad_definitions.all;" 3293 3314 tm "PackageList" 3294 3315 ) … … 3372 3393 ) 3373 3394 windowSize "0,0,1281,1024" 3374 viewArea "- 28103,-9825,97891,94082"3375 cachedDiagramExtent "0, 0,73000,46000"3395 viewArea "-5400,-10460,75236,56040" 3396 cachedDiagramExtent "0,-16000,73000,46000" 3376 3397 pageSetupInfo (PageSetupInfo 3377 3398 ptrCmd "" … … 3384 3405 ) 3385 3406 hasePageBreakOrigin 1 3386 pageBreakOrigin "0, 0"3387 lastUid 1 655,03407 pageBreakOrigin "0,-49000" 3408 lastUid 1830,0 3388 3409 defaultCommentText (CommentText 3389 3410 shape (Rectangle … … 4352 4373 font "arial,8,1" 4353 4374 ) 4354 xt " 20000,0,25400,1000"4375 xt "9000,-16000,14400,-15000" 4355 4376 st "Declarations" 4356 blo " 20000,800"4377 blo "9000,-15200" 4357 4378 ) 4358 4379 portLabel (Text … … 4361 4382 font "arial,8,1" 4362 4383 ) 4363 xt " 20000,1000,22700,2000"4384 xt "9000,-15000,11700,-14000" 4364 4385 st "Ports:" 4365 blo " 20000,1800"4386 blo "9000,-14200" 4366 4387 ) 4367 4388 preUserLabel (Text … … 4371 4392 font "arial,8,1" 4372 4393 ) 4373 xt " 20000,0,23800,1000"4394 xt "9000,-16000,12800,-15000" 4374 4395 st "Pre User:" 4375 blo " 20000,800"4396 blo "9000,-15200" 4376 4397 ) 4377 4398 preUserText (MLText … … 4381 4402 font "Courier New,8,0" 4382 4403 ) 4383 xt " 20000,0,20000,0"4404 xt "9000,-16000,9000,-16000" 4384 4405 tm "BdDeclarativeTextMgr" 4385 4406 ) … … 4389 4410 font "arial,8,1" 4390 4411 ) 4391 xt " 20000,8400,27100,9400"4412 xt "9000,-7600,16100,-6600" 4392 4413 st "Diagram Signals:" 4393 blo " 20000,9200"4414 blo "9000,-6800" 4394 4415 ) 4395 4416 postUserLabel (Text … … 4399 4420 font "arial,8,1" 4400 4421 ) 4401 xt " 20000,0,24700,1000"4422 xt "9000,-16000,13700,-15000" 4402 4423 st "Post User:" 4403 blo " 20000,800"4424 blo "9000,-15200" 4404 4425 ) 4405 4426 postUserText (MLText … … 4409 4430 font "Courier New,8,0" 4410 4431 ) 4411 xt " 20000,0,20000,0"4432 xt "9000,-16000,9000,-16000" 4412 4433 tm "BdDeclarativeTextMgr" 4413 4434 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb
r10129 r10155 523 523 (vvPair 524 524 variable "date" 525 value " 04.02.2011"525 value "12.02.2011" 526 526 ) 527 527 (vvPair 528 528 variable "day" 529 value " Fr"529 value "Sa" 530 530 ) 531 531 (vvPair 532 532 variable "day_long" 533 value " Freitag"533 value "Samstag" 534 534 ) 535 535 (vvPair 536 536 variable "dd" 537 value " 04"537 value "12" 538 538 ) 539 539 (vvPair … … 671 671 (vvPair 672 672 variable "time" 673 value "1 2:52:25"673 value "13:16:51" 674 674 ) 675 675 (vvPair … … 1752 1752 ) 1753 1753 ) 1754 lastUid 1 044,01754 lastUid 1113,0 1755 1755 okToSyncOnLoad 1 1756 1756 OkToSyncGenericsOnLoad 1 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb
r10121 r10155 29 29 ) 30 30 version "24.1" 31 appVersion "2009. 1 (Build 12)"31 appVersion "2009.2 (Build 10)" 32 32 model (Symbol 33 33 commonDM (CommonDM 34 34 ldm (LogicalDM 35 35 ordering 1 36 suid 63,036 suid 75,0 37 37 usingSuid 1 38 38 emptyRow *1 (LEmptyRow … … 153 153 t "std_logic_vector" 154 154 b "(3 downto 0)" 155 prec "-- 156 157 -- EVT HEADER - part 4" 155 158 preAdd 0 156 159 posAdd 0 157 o 24160 o 31 158 161 suid 9,0 159 162 ) … … 164 167 port (LogicalPort 165 168 decl (Decl 166 n "trigger _id"167 t "std_logic _vector"168 b "(47 downto 0)"169 n "trigger" 170 t "std_logic" 171 prec "--" 169 172 preAdd 0 170 173 posAdd 0 171 o 26172 suid 1 0,0173 ) 174 ) 175 uid 12 7,0174 o 38 175 suid 11,0 176 ) 177 ) 178 uid 129,0 176 179 ) 177 180 *21 (LogPort 178 port (LogicalPort179 decl (Decl180 n "trigger"181 t "std_logic"182 preAdd 0183 posAdd 0184 o 27185 suid 11,0186 )187 )188 uid 129,0189 )190 *22 (LogPort191 181 port (LogicalPort 192 182 decl (Decl … … 194 184 t "std_logic_vector" 195 185 b "(1 downto 0)" 196 o 25 186 posAdd 0 187 o 32 197 188 suid 12,0 198 189 ) … … 200 191 uid 290,0 201 192 ) 202 *2 3(LogPort193 *22 (LogPort 203 194 port (LogicalPort 204 195 decl (Decl … … 211 202 uid 421,0 212 203 ) 213 *2 4(LogPort204 *23 (LogPort 214 205 port (LogicalPort 215 206 m 1 … … 225 216 uid 423,0 226 217 ) 227 *2 5(LogPort218 *24 (LogPort 228 219 port (LogicalPort 229 220 decl (Decl … … 236 227 uid 425,0 237 228 ) 238 *2 6(LogPort229 *25 (LogPort 239 230 port (LogicalPort 240 231 decl (Decl … … 247 238 uid 478,0 248 239 ) 249 *2 7(LogPort240 *26 (LogPort 250 241 port (LogicalPort 251 242 decl (Decl … … 253 244 t "std_logic_vector" 254 245 b "(15 downto 0)" 246 prec "-- EVT HEADER - part 1" 247 preAdd 0 255 248 o 23 256 249 suid 20,0 … … 259 252 uid 531,0 260 253 ) 261 *2 8(LogPort254 *27 (LogPort 262 255 port (LogicalPort 263 256 m 1 … … 265 258 n "adc_oeb" 266 259 t "std_logic" 267 o 31260 o 42 268 261 suid 23,0 269 262 i "'1'" … … 272 265 uid 649,0 273 266 ) 274 *2 9(LogPort267 *28 (LogPort 275 268 port (LogicalPort 276 269 m 1 … … 280 273 b "(3 downto 0)" 281 274 posAdd 0 282 o 34275 o 45 283 276 suid 25,0 284 277 i "(others => '0')" … … 287 280 uid 701,0 288 281 ) 289 * 30(LogPort282 *29 (LogPort 290 283 port (LogicalPort 291 284 m 1 … … 296 289 preAdd 0 297 290 posAdd 0 298 o 37291 o 48 299 292 suid 26,0 300 293 i "'0'" … … 303 296 uid 703,0 304 297 ) 305 *3 1(LogPort298 *30 (LogPort 306 299 port (LogicalPort 307 300 m 1 … … 311 304 prec "-- --" 312 305 preAdd 0 313 o 38306 o 49 314 307 suid 33,0 315 308 i "'0'" … … 318 311 uid 816,0 319 312 ) 313 *31 (LogPort 314 port (LogicalPort 315 decl (Decl 316 n "drs_read_s_cell_ready" 317 t "std_logic" 318 o 54 319 suid 34,0 320 ) 321 ) 322 uid 818,0 323 ) 320 324 *32 (LogPort 321 port (LogicalPort322 decl (Decl323 n "drs_read_s_cell_ready"324 t "std_logic"325 o 43326 suid 34,0327 )328 )329 uid 818,0330 )331 *33 (LogPort332 325 port (LogicalPort 333 326 decl (Decl 334 327 n "drs_s_cell_array" 335 328 t "drs_s_cell_array_type" 336 o 44329 o 55 337 330 suid 35,0 338 331 ) … … 340 333 uid 820,0 341 334 ) 342 *3 4(LogPort335 *33 (LogPort 343 336 port (LogicalPort 344 337 decl (Decl 345 338 n "adc_data_array" 346 339 t "adc_data_array_type" 347 o 30340 o 41 348 341 suid 37,0 349 342 ) … … 351 344 uid 903,0 352 345 ) 353 *3 5(LogPort346 *34 (LogPort 354 347 port (LogicalPort 355 348 decl (Decl … … 362 355 uid 968,0 363 356 ) 364 *3 6(LogPort357 *35 (LogPort 365 358 port (LogicalPort 366 359 m 1 … … 378 371 uid 970,0 379 372 ) 380 *3 7(LogPort373 *36 (LogPort 381 374 port (LogicalPort 382 375 decl (Decl … … 389 382 uid 1058,0 390 383 ) 391 *3 8(LogPort384 *37 (LogPort 392 385 port (LogicalPort 393 386 decl (Decl … … 400 393 uid 1060,0 401 394 ) 402 *3 9(LogPort395 *38 (LogPort 403 396 port (LogicalPort 404 397 decl (Decl … … 411 404 uid 1095,0 412 405 ) 413 * 40(LogPort406 *39 (LogPort 414 407 port (LogicalPort 415 408 decl (Decl … … 422 415 uid 1097,0 423 416 ) 424 *4 1(LogPort417 *40 (LogPort 425 418 port (LogicalPort 426 419 m 1 … … 438 431 uid 1132,0 439 432 ) 440 *4 2(LogPort433 *41 (LogPort 441 434 port (LogicalPort 442 435 m 1 … … 453 446 uid 1134,0 454 447 ) 455 *4 3(LogPort448 *42 (LogPort 456 449 port (LogicalPort 457 450 m 1 … … 459 452 n "config_started" 460 453 t "std_logic" 461 o 29454 o 40 462 455 suid 48,0 463 456 i "'0'" … … 466 459 uid 1169,0 467 460 ) 468 *4 4(LogPort461 *43 (LogPort 469 462 port (LogicalPort 470 463 decl (Decl … … 473 466 prec "-- s_trigger : in std_logic;" 474 467 preAdd 0 475 o 28468 o 39 476 469 suid 49,0 477 470 ) … … 479 472 uid 1171,0 480 473 ) 481 *4 5(LogPort474 *44 (LogPort 482 475 port (LogicalPort 483 476 decl (Decl … … 490 483 uid 1211,0 491 484 ) 492 *4 6(LogPort485 *45 (LogPort 493 486 port (LogicalPort 494 487 decl (Decl … … 501 494 uid 1213,0 502 495 ) 503 *4 7(LogPort496 *46 (LogPort 504 497 port (LogicalPort 505 498 decl (Decl … … 512 505 uid 1215,0 513 506 ) 514 *4 8(LogPort507 *47 (LogPort 515 508 port (LogicalPort 516 509 decl (Decl 517 510 n "dac_array" 518 511 t "dac_array_type" 512 posAdd 0 519 513 o 22 520 514 suid 53,0 … … 523 517 uid 1245,0 524 518 ) 525 *4 9(LogPort519 *48 (LogPort 526 520 port (LogicalPort 527 521 m 1 … … 529 523 n "adc_clk_en" 530 524 t "std_logic" 531 o 32525 o 43 532 526 suid 54,0 533 527 i "'0'" … … 536 530 uid 1400,0 537 531 ) 538 * 50(LogPort532 *49 (LogPort 539 533 port (LogicalPort 540 534 decl (Decl … … 542 536 t "std_logic_vector" 543 537 b "(3 downto 0)" 544 o 33538 o 44 545 539 suid 55,0 546 540 ) … … 548 542 uid 1432,0 549 543 ) 550 *5 1(LogPort544 *50 (LogPort 551 545 port (LogicalPort 552 546 m 1 … … 555 549 t "std_logic_vector" 556 550 b "(7 downto 0)" 557 o 41551 o 52 558 552 suid 56,0 559 553 i "(others => '0')" … … 562 556 uid 1484,0 563 557 ) 564 *5 2(LogPort558 *51 (LogPort 565 559 port (LogicalPort 566 560 m 1 … … 568 562 n "drs_srin_write_8b" 569 563 t "std_logic" 570 o 39564 o 50 571 565 suid 57,0 572 566 i "'0'" … … 575 569 uid 1486,0 576 570 ) 571 *52 (LogPort 572 port (LogicalPort 573 decl (Decl 574 n "drs_srin_write_ack" 575 t "std_logic" 576 o 51 577 suid 58,0 578 ) 579 ) 580 uid 1488,0 581 ) 577 582 *53 (LogPort 578 583 port (LogicalPort 579 584 decl (Decl 580 n "drs_srin_write_ ack"581 t "std_logic" 582 o 40583 suid 5 8,0584 ) 585 ) 586 uid 14 88,0585 n "drs_srin_write_ready" 586 t "std_logic" 587 o 53 588 suid 59,0 589 ) 590 ) 591 uid 1490,0 587 592 ) 588 593 *54 (LogPort 589 port (LogicalPort590 decl (Decl591 n "drs_srin_write_ready"592 t "std_logic"593 o 42594 suid 59,0595 )596 )597 uid 1490,0598 )599 *55 (LogPort600 594 port (LogicalPort 601 595 decl (Decl … … 611 605 uid 1492,0 612 606 ) 613 *5 6(LogPort607 *55 (LogPort 614 608 port (LogicalPort 615 609 m 1 … … 617 611 n "drs_readout_started" 618 612 t "std_logic" 619 o 45613 o 56 620 614 suid 61,0 621 615 i "'0'" … … 624 618 uid 1524,0 625 619 ) 626 *5 7(LogPort620 *56 (LogPort 627 621 port (LogicalPort 628 622 m 1 … … 634 628 preAdd 0 635 629 posAdd 0 636 o 35630 o 46 637 631 suid 62,0 638 632 i "'0'" … … 641 635 uid 1556,0 642 636 ) 637 *57 (LogPort 638 port (LogicalPort 639 decl (Decl 640 n "drs_readout_ready_ack" 641 t "std_logic" 642 o 47 643 suid 63,0 644 ) 645 ) 646 uid 1588,0 647 ) 643 648 *58 (LogPort 644 649 port (LogicalPort 645 650 decl (Decl 646 n "drs_readout_ready_ack" 647 t "std_logic" 651 n "pll_lock" 652 t "std_logic_vector" 653 b "( 3 downto 0)" 654 posAdd 0 655 o 24 656 suid 64,0 657 ) 658 ) 659 uid 1620,0 660 ) 661 *59 (LogPort 662 port (LogicalPort 663 decl (Decl 664 n "fad_event_counter" 665 t "std_logic_vector" 666 b "(31 downto 0)" 667 prec "-- 668 669 -- EVT HEADER - part 3" 670 preAdd 0 671 o 27 672 suid 65,0 673 ) 674 ) 675 uid 1652,0 676 ) 677 *60 (LogPort 678 port (LogicalPort 679 decl (Decl 680 n "refclk_counter" 681 t "std_logic_vector" 682 b "(11 downto 0)" 683 o 28 684 suid 66,0 685 ) 686 ) 687 uid 1694,0 688 ) 689 *61 (LogPort 690 port (LogicalPort 691 decl (Decl 692 n "refclk_too_high" 693 t "std_logic" 694 o 29 695 suid 67,0 696 ) 697 ) 698 uid 1696,0 699 ) 700 *62 (LogPort 701 port (LogicalPort 702 decl (Decl 703 n "refclk_too_low" 704 t "std_logic" 705 posAdd 0 706 o 30 707 suid 68,0 708 ) 709 ) 710 uid 1698,0 711 ) 712 *63 (LogPort 713 port (LogicalPort 714 decl (Decl 715 n "FTM_RS485_ready" 716 t "std_logic" 717 prec "-- 718 719 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 720 -- during EVT header wrinting, this field is left out ... and only written into event header, 721 -- when the DRS chip were read out already." 722 preAdd 0 723 o 25 724 suid 69,0 725 ) 726 ) 727 uid 1735,0 728 ) 729 *64 (LogPort 730 port (LogicalPort 731 decl (Decl 732 n "FTM_trigger_info" 733 t "std_logic_vector" 734 b "(55 downto 0)" 735 eolc "--7 byte" 736 posAdd 0 737 o 26 738 suid 70,0 739 ) 740 ) 741 uid 1737,0 742 ) 743 *65 (LogPort 744 port (LogicalPort 745 decl (Decl 746 n "DCM_PS_status" 747 t "std_logic_vector" 748 b "(7 downto 0)" 749 o 33 750 suid 71,0 751 ) 752 ) 753 uid 1779,0 754 ) 755 *66 (LogPort 756 port (LogicalPort 757 decl (Decl 758 n "TRG_GEN_div" 759 t "std_logic_vector" 760 b "(15 downto 0)" 761 posAdd 0 762 o 35 763 suid 72,0 764 ) 765 ) 766 uid 1781,0 767 ) 768 *67 (LogPort 769 port (LogicalPort 770 decl (Decl 771 n "TRG_GEN_no" 772 t "std_logic_vector" 773 b "(15 downto 0)" 774 o 34 775 suid 73,0 776 ) 777 ) 778 uid 1783,0 779 ) 780 *68 (LogPort 781 port (LogicalPort 782 decl (Decl 783 n "dna" 784 t "std_logic_vector" 785 b "(63 downto 0)" 786 prec "-- 787 788 -- EVT HEADER - part 5" 789 preAdd 0 790 posAdd 0 648 791 o 36 649 suid 63,0 650 ) 651 ) 652 uid 1588,0 792 suid 74,0 793 ) 794 ) 795 uid 1815,0 796 ) 797 *69 (LogPort 798 port (LogicalPort 799 decl (Decl 800 n "timer_value" 801 t "std_logic_vector" 802 b "(31 downto 0)" 803 prec "-- 804 805 -- EVT HEADER - part 6" 806 eolc "-- time in units of 100us" 807 preAdd 0 808 posAdd 0 809 o 37 810 suid 75,0 811 ) 812 ) 813 uid 1847,0 653 814 ) 654 815 ] … … 659 820 uid 149,0 660 821 optionalChildren [ 661 * 59(Sheet822 *70 (Sheet 662 823 sheetRow (SheetRow 663 824 headerVa (MVa … … 676 837 font "Tahoma,10,0" 677 838 ) 678 emptyMRCItem * 60(MRCItem839 emptyMRCItem *71 (MRCItem 679 840 litem &1 680 841 pos 3 … … 683 844 uid 151,0 684 845 optionalChildren [ 685 * 61(MRCItem846 *72 (MRCItem 686 847 litem &2 687 848 pos 0 … … 689 850 uid 152,0 690 851 ) 691 * 62(MRCItem852 *73 (MRCItem 692 853 litem &3 693 854 pos 1 … … 695 856 uid 153,0 696 857 ) 697 * 63(MRCItem858 *74 (MRCItem 698 859 litem &4 699 860 pos 2 … … 702 863 uid 154,0 703 864 ) 704 * 64(MRCItem865 *75 (MRCItem 705 866 litem &14 706 867 pos 0 … … 708 869 uid 110,0 709 870 ) 710 * 65(MRCItem871 *76 (MRCItem 711 872 litem &15 712 873 pos 1 … … 714 875 uid 112,0 715 876 ) 716 * 66(MRCItem877 *77 (MRCItem 717 878 litem &16 718 879 pos 2 … … 720 881 uid 114,0 721 882 ) 722 * 67(MRCItem883 *78 (MRCItem 723 884 litem &17 724 885 pos 3 … … 726 887 uid 120,0 727 888 ) 728 * 68(MRCItem889 *79 (MRCItem 729 890 litem &18 730 891 pos 4 … … 732 893 uid 122,0 733 894 ) 734 * 69(MRCItem895 *80 (MRCItem 735 896 litem &19 736 897 pos 5 … … 738 899 uid 126,0 739 900 ) 740 * 70(MRCItem901 *81 (MRCItem 741 902 litem &20 742 903 pos 6 743 904 dimension 20 744 uid 1 28,0745 ) 746 * 71(MRCItem905 uid 130,0 906 ) 907 *82 (MRCItem 747 908 litem &21 748 909 pos 7 749 910 dimension 20 750 uid 130,0751 ) 752 * 72(MRCItem911 uid 291,0 912 ) 913 *83 (MRCItem 753 914 litem &22 754 915 pos 8 755 916 dimension 20 756 uid 291,0757 ) 758 * 73(MRCItem917 uid 422,0 918 ) 919 *84 (MRCItem 759 920 litem &23 760 921 pos 9 761 922 dimension 20 762 uid 42 2,0763 ) 764 * 74(MRCItem923 uid 424,0 924 ) 925 *85 (MRCItem 765 926 litem &24 766 927 pos 10 767 928 dimension 20 768 uid 42 4,0769 ) 770 * 75(MRCItem929 uid 426,0 930 ) 931 *86 (MRCItem 771 932 litem &25 772 933 pos 11 773 934 dimension 20 774 uid 4 26,0775 ) 776 * 76(MRCItem935 uid 479,0 936 ) 937 *87 (MRCItem 777 938 litem &26 778 939 pos 12 779 940 dimension 20 780 uid 479,0781 ) 782 * 77(MRCItem941 uid 532,0 942 ) 943 *88 (MRCItem 783 944 litem &27 784 945 pos 13 785 946 dimension 20 786 uid 532,0787 ) 788 * 78(MRCItem947 uid 650,0 948 ) 949 *89 (MRCItem 789 950 litem &28 790 951 pos 14 791 952 dimension 20 792 uid 650,0793 ) 794 * 79(MRCItem953 uid 702,0 954 ) 955 *90 (MRCItem 795 956 litem &29 796 957 pos 15 797 958 dimension 20 798 uid 70 2,0799 ) 800 * 80(MRCItem959 uid 704,0 960 ) 961 *91 (MRCItem 801 962 litem &30 802 963 pos 16 803 964 dimension 20 804 uid 704,0805 ) 806 * 81(MRCItem965 uid 817,0 966 ) 967 *92 (MRCItem 807 968 litem &31 808 969 pos 17 809 970 dimension 20 810 uid 81 7,0811 ) 812 * 82(MRCItem971 uid 819,0 972 ) 973 *93 (MRCItem 813 974 litem &32 814 975 pos 18 815 976 dimension 20 816 uid 8 19,0817 ) 818 * 83(MRCItem977 uid 821,0 978 ) 979 *94 (MRCItem 819 980 litem &33 820 981 pos 19 821 982 dimension 20 822 uid 821,0823 ) 824 * 84(MRCItem983 uid 904,0 984 ) 985 *95 (MRCItem 825 986 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(MRCItem 915 1076 litem &49 916 1077 pos 35 917 1078 dimension 20 918 uid 14 01,0919 ) 920 *1 00(MRCItem1079 uid 1433,0 1080 ) 1081 *111 (MRCItem 921 1082 litem &50 922 1083 pos 36 923 1084 dimension 20 924 uid 14 33,0925 ) 926 *1 01(MRCItem1085 uid 1485,0 1086 ) 1087 *112 (MRCItem 927 1088 litem &51 928 1089 pos 37 929 1090 dimension 20 930 uid 148 5,0931 ) 932 *1 02(MRCItem1091 uid 1487,0 1092 ) 1093 *113 (MRCItem 933 1094 litem &52 934 1095 pos 38 935 1096 dimension 20 936 uid 148 7,0937 ) 938 *1 03(MRCItem1097 uid 1489,0 1098 ) 1099 *114 (MRCItem 939 1100 litem &53 940 1101 pos 39 941 1102 dimension 20 942 uid 14 89,0943 ) 944 *1 04(MRCItem1103 uid 1491,0 1104 ) 1105 *115 (MRCItem 945 1106 litem &54 946 1107 pos 40 947 1108 dimension 20 948 uid 149 1,0949 ) 950 *1 05(MRCItem1109 uid 1493,0 1110 ) 1111 *116 (MRCItem 951 1112 litem &55 952 1113 pos 41 953 1114 dimension 20 954 uid 1 493,0955 ) 956 *1 06(MRCItem1115 uid 1525,0 1116 ) 1117 *117 (MRCItem 957 1118 litem &56 958 1119 pos 42 959 1120 dimension 20 960 uid 15 25,0961 ) 962 *1 07(MRCItem1121 uid 1557,0 1122 ) 1123 *118 (MRCItem 963 1124 litem &57 964 1125 pos 43 965 1126 dimension 20 966 uid 15 57,0967 ) 968 *1 08(MRCItem1127 uid 1589,0 1128 ) 1129 *119 (MRCItem 969 1130 litem &58 970 1131 pos 44 971 1132 dimension 20 972 uid 1589,0 1133 uid 1621,0 1134 ) 1135 *120 (MRCItem 1136 litem &59 1137 pos 45 1138 dimension 20 1139 uid 1653,0 1140 ) 1141 *121 (MRCItem 1142 litem &60 1143 pos 46 1144 dimension 20 1145 uid 1695,0 1146 ) 1147 *122 (MRCItem 1148 litem &61 1149 pos 47 1150 dimension 20 1151 uid 1697,0 1152 ) 1153 *123 (MRCItem 1154 litem &62 1155 pos 48 1156 dimension 20 1157 uid 1699,0 1158 ) 1159 *124 (MRCItem 1160 litem &63 1161 pos 49 1162 dimension 20 1163 uid 1736,0 1164 ) 1165 *125 (MRCItem 1166 litem &64 1167 pos 50 1168 dimension 20 1169 uid 1738,0 1170 ) 1171 *126 (MRCItem 1172 litem &65 1173 pos 51 1174 dimension 20 1175 uid 1780,0 1176 ) 1177 *127 (MRCItem 1178 litem &66 1179 pos 52 1180 dimension 20 1181 uid 1782,0 1182 ) 1183 *128 (MRCItem 1184 litem &67 1185 pos 53 1186 dimension 20 1187 uid 1784,0 1188 ) 1189 *129 (MRCItem 1190 litem &68 1191 pos 54 1192 dimension 20 1193 uid 1816,0 1194 ) 1195 *130 (MRCItem 1196 litem &69 1197 pos 55 1198 dimension 20 1199 uid 1848,0 973 1200 ) 974 1201 ] … … 983 1210 uid 155,0 984 1211 optionalChildren [ 985 *1 09(MRCItem1212 *131 (MRCItem 986 1213 litem &5 987 1214 pos 0 … … 989 1216 uid 156,0 990 1217 ) 991 *1 10(MRCItem1218 *132 (MRCItem 992 1219 litem &7 993 1220 pos 1 … … 995 1222 uid 157,0 996 1223 ) 997 *1 11(MRCItem1224 *133 (MRCItem 998 1225 litem &8 999 1226 pos 2 … … 1001 1228 uid 158,0 1002 1229 ) 1003 *1 12(MRCItem1230 *134 (MRCItem 1004 1231 litem &9 1005 1232 pos 3 … … 1007 1234 uid 159,0 1008 1235 ) 1009 *1 13(MRCItem1236 *135 (MRCItem 1010 1237 litem &10 1011 1238 pos 4 … … 1013 1240 uid 160,0 1014 1241 ) 1015 *1 14(MRCItem1242 *136 (MRCItem 1016 1243 litem &11 1017 1244 pos 5 … … 1019 1246 uid 161,0 1020 1247 ) 1021 *1 15(MRCItem1248 *137 (MRCItem 1022 1249 litem &12 1023 1250 pos 6 … … 1025 1252 uid 162,0 1026 1253 ) 1027 *1 16(MRCItem1254 *138 (MRCItem 1028 1255 litem &13 1029 1256 pos 7 … … 1046 1273 genericsCommonDM (CommonDM 1047 1274 ldm (LogicalDM 1048 emptyRow *1 17(LEmptyRow1275 emptyRow *139 (LEmptyRow 1049 1276 ) 1050 1277 uid 165,0 1051 1278 optionalChildren [ 1052 *1 18(RefLabelRowHdr1053 ) 1054 *1 19(TitleRowHdr1055 ) 1056 *1 20(FilterRowHdr1057 ) 1058 *1 21(RefLabelColHdr1279 *140 (RefLabelRowHdr 1280 ) 1281 *141 (TitleRowHdr 1282 ) 1283 *142 (FilterRowHdr 1284 ) 1285 *143 (RefLabelColHdr 1059 1286 tm "RefLabelColHdrMgr" 1060 1287 ) 1061 *1 22(RowExpandColHdr1288 *144 (RowExpandColHdr 1062 1289 tm "RowExpandColHdrMgr" 1063 1290 ) 1064 *1 23(GroupColHdr1291 *145 (GroupColHdr 1065 1292 tm "GroupColHdrMgr" 1066 1293 ) 1067 *1 24(NameColHdr1294 *146 (NameColHdr 1068 1295 tm "GenericNameColHdrMgr" 1069 1296 ) 1070 *1 25(TypeColHdr1297 *147 (TypeColHdr 1071 1298 tm "GenericTypeColHdrMgr" 1072 1299 ) 1073 *1 26(InitColHdr1300 *148 (InitColHdr 1074 1301 tm "GenericValueColHdrMgr" 1075 1302 ) 1076 *1 27(PragmaColHdr1303 *149 (PragmaColHdr 1077 1304 tm "GenericPragmaColHdrMgr" 1078 1305 ) 1079 *1 28(EolColHdr1306 *150 (EolColHdr 1080 1307 tm "GenericEolColHdrMgr" 1081 1308 ) 1082 *1 29(LogGeneric1309 *151 (LogGeneric 1083 1310 generic (GiElement 1084 1311 name "RAM_ADDR_WIDTH" … … 1086 1313 value "12" 1087 1314 ) 1088 uid 1 590,01315 uid 1849,0 1089 1316 ) 1090 1317 ] … … 1095 1322 uid 177,0 1096 1323 optionalChildren [ 1097 *1 30(Sheet1324 *152 (Sheet 1098 1325 sheetRow (SheetRow 1099 1326 headerVa (MVa … … 1112 1339 font "Tahoma,10,0" 1113 1340 ) 1114 emptyMRCItem *1 31(MRCItem1115 litem &1 171341 emptyMRCItem *153 (MRCItem 1342 litem &139 1116 1343 pos 3 1117 1344 dimension 20 … … 1119 1346 uid 179,0 1120 1347 optionalChildren [ 1121 *1 32(MRCItem1122 litem &1 181348 *154 (MRCItem 1349 litem &140 1123 1350 pos 0 1124 1351 dimension 20 1125 1352 uid 180,0 1126 1353 ) 1127 *1 33(MRCItem1128 litem &1 191354 *155 (MRCItem 1355 litem &141 1129 1356 pos 1 1130 1357 dimension 23 1131 1358 uid 181,0 1132 1359 ) 1133 *1 34(MRCItem1134 litem &1 201360 *156 (MRCItem 1361 litem &142 1135 1362 pos 2 1136 1363 hidden 1 … … 1138 1365 uid 182,0 1139 1366 ) 1140 *1 35(MRCItem1141 litem &1 291367 *157 (MRCItem 1368 litem &151 1142 1369 pos 0 1143 1370 dimension 20 1144 uid 1 591,01371 uid 1850,0 1145 1372 ) 1146 1373 ] … … 1155 1382 uid 183,0 1156 1383 optionalChildren [ 1157 *1 36(MRCItem1158 litem &1 211384 *158 (MRCItem 1385 litem &143 1159 1386 pos 0 1160 1387 dimension 20 1161 1388 uid 184,0 1162 1389 ) 1163 *1 37(MRCItem1164 litem &1 231390 *159 (MRCItem 1391 litem &145 1165 1392 pos 1 1166 1393 dimension 50 1167 1394 uid 185,0 1168 1395 ) 1169 *1 38(MRCItem1170 litem &1 241396 *160 (MRCItem 1397 litem &146 1171 1398 pos 2 1172 1399 dimension 100 1173 1400 uid 186,0 1174 1401 ) 1175 *1 39(MRCItem1176 litem &1 251402 *161 (MRCItem 1403 litem &147 1177 1404 pos 3 1178 1405 dimension 100 1179 1406 uid 187,0 1180 1407 ) 1181 *1 40(MRCItem1182 litem &1 261408 *162 (MRCItem 1409 litem &148 1183 1410 pos 4 1184 1411 dimension 50 1185 1412 uid 188,0 1186 1413 ) 1187 *1 41(MRCItem1188 litem &1 271414 *163 (MRCItem 1415 litem &149 1189 1416 pos 5 1190 1417 dimension 50 1191 1418 uid 189,0 1192 1419 ) 1193 *1 42(MRCItem1194 litem &1 281420 *164 (MRCItem 1421 litem &150 1195 1422 pos 6 1196 1423 dimension 80 … … 1215 1442 (vvPair 1216 1443 variable "HDLDir" 1217 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl"1444 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 1218 1445 ) 1219 1446 (vvPair 1220 1447 variable "HDSDir" 1221 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"1448 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1222 1449 ) 1223 1450 (vvPair 1224 1451 variable "SideDataDesignDir" 1225 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info"1452 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info" 1226 1453 ) 1227 1454 (vvPair 1228 1455 variable "SideDataUserDir" 1229 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user"1456 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user" 1230 1457 ) 1231 1458 (vvPair 1232 1459 variable "SourceDir" 1233 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds"1460 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 1234 1461 ) 1235 1462 (vvPair … … 1247 1474 (vvPair 1248 1475 variable "d" 1249 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"1476 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" 1250 1477 ) 1251 1478 (vvPair 1252 1479 variable "d_logical" 1253 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator"1480 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" 1254 1481 ) 1255 1482 (vvPair 1256 1483 variable "date" 1257 value "1 4.01.2011"1484 value "15.02.2011" 1258 1485 ) 1259 1486 (vvPair 1260 1487 variable "day" 1261 value " Fr"1488 value "Di" 1262 1489 ) 1263 1490 (vvPair 1264 1491 variable "day_long" 1265 value " Freitag"1492 value "Dienstag" 1266 1493 ) 1267 1494 (vvPair 1268 1495 variable "dd" 1269 value "1 4"1496 value "15" 1270 1497 ) 1271 1498 (vvPair … … 1295 1522 (vvPair 1296 1523 variable "host" 1297 value " IHP110"1524 value "E5B-LABOR6" 1298 1525 ) 1299 1526 (vvPair … … 1331 1558 (vvPair 1332 1559 variable "mm" 1333 value "0 1"1560 value "02" 1334 1561 ) 1335 1562 (vvPair … … 1339 1566 (vvPair 1340 1567 variable "month" 1341 value " Jan"1568 value "Feb" 1342 1569 ) 1343 1570 (vvPair 1344 1571 variable "month_long" 1345 value " Januar"1572 value "Februar" 1346 1573 ) 1347 1574 (vvPair 1348 1575 variable "p" 1349 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"1576 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" 1350 1577 ) 1351 1578 (vvPair 1352 1579 variable "p_logical" 1353 value " D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb"1580 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" 1354 1581 ) 1355 1582 (vvPair … … 1375 1602 (vvPair 1376 1603 variable "task_ModelSimPath" 1377 value " D:\\modeltech_6.5e\\win32"1604 value "C:\\modeltech_6.6a\\win32" 1378 1605 ) 1379 1606 (vvPair … … 1407 1634 (vvPair 1408 1635 variable "time" 1409 value "1 1:17:29"1636 value "10:09:00" 1410 1637 ) 1411 1638 (vvPair … … 1415 1642 (vvPair 1416 1643 variable "user" 1417 value "d aqct3"1644 value "dneise" 1418 1645 ) 1419 1646 (vvPair 1420 1647 variable "version" 1421 value "2009. 1 (Build 12)"1648 value "2009.2 (Build 10)" 1422 1649 ) 1423 1650 (vvPair … … 1438 1665 uid 134,0 1439 1666 optionalChildren [ 1440 *1 43(SymbolBody1667 *165 (SymbolBody 1441 1668 uid 8,0 1442 1669 optionalChildren [ 1443 *1 44(CptPort1670 *166 (CptPort 1444 1671 uid 48,0 1445 1672 ps "OnEdgeStrategy" … … 1489 1716 ) 1490 1717 ) 1491 *1 45(CptPort1718 *167 (CptPort 1492 1719 uid 53,0 1493 1720 ps "OnEdgeStrategy" … … 1538 1765 ) 1539 1766 ) 1540 *1 46(CptPort1767 *168 (CptPort 1541 1768 uid 58,0 1542 1769 ps "OnEdgeStrategy" … … 1587 1814 ) 1588 1815 ) 1589 *1 47(CptPort1816 *169 (CptPort 1590 1817 uid 73,0 1591 1818 ps "OnEdgeStrategy" … … 1637 1864 ) 1638 1865 ) 1639 *1 48(CptPort1866 *170 (CptPort 1640 1867 uid 78,0 1641 1868 ps "OnEdgeStrategy" … … 1685 1912 ) 1686 1913 ) 1687 *1 49(CptPort1914 *171 (CptPort 1688 1915 uid 88,0 1689 1916 ps "OnEdgeStrategy" … … 1716 1943 font "Courier New,8,0" 1717 1944 ) 1718 xt "2000,34400,35000,35200" 1719 st "board_id : IN std_logic_vector (3 downto 0) ; 1945 xt "2000,47200,35000,50400" 1946 st "-- 1947 1948 -- EVT HEADER - part 4 1949 board_id : IN std_logic_vector (3 downto 0) ; 1720 1950 " 1721 1951 ) … … 1725 1955 t "std_logic_vector" 1726 1956 b "(3 downto 0)" 1957 prec "-- 1958 1959 -- EVT HEADER - part 4" 1727 1960 preAdd 0 1728 1961 posAdd 0 1729 o 241962 o 31 1730 1963 suid 9,0 1731 1964 ) 1732 1965 ) 1733 1966 ) 1734 *150 (CptPort 1735 uid 93,0 1736 ps "OnEdgeStrategy" 1737 shape (Triangle 1738 uid 94,0 1739 ro 90 1740 va (VaSet 1741 vasetType 1 1742 fg "0,65535,0" 1743 ) 1744 xt "36250,11625,37000,12375" 1745 ) 1746 tg (CPTG 1747 uid 95,0 1748 ps "CptPortTextPlaceStrategy" 1749 stg "VerticalLayoutStrategy" 1750 f (Text 1751 uid 96,0 1752 va (VaSet 1753 ) 1754 xt "38000,11500,44800,12500" 1755 st "trigger_id : (47:0)" 1756 blo "38000,12300" 1757 tm "CptPortNameMgr" 1758 ) 1759 ) 1760 dt (MLText 1761 uid 97,0 1762 va (VaSet 1763 font "Courier New,8,0" 1764 ) 1765 xt "2000,36000,35500,36800" 1766 st "trigger_id : IN std_logic_vector (47 downto 0) ; 1767 " 1768 ) 1769 thePort (LogicalPort 1770 decl (Decl 1771 n "trigger_id" 1772 t "std_logic_vector" 1773 b "(47 downto 0)" 1774 preAdd 0 1775 posAdd 0 1776 o 26 1777 suid 10,0 1778 ) 1779 ) 1780 ) 1781 *151 (CptPort 1967 *172 (CptPort 1782 1968 uid 98,0 1783 1969 ps "OnEdgeStrategy" … … 1810 1996 font "Courier New,8,0" 1811 1997 ) 1812 xt "2000,36800,25500,37600" 1813 st "trigger : IN std_logic ; 1998 xt "2000,60000,25500,61600" 1999 st "-- 2000 trigger : IN std_logic ; 1814 2001 " 1815 2002 ) … … 1818 2005 n "trigger" 1819 2006 t "std_logic" 2007 prec "--" 1820 2008 preAdd 0 1821 2009 posAdd 0 1822 o 272010 o 38 1823 2011 suid 11,0 1824 2012 ) 1825 2013 ) 1826 2014 ) 1827 *1 52(CommentText2015 *173 (CommentText 1828 2016 uid 106,0 1829 2017 ps "EdgeToEdgeStrategy" … … 1859 2047 excludeCommentLeader 1 1860 2048 ) 1861 *1 53(CptPort2049 *174 (CptPort 1862 2050 uid 285,0 1863 2051 ps "OnEdgeStrategy" … … 1890 2078 font "Courier New,8,0" 1891 2079 ) 1892 xt "2000, 35200,35000,36000"2080 xt "2000,50400,35000,51200" 1893 2081 st "crate_id : IN std_logic_vector (1 downto 0) ; 1894 2082 " … … 1899 2087 t "std_logic_vector" 1900 2088 b "(1 downto 0)" 1901 o 25 2089 posAdd 0 2090 o 32 1902 2091 suid 12,0 1903 2092 ) 1904 2093 ) 1905 2094 ) 1906 *1 54(CptPort2095 *175 (CptPort 1907 2096 uid 402,0 1908 2097 ps "OnEdgeStrategy" … … 1948 2137 ) 1949 2138 ) 1950 *1 55(CptPort2139 *176 (CptPort 1951 2140 uid 407,0 1952 2141 ps "OnEdgeStrategy" … … 1996 2185 ) 1997 2186 ) 1998 *1 56(CptPort2187 *177 (CptPort 1999 2188 uid 412,0 2000 2189 ps "OnEdgeStrategy" … … 2040 2229 ) 2041 2230 ) 2042 *1 57(CptPort2231 *178 (CptPort 2043 2232 uid 473,0 2044 2233 ps "OnEdgeStrategy" … … 2084 2273 ) 2085 2274 ) 2086 *1 58(CptPort2275 *179 (CptPort 2087 2276 uid 526,0 2088 2277 ps "OnEdgeStrategy" … … 2115 2304 font "Courier New,8,0" 2116 2305 ) 2117 xt "2000,33600,35500,34400" 2118 st "package_length : IN std_logic_vector (15 downto 0) ; 2306 xt "2000,33600,35500,35200" 2307 st "-- EVT HEADER - part 1 2308 package_length : IN std_logic_vector (15 downto 0) ; 2119 2309 " 2120 2310 ) … … 2124 2314 t "std_logic_vector" 2125 2315 b "(15 downto 0)" 2316 prec "-- EVT HEADER - part 1" 2317 preAdd 0 2126 2318 o 23 2127 2319 suid 20,0 … … 2129 2321 ) 2130 2322 ) 2131 *1 59(CptPort2323 *180 (CptPort 2132 2324 uid 637,0 2133 2325 ps "OnEdgeStrategy" … … 2161 2353 font "Courier New,8,0" 2162 2354 ) 2163 xt "2000, 40800,38500,41600"2355 xt "2000,64800,38500,65600" 2164 2356 st "adc_oeb : OUT std_logic := '1' ; 2165 2357 " … … 2170 2362 n "adc_oeb" 2171 2363 t "std_logic" 2172 o 312364 o 42 2173 2365 suid 23,0 2174 2366 i "'1'" … … 2176 2368 ) 2177 2369 ) 2178 *1 60(CptPort2370 *181 (CptPort 2179 2371 uid 676,0 2180 2372 ps "OnEdgeStrategy" … … 2208 2400 font "Courier New,8,0" 2209 2401 ) 2210 xt "2000, 43200,44500,44000"2402 xt "2000,67200,44500,68000" 2211 2403 st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ; 2212 2404 " … … 2219 2411 b "(3 downto 0)" 2220 2412 posAdd 0 2221 o 342413 o 45 2222 2414 suid 25,0 2223 2415 i "(others => '0')" … … 2225 2417 ) 2226 2418 ) 2227 *1 61(CptPort2419 *182 (CptPort 2228 2420 uid 681,0 2229 2421 ps "OnEdgeStrategy" … … 2257 2449 font "Courier New,8,0" 2258 2450 ) 2259 xt "2000, 47200,38500,48800"2451 xt "2000,71200,38500,72800" 2260 2452 st "-- -- 2261 2453 drs_clk_en : OUT std_logic := '0' ; … … 2270 2462 preAdd 0 2271 2463 posAdd 0 2272 o 372464 o 48 2273 2465 suid 26,0 2274 2466 i "'0'" … … 2276 2468 ) 2277 2469 ) 2278 *1 62(CptPort2470 *183 (CptPort 2279 2471 uid 801,0 2280 2472 ps "OnEdgeStrategy" … … 2308 2500 font "Courier New,8,0" 2309 2501 ) 2310 xt "2000, 48800,38500,50400"2502 xt "2000,72800,38500,74400" 2311 2503 st "-- -- 2312 2504 drs_read_s_cell : OUT std_logic := '0' ; … … 2320 2512 prec "-- --" 2321 2513 preAdd 0 2322 o 382514 o 49 2323 2515 suid 33,0 2324 2516 i "'0'" … … 2326 2518 ) 2327 2519 ) 2328 *1 63(CptPort2520 *184 (CptPort 2329 2521 uid 806,0 2330 2522 ps "OnEdgeStrategy" … … 2357 2549 font "Courier New,8,0" 2358 2550 ) 2359 xt "2000, 53600,25500,54400"2551 xt "2000,77600,25500,78400" 2360 2552 st "drs_read_s_cell_ready : IN std_logic ; 2361 2553 " … … 2365 2557 n "drs_read_s_cell_ready" 2366 2558 t "std_logic" 2367 o 432559 o 54 2368 2560 suid 34,0 2369 2561 ) 2370 2562 ) 2371 2563 ) 2372 *1 64(CptPort2564 *185 (CptPort 2373 2565 uid 811,0 2374 2566 ps "OnEdgeStrategy" … … 2401 2593 font "Courier New,8,0" 2402 2594 ) 2403 xt "2000, 54400,31500,55200"2595 xt "2000,78400,31500,79200" 2404 2596 st "drs_s_cell_array : IN drs_s_cell_array_type ; 2405 2597 " … … 2409 2601 n "drs_s_cell_array" 2410 2602 t "drs_s_cell_array_type" 2411 o 442603 o 55 2412 2604 suid 35,0 2413 2605 ) 2414 2606 ) 2415 2607 ) 2416 *1 65(CptPort2608 *186 (CptPort 2417 2609 uid 898,0 2418 2610 ps "OnEdgeStrategy" … … 2445 2637 font "Courier New,8,0" 2446 2638 ) 2447 xt "2000, 40000,30500,40800"2639 xt "2000,64000,30500,64800" 2448 2640 st "adc_data_array : IN adc_data_array_type ; 2449 2641 " … … 2453 2645 n "adc_data_array" 2454 2646 t "adc_data_array_type" 2455 o 302647 o 41 2456 2648 suid 37,0 2457 2649 ) 2458 2650 ) 2459 2651 ) 2460 *1 66(CptPort2652 *187 (CptPort 2461 2653 uid 958,0 2462 2654 ps "OnEdgeStrategy" … … 2502 2694 ) 2503 2695 ) 2504 *1 67(CptPort2696 *188 (CptPort 2505 2697 uid 963,0 2506 2698 ps "OnEdgeStrategy" … … 2553 2745 ) 2554 2746 ) 2555 *1 68(CptPort2747 *189 (CptPort 2556 2748 uid 1048,0 2557 2749 ps "OnEdgeStrategy" … … 2597 2789 ) 2598 2790 ) 2599 *1 69(CptPort2791 *190 (CptPort 2600 2792 uid 1053,0 2601 2793 ps "OnEdgeStrategy" … … 2641 2833 ) 2642 2834 ) 2643 *1 70(CptPort2835 *191 (CptPort 2644 2836 uid 1085,0 2645 2837 ps "OnEdgeStrategy" … … 2685 2877 ) 2686 2878 ) 2687 *1 71(CptPort2879 *192 (CptPort 2688 2880 uid 1090,0 2689 2881 ps "OnEdgeStrategy" … … 2729 2921 ) 2730 2922 ) 2731 *1 72(CptPort2923 *193 (CptPort 2732 2924 uid 1122,0 2733 2925 ps "OnEdgeStrategy" … … 2780 2972 ) 2781 2973 ) 2782 *1 73(CptPort2974 *194 (CptPort 2783 2975 uid 1127,0 2784 2976 ps "OnEdgeStrategy" … … 2830 3022 ) 2831 3023 ) 2832 *1 74(CptPort3024 *195 (CptPort 2833 3025 uid 1159,0 2834 3026 ps "OnEdgeStrategy" … … 2862 3054 font "Courier New,8,0" 2863 3055 ) 2864 xt "2000, 39200,38500,40000"3056 xt "2000,63200,38500,64000" 2865 3057 st "config_started : OUT std_logic := '0' ; 2866 3058 " … … 2871 3063 n "config_started" 2872 3064 t "std_logic" 2873 o 293065 o 40 2874 3066 suid 48,0 2875 3067 i "'0'" … … 2877 3069 ) 2878 3070 ) 2879 *1 75(CptPort3071 *196 (CptPort 2880 3072 uid 1164,0 2881 3073 ps "OnEdgeStrategy" … … 2908 3100 font "Courier New,8,0" 2909 3101 ) 2910 xt "2000, 37600,25500,39200"3102 xt "2000,61600,25500,63200" 2911 3103 st "-- s_trigger : in std_logic; 2912 3104 new_config : IN std_logic ; … … 2919 3111 prec "-- s_trigger : in std_logic;" 2920 3112 preAdd 0 2921 o 283113 o 39 2922 3114 suid 49,0 2923 3115 ) 2924 3116 ) 2925 3117 ) 2926 *1 76(CptPort3118 *197 (CptPort 2927 3119 uid 1196,0 2928 3120 ps "OnEdgeStrategy" … … 2968 3160 ) 2969 3161 ) 2970 *1 77(CptPort3162 *198 (CptPort 2971 3163 uid 1201,0 2972 3164 ps "OnEdgeStrategy" … … 3012 3204 ) 3013 3205 ) 3014 *1 78(CptPort3206 *199 (CptPort 3015 3207 uid 1206,0 3016 3208 ps "OnEdgeStrategy" … … 3056 3248 ) 3057 3249 ) 3058 * 179(CptPort3250 *200 (CptPort 3059 3251 uid 1240,0 3060 3252 ps "OnEdgeStrategy" … … 3095 3287 n "dac_array" 3096 3288 t "dac_array_type" 3289 posAdd 0 3097 3290 o 22 3098 3291 suid 53,0 … … 3100 3293 ) 3101 3294 ) 3102 * 180(CptPort3295 *201 (CptPort 3103 3296 uid 1395,0 3104 3297 ps "OnEdgeStrategy" … … 3132 3325 font "Courier New,8,0" 3133 3326 ) 3134 xt "2000, 41600,38500,42400"3327 xt "2000,65600,38500,66400" 3135 3328 st "adc_clk_en : OUT std_logic := '0' ; 3136 3329 " … … 3141 3334 n "adc_clk_en" 3142 3335 t "std_logic" 3143 o 323336 o 43 3144 3337 suid 54,0 3145 3338 i "'0'" … … 3147 3340 ) 3148 3341 ) 3149 * 181(CptPort3342 *202 (CptPort 3150 3343 uid 1427,0 3151 3344 ps "OnEdgeStrategy" … … 3178 3371 font "Courier New,8,0" 3179 3372 ) 3180 xt "2000, 42400,35000,43200"3373 xt "2000,66400,35000,67200" 3181 3374 st "adc_otr : IN std_logic_vector (3 downto 0) ; 3182 3375 " … … 3187 3380 t "std_logic_vector" 3188 3381 b "(3 downto 0)" 3189 o 333382 o 44 3190 3383 suid 55,0 3191 3384 ) 3192 3385 ) 3193 3386 ) 3194 * 182(CptPort3387 *203 (CptPort 3195 3388 uid 1459,0 3196 3389 ps "OnEdgeStrategy" … … 3224 3417 font "Courier New,8,0" 3225 3418 ) 3226 xt "2000, 52000,44500,52800"3419 xt "2000,76000,44500,76800" 3227 3420 st "drs_srin_data : OUT std_logic_vector (7 downto 0) := (others => '0') ; 3228 3421 " … … 3234 3427 t "std_logic_vector" 3235 3428 b "(7 downto 0)" 3236 o 413429 o 52 3237 3430 suid 56,0 3238 3431 i "(others => '0')" … … 3240 3433 ) 3241 3434 ) 3242 * 183(CptPort3435 *204 (CptPort 3243 3436 uid 1464,0 3244 3437 ps "OnEdgeStrategy" … … 3272 3465 font "Courier New,8,0" 3273 3466 ) 3274 xt "2000, 50400,38500,51200"3467 xt "2000,74400,38500,75200" 3275 3468 st "drs_srin_write_8b : OUT std_logic := '0' ; 3276 3469 " … … 3281 3474 n "drs_srin_write_8b" 3282 3475 t "std_logic" 3283 o 393476 o 50 3284 3477 suid 57,0 3285 3478 i "'0'" … … 3287 3480 ) 3288 3481 ) 3289 * 184(CptPort3482 *205 (CptPort 3290 3483 uid 1469,0 3291 3484 ps "OnEdgeStrategy" … … 3318 3511 font "Courier New,8,0" 3319 3512 ) 3320 xt "2000, 51200,25500,52000"3513 xt "2000,75200,25500,76000" 3321 3514 st "drs_srin_write_ack : IN std_logic ; 3322 3515 " … … 3326 3519 n "drs_srin_write_ack" 3327 3520 t "std_logic" 3328 o 403521 o 51 3329 3522 suid 58,0 3330 3523 ) 3331 3524 ) 3332 3525 ) 3333 * 185(CptPort3526 *206 (CptPort 3334 3527 uid 1474,0 3335 3528 ps "OnEdgeStrategy" … … 3362 3555 font "Courier New,8,0" 3363 3556 ) 3364 xt "2000, 52800,25500,53600"3557 xt "2000,76800,25500,77600" 3365 3558 st "drs_srin_write_ready : IN std_logic ; 3366 3559 " … … 3370 3563 n "drs_srin_write_ready" 3371 3564 t "std_logic" 3372 o 423565 o 53 3373 3566 suid 59,0 3374 3567 ) 3375 3568 ) 3376 3569 ) 3377 * 186(CptPort3570 *207 (CptPort 3378 3571 uid 1479,0 3379 3572 ps "OnEdgeStrategy" … … 3423 3616 ) 3424 3617 ) 3425 * 187(CptPort3618 *208 (CptPort 3426 3619 uid 1519,0 3427 3620 ps "OnEdgeStrategy" … … 3455 3648 font "Courier New,8,0" 3456 3649 ) 3457 xt "2000, 55200,37500,56000"3650 xt "2000,79200,37500,80000" 3458 3651 st "drs_readout_started : OUT std_logic := '0' 3459 3652 " … … 3464 3657 n "drs_readout_started" 3465 3658 t "std_logic" 3466 o 453659 o 56 3467 3660 suid 61,0 3468 3661 i "'0'" … … 3470 3663 ) 3471 3664 ) 3472 * 188(CptPort3665 *209 (CptPort 3473 3666 uid 1551,0 3474 3667 ps "OnEdgeStrategy" … … 3502 3695 font "Courier New,8,0" 3503 3696 ) 3504 xt "2000, 44000,38500,46400"3697 xt "2000,68000,38500,70400" 3505 3698 st "-- -- 3506 3699 -- drs_dwrite : out std_logic := '1'; … … 3517 3710 preAdd 0 3518 3711 posAdd 0 3519 o 353712 o 46 3520 3713 suid 62,0 3521 3714 i "'0'" … … 3523 3716 ) 3524 3717 ) 3525 * 189(CptPort3718 *210 (CptPort 3526 3719 uid 1583,0 3527 3720 ps "OnEdgeStrategy" … … 3554 3747 font "Courier New,8,0" 3555 3748 ) 3749 xt "2000,70400,25500,71200" 3750 st "drs_readout_ready_ack : IN std_logic ; 3751 " 3752 ) 3753 thePort (LogicalPort 3754 decl (Decl 3755 n "drs_readout_ready_ack" 3756 t "std_logic" 3757 o 47 3758 suid 63,0 3759 ) 3760 ) 3761 ) 3762 *211 (CptPort 3763 uid 1615,0 3764 ps "OnEdgeStrategy" 3765 shape (Triangle 3766 uid 1616,0 3767 ro 90 3768 va (VaSet 3769 vasetType 1 3770 fg "0,65535,0" 3771 ) 3772 xt "36250,39625,37000,40375" 3773 ) 3774 tg (CPTG 3775 uid 1617,0 3776 ps "CptPortTextPlaceStrategy" 3777 stg "VerticalLayoutStrategy" 3778 f (Text 3779 uid 1618,0 3780 va (VaSet 3781 ) 3782 xt "38000,39500,43500,40500" 3783 st "pll_lock : (3:0)" 3784 blo "38000,40300" 3785 tm "CptPortNameMgr" 3786 ) 3787 ) 3788 dt (MLText 3789 uid 1619,0 3790 va (VaSet 3791 font "Courier New,8,0" 3792 ) 3793 xt "2000,35200,35500,36000" 3794 st "pll_lock : IN std_logic_vector ( 3 downto 0) ; 3795 " 3796 ) 3797 thePort (LogicalPort 3798 decl (Decl 3799 n "pll_lock" 3800 t "std_logic_vector" 3801 b "( 3 downto 0)" 3802 posAdd 0 3803 o 24 3804 suid 64,0 3805 ) 3806 ) 3807 ) 3808 *212 (CptPort 3809 uid 1647,0 3810 ps "OnEdgeStrategy" 3811 shape (Triangle 3812 uid 1648,0 3813 ro 90 3814 va (VaSet 3815 vasetType 1 3816 fg "0,65535,0" 3817 ) 3818 xt "36250,40625,37000,41375" 3819 ) 3820 tg (CPTG 3821 uid 1649,0 3822 ps "CptPortTextPlaceStrategy" 3823 stg "VerticalLayoutStrategy" 3824 f (Text 3825 uid 1650,0 3826 va (VaSet 3827 ) 3828 xt "38000,40500,47800,41500" 3829 st "fad_event_counter : (31:0)" 3830 blo "38000,41300" 3831 tm "CptPortNameMgr" 3832 ) 3833 ) 3834 dt (MLText 3835 uid 1651,0 3836 va (VaSet 3837 font "Courier New,8,0" 3838 ) 3839 xt "2000,41600,35500,44800" 3840 st "-- 3841 3842 -- EVT HEADER - part 3 3843 fad_event_counter : IN std_logic_vector (31 downto 0) ; 3844 " 3845 ) 3846 thePort (LogicalPort 3847 decl (Decl 3848 n "fad_event_counter" 3849 t "std_logic_vector" 3850 b "(31 downto 0)" 3851 prec "-- 3852 3853 -- EVT HEADER - part 3" 3854 preAdd 0 3855 o 27 3856 suid 65,0 3857 ) 3858 ) 3859 ) 3860 *213 (CptPort 3861 uid 1679,0 3862 ps "OnEdgeStrategy" 3863 shape (Triangle 3864 uid 1680,0 3865 ro 90 3866 va (VaSet 3867 vasetType 1 3868 fg "0,65535,0" 3869 ) 3870 xt "36250,41625,37000,42375" 3871 ) 3872 tg (CPTG 3873 uid 1681,0 3874 ps "CptPortTextPlaceStrategy" 3875 stg "VerticalLayoutStrategy" 3876 f (Text 3877 uid 1682,0 3878 va (VaSet 3879 ) 3880 xt "38000,41500,46500,42500" 3881 st "refclk_counter : (11:0)" 3882 blo "38000,42300" 3883 tm "CptPortNameMgr" 3884 ) 3885 ) 3886 dt (MLText 3887 uid 1683,0 3888 va (VaSet 3889 font "Courier New,8,0" 3890 ) 3891 xt "2000,44800,35500,45600" 3892 st "refclk_counter : IN std_logic_vector (11 downto 0) ; 3893 " 3894 ) 3895 thePort (LogicalPort 3896 decl (Decl 3897 n "refclk_counter" 3898 t "std_logic_vector" 3899 b "(11 downto 0)" 3900 o 28 3901 suid 66,0 3902 ) 3903 ) 3904 ) 3905 *214 (CptPort 3906 uid 1684,0 3907 ps "OnEdgeStrategy" 3908 shape (Triangle 3909 uid 1685,0 3910 ro 90 3911 va (VaSet 3912 vasetType 1 3913 fg "0,65535,0" 3914 ) 3915 xt "36250,42625,37000,43375" 3916 ) 3917 tg (CPTG 3918 uid 1686,0 3919 ps "CptPortTextPlaceStrategy" 3920 stg "VerticalLayoutStrategy" 3921 f (Text 3922 uid 1687,0 3923 va (VaSet 3924 ) 3925 xt "38000,42500,43900,43500" 3926 st "refclk_too_high" 3927 blo "38000,43300" 3928 tm "CptPortNameMgr" 3929 ) 3930 ) 3931 dt (MLText 3932 uid 1688,0 3933 va (VaSet 3934 font "Courier New,8,0" 3935 ) 3936 xt "2000,45600,25500,46400" 3937 st "refclk_too_high : IN std_logic ; 3938 " 3939 ) 3940 thePort (LogicalPort 3941 decl (Decl 3942 n "refclk_too_high" 3943 t "std_logic" 3944 o 29 3945 suid 67,0 3946 ) 3947 ) 3948 ) 3949 *215 (CptPort 3950 uid 1689,0 3951 ps "OnEdgeStrategy" 3952 shape (Triangle 3953 uid 1690,0 3954 ro 90 3955 va (VaSet 3956 vasetType 1 3957 fg "0,65535,0" 3958 ) 3959 xt "36250,43625,37000,44375" 3960 ) 3961 tg (CPTG 3962 uid 1691,0 3963 ps "CptPortTextPlaceStrategy" 3964 stg "VerticalLayoutStrategy" 3965 f (Text 3966 uid 1692,0 3967 va (VaSet 3968 ) 3969 xt "38000,43500,43500,44500" 3970 st "refclk_too_low" 3971 blo "38000,44300" 3972 tm "CptPortNameMgr" 3973 ) 3974 ) 3975 dt (MLText 3976 uid 1693,0 3977 va (VaSet 3978 font "Courier New,8,0" 3979 ) 3556 3980 xt "2000,46400,25500,47200" 3557 st "drs_readout_ready_ack : IN std_logic ; 3558 " 3559 ) 3560 thePort (LogicalPort 3561 decl (Decl 3562 n "drs_readout_ready_ack" 3563 t "std_logic" 3981 st "refclk_too_low : IN std_logic ; 3982 " 3983 ) 3984 thePort (LogicalPort 3985 decl (Decl 3986 n "refclk_too_low" 3987 t "std_logic" 3988 posAdd 0 3989 o 30 3990 suid 68,0 3991 ) 3992 ) 3993 ) 3994 *216 (CptPort 3995 uid 1725,0 3996 ps "OnEdgeStrategy" 3997 shape (Triangle 3998 uid 1726,0 3999 ro 90 4000 va (VaSet 4001 vasetType 1 4002 fg "0,65535,0" 4003 ) 4004 xt "36250,44625,37000,45375" 4005 ) 4006 tg (CPTG 4007 uid 1727,0 4008 ps "CptPortTextPlaceStrategy" 4009 stg "VerticalLayoutStrategy" 4010 f (Text 4011 uid 1728,0 4012 va (VaSet 4013 ) 4014 xt "38000,44500,45400,45500" 4015 st "FTM_RS485_ready" 4016 blo "38000,45300" 4017 tm "CptPortNameMgr" 4018 ) 4019 ) 4020 dt (MLText 4021 uid 1729,0 4022 va (VaSet 4023 font "Courier New,8,0" 4024 ) 4025 xt "2000,36000,50500,40800" 4026 st "-- 4027 4028 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 4029 -- during EVT header wrinting, this field is left out ... and only written into event header, 4030 -- when the DRS chip were read out already. 4031 FTM_RS485_ready : IN std_logic ; 4032 " 4033 ) 4034 thePort (LogicalPort 4035 decl (Decl 4036 n "FTM_RS485_ready" 4037 t "std_logic" 4038 prec "-- 4039 4040 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 4041 -- during EVT header wrinting, this field is left out ... and only written into event header, 4042 -- when the DRS chip were read out already." 4043 preAdd 0 4044 o 25 4045 suid 69,0 4046 ) 4047 ) 4048 ) 4049 *217 (CptPort 4050 uid 1730,0 4051 ps "OnEdgeStrategy" 4052 shape (Triangle 4053 uid 1731,0 4054 ro 90 4055 va (VaSet 4056 vasetType 1 4057 fg "0,65535,0" 4058 ) 4059 xt "36250,45625,37000,46375" 4060 ) 4061 tg (CPTG 4062 uid 1732,0 4063 ps "CptPortTextPlaceStrategy" 4064 stg "VerticalLayoutStrategy" 4065 f (Text 4066 uid 1733,0 4067 va (VaSet 4068 ) 4069 xt "38000,45500,47900,46500" 4070 st "FTM_trigger_info : (55:0)" 4071 blo "38000,46300" 4072 tm "CptPortNameMgr" 4073 ) 4074 ) 4075 dt (MLText 4076 uid 1734,0 4077 va (VaSet 4078 font "Courier New,8,0" 4079 ) 4080 xt "2000,40800,40000,41600" 4081 st "FTM_trigger_info : IN std_logic_vector (55 downto 0) ; --7 byte 4082 " 4083 ) 4084 thePort (LogicalPort 4085 decl (Decl 4086 n "FTM_trigger_info" 4087 t "std_logic_vector" 4088 b "(55 downto 0)" 4089 eolc "--7 byte" 4090 posAdd 0 4091 o 26 4092 suid 70,0 4093 ) 4094 ) 4095 ) 4096 *218 (CptPort 4097 uid 1764,0 4098 ps "OnEdgeStrategy" 4099 shape (Triangle 4100 uid 1765,0 4101 ro 90 4102 va (VaSet 4103 vasetType 1 4104 fg "0,65535,0" 4105 ) 4106 xt "36250,46625,37000,47375" 4107 ) 4108 tg (CPTG 4109 uid 1766,0 4110 ps "CptPortTextPlaceStrategy" 4111 stg "VerticalLayoutStrategy" 4112 f (Text 4113 uid 1767,0 4114 va (VaSet 4115 ) 4116 xt "38000,46500,47100,47500" 4117 st "DCM_PS_status : (7:0)" 4118 blo "38000,47300" 4119 tm "CptPortNameMgr" 4120 ) 4121 ) 4122 dt (MLText 4123 uid 1768,0 4124 va (VaSet 4125 font "Courier New,8,0" 4126 ) 4127 xt "2000,51200,35000,52000" 4128 st "DCM_PS_status : IN std_logic_vector (7 downto 0) ; 4129 " 4130 ) 4131 thePort (LogicalPort 4132 decl (Decl 4133 n "DCM_PS_status" 4134 t "std_logic_vector" 4135 b "(7 downto 0)" 4136 o 33 4137 suid 71,0 4138 ) 4139 ) 4140 ) 4141 *219 (CptPort 4142 uid 1769,0 4143 ps "OnEdgeStrategy" 4144 shape (Triangle 4145 uid 1770,0 4146 ro 90 4147 va (VaSet 4148 vasetType 1 4149 fg "0,65535,0" 4150 ) 4151 xt "36250,47625,37000,48375" 4152 ) 4153 tg (CPTG 4154 uid 1771,0 4155 ps "CptPortTextPlaceStrategy" 4156 stg "VerticalLayoutStrategy" 4157 f (Text 4158 uid 1772,0 4159 va (VaSet 4160 ) 4161 xt "38000,47500,46900,48500" 4162 st "TRG_GEN_div : (15:0)" 4163 blo "38000,48300" 4164 tm "CptPortNameMgr" 4165 ) 4166 ) 4167 dt (MLText 4168 uid 1773,0 4169 va (VaSet 4170 font "Courier New,8,0" 4171 ) 4172 xt "2000,52800,35500,53600" 4173 st "TRG_GEN_div : IN std_logic_vector (15 downto 0) ; 4174 " 4175 ) 4176 thePort (LogicalPort 4177 decl (Decl 4178 n "TRG_GEN_div" 4179 t "std_logic_vector" 4180 b "(15 downto 0)" 4181 posAdd 0 4182 o 35 4183 suid 72,0 4184 ) 4185 ) 4186 ) 4187 *220 (CptPort 4188 uid 1774,0 4189 ps "OnEdgeStrategy" 4190 shape (Triangle 4191 uid 1775,0 4192 ro 90 4193 va (VaSet 4194 vasetType 1 4195 fg "0,65535,0" 4196 ) 4197 xt "36250,48625,37000,49375" 4198 ) 4199 tg (CPTG 4200 uid 1776,0 4201 ps "CptPortTextPlaceStrategy" 4202 stg "VerticalLayoutStrategy" 4203 f (Text 4204 uid 1777,0 4205 va (VaSet 4206 ) 4207 xt "38000,48500,46400,49500" 4208 st "TRG_GEN_no : (15:0)" 4209 blo "38000,49300" 4210 tm "CptPortNameMgr" 4211 ) 4212 ) 4213 dt (MLText 4214 uid 1778,0 4215 va (VaSet 4216 font "Courier New,8,0" 4217 ) 4218 xt "2000,52000,35500,52800" 4219 st "TRG_GEN_no : IN std_logic_vector (15 downto 0) ; 4220 " 4221 ) 4222 thePort (LogicalPort 4223 decl (Decl 4224 n "TRG_GEN_no" 4225 t "std_logic_vector" 4226 b "(15 downto 0)" 4227 o 34 4228 suid 73,0 4229 ) 4230 ) 4231 ) 4232 *221 (CptPort 4233 uid 1810,0 4234 ps "OnEdgeStrategy" 4235 shape (Triangle 4236 uid 1811,0 4237 ro 90 4238 va (VaSet 4239 vasetType 1 4240 fg "0,65535,0" 4241 ) 4242 xt "36250,49625,37000,50375" 4243 ) 4244 tg (CPTG 4245 uid 1812,0 4246 ps "CptPortTextPlaceStrategy" 4247 stg "VerticalLayoutStrategy" 4248 f (Text 4249 uid 1813,0 4250 va (VaSet 4251 ) 4252 xt "38000,49500,42600,50500" 4253 st "dna : (63:0)" 4254 blo "38000,50300" 4255 tm "CptPortNameMgr" 4256 ) 4257 ) 4258 dt (MLText 4259 uid 1814,0 4260 va (VaSet 4261 font "Courier New,8,0" 4262 ) 4263 xt "2000,53600,35500,56800" 4264 st "-- 4265 4266 -- EVT HEADER - part 5 4267 dna : IN std_logic_vector (63 downto 0) ; 4268 " 4269 ) 4270 thePort (LogicalPort 4271 decl (Decl 4272 n "dna" 4273 t "std_logic_vector" 4274 b "(63 downto 0)" 4275 prec "-- 4276 4277 -- EVT HEADER - part 5" 4278 preAdd 0 4279 posAdd 0 3564 4280 o 36 3565 suid 63,0 4281 suid 74,0 4282 ) 4283 ) 4284 ) 4285 *222 (CptPort 4286 uid 1842,0 4287 ps "OnEdgeStrategy" 4288 shape (Triangle 4289 uid 1843,0 4290 ro 90 4291 va (VaSet 4292 vasetType 1 4293 fg "0,65535,0" 4294 ) 4295 xt "36250,50625,37000,51375" 4296 ) 4297 tg (CPTG 4298 uid 1844,0 4299 ps "CptPortTextPlaceStrategy" 4300 stg "VerticalLayoutStrategy" 4301 f (Text 4302 uid 1845,0 4303 va (VaSet 4304 ) 4305 xt "38000,50500,45600,51500" 4306 st "timer_value : (31:0)" 4307 blo "38000,51300" 4308 tm "CptPortNameMgr" 4309 ) 4310 ) 4311 dt (MLText 4312 uid 1846,0 4313 va (VaSet 4314 font "Courier New,8,0" 4315 ) 4316 xt "2000,56800,48500,60000" 4317 st "-- 4318 4319 -- EVT HEADER - part 6 4320 timer_value : IN std_logic_vector (31 downto 0) ; -- time in units of 100us 4321 " 4322 ) 4323 thePort (LogicalPort 4324 decl (Decl 4325 n "timer_value" 4326 t "std_logic_vector" 4327 b "(31 downto 0)" 4328 prec "-- 4329 4330 -- EVT HEADER - part 6" 4331 eolc "-- time in units of 100us" 4332 preAdd 0 4333 posAdd 0 4334 o 37 4335 suid 75,0 3566 4336 ) 3567 4337 ) … … 3576 4346 lineWidth 2 3577 4347 ) 3578 xt "37000,1000,67000, 40000"4348 xt "37000,1000,67000,52000" 3579 4349 ) 3580 4350 oxt "37000,1000,51000,21000" … … 3602 4372 ) 3603 4373 ) 3604 gi * 190(GenericInterface4374 gi *223 (GenericInterface 3605 4375 uid 13,0 3606 4376 ps "CenterOffsetStrategy" … … 3635 4405 ) 3636 4406 ) 3637 * 191(Grouping4407 *224 (Grouping 3638 4408 uid 16,0 3639 4409 optionalChildren [ 3640 * 192(CommentText4410 *225 (CommentText 3641 4411 uid 18,0 3642 4412 shape (Rectangle … … 3669 4439 titleBlock 1 3670 4440 ) 3671 * 193(CommentText4441 *226 (CommentText 3672 4442 uid 21,0 3673 4443 shape (Rectangle … … 3700 4470 titleBlock 1 3701 4471 ) 3702 * 194(CommentText4472 *227 (CommentText 3703 4473 uid 24,0 3704 4474 shape (Rectangle … … 3731 4501 titleBlock 1 3732 4502 ) 3733 * 195(CommentText4503 *228 (CommentText 3734 4504 uid 27,0 3735 4505 shape (Rectangle … … 3762 4532 titleBlock 1 3763 4533 ) 3764 * 196(CommentText4534 *229 (CommentText 3765 4535 uid 30,0 3766 4536 shape (Rectangle … … 3792 4562 titleBlock 1 3793 4563 ) 3794 * 197(CommentText4564 *230 (CommentText 3795 4565 uid 33,0 3796 4566 shape (Rectangle … … 3823 4593 titleBlock 1 3824 4594 ) 3825 * 198(CommentText4595 *231 (CommentText 3826 4596 uid 36,0 3827 4597 shape (Rectangle … … 3854 4624 titleBlock 1 3855 4625 ) 3856 * 199(CommentText4626 *232 (CommentText 3857 4627 uid 39,0 3858 4628 shape (Rectangle … … 3885 4655 titleBlock 1 3886 4656 ) 3887 *2 00(CommentText4657 *233 (CommentText 3888 4658 uid 42,0 3889 4659 shape (Rectangle … … 3916 4686 titleBlock 1 3917 4687 ) 3918 *2 01(CommentText4688 *234 (CommentText 3919 4689 uid 45,0 3920 4690 shape (Rectangle … … 3960 4730 oxt "14000,66000,55000,71000" 3961 4731 ) 3962 *2 02(CommentText4732 *235 (CommentText 3963 4733 uid 103,0 3964 4734 shape (Rectangle … … 4003 4773 color "26368,26368,26368" 4004 4774 ) 4005 packageList *2 03(PackageList4775 packageList *236 (PackageList 4006 4776 uid 131,0 4007 4777 stg "VerticalLayoutStrategy" 4008 4778 textVec [ 4009 *2 04(Text4779 *237 (Text 4010 4780 uid 132,0 4011 4781 va (VaSet … … 4016 4786 blo "0,1800" 4017 4787 ) 4018 *2 05(MLText4788 *238 (MLText 4019 4789 uid 133,0 4020 4790 va (VaSet … … 4117 4887 ) 4118 4888 ) 4119 gi *2 06(GenericInterface4889 gi *239 (GenericInterface 4120 4890 ps "CenterOffsetStrategy" 4121 4891 matrix (Matrix … … 4214 4984 ) 4215 4985 ) 4216 DeclarativeBlock *2 07(SymDeclBlock4986 DeclarativeBlock *240 (SymDeclBlock 4217 4987 uid 1,0 4218 4988 stg "SymDeclLayoutStrategy" … … 4240 5010 font "Arial,8,1" 4241 5011 ) 4242 xt "0, 56000,2400,57000"5012 xt "0,80000,2400,81000" 4243 5013 st "User:" 4244 blo "0, 56800"5014 blo "0,80800" 4245 5015 ) 4246 5016 internalLabel (Text … … 4259 5029 font "Courier New,8,0" 4260 5030 ) 4261 xt "2000, 57000,2000,57000"5031 xt "2000,81000,2000,81000" 4262 5032 tm "SyDeclarativeTextMgr" 4263 5033 ) … … 4272 5042 ) 4273 5043 ) 4274 lastUid 1 591,05044 lastUid 1850,0 4275 5045 activeModelName "Symbol:CDM" 4276 5046 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb
r10129 r10155 27 27 ldm (LogicalDM 28 28 ordering 1 29 suid 1 5,029 suid 17,0 30 30 usingSuid 1 31 31 emptyRow *1 (LEmptyRow … … 144 144 n "LOCKED" 145 145 t "std_logic" 146 eolc "-- when is this going high?" 146 147 preAdd 0 147 148 posAdd 0 … … 189 190 preAdd 0 190 191 posAdd 0 191 o 1 0192 o 11 192 193 suid 10,0 193 194 i "'0'" … … 204 205 preAdd 0 205 206 posAdd 0 206 o 1 1207 o 12 207 208 suid 11,0 208 209 i "'0'" … … 220 221 preAdd 0 221 222 posAdd 0 222 o 1 2223 o 13 223 224 suid 12,0 224 225 i "(OTHERS => '0')" … … 231 232 m 1 232 233 decl (Decl 233 n "DCM_locked" 234 t "std_logic" 235 preAdd 0 236 posAdd 0 237 o 13 238 suid 13,0 239 ) 240 ) 241 uid 148,0 234 n "rst" 235 t "std_logic" 236 eolc "--asynch in of DCM" 237 posAdd 0 238 o 2 239 suid 15,0 240 i "'0'" 241 ) 242 ) 243 uid 286,0 242 244 ) 243 245 *26 (LogPort 244 246 port (LogicalPort 245 247 decl (Decl 246 n "r st"247 t "std_logic" 248 eolc "-- asynch in ofDCM"249 posAdd 0 250 o 2251 suid 1 5,0252 ) 253 ) 254 uid 286,0248 n "reset_DCM" 249 t "std_logic" 250 eolc "-- asynch in: orders us, to reset the DCM" 251 posAdd 0 252 o 10 253 suid 17,0 254 ) 255 ) 256 uid 369,0 255 257 ) 256 258 ] … … 374 376 pos 11 375 377 dimension 20 376 uid 149,0378 uid 287,0 377 379 ) 378 380 *44 (MRCItem … … 380 382 pos 12 381 383 dimension 20 382 uid 287,0384 uid 370,0 383 385 ) 384 386 ] … … 651 653 (vvPair 652 654 variable "date" 653 value " 04.02.2011"655 value "12.02.2011" 654 656 ) 655 657 (vvPair 656 658 variable "day" 657 value " Fr"659 value "Sa" 658 660 ) 659 661 (vvPair 660 662 variable "day_long" 661 value " Freitag"663 value "Samstag" 662 664 ) 663 665 (vvPair 664 666 variable "dd" 665 value " 04"667 value "12" 666 668 ) 667 669 (vvPair … … 799 801 (vvPair 800 802 variable "time" 801 value "1 1:34:15"803 value "13:16:20" 802 804 ) 803 805 (vvPair … … 889 891 fg "0,65535,0" 890 892 ) 891 xt "6 3000,8625,63750,9375"893 xt "65000,8625,65750,9375" 892 894 ) 893 895 tg (CPTG … … 899 901 va (VaSet 900 902 ) 901 xt " 59100,8500,62000,9500"903 xt "61100,8500,64000,9500" 902 904 st "PSCLK" 903 905 ju 2 904 blo "6 2000,9300"906 blo "64000,9300" 905 907 tm "CptPortNameMgr" 906 908 ) … … 939 941 fg "0,65535,0" 940 942 ) 941 xt "6 3000,10625,63750,11375"943 xt "65000,10625,65750,11375" 942 944 ) 943 945 tg (CPTG … … 949 951 va (VaSet 950 952 ) 951 xt " 59500,10500,62000,11500"953 xt "61500,10500,64000,11500" 952 954 st "PSEN" 953 955 ju 2 954 blo "6 2000,11300"956 blo "64000,11300" 955 957 tm "CptPortNameMgr" 956 958 ) … … 988 990 fg "0,65535,0" 989 991 ) 990 xt "6 3000,12625,63750,13375"992 xt "65000,12625,65750,13375" 991 993 ) 992 994 tg (CPTG … … 998 1000 va (VaSet 999 1001 ) 1000 xt "5 7500,12500,62000,13500"1002 xt "59500,12500,64000,13500" 1001 1003 st "PSINCDEC" 1002 1004 ju 2 1003 blo "6 2000,13300"1005 blo "64000,13300" 1004 1006 tm "CptPortNameMgr" 1005 1007 ) … … 1106 1108 font "Courier New,8,0" 1107 1109 ) 1108 xt "2000,13600, 20000,14400"1109 st "LOCKED : IN std_logic ; 1110 xt "2000,13600,34500,14400" 1111 st "LOCKED : IN std_logic ; -- when is this going high? 1110 1112 " 1111 1113 ) … … 1114 1116 n "LOCKED" 1115 1117 t "std_logic" 1118 eolc "-- when is this going high?" 1116 1119 preAdd 0 1117 1120 posAdd 0 … … 1226 1229 fg "0,65535,0" 1227 1230 ) 1228 xt "6 3000,14625,63750,15375"1231 xt "65000,14625,65750,15375" 1229 1232 ) 1230 1233 tg (CPTG … … 1236 1239 va (VaSet 1237 1240 ) 1238 xt " 59100,14500,62000,15500"1241 xt "61100,14500,64000,15500" 1239 1242 st "shifting" 1240 1243 ju 2 1241 blo "6 2000,15300"1244 blo "64000,15300" 1242 1245 tm "CptPortNameMgr" 1243 1246 ) … … 1248 1251 font "Courier New,8,0" 1249 1252 ) 1250 xt "2000,1 6800,33500,18400"1253 xt "2000,17600,33500,19200" 1251 1254 st "-- status: 1252 1255 shifting : OUT std_logic := '0' ; … … 1261 1264 preAdd 0 1262 1265 posAdd 0 1263 o 1 01266 o 11 1264 1267 suid 10,0 1265 1268 i "'0'" … … 1277 1280 fg "0,65535,0" 1278 1281 ) 1279 xt "6 3000,16625,63750,17375"1282 xt "65000,16625,65750,17375" 1280 1283 ) 1281 1284 tg (CPTG … … 1287 1290 va (VaSet 1288 1291 ) 1289 xt " 59800,16500,62000,17500"1292 xt "61800,16500,64000,17500" 1290 1293 st "ready" 1291 1294 ju 2 1292 blo "6 2000,17300"1295 blo "64000,17300" 1293 1296 tm "CptPortNameMgr" 1294 1297 ) … … 1299 1302 font "Courier New,8,0" 1300 1303 ) 1301 xt "2000,1 8400,33500,19200"1304 xt "2000,19200,33500,20000" 1302 1305 st "ready : OUT std_logic := '0' ; 1303 1306 " … … 1310 1313 preAdd 0 1311 1314 posAdd 0 1312 o 1 11315 o 12 1313 1316 suid 11,0 1314 1317 i "'0'" … … 1326 1329 fg "0,65535,0" 1327 1330 ) 1328 xt "6 3000,18625,63750,19375"1331 xt "65000,18625,65750,19375" 1329 1332 ) 1330 1333 tg (CPTG … … 1336 1339 va (VaSet 1337 1340 ) 1338 xt " 59800,18500,62000,19500"1341 xt "61800,18500,64000,19500" 1339 1342 st "offset" 1340 1343 ju 2 1341 blo "6 2000,19300"1344 blo "64000,19300" 1342 1345 tm "CptPortNameMgr" 1343 1346 ) … … 1348 1351 font "Courier New,8,0" 1349 1352 ) 1350 xt "2000, 19200,39500,20000"1351 st "offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;1353 xt "2000,20000,38500,20800" 1354 st "offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 1352 1355 " 1353 1356 ) … … 1360 1363 preAdd 0 1361 1364 posAdd 0 1362 o 1 21365 o 13 1363 1366 suid 12,0 1364 1367 i "(OTHERS => '0')" … … 1366 1369 ) 1367 1370 ) 1368 *89 (CptPort 1369 uid 108,0 1370 ps "OnEdgeStrategy" 1371 shape (Triangle 1372 uid 109,0 1373 ro 90 1374 va (VaSet 1375 vasetType 1 1376 fg "0,65535,0" 1377 ) 1378 xt "63000,20625,63750,21375" 1379 ) 1380 tg (CPTG 1381 uid 110,0 1382 ps "CptPortTextPlaceStrategy" 1383 stg "RightVerticalLayoutStrategy" 1384 f (Text 1385 uid 111,0 1386 va (VaSet 1387 ) 1388 xt "56800,20500,62000,21500" 1389 st "DCM_locked" 1390 ju 2 1391 blo "62000,21300" 1392 tm "CptPortNameMgr" 1393 ) 1394 ) 1395 dt (MLText 1396 uid 112,0 1397 va (VaSet 1398 font "Courier New,8,0" 1399 ) 1400 xt "2000,20000,19000,20800" 1401 st "DCM_locked : OUT std_logic 1402 " 1403 ) 1404 thePort (LogicalPort 1405 m 1 1406 decl (Decl 1407 n "DCM_locked" 1408 t "std_logic" 1409 preAdd 0 1410 posAdd 0 1411 o 13 1412 suid 13,0 1413 ) 1414 ) 1415 ) 1416 *90 (CommentText 1371 *89 (CommentText 1417 1372 uid 121,0 1418 1373 ps "EdgeToEdgeStrategy" … … 1445 1400 excludeCommentLeader 1 1446 1401 ) 1447 *9 1(CptPort1402 *90 (CptPort 1448 1403 uid 281,0 1449 1404 ps "OnEdgeStrategy" 1450 1405 shape (Triangle 1451 uid 282,01452 ro 901406 uid 394,0 1407 ro 270 1453 1408 va (VaSet 1454 1409 vasetType 1 … … 1476 1431 font "Courier New,8,0" 1477 1432 ) 1478 xt "2000,8800, 30000,9600"1479 st "rst : IN std_logic; --asynch in of DCM1433 xt "2000,8800,43000,9600" 1434 st "rst : OUT std_logic := '0' ; --asynch in of DCM 1480 1435 " 1481 1436 ) 1482 1437 thePort (LogicalPort 1438 m 1 1483 1439 decl (Decl 1484 1440 n "rst" … … 1488 1444 o 2 1489 1445 suid 15,0 1446 i "'0'" 1447 ) 1448 ) 1449 ) 1450 *91 (CptPort 1451 uid 362,0 1452 ps "OnEdgeStrategy" 1453 shape (Triangle 1454 uid 363,0 1455 ro 90 1456 va (VaSet 1457 vasetType 1 1458 fg "0,65535,0" 1459 ) 1460 xt "49250,21625,50000,22375" 1461 ) 1462 tg (CPTG 1463 uid 364,0 1464 ps "CptPortTextPlaceStrategy" 1465 stg "VerticalLayoutStrategy" 1466 f (Text 1467 uid 365,0 1468 va (VaSet 1469 ) 1470 xt "51000,21500,55400,22500" 1471 st "reset_DCM" 1472 blo "51000,22300" 1473 tm "CptPortNameMgr" 1474 ) 1475 ) 1476 dt (MLText 1477 uid 366,0 1478 va (VaSet 1479 font "Courier New,8,0" 1480 ) 1481 xt "2000,16800,41500,17600" 1482 st "reset_DCM : IN std_logic ; -- asynch in: orders us, to reset the DCM 1483 " 1484 ) 1485 thePort (LogicalPort 1486 decl (Decl 1487 n "reset_DCM" 1488 t "std_logic" 1489 eolc "-- asynch in: orders us, to reset the DCM" 1490 posAdd 0 1491 o 10 1492 suid 17,0 1490 1493 ) 1491 1494 ) … … 1500 1503 lineWidth 2 1501 1504 ) 1502 xt "50000,7000,63000,25000" 1503 ) 1505 xt "50000,7000,65000,25000" 1506 ) 1507 oxt "50000,7000,63000,25000" 1504 1508 biTextGroup (BiTextGroup 1505 1509 uid 10,0 … … 2189 2193 ) 2190 2194 ) 2191 lastUid 3 33,02195 lastUid 394,0 2192 2196 activeModelName "Symbol:CDM" 2193 2197 ) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb
r9912 r10155 72 72 n "trigger_id" 73 73 t "std_logic_vector" 74 b "( 47downto 0)"74 b "(31 downto 0)" 75 75 preAdd 0 76 76 posAdd 0 … … 404 404 (vvPair 405 405 variable "HDLDir" 406 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl"406 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" 407 407 ) 408 408 (vvPair 409 409 variable "HDSDir" 410 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"410 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 411 411 ) 412 412 (vvPair 413 413 variable "SideDataDesignDir" 414 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info"414 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info" 415 415 ) 416 416 (vvPair 417 417 variable "SideDataUserDir" 418 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user"418 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user" 419 419 ) 420 420 (vvPair 421 421 variable "SourceDir" 422 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"422 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" 423 423 ) 424 424 (vvPair … … 436 436 (vvPair 437 437 variable "d" 438 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter"438 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter" 439 439 ) 440 440 (vvPair 441 441 variable "d_logical" 442 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter"442 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter" 443 443 ) 444 444 (vvPair 445 445 variable "date" 446 value " 22.06.2010"446 value "15.02.2011" 447 447 ) 448 448 (vvPair … … 456 456 (vvPair 457 457 variable "dd" 458 value " 22"458 value "15" 459 459 ) 460 460 (vvPair … … 484 484 (vvPair 485 485 variable "host" 486 value " TU-CC4900F8C7D2"486 value "E5B-LABOR6" 487 487 ) 488 488 (vvPair … … 495 495 ) 496 496 (vvPair 497 variable "library_downstream_HdsLintPlugin" 498 value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" 499 ) 500 (vvPair 497 501 variable "library_downstream_ISEPARInvoke" 498 502 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 512 516 (vvPair 513 517 variable "mm" 514 value "0 6"518 value "02" 515 519 ) 516 520 (vvPair … … 520 524 (vvPair 521 525 variable "month" 522 value " Jun"526 value "Feb" 523 527 ) 524 528 (vvPair 525 529 variable "month_long" 526 value " Juni"530 value "Februar" 527 531 ) 528 532 (vvPair 529 533 variable "p" 530 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"534 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" 531 535 ) 532 536 (vvPair 533 537 variable "p_logical" 534 value "C:\\ FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb"538 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" 535 539 ) 536 540 (vvPair … … 556 560 (vvPair 557 561 variable "task_ModelSimPath" 558 value " <TBD>"562 value "C:\\modeltech_6.6a\\win32" 559 563 ) 560 564 (vvPair … … 588 592 (vvPair 589 593 variable "time" 590 value " 10:22:01"594 value "09:26:17" 591 595 ) 592 596 (vvPair … … 608 612 (vvPair 609 613 variable "year" 610 value "201 0"614 value "2011" 611 615 ) 612 616 (vvPair 613 617 variable "yy" 614 value "1 0"618 value "11" 615 619 ) 616 620 ] … … 655 659 ) 656 660 xt "2000,9000,30000,9800" 657 st "trigger_id : OUT std_logic_vector (47 downto 0) ;" 661 st "trigger_id : OUT std_logic_vector (31 downto 0) ; 662 " 658 663 ) 659 664 thePort (LogicalPort … … 663 668 n "trigger_id" 664 669 t "std_logic_vector" 665 b "( 47downto 0)"670 b "(31 downto 0)" 666 671 preAdd 0 667 672 posAdd 0 … … 703 708 ) 704 709 xt "2000,9800,19500,10600" 705 st "trigger : IN std_logic ;" 710 st "trigger : IN std_logic ; 711 " 706 712 ) 707 713 thePort (LogicalPort … … 749 755 ) 750 756 xt "2000,10600,18500,11400" 751 st "clk : IN std_logic " 757 st "clk : IN std_logic 758 " 752 759 ) 753 760 thePort (LogicalPort … … 844 851 bg "0,0,32768" 845 852 ) 846 xt "36200,20000,4 4500,21000"853 xt "36200,20000,45700,21000" 847 854 st " 848 855 by %user on %dd %month %year … … 1460 1467 ) 1461 1468 ) 1462 lastUid 177,01469 lastUid 200,0 1463 1470 activeModelName "Symbol:CDM" 1464 1471 )
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