Changeset 10172
- Timestamp:
- 02/23/11 15:53:28 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 1 added
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/continous_pulser_beha.vhd
r10121 r10172 21 21 22 22 GENERIC( 23 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000 23 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000; 24 TRIGGER_WIDTH : integer := 5 24 25 ); 25 26 PORT( 26 27 CLK : IN std_logic; -- 25MHz = 40ns 27 28 28 enable : in std_logic; 29 multiplier : IN std_logic_vector (7 downto 0); 30 31 trigger : out std_logic 29 multiplier : IN std_logic_vector (15 downto 0); 30 trigger : out std_logic 32 31 ); 33 32 END ENTITY continous_pulser; … … 40 39 -- noninverted logic 41 40 signal trigger_loc : std_logic := '0'; 42 signal mult_int : integer range 0 to 1023 :=0; 41 signal mult_int : integer range 0 to 65535 :=0; 42 43 43 BEGIN 44 44 trigger <= trigger_loc and enable; … … 68 68 trigger_loc <= '1'; 69 69 end if; 70 if (Y = 5) then70 if (Y = TRIGGER_WIDTH) then 71 71 trigger_loc <= '0'; 72 72 end if; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd
r10129 r10172 118 118 when CTRL_LOAD_WAIT => 119 119 ctrl_state <= CTRL_LOAD_DATA; 120 121 122 123 124 125 126 127 128 129 130 131 132 133 120 when CTRL_LOAD_DATA => 121 addr_cntr <= addr_cntr + 1; 122 if (addr_cntr < NO_OF_ROI) then 123 roi_array(addr_cntr) <= conv_integer(ram_data_out); 124 ctrl_state <= CTRL_LOAD_ADDR; 125 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then 126 dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); 127 ctrl_state <= CTRL_LOAD_ADDR; 128 else 129 addr_cntr <= 0; 130 config_started <= '0'; 131 config_ready <= '1'; 132 ctrl_state <= CTRL_WAIT_IDLE; 133 end if; 134 134 135 135 when CTRL_WRITE => -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd
r10155 r10172 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 3:10:37 12.02.20115 -- at - 14:02:35 23.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 42 42 -- Created: 43 43 -- by - dneise.UNKNOWN (E5B-LABOR6) 44 -- at - 1 3:10:37 12.02.201144 -- at - 14:02:35 23.02.2011 45 45 -- 46 46 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10155 r10172 69 69 crate_id : in std_logic_vector (1 downto 0); 70 70 DCM_PS_status : in std_logic_vector (7 downto 0); 71 TRG_GEN_no : in std_logic_vector (15 downto 0);72 71 TRG_GEN_div : in std_logic_vector (15 downto 0); 73 72 -- … … 143 142 144 143 begin 145 146 drs_readout_started <= sig_drs_readout_started; 147 148 generate_data : process (clk) 149 begin 150 if rising_edge (clk) then 151 trigger_flag <= trigger; 152 153 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); 154 155 case state_generate is 156 when INIT => 157 state_generate <= CONFIG; 158 159 when CONFIG => 160 config_started <= '1'; 161 if (new_config = '0') then 162 config_started <= '0'; 163 -- config config manager 164 config_start_cm <= '1'; 165 if (config_started_cm = '1') then 166 config_start_cm <= '0'; 167 state_generate <= CONFIG1; 168 end if; 169 end if; 170 when CONFIG1 => 171 if (config_ready_cm = '1') then 172 config_start_mm <= '1'; 173 end if; 174 if (config_started_mm = '1') then 175 config_start_mm <= '0'; 176 state_generate <= CONFIG2; 177 end if; 144 drs_readout_started <= sig_drs_readout_started; 145 146 generate_data : process (clk) 147 begin 148 if rising_edge (clk) then 149 trigger_flag <= trigger; 150 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); 151 case state_generate is 152 when INIT => 153 state_generate <= CONFIG; 154 when CONFIG => 155 config_started <= '1'; 156 if (new_config = '0') then 157 config_started <= '0'; 158 -- config config manager 159 config_start_cm <= '1'; 160 if (config_started_cm = '1') then 161 config_start_cm <= '0'; 162 state_generate <= CONFIG1; 163 end if; 164 end if; 165 when CONFIG1 => 166 if (config_ready_cm = '1') then 167 config_start_mm <= '1'; 168 end if; 169 if (config_started_mm = '1') then 170 config_start_mm <= '0'; 171 state_generate <= CONFIG2; 172 end if; 178 173 when CONFIG2 => 179 174 if (config_ready_mm = '1') then … … 261 256 -- status of the trigger generator 262 257 when WRITE_BOARD_ID => 263 data_out <= TRG_GEN_div & TRG_GEN_no& X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id;258 data_out <= TRG_GEN_div & X"0000" & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; 264 259 addr_cntr <= addr_cntr + 1; 265 260 state_generate <= WRITE_DNA; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10170 r10172 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 7:38:00 16.02.20115 -- at - 14:09:41 23.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 76 76 -- Created: 77 77 -- by - dneise.UNKNOWN (E5B-LABOR6) 78 -- at - 1 7:38:00 16.02.201178 -- at - 14:09:41 23.02.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 126 126 board_id : IN std_logic_vector (3 DOWNTO 0); 127 127 crate_id : IN std_logic_vector (1 DOWNTO 0); 128 drs_refclk_in : IN std_logic ; 129 plllock_in : IN std_logic_vector (3 DOWNTO 0); 128 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit 129 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 130 130 trigger : IN std_logic ; 131 131 wiz_int : IN std_logic ; 132 132 CLK_25_PS : OUT std_logic ; 133 133 CLK_50 : OUT std_logic ; 134 RSRLOAD : OUT std_logic 135 SRCLK : OUT std_logic 136 SRIN_out : OUT std_logic 137 adc_clk_en : OUT std_logic 138 adc_oeb : OUT std_logic 134 RSRLOAD : OUT std_logic := '0'; 135 SRCLK : OUT std_logic := '0'; 136 SRIN_out : OUT std_logic := '0'; 137 adc_clk_en : OUT std_logic := '0'; 138 adc_oeb : OUT std_logic := '1'; 139 139 additional_flasher_out : OUT std_logic ; 140 alarm_refclk_too_high : OUT std_logic := '0'; -- default domino wave off141 alarm_refclk_too_low : OUT std_logic := '0'; -- default domino wave off140 alarm_refclk_too_high : OUT std_logic ; 141 alarm_refclk_too_low : OUT std_logic ; 142 142 amber : OUT std_logic ; 143 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0');143 counter_result : OUT std_logic_vector (11 DOWNTO 0); 144 144 dac_cs : OUT std_logic ; 145 denable : OUT std_logic 146 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) 147 drs_dwrite : OUT std_logic 145 denable : OUT std_logic := '0'; -- default domino wave off 146 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 147 drs_dwrite : OUT std_logic := '1'; 148 148 green : OUT std_logic ; 149 led : OUT std_logic_vector (7 DOWNTO 0) 150 mosi : OUT std_logic 149 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 150 mosi : OUT std_logic := '0'; 151 151 red : OUT std_logic ; 152 152 sclk : OUT std_logic ; 153 153 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 154 154 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 155 wiz_cs : OUT std_logic 156 wiz_rd : OUT std_logic 157 wiz_reset : OUT std_logic 158 wiz_wr : OUT std_logic 155 wiz_cs : OUT std_logic := '1'; 156 wiz_rd : OUT std_logic := '1'; 157 wiz_reset : OUT std_logic := '1'; 158 wiz_wr : OUT std_logic := '1'; 159 159 sio : INOUT std_logic ; 160 160 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10170 r10172 133 133 134 134 -- Commands 135 constant CMD_START : std_logic_vector := X"C0"; 136 constant CMD_STOP : std_logic_vector := X"30"; 137 constant CMD_TRIGGER : std_logic_vector := X"A0"; 138 139 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; 140 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 141 constant CMD_READ : std_logic_vector := X"0A"; 142 constant CMD_WRITE : std_logic_vector := X"05"; 143 -- Config-RAM 144 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values 145 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values 146 147 constant CMD_DENABLE : std_logic_vector := X"06"; 148 constant CMD_DDISABLE : std_logic_vector := X"07"; 149 constant CMD_DWRITE_RUN : std_logic_vector := X"08"; 150 constant CMD_DWRITE_STOP : std_logic_vector := X"09"; 151 constant CMD_SCLK_ON : std_logic_vector := X"10"; 152 constant CMD_SCLK_OFF : std_logic_vector := X"11"; 153 154 constant CMD_PS_DIRINC : std_logic_vector := X"12"; 155 constant CMD_PS_DIRDEC : std_logic_vector := X"13"; 156 constant CMD_PS_DO : std_logic_vector := X"14"; 157 158 constant CMD_SRCLK_ON : std_logic_vector := X"15"; 159 constant CMD_SRCLK_OFF : std_logic_vector := X"16"; 160 161 constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; 162 constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; 163 164 constant CMD_PS_RESET : std_logic_vector := X"17"; 165 166 constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; 135 constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values 136 constant CMD_WRITE : std_logic_vector := X"05"; 137 constant CMD_DENABLE : std_logic_vector := X"06"; 138 constant CMD_DDISABLE : std_logic_vector := X"07"; 139 constant CMD_DWRITE_RUN : std_logic_vector := X"08"; 140 constant CMD_DWRITE_STOP : std_logic_vector := X"09"; 141 constant CMD_READ : std_logic_vector := X"0A"; 142 constant CMD_SCLK_ON : std_logic_vector := X"10"; 143 constant CMD_SCLK_OFF : std_logic_vector := X"11"; 144 constant CMD_PS_DIRINC : std_logic_vector := X"12"; 145 constant CMD_PS_DIRDEC : std_logic_vector := X"13"; 146 constant CMD_PS_DO : std_logic_vector := X"14"; 147 constant CMD_SRCLK_ON : std_logic_vector := X"15"; 148 constant CMD_SRCLK_OFF : std_logic_vector := X"16"; 149 constant CMD_PS_RESET : std_logic_vector := X"17"; 150 constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; 151 constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; 152 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 153 constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; 154 constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode 155 constant CMD_STOP : std_logic_vector := X"23"; -- set data generator in STOP-mode 156 constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values 157 constant CMC_MODE_COMMAND : std_logic_vector := X"30"; 158 constant CMD_TRIGGER : std_logic_vector := X"A0"; 159 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; 160 constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"C0"; 167 161 168 162 -- DRS Registers -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10170 r10172 1 -- VHDL Entity FACT_FAD_lib.FAD_main.symbol 2 -- 3 -- Created: 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 14:08:52 23.02.2011 6 -- 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 8 -- 9 LIBRARY ieee; 10 USE ieee.std_logic_1164.all; 11 USE ieee.std_logic_arith.all; 12 LIBRARY FACT_FAD_lib; 13 USE FACT_FAD_lib.fad_definitions.all; 14 15 ENTITY FAD_main IS 16 GENERIC( 17 RAMADDRWIDTH64b : integer := 12 18 ); 19 PORT( 20 CLK : IN std_logic; 21 D_T_in : IN std_logic_vector (1 DOWNTO 0); 22 SROUT_in_0 : IN std_logic; 23 SROUT_in_1 : IN std_logic; 24 SROUT_in_2 : IN std_logic; 25 SROUT_in_3 : IN std_logic; 26 adc_data_array : IN adc_data_array_type; 27 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 28 board_id : IN std_logic_vector (3 DOWNTO 0); 29 crate_id : IN std_logic_vector (1 DOWNTO 0); 30 drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit 31 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 32 trigger : IN std_logic; 33 wiz_int : IN std_logic; 34 CLK_25_PS : OUT std_logic; 35 CLK_50 : OUT std_logic; 36 RSRLOAD : OUT std_logic := '0'; 37 SRCLK : OUT std_logic := '0'; 38 SRIN_out : OUT std_logic := '0'; 39 adc_clk_en : OUT std_logic := '0'; 40 adc_oeb : OUT std_logic := '1'; 41 additional_flasher_out : OUT std_logic; 42 alarm_refclk_too_high : OUT std_logic; 43 alarm_refclk_too_low : OUT std_logic; 44 amber : OUT std_logic; 45 counter_result : OUT std_logic_vector (11 DOWNTO 0); 46 dac_cs : OUT std_logic; 47 denable : OUT std_logic := '0'; -- default domino wave off 48 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 49 drs_dwrite : OUT std_logic := '1'; 50 green : OUT std_logic; 51 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 52 mosi : OUT std_logic := '0'; 53 red : OUT std_logic; 54 sclk : OUT std_logic; 55 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 56 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 57 wiz_cs : OUT std_logic := '1'; 58 wiz_rd : OUT std_logic := '1'; 59 wiz_reset : OUT std_logic := '1'; 60 wiz_wr : OUT std_logic := '1'; 61 sio : INOUT std_logic; 62 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 63 ); 64 65 -- Declarations 66 67 END FAD_main ; 68 69 -- 70 -- VHDL Architecture FACT_FAD_lib.FAD_main.struct 71 -- 72 -- Created: 73 -- by - dneise.UNKNOWN (E5B-LABOR6) 74 -- at - 14:08:53 23.02.2011 75 -- 76 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) 77 -- 78 library ieee; 79 use ieee.std_logic_1164.all; 80 use IEEE.STD_LOGIC_ARITH.all; 81 use ieee.STD_LOGIC_UNSIGNED.all; 82 83 library fact_fad_lib; 84 use fact_fad_lib.fad_definitions.all; 85 86 library UNISIM; 87 --use UNISIM.VComponents.all; 88 USE IEEE.NUMERIC_STD.all; 89 USE IEEE.std_logic_signed.all; 90 USE UNISIM.VComponents.all; 91 92 LIBRARY FACT_FAD_lib; 93 94 ARCHITECTURE struct OF FAD_main IS 95 96 -- Architecture declarations 97 98 -- Internal signal declarations 99 SIGNAL CLK_25 : std_logic; 100 SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 101 -- 102 103 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 104 -- during EVT header wrinting, this field is left out ... and only written into event header, 105 -- when the DRS chip were read out already. 106 SIGNAL FTM_RS485_ready : std_logic; 107 SIGNAL SRCLK1 : std_logic := '0'; 108 SIGNAL adc_data_array_int : adc_data_array_type; 109 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); 110 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 111 SIGNAL c_trigger_enable : std_logic := '0'; 112 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); 113 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); 114 SIGNAL config_busy : std_logic; 115 SIGNAL config_data : std_logic_vector(15 DOWNTO 0); 116 SIGNAL config_data_valid : std_logic; 117 SIGNAL config_rd_en : std_logic; 118 SIGNAL config_ready : std_logic; 119 SIGNAL config_ready_cm : std_logic; 120 SIGNAL config_ready_spi : std_logic; 121 -- -- 122 SIGNAL config_rw_ack : std_logic := '0'; 123 -- -- 124 SIGNAL config_rw_ready : std_logic := '0'; 125 SIGNAL config_start : std_logic := '0'; 126 SIGNAL config_start_cm : std_logic; 127 SIGNAL config_start_spi : std_logic := '0'; 128 SIGNAL config_started : std_logic; 129 SIGNAL config_started_cu : std_logic := '0'; 130 SIGNAL config_started_mm : std_logic; 131 SIGNAL config_started_spi : std_logic := '0'; 132 SIGNAL config_wr_en : std_logic; 133 SIGNAL crc : std_logic_vector(7 DOWNTO 0); 134 SIGNAL dac_array : dac_array_type; 135 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 136 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 137 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 138 SIGNAL din1 : std_logic := '0'; -- default domino wave off 139 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 140 SIGNAL dout : std_logic; 141 SIGNAL dout1 : std_logic; 142 SIGNAL drs_clk_en : std_logic := '0'; 143 SIGNAL drs_read_s_cell : std_logic := '0'; 144 SIGNAL drs_read_s_cell_ready : std_logic; 145 -- -- 146 -- drs_dwrite : out std_logic := '1'; 147 SIGNAL drs_readout_ready : std_logic := '0'; 148 SIGNAL drs_readout_ready_ack : std_logic; 149 SIGNAL drs_readout_started : std_logic; 150 SIGNAL drs_s_cell_array : drs_s_cell_array_type; 151 SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); 152 SIGNAL dwrite : std_logic := '1'; 153 SIGNAL dwrite_enable : std_logic := '1'; 154 SIGNAL enable_i : std_logic; 155 SIGNAL new_config : std_logic := '0'; 156 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 157 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 158 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 159 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 160 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 161 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); 162 SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 163 SIGNAL ram_write_ea : std_logic; 164 SIGNAL ram_write_ready : std_logic := '0'; 165 -- -- 166 SIGNAL ram_write_ready_ack : std_logic := '0'; 167 SIGNAL ready : STD_LOGIC := '0'; 168 SIGNAL reset_synch_i : std_logic; 169 SIGNAL roi_array : roi_array_type; 170 SIGNAL roi_max : roi_max_type; 171 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 172 SIGNAL s_trigger : std_logic; 173 SIGNAL s_trigger_0 : std_logic; 174 SIGNAL sclk1 : std_logic; 175 SIGNAL sclk_enable : std_logic; 176 SIGNAL sensor_array : sensor_array_type; 177 SIGNAL sensor_ready : std_logic; 178 SIGNAL socks_connected : std_logic; 179 SIGNAL socks_waiting : std_logic; 180 SIGNAL srclk_enable : std_logic := '0'; 181 SIGNAL srin_write_ack : std_logic := '0'; 182 SIGNAL srin_write_ready : std_logic := '0'; 183 SIGNAL start_srin_write_8b : std_logic; 184 SIGNAL time : std_logic_vector(31 DOWNTO 0); 185 SIGNAL trigger1 : std_logic; 186 SIGNAL trigger_enable : std_logic; 187 SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); 188 SIGNAL trigger_out : std_logic; 189 SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); 190 SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); 191 SIGNAL wiz_ack : std_logic; 192 SIGNAL wiz_busy : std_logic; 193 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); 194 SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); 195 SIGNAL wiz_write_ea : std_logic := '0'; 196 SIGNAL wiz_write_end : std_logic := '0'; 197 SIGNAL wiz_write_header : std_logic := '0'; 198 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); 199 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; 200 201 -- Implicit buffer signal declarations 202 SIGNAL CLK_25_PS_internal : std_logic; 203 SIGNAL CLK_50_internal : std_logic; 204 SIGNAL alarm_refclk_too_high_internal : std_logic; 205 SIGNAL alarm_refclk_too_low_internal : std_logic; 206 SIGNAL counter_result_internal : std_logic_vector (11 DOWNTO 0); 207 208 209 -- Component Declarations 210 COMPONENT REFCLK_counter 211 PORT ( 212 clk : IN std_logic; 213 refclk_in : IN std_logic; 214 alarm_refclk_too_high : OUT std_logic := '0'; 215 alarm_refclk_too_low : OUT std_logic := '0'; 216 counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0') 217 ); 218 END COMPONENT; 219 COMPONENT RS485_receiver_fake 220 PORT ( 221 crc : IN std_logic_vector (7 DOWNTO 0); 222 trigger_no : IN std_logic_vector (31 DOWNTO 0); 223 trigger_type1 : IN std_logic_vector (7 DOWNTO 0); 224 trigger_type2 : IN std_logic_vector (7 DOWNTO 0); 225 rs465_data : OUT std_logic_vector (55 DOWNTO 0); 226 rs485_ready : OUT std_logic 227 ); 228 END COMPONENT; 229 COMPONENT adc_buffer 230 PORT ( 231 adc_data_array : IN adc_data_array_type; 232 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 233 clk_ps : IN std_logic; 234 adc_data_array_int : OUT adc_data_array_type; 235 adc_otr : OUT std_logic_vector (3 DOWNTO 0) 236 ); 237 END COMPONENT; 238 COMPONENT clock_generator_var_ps 239 PORT ( 240 CLK : IN std_logic ; 241 RST_IN : IN std_logic ; 242 direction : IN std_logic ; 243 do_shift : IN std_logic ; 244 CLK_25 : OUT std_logic ; 245 CLK_25_PS : OUT std_logic ; 246 CLK_50 : OUT std_logic ; 247 offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') 248 ); 249 END COMPONENT; 250 COMPONENT continous_pulser 251 GENERIC ( 252 MINIMAL_TRIGGER_WAIT_TIME : integer := 250000; 253 TRIGGER_WIDTH : integer := 5 254 ); 255 PORT ( 256 CLK : IN std_logic; 257 enable : IN std_logic; 258 multiplier : IN std_logic_vector (15 DOWNTO 0); 259 trigger : OUT std_logic 260 ); 261 END COMPONENT; 262 COMPONENT control_unit 263 PORT ( 264 clk : IN STD_LOGIC ; 265 config_addr : IN std_logic_vector (7 DOWNTO 0); 266 config_rd_en : IN std_logic ; 267 config_start : IN std_logic ; 268 config_wr_en : IN std_logic ; 269 config_busy : OUT std_logic ; 270 config_data_valid : OUT std_logic ; 271 config_ready : OUT std_logic ; 272 -- -- 273 config_rw_ack : OUT std_logic := '0'; 274 -- -- 275 config_rw_ready : OUT std_logic := '0'; 276 config_started : OUT std_logic := '0'; 277 dac_array : OUT dac_array_type ; 278 roi_array : OUT roi_array_type ; 279 config_data : INOUT std_logic_vector (15 DOWNTO 0) 280 ); 281 END COMPONENT; 282 COMPONENT dataRAM_64b_16b_width14_5 283 PORT ( 284 clka : IN std_logic ; 285 dina : IN std_logic_VECTOR (63 DOWNTO 0); 286 addra : IN std_logic_VECTOR (14 DOWNTO 0); 287 wea : IN std_logic_VECTOR (0 DOWNTO 0); 288 clkb : IN std_logic ; 289 addrb : IN std_logic_VECTOR (16 DOWNTO 0); 290 doutb : OUT std_logic_VECTOR (15 DOWNTO 0) 291 ); 292 END COMPONENT; 293 COMPONENT data_generator 294 GENERIC ( 295 RAM_ADDR_WIDTH : integer := 12 296 ); 297 PORT ( 298 -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 299 clk : IN std_logic ; 300 data_out : OUT std_logic_vector (63 DOWNTO 0); 301 addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 302 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; 303 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 304 ram_write_ea : IN std_logic ; 305 ram_write_ready : OUT std_logic := '0'; 306 -- -- 307 ram_write_ready_ack : IN std_logic ; 308 -- -- 309 config_start_mm : OUT std_logic := '0'; 310 -- -- 311 config_start_cm : OUT std_logic := '0'; 312 -- -- 313 config_start_spi : OUT std_logic := '0'; 314 config_ready_mm : IN std_logic ; 315 config_ready_cm : IN std_logic ; 316 config_ready_spi : IN std_logic ; 317 config_started_mm : IN std_logic ; 318 config_started_cm : IN std_logic ; 319 config_started_spi : IN std_logic ; 320 roi_array : IN roi_array_type ; 321 roi_max : IN roi_max_type ; 322 sensor_array : IN sensor_array_type ; 323 sensor_ready : IN std_logic ; 324 dac_array : IN dac_array_type ; 325 -- EVT HEADER - part 1 326 package_length : IN std_logic_vector (15 DOWNTO 0); 327 pll_lock : IN std_logic_vector ( 3 DOWNTO 0); 328 -- 329 330 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 331 -- during EVT header wrinting, this field is left out ... and only written into event header, 332 -- when the DRS chip were read out already. 333 FTM_RS485_ready : IN std_logic ; 334 FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte 335 -- 336 337 -- EVT HEADER - part 3 338 fad_event_counter : IN std_logic_vector (31 DOWNTO 0); 339 refclk_counter : IN std_logic_vector (11 DOWNTO 0); 340 refclk_too_high : IN std_logic ; 341 refclk_too_low : IN std_logic ; 342 -- 343 344 -- EVT HEADER - part 4 345 board_id : IN std_logic_vector (3 DOWNTO 0); 346 crate_id : IN std_logic_vector (1 DOWNTO 0); 347 DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); 348 TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); 349 -- 350 351 -- EVT HEADER - part 5 352 dna : IN std_logic_vector (63 DOWNTO 0); 353 -- 354 355 -- EVT HEADER - part 6 356 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 357 -- 358 trigger : IN std_logic ; 359 -- s_trigger : in std_logic; 360 new_config : IN std_logic ; 361 config_started : OUT std_logic := '0'; 362 adc_data_array : IN adc_data_array_type ; 363 adc_oeb : OUT std_logic := '1'; 364 adc_clk_en : OUT std_logic := '0'; 365 adc_otr : IN std_logic_vector (3 DOWNTO 0); 366 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 367 -- -- 368 -- drs_dwrite : out std_logic := '1'; 369 drs_readout_ready : OUT std_logic := '0'; 370 drs_readout_ready_ack : IN std_logic ; 371 -- -- 372 drs_clk_en : OUT std_logic := '0'; 373 -- -- 374 drs_read_s_cell : OUT std_logic := '0'; 375 drs_srin_write_8b : OUT std_logic := '0'; 376 drs_srin_write_ack : IN std_logic ; 377 drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); 378 drs_srin_write_ready : IN std_logic ; 379 drs_read_s_cell_ready : IN std_logic ; 380 drs_s_cell_array : IN drs_s_cell_array_type ; 381 drs_readout_started : OUT std_logic := '0' 382 ); 383 END COMPONENT; 384 COMPONENT dna_gen 385 PORT ( 386 clk : IN STD_LOGIC ; 387 dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0'); 388 ready : OUT STD_LOGIC := '0' 389 ); 390 END COMPONENT; 391 COMPONENT drs_pulser 392 PORT ( 393 CLK : IN std_logic; 394 SROUT_in_0 : IN std_logic; 395 SROUT_in_1 : IN std_logic; 396 SROUT_in_2 : IN std_logic; 397 SROUT_in_3 : IN std_logic; 398 srin_data : IN std_logic_vector (7 DOWNTO 0); 399 start_endless_mode : IN std_logic; 400 start_read_stop_pos_mode : IN std_logic; 401 start_srin_write_8b : IN std_logic; 402 RSRLOAD : OUT std_logic := '0'; 403 SRCLK : OUT std_logic := '0'; 404 SRIN_out : OUT std_logic := '0'; 405 srin_write_ack : OUT std_logic := '0'; 406 srin_write_ready : OUT std_logic := '0'; 407 stop_pos : OUT drs_s_cell_array_type; 408 stop_pos_valid : OUT std_logic := '0' 409 ); 410 END COMPONENT; 411 COMPONENT led_controller 412 GENERIC ( 413 HEARTBEAT_PWM_DIVIDER : integer := 500; 414 MAX_DELAY : integer := 100; --not used anymore at all :-( 415 WAITING_DIVIDER : integer := 500000000 416 ); 417 PORT ( 418 CLK : IN std_logic; 419 socks_connected : IN std_logic; 420 socks_waiting : IN std_logic; 421 trigger : IN std_logic; 422 additional_flasher_out : OUT std_logic; 423 amber : OUT std_logic; 424 green : OUT std_logic; 425 red : OUT std_logic 426 ); 427 END COMPONENT; 428 COMPONENT memory_manager 429 GENERIC ( 430 RAM_ADDR_WIDTH_64B : integer := 12; 431 RAM_ADDR_WIDTH_16B : integer := 14 432 ); 433 PORT ( 434 clk : IN std_logic ; 435 config_start : IN std_logic ; 436 ram_write_ready : IN std_logic ; 437 -- -- 438 ram_write_ready_ack : OUT std_logic := '0'; 439 -- -- 440 roi_array : IN roi_array_type ; 441 ram_write_ea : OUT std_logic := '0'; 442 config_ready : OUT std_logic := '0'; 443 config_started : OUT std_logic := '0'; 444 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); 445 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 446 wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); 447 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); 448 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 449 wiz_write_ea : OUT std_logic := '0'; 450 wiz_write_header : OUT std_logic := '0'; 451 wiz_write_end : OUT std_logic := '0'; 452 wiz_busy : IN std_logic ; 453 wiz_ack : IN std_logic ; 454 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 455 ); 456 END COMPONENT; 457 COMPONENT spi_interface 458 PORT ( 459 clk_50MHz : IN std_logic ; 460 config_start : IN std_logic ; 461 dac_array : IN dac_array_type ; 462 config_ready : OUT std_logic ; 463 config_started : OUT std_logic := '0'; 464 dac_cs : OUT std_logic ; 465 mosi : OUT std_logic := '0'; 466 sclk : OUT std_logic ; 467 sensor_array : OUT sensor_array_type ; 468 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 469 sensor_ready : OUT std_logic ; 470 miso : INOUT std_logic 471 ); 472 END COMPONENT; 473 COMPONENT timer 474 GENERIC ( 475 TIMER_WIDTH : integer := 32; 476 PRESCALER : integer := 5000 477 ); 478 PORT ( 479 clk : IN std_logic; 480 enable_i : IN std_logic; 481 reset_synch_i : IN std_logic; 482 synch_i : IN std_logic; 483 synched_o : OUT std_logic := '0'; 484 time_o : OUT std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0) 485 ); 486 END COMPONENT; 487 COMPONENT trigger_counter 488 PORT ( 489 trigger_id : OUT std_logic_vector (31 DOWNTO 0); 490 trigger : IN std_logic ; 491 clk : IN std_logic 492 ); 493 END COMPONENT; 494 COMPONENT trigger_manager 495 PORT ( 496 clk : IN std_logic; 497 drs_readout_ready : IN std_logic; 498 trigger_in : IN std_logic; 499 drs_readout_ready_ack : OUT std_logic := '0'; 500 drs_write : OUT std_logic := '1'; 501 trigger_out : OUT std_logic := '0' 502 ); 503 END COMPONENT; 504 COMPONENT w5300_modul 505 GENERIC ( 506 RAM_ADDR_WIDTH : integer := 14 507 ); 508 PORT ( 509 clk : IN std_logic ; 510 wiz_reset : OUT std_logic := '1'; 511 addr : OUT std_logic_vector (9 DOWNTO 0); 512 data : INOUT std_logic_vector (15 DOWNTO 0); 513 cs : OUT std_logic := '1'; 514 wr : OUT std_logic := '1'; 515 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 516 rd : OUT std_logic := '1'; 517 int : IN std_logic ; 518 write_length : IN std_logic_vector (16 DOWNTO 0); 519 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 520 ram_data : IN std_logic_vector (15 DOWNTO 0); 521 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 522 data_valid : IN std_logic ; 523 data_valid_ack : OUT std_logic := '0'; 524 busy : OUT std_logic := '1'; 525 write_header_flag : IN std_logic ; 526 write_end_flag : IN std_logic ; 527 fifo_channels : IN std_logic_vector (3 DOWNTO 0); 528 -- softtrigger: 529 s_trigger : OUT std_logic := '0'; 530 c_trigger_enable : OUT std_logic := '0'; 531 c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes 532 -- FAD configuration signals: 533 ------------------------------------------------------------------------------ 534 -- start entire configuration chain 535 new_config : OUT std_logic := '0'; 536 config_started : IN std_logic ; 537 -- read/write configRAM 538 config_addr : OUT std_logic_vector (7 DOWNTO 0); 539 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 540 config_wr_en : OUT std_logic := '0'; 541 config_rd_en : OUT std_logic := '0'; 542 config_rw_ack : IN std_logic ; 543 config_rw_ready : IN std_logic ; 544 config_busy : IN std_logic ; 545 ------------------------------------------------------------------------------ 546 547 -- MAC/IP calculation signals: 548 ------------------------------------------------------------------------------ 549 MAC_jumper : IN std_logic_vector (1 DOWNTO 0); 550 BoardID : IN std_logic_vector (3 DOWNTO 0); 551 CrateID : IN std_logic_vector (1 DOWNTO 0); 552 ------------------------------------------------------------------------------ 553 554 -- user controllable enable signals 555 ------------------------------------------------------------------------------ 556 trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted 557 denable : OUT std_logic := '0'; -- default domino wave off 558 dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. 559 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 560 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 561 ------------------------------------------------------------------------------ 562 563 -- ADC CLK generator, is able to shift phase with respect to X_50M 564 -- these signals control the behavior of the digital clock manager (DCM) 565 ------------------------------------------------------------------------------ 566 ps_direction : OUT std_logic := '1'; -- default phase shift upwards 567 ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once 568 ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift 569 ------------------------------------------------------------------------------ 570 571 -- signals used to control FAD LED bahavior: 572 -- one of the three LEDs is used for com-status info 573 ------------------------------------------------------------------------------ 574 socks_waiting : OUT std_logic ; 575 socks_connected : OUT std_logic 576 ------------------------------------------------------------------------------ 577 ); 578 END COMPONENT; 579 580 -- Optional embedded configurations 581 -- pragma synthesis_off 582 FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter; 583 FOR ALL : RS485_receiver_fake USE ENTITY FACT_FAD_lib.RS485_receiver_fake; 584 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; 585 FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; 586 FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser; 587 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; 588 FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; 589 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; 590 FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen; 591 FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; 592 FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; 593 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; 594 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; 595 FOR ALL : timer USE ENTITY FACT_FAD_lib.timer; 596 FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; 597 FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager; 598 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; 599 -- pragma synthesis_on 600 601 602 BEGIN 603 -- Architecture concurrent statements 604 -- HDL Embedded Text Block 1 eb1 605 trigger_type1 <= "00000010"; 606 trigger_type2 <= "00000000"; 607 crc <= X"5A"; 608 609 610 -- ModuleWare code(v1.9) for instance 'I5' of 'and' 611 drs_dwrite <= dwrite AND dwrite_enable; 612 613 -- ModuleWare code(v1.9) for instance 'I6' of 'and' 614 SRCLK <= SRCLK1 AND srclk_enable; 615 616 -- ModuleWare code(v1.9) for instance 'U_1' of 'and' 617 sclk <= sclk_enable AND sclk1; 618 619 -- ModuleWare code(v1.9) for instance 'U_5' of 'and' 620 denable <= denable_prim AND din1; 621 622 -- ModuleWare code(v1.9) for instance 'U_11' of 'and' 623 dout1 <= dout AND trigger_enable; 624 625 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' 626 reset_synch_i <= '0'; 627 628 -- ModuleWare code(v1.9) for instance 'U_7' of 'inv' 629 din1 <= NOT(denable_inhibit); 630 631 -- ModuleWare code(v1.9) for instance 'U_6' of 'or' 632 denable_inhibit <= alarm_refclk_too_low_internal 633 OR alarm_refclk_too_high_internal; 634 635 -- ModuleWare code(v1.9) for instance 'U_9' of 'or' 636 dout <= s_trigger OR trigger; 637 638 -- ModuleWare code(v1.9) for instance 'U_13' of 'or' 639 s_trigger <= s_trigger_0 OR trigger1; 640 641 -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd' 642 enable_i <= '1'; 643 644 -- Instance port mappings. 645 REFCLK_counter_main : REFCLK_counter 646 PORT MAP ( 647 clk => CLK_50_internal, 648 refclk_in => drs_refclk_in, 649 counter_result => counter_result_internal, 650 alarm_refclk_too_high => alarm_refclk_too_high_internal, 651 alarm_refclk_too_low => alarm_refclk_too_low_internal 652 ); 653 U_16 : RS485_receiver_fake 654 PORT MAP ( 655 trigger_no => trigger_id, 656 trigger_type1 => trigger_type1, 657 trigger_type2 => trigger_type2, 658 crc => crc, 659 rs465_data => rs465_data, 660 rs485_ready => FTM_RS485_ready 661 ); 662 I_main_adc_buffer : adc_buffer 663 PORT MAP ( 664 clk_ps => CLK_25_PS_internal, 665 adc_data_array => adc_data_array, 666 adc_otr_array => adc_otr_array, 667 adc_data_array_int => adc_data_array_int, 668 adc_otr => adc_otr 669 ); 670 U_2 : clock_generator_var_ps 671 PORT MAP ( 672 CLK => CLK, 673 RST_IN => ps_reset, 674 direction => ps_direction, 675 do_shift => ps_do_phase_shift, 676 CLK_25 => CLK_25, 677 CLK_25_PS => CLK_25_PS_internal, 678 CLK_50 => CLK_50_internal, 679 offset => DCM_PS_status 680 ); 681 U_3 : continous_pulser 682 GENERIC MAP ( 683 MINIMAL_TRIGGER_WAIT_TIME => 250000, 684 TRIGGER_WIDTH => 5 685 ) 686 PORT MAP ( 687 CLK => CLK_25, 688 enable => c_trigger_enable, 689 multiplier => c_trigger_mult, 690 trigger => trigger1 691 ); 692 I_main_control_unit : control_unit 693 PORT MAP ( 694 clk => CLK_50_internal, 695 config_addr => config_addr, 696 config_rd_en => config_rd_en, 697 config_start => config_start_cm, 698 config_wr_en => config_wr_en, 699 config_busy => config_busy, 700 config_data_valid => config_data_valid, 701 config_ready => config_ready_cm, 702 config_rw_ack => config_rw_ack, 703 config_rw_ready => config_rw_ready, 704 config_started => config_started_cu, 705 dac_array => dac_array, 706 roi_array => roi_array, 707 config_data => config_data 708 ); 709 U_4 : dataRAM_64b_16b_width14_5 710 PORT MAP ( 711 clka => CLK_25, 712 dina => data_out, 713 addra => addr_out, 714 wea => write_ea, 715 clkb => CLK_50_internal, 716 addrb => ram_addr, 717 doutb => ram_data 718 ); 719 I_main_data_generator : data_generator 720 GENERIC MAP ( 721 RAM_ADDR_WIDTH => RAMADDRWIDTH64b 722 ) 723 PORT MAP ( 724 clk => CLK_25, 725 data_out => data_out, 726 addr_out => addr_out, 727 write_ea => write_ea, 728 ram_start_addr => ram_start_addr, 729 ram_write_ea => ram_write_ea, 730 ram_write_ready => ram_write_ready, 731 ram_write_ready_ack => ram_write_ready_ack, 732 config_start_mm => config_start, 733 config_start_cm => config_start_cm, 734 config_start_spi => config_start_spi, 735 config_ready_mm => config_ready, 736 config_ready_cm => config_ready_cm, 737 config_ready_spi => config_ready_spi, 738 config_started_mm => config_started_mm, 739 config_started_cm => config_started_cu, 740 config_started_spi => config_started_spi, 741 roi_array => roi_array, 742 roi_max => roi_max, 743 sensor_array => sensor_array, 744 sensor_ready => sensor_ready, 745 dac_array => dac_array, 746 package_length => package_length, 747 pll_lock => plllock_in, 748 FTM_RS485_ready => FTM_RS485_ready, 749 FTM_trigger_info => rs465_data, 750 fad_event_counter => trigger_id, 751 refclk_counter => counter_result_internal, 752 refclk_too_high => alarm_refclk_too_high_internal, 753 refclk_too_low => alarm_refclk_too_low_internal, 754 board_id => board_id, 755 crate_id => crate_id, 756 DCM_PS_status => DCM_PS_status, 757 TRG_GEN_div => c_trigger_mult, 758 dna => dna, 759 timer_value => time, 760 trigger => trigger_out, 761 new_config => new_config, 762 config_started => config_started, 763 adc_data_array => adc_data_array_int, 764 adc_oeb => adc_oeb, 765 adc_clk_en => adc_clk_en, 766 adc_otr => adc_otr, 767 drs_channel_id => drs_channel_id, 768 drs_readout_ready => drs_readout_ready, 769 drs_readout_ready_ack => drs_readout_ready_ack, 770 drs_clk_en => drs_clk_en, 771 drs_read_s_cell => drs_read_s_cell, 772 drs_srin_write_8b => start_srin_write_8b, 773 drs_srin_write_ack => srin_write_ack, 774 drs_srin_data => drs_srin_data, 775 drs_srin_write_ready => srin_write_ready, 776 drs_read_s_cell_ready => drs_read_s_cell_ready, 777 drs_s_cell_array => drs_s_cell_array, 778 drs_readout_started => drs_readout_started 779 ); 780 U_0 : dna_gen 781 PORT MAP ( 782 clk => CLK_25, 783 dna => dna, 784 ready => ready 785 ); 786 I_main_drs_pulser : drs_pulser 787 PORT MAP ( 788 CLK => CLK_25, 789 start_endless_mode => drs_clk_en, 790 start_read_stop_pos_mode => drs_read_s_cell, 791 SROUT_in_0 => SROUT_in_0, 792 SROUT_in_1 => SROUT_in_1, 793 SROUT_in_2 => SROUT_in_2, 794 SROUT_in_3 => SROUT_in_3, 795 stop_pos => drs_s_cell_array, 796 stop_pos_valid => drs_read_s_cell_ready, 797 start_srin_write_8b => start_srin_write_8b, 798 srin_write_ready => srin_write_ready, 799 srin_write_ack => srin_write_ack, 800 srin_data => drs_srin_data, 801 SRIN_out => SRIN_out, 802 RSRLOAD => RSRLOAD, 803 SRCLK => SRCLK1 804 ); 805 U_10 : led_controller 806 GENERIC MAP ( 807 HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz 808 MAX_DELAY => 100, 809 WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz 810 ) 811 PORT MAP ( 812 CLK => CLK_50_internal, 813 green => green, 814 amber => amber, 815 red => red, 816 additional_flasher_out => additional_flasher_out, 817 trigger => drs_readout_started, 818 socks_waiting => socks_waiting, 819 socks_connected => socks_connected 820 ); 821 I_main_memory_manager : memory_manager 822 GENERIC MAP ( 823 RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, 824 RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 825 ) 826 PORT MAP ( 827 clk => CLK_25, 828 config_start => config_start, 829 ram_write_ready => ram_write_ready, 830 ram_write_ready_ack => ram_write_ready_ack, 831 roi_array => roi_array, 832 ram_write_ea => ram_write_ea, 833 config_ready => config_ready, 834 config_started => config_started_mm, 835 roi_max => roi_max, 836 package_length => package_length, 837 wiz_ram_start_addr => wiz_ram_start_addr, 838 wiz_write_length => wiz_write_length, 839 wiz_number_of_channels => wiz_number_of_channels, 840 wiz_write_ea => wiz_write_ea, 841 wiz_write_header => wiz_write_header, 842 wiz_write_end => wiz_write_end, 843 wiz_busy => wiz_busy, 844 wiz_ack => wiz_ack, 845 ram_start_addr => ram_start_addr 846 ); 847 I_main_SPI_interface : spi_interface 848 PORT MAP ( 849 clk_50MHz => CLK_50_internal, 850 config_start => config_start_spi, 851 dac_array => dac_array, 852 config_ready => config_ready_spi, 853 config_started => config_started_spi, 854 dac_cs => dac_cs, 855 mosi => mosi, 856 sclk => sclk1, 857 sensor_array => sensor_array, 858 sensor_cs => sensor_cs, 859 sensor_ready => sensor_ready, 860 miso => sio 861 ); 862 U_8 : timer 863 GENERIC MAP ( 864 TIMER_WIDTH => 32, 865 PRESCALER => 5000 866 ) 867 PORT MAP ( 868 clk => CLK_50_internal, 869 time_o => time, 870 synch_i => trigger_out, 871 synched_o => OPEN, 872 reset_synch_i => reset_synch_i, 873 enable_i => enable_i 874 ); 875 I_main_ext_trigger : trigger_counter 876 PORT MAP ( 877 trigger_id => trigger_id, 878 trigger => trigger_out, 879 clk => CLK_25_PS_internal 880 ); 881 U_12 : trigger_manager 882 PORT MAP ( 883 clk => CLK_25, 884 trigger_in => dout1, 885 trigger_out => trigger_out, 886 drs_write => dwrite, 887 drs_readout_ready => drs_readout_ready, 888 drs_readout_ready_ack => drs_readout_ready_ack 889 ); 890 I_main_ethernet : w5300_modul 891 GENERIC MAP ( 892 RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 893 ) 894 PORT MAP ( 895 clk => CLK_50_internal, 896 wiz_reset => wiz_reset, 897 addr => wiz_addr, 898 data => wiz_data, 899 cs => wiz_cs, 900 wr => wiz_wr, 901 led => led, 902 rd => wiz_rd, 903 int => wiz_int, 904 write_length => wiz_write_length, 905 ram_start_addr => wiz_ram_start_addr, 906 ram_data => ram_data, 907 ram_addr => ram_addr, 908 data_valid => wiz_write_ea, 909 data_valid_ack => wiz_ack, 910 busy => wiz_busy, 911 write_header_flag => wiz_write_header, 912 write_end_flag => wiz_write_end, 913 fifo_channels => wiz_number_of_channels, 914 s_trigger => s_trigger_0, 915 c_trigger_enable => c_trigger_enable, 916 c_trigger_mult => c_trigger_mult, 917 new_config => new_config, 918 config_started => config_started, 919 config_addr => config_addr, 920 config_data => config_data, 921 config_wr_en => config_wr_en, 922 config_rd_en => config_rd_en, 923 config_rw_ack => config_rw_ack, 924 config_rw_ready => config_rw_ready, 925 config_busy => config_busy, 926 MAC_jumper => D_T_in, 927 BoardID => board_id, 928 CrateID => crate_id, 929 trigger_enable => trigger_enable, 930 denable => denable_prim, 931 dwrite_enable => dwrite_enable, 932 sclk_enable => sclk_enable, 933 srclk_enable => srclk_enable, 934 ps_direction => ps_direction, 935 ps_do_phase_shift => ps_do_phase_shift, 936 ps_reset => ps_reset, 937 socks_waiting => socks_waiting, 938 socks_connected => socks_connected 939 ); 940 941 -- Implicit buffered output assignments 942 CLK_25_PS <= CLK_25_PS_internal; 943 CLK_50 <= CLK_50_internal; 944 alarm_refclk_too_high <= alarm_refclk_too_high_internal; 945 alarm_refclk_too_low <= alarm_refclk_too_low_internal; 946 counter_result <= counter_result_internal; 947 948 END struct; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
r10156 r10172 52 52 wiz_busy : IN std_logic; 53 53 wiz_ack : IN std_logic; 54 buffer_ram_empty : out std_logic; 54 55 ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') 55 56 ); … … 104 105 105 106 -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; 107 buffer_ram_empty <= '0' when events_in_ram=0 else '1'; 106 108 107 109 mm : process (clk) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd
r10170 r10172 8 8 -- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) 9 9 10 --11 12 13 14 15 10 LIBRARY ieee; 16 11 USE ieee.std_logic_1164.all; 17 12 USE ieee.std_logic_arith.all; 18 13 USE ieee.std_logic_unsigned.all; 19 20 14 21 15 ENTITY timer IS … … 29 23 synch_i : in std_logic ; 30 24 synched_o : out std_logic := '0'; 25 reset_synch_i : in std_logic; 31 26 enable_i : in std_logic 32 27 ); … … 42 37 signal en_sr : std_logic_vector(1 downto 0) := "00"; 43 38 signal sy_sr : std_logic_vector(1 downto 0) := "00"; 39 signal reset_synch_sr : std_logic_vector(1 downto 0) := "00"; 44 40 45 41 signal timer_proc_enabled : std_logic := '0'; 42 signal synched : std_logic := '0'; 43 46 44 BEGIN 47 45 --time_o <= conv_std_logic_vector(time_s, TIMER_WIDTH); 48 46 time_o <= time_s; 47 synched_o <= synched; 48 49 49 50 50 main_proc: process (clk) … … 53 53 en_sr <= en_sr(0) & enable_i; 54 54 sy_sr <= sy_sr(0) & synch_i; 55 reset_synch_sr <= reset_synch_sr(0) & reset_synch_i; 55 56 56 if (sy_sr = "01") then -- rising edge on synchronizstion_input detected 57 if ( reset_synch_sr = "01" ) then 58 synched <= '0'; 59 end if; 60 61 if (sy_sr = "01" and synched = '0') then -- rising edge on synchronizstion_input detected AND if not already synched 57 62 time_s <= conv_std_logic_vector(0,TIMER_WIDTH); 58 63 prescale_counter <= 1; 59 synched _o<= '1';64 synched <= '1'; 60 65 end if; 61 66 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10170 r10172 33 33 s_trigger : OUT std_logic := '0'; 34 34 c_trigger_enable: out std_logic := '0'; 35 c_trigger_mult: out std_logic_vector ( 7 DOWNTO 0) := (OTHERS => '1'); --subject to changes35 c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject to changes 36 36 37 37 -- FAD configuration signals: … … 59 59 ------------------------------------------------------------------------------ 60 60 trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted 61 data_generator_run_mode : out std_logic := '0'; -- default triggers are NOT accepted 61 62 denable : out std_logic := '0'; -- default domino wave off 62 63 dwrite_enable : out std_logic := '0'; -- default DWRITE low. … … 191 192 signal mod7_result : std_logic_vector(2 downto 0); 192 193 194 signal set_new_CONT_TRIGGER_MULT_FACTOR : std_logic := '0'; 195 193 196 COMPONENT mod7 194 197 PORT ( … … 209 212 PORT MAP ( 210 213 --locals => actuals 211 clk =>clk 214 clk =>clk , 212 215 number =>event_number , 213 216 start =>mod7_start , … … 620 623 --data_valid_int <= data_valid; 621 624 when MAIN1 => 622 623 624 625 626 627 625 if (chk_recv_cntr = 1000) then 626 chk_recv_cntr <= 0; 627 state_read_data <= RD_1; 628 state_init <= READ_DATA; 629 busy <= '1'; 630 else 628 631 chk_recv_cntr <= chk_recv_cntr + 1; 629 632 state_init <= MAIN2; … … 705 708 case data_read (15 downto 8) is 706 709 707 when CMD_START => -- all data will be send via socket 1..7708 socket_send_mode <= '1';710 when CMD_START => 711 data_generator_run_mode <= '1'; 709 712 state_read_data <= RD_5; 710 when CMD_STOP => -- all data will be send via socket 0711 socket_send_mode <= '0';712 state_read_data <= RD_5; 713 when CMD_STOP => 714 data_generator_run_mode <= '0'; 715 state_read_data <= RD_5; 713 716 717 when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 718 socket_send_mode <= '1'; 719 state_read_data <= RD_5; 720 721 when CMC_MODE_COMMAND => -- all data will be send via socket 0 722 socket_send_mode <= '0'; 723 state_read_data <= RD_5; 714 724 715 725 when CMD_TRIGGER => … … 745 755 state_read_data <= RD_5; 746 756 when CMD_SET_TRIGGER_MULT => 747 c_trigger_mult <= data_read (7 downto 0); 748 state_read_data <= RD_5; 757 set_new_CONT_TRIGGER_MULT_FACTOR <= '1'; 758 next_packet_data <= '1'; 759 state_read_data <= RD_5; 749 760 750 761 -- phase shift commands here: … … 778 789 state_read_data <= RD_5; 779 790 when CMD_WRITE => 780 next_packet_data <= '1';781 config_addr <= data_read (7 downto 0);782 791 config_addr <= data_read (7 downto 0); 792 next_packet_data <= '1'; 793 state_read_data <= RD_5; 783 794 when others => 784 795 state_read_data <= RD_5; … … 786 797 -- read data 787 798 else 788 if (config_busy = '0') then 789 config_data <= data_read; 790 config_wr_en <= '1'; 791 new_config_flag <= '1'; 792 next_packet_data <= '0'; 793 state_read_data <= RD_WAIT; 794 end if; 799 if ( set_new_CONT_TRIGGER_MULT_FACTOR = '1' ) then 800 set_new_CONT_TRIGGER_MULT_FACTOR <= '0'; 801 c_trigger_mult <= data_read; 802 state_read_data <= RD_5; 803 else 804 if (config_busy = '0') then 805 config_data <= data_read; 806 config_wr_en <= '1'; 807 new_config_flag <= '1'; 808 next_packet_data <= '0'; 809 state_read_data <= RD_WAIT; 810 end if; 811 end if; 795 812 end if; 796 813 when RD_WAIT => … … 885 902 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 886 903 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then 887 state_write <= WR_ 01;904 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 888 905 else 889 906 if (local_write_header_flag = '1') then
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