Changeset 10180 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl
- Timestamp:
- 02/25/11 15:56:47 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl
- Files:
-
- 8 added
- 2 edited
-
clock_generator_var_ps_tb_struct.vhd (added)
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clock_generator_var_ps_tester_beha.vhd (added)
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fad_main_tb_struct.vhd (modified) (10 diffs)
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mod7_tb_struct.vhd (added)
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mod7_tester_beha.vhd (added)
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phase_shifter_tb_struct.vhd (added)
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phase_shifter_tester_beha.vhd (added)
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timer_tb_struct.vhd (added)
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timer_tester_beha.vhd (added)
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w5300_emulator_beha.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd
r9912 r10180 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 5:53:42 30.06.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 16:10:14 25.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 20 20 -- 21 21 -- Created: 22 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)23 -- at - 1 5:53:42 30.06.201022 -- by - dneise.UNKNOWN (E5B-LABOR6) 23 -- at - 16:10:15 25.02.2011 24 24 -- 25 25 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 44 44 45 45 -- Internal signal declarations 46 SIGNAL CLK_25_PS : std_logic; 47 SIGNAL CLK_50 : std_logic; 48 SIGNAL RSRLOAD : std_logic := '0'; 49 SIGNAL SRCLK : std_logic := '0'; 50 SIGNAL SROUT_in_0 : std_logic; 51 SIGNAL SROUT_in_1 : std_logic; 52 SIGNAL SROUT_in_2 : std_logic; 53 SIGNAL SROUT_in_3 : std_logic; 54 SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); 55 SIGNAL adc_data_array : adc_data_array_type; 56 SIGNAL adc_oeb : std_logic; 57 SIGNAL adc_otr : STD_LOGIC; 58 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); 59 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 60 SIGNAL clk : STD_LOGIC; 61 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 62 SIGNAL dac_cs : std_logic; 63 SIGNAL denable : std_logic := '0'; -- default domino wave off 64 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 65 SIGNAL drs_dwrite : std_logic := '1'; 66 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 67 SIGNAL mosi : std_logic := '0'; 68 SIGNAL sclk : std_logic; 69 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 70 SIGNAL sio : std_logic; 71 SIGNAL trigger : std_logic; 72 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 73 SIGNAL wiz_cs : std_logic := '1'; 74 SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); 75 SIGNAL wiz_int : std_logic; 76 SIGNAL wiz_rd : std_logic := '1'; 77 SIGNAL wiz_reset : std_logic := '1'; 78 SIGNAL wiz_wr : std_logic := '1'; 46 SIGNAL ADC_CLK : std_logic; 47 SIGNAL CLK_25_PS : std_logic; 48 SIGNAL CLK_50 : std_logic; 49 SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0); 50 SIGNAL REF_CLK : STD_LOGIC := '0'; 51 SIGNAL RSRLOAD : std_logic := '0'; 52 SIGNAL SRCLK : std_logic := '0'; 53 SIGNAL SRIN_out : std_logic := '0'; 54 SIGNAL SROUT_in_0 : std_logic; 55 SIGNAL SROUT_in_1 : std_logic; 56 SIGNAL SROUT_in_2 : std_logic; 57 SIGNAL SROUT_in_3 : std_logic; 58 SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); 59 SIGNAL adc_data_array : adc_data_array_type; 60 SIGNAL adc_oeb : std_logic; 61 SIGNAL adc_otr : STD_LOGIC; 62 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); 63 SIGNAL alarm_refclk_too_high : std_logic; 64 SIGNAL alarm_refclk_too_low : std_logic; 65 SIGNAL amber : std_logic; 66 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 67 SIGNAL clk : STD_LOGIC; 68 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0); 69 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 70 SIGNAL dac_cs : std_logic; 71 SIGNAL denable : std_logic := '0'; -- default domino wave off 72 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 73 SIGNAL drs_dwrite : std_logic := '1'; 74 SIGNAL green : std_logic; 75 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 76 SIGNAL mosi : std_logic := '0'; 77 SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 78 SIGNAL red : std_logic; 79 SIGNAL sclk : std_logic; 80 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 81 SIGNAL sio : std_logic; 82 SIGNAL trigger : std_logic; 83 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 84 SIGNAL wiz_cs : std_logic := '1'; 85 SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); 86 SIGNAL wiz_int : std_logic; 87 SIGNAL wiz_rd : std_logic := '1'; 88 SIGNAL wiz_reset : std_logic := '1'; 89 SIGNAL wiz_wr : std_logic := '1'; 79 90 80 91 … … 85 96 ); 86 97 PORT ( 87 CLK : IN std_logic ; 88 SROUT_in_0 : IN std_logic ; 89 SROUT_in_1 : IN std_logic ; 90 SROUT_in_2 : IN std_logic ; 91 SROUT_in_3 : IN std_logic ; 92 adc_data_array : IN adc_data_array_type ; 93 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 94 board_id : IN std_logic_vector (3 DOWNTO 0); 95 crate_id : IN std_logic_vector (1 DOWNTO 0); 96 trigger : IN std_logic ; 97 wiz_int : IN std_logic ; 98 CLK_25_PS : OUT std_logic ; 99 CLK_50 : OUT std_logic ; 100 RSRLOAD : OUT std_logic := '0'; 101 SRCLK : OUT std_logic := '0'; 102 adc_oeb : OUT std_logic := '1'; 103 dac_cs : OUT std_logic ; 104 denable : OUT std_logic := '0'; -- default domino wave off 105 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 106 drs_dwrite : OUT std_logic := '1'; 107 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 108 mosi : OUT std_logic := '0'; 109 sclk : OUT std_logic ; 110 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 111 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 112 wiz_cs : OUT std_logic := '1'; 113 wiz_rd : OUT std_logic := '1'; 114 wiz_reset : OUT std_logic := '1'; 115 wiz_wr : OUT std_logic := '1'; 116 sio : INOUT std_logic ; 117 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 98 CLK : IN std_logic ; 99 D_T_in : IN std_logic_vector (1 DOWNTO 0); 100 SROUT_in_0 : IN std_logic ; 101 SROUT_in_1 : IN std_logic ; 102 SROUT_in_2 : IN std_logic ; 103 SROUT_in_3 : IN std_logic ; 104 adc_data_array : IN adc_data_array_type ; 105 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 106 board_id : IN std_logic_vector (3 DOWNTO 0); 107 crate_id : IN std_logic_vector (1 DOWNTO 0); 108 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit 109 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 110 trigger : IN std_logic ; 111 wiz_int : IN std_logic ; 112 ADC_CLK : OUT std_logic ; 113 CLK_25_PS : OUT std_logic ; 114 CLK_50 : OUT std_logic ; 115 RSRLOAD : OUT std_logic := '0'; 116 SRCLK : OUT std_logic := '0'; 117 SRIN_out : OUT std_logic := '0'; 118 adc_oeb : OUT std_logic := '1'; 119 alarm_refclk_too_high : OUT std_logic ; 120 alarm_refclk_too_low : OUT std_logic ; 121 amber : OUT std_logic ; 122 counter_result : OUT std_logic_vector (11 DOWNTO 0); 123 dac_cs : OUT std_logic ; 124 denable : OUT std_logic := '0'; -- default domino wave off 125 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 126 drs_dwrite : OUT std_logic := '1'; 127 green : OUT std_logic ; 128 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 129 mosi : OUT std_logic := '0'; 130 red : OUT std_logic ; 131 sclk : OUT std_logic ; 132 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 133 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 134 wiz_cs : OUT std_logic := '1'; 135 wiz_rd : OUT std_logic := '1'; 136 wiz_reset : OUT std_logic := '1'; 137 wiz_wr : OUT std_logic := '1'; 138 sio : INOUT std_logic ; 139 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 118 140 ); 119 141 END COMPONENT; … … 160 182 COMPONENT w5300_emulator 161 183 PORT ( 184 int : OUT std_logic := '0'; 162 185 addr : IN std_logic_vector (9 DOWNTO 0); 163 186 data : INOUT std_logic_vector (15 DOWNTO 0); … … 196 219 adc_otr_array(3) <= adc_otr; 197 220 221 -- HDL Embedded Text Block 3 eb_mainTB_adc1 222 223 D_T_in(1 downto 0) <= "00"; 224 plllock_in(3 downto 0) <= "1111"; 225 SROUT_in_0 <= '1'; 226 SROUT_in_1 <= '0'; 227 SROUT_in_2 <= '1'; 228 SROUT_in_3 <= '0'; 229 198 230 199 231 -- Instance port mappings. … … 203 235 ) 204 236 PORT MAP ( 205 CLK => clk, 206 SROUT_in_0 => SROUT_in_0, 207 SROUT_in_1 => SROUT_in_1, 208 SROUT_in_2 => SROUT_in_2, 209 SROUT_in_3 => SROUT_in_3, 210 adc_data_array => adc_data_array, 211 adc_otr_array => adc_otr_array, 212 board_id => board_id, 213 crate_id => crate_id, 214 trigger => trigger, 215 wiz_int => wiz_int, 216 CLK_25_PS => CLK_25_PS, 217 CLK_50 => CLK_50, 218 RSRLOAD => RSRLOAD, 219 SRCLK => SRCLK, 220 adc_oeb => adc_oeb, 221 dac_cs => dac_cs, 222 denable => denable, 223 drs_channel_id => drs_channel_id, 224 drs_dwrite => drs_dwrite, 225 led => led, 226 mosi => mosi, 227 sclk => sclk, 228 sensor_cs => sensor_cs, 229 wiz_addr => wiz_addr, 230 wiz_cs => wiz_cs, 231 wiz_rd => wiz_rd, 232 wiz_reset => wiz_reset, 233 wiz_wr => wiz_wr, 234 sio => sio, 235 wiz_data => wiz_data 237 CLK => clk, 238 D_T_in => D_T_in, 239 SROUT_in_0 => SROUT_in_0, 240 SROUT_in_1 => SROUT_in_1, 241 SROUT_in_2 => SROUT_in_2, 242 SROUT_in_3 => SROUT_in_3, 243 adc_data_array => adc_data_array, 244 adc_otr_array => adc_otr_array, 245 board_id => board_id, 246 crate_id => crate_id, 247 drs_refclk_in => REF_CLK, 248 plllock_in => plllock_in, 249 trigger => trigger, 250 wiz_int => wiz_int, 251 ADC_CLK => ADC_CLK, 252 CLK_25_PS => CLK_25_PS, 253 CLK_50 => CLK_50, 254 RSRLOAD => RSRLOAD, 255 SRCLK => SRCLK, 256 SRIN_out => SRIN_out, 257 adc_oeb => adc_oeb, 258 alarm_refclk_too_high => alarm_refclk_too_high, 259 alarm_refclk_too_low => alarm_refclk_too_low, 260 amber => amber, 261 counter_result => counter_result, 262 dac_cs => dac_cs, 263 denable => denable, 264 drs_channel_id => drs_channel_id, 265 drs_dwrite => drs_dwrite, 266 green => green, 267 led => led, 268 mosi => mosi, 269 red => red, 270 sclk => sclk, 271 sensor_cs => sensor_cs, 272 wiz_addr => wiz_addr, 273 wiz_cs => wiz_cs, 274 wiz_rd => wiz_rd, 275 wiz_reset => wiz_reset, 276 wiz_wr => wiz_wr, 277 sio => sio, 278 wiz_data => wiz_data 236 279 ); 237 280 I_mainTB_adc : adc_emulator … … 240 283 ) 241 284 PORT MAP ( 242 clk => clk,285 clk => ADC_CLK, 243 286 data => adc_data, 244 287 otr => adc_otr, … … 254 297 rst => OPEN 255 298 ); 299 I_mainTB_clock1 : clock_generator 300 GENERIC MAP ( 301 clock_period => 1 us, 302 reset_time => 1 us 303 ) 304 PORT MAP ( 305 clk => REF_CLK, 306 rst => OPEN 307 ); 256 308 I_mainTB_max6662 : max6662_emulator 257 309 GENERIC MAP ( … … 273 325 I_mainTB_w5300 : w5300_emulator 274 326 PORT MAP ( 327 int => wiz_int, 275 328 addr => wiz_addr, 276 329 data => wiz_data, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd
r9912 r10180 17 17 ENTITY w5300_emulator IS 18 18 PORT( 19 int : out std_logic := '0'; 19 20 addr : in std_logic_vector (9 DOWNTO 0); 20 21 data : inout std_logic_vector (15 DOWNTO 0); … … 71 72 elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then 72 73 if (FIFOR_CNT = 0) then 73 data_temp <= X" B000";74 --FIFOR_CNT <= 1;74 data_temp <= X"1800"; 75 FIFOR_CNT <= 1; 75 76 elsif (FIFOR_CNT = 1) then 76 data_temp <= X" 0500";77 data_temp <= X"2200"; 77 78 FIFOR_CNT <= 2; 78 79 elsif (FIFOR_CNT = 2) then 79 data_temp <= X"0000"; 80 end if; 80 data_temp <= X"A000"; 81 FIFOR_CNT <= 3; 82 83 elsif (FIFOR_CNT = 3) then 84 data_temp <= X"B000"; 85 end if; 81 86 else 82 87 null;
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