Ignore:
Timestamp:
03/04/11 10:16:36 (14 years ago)
Author:
neise
Message:
new data format implemented.
setting of DAC during run is possible.
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/REFCLK_counter_tester_beha.vhd

    r10129 r10225  
    1919      alarm_refclk_too_low  : IN     std_logic;
    2020      counter_result        : IN     std_logic_vector (11 DOWNTO 0);
     21      clk                   : out   std_logic;
    2122      refclk_in             : OUT    std_logic
    2223   );
    … …  
    2829--
    2930ARCHITECTURE beha OF REFCLK_counter_tester IS
    30   constant REFCLK_PERIOD : time := 1012ns;
     31constant REFCLK_PERIOD : time := 1012ns;
     32constant clock_period : time := 20ns;
     33
     34signal refclk_i : std_logic := '0';
     35signal refclk_en : std_logic;
    3136 
    3237BEGIN
     38  refclk_in <= refclk_i and refclk_en;
    3339 
    34   clock_gen_proc: process
     40  clk_en_proc: process
     41  begin
     42    refclk_en <= '1';
     43    wait for 4500 us;
     44    refclk_en <= '0';
     45    wait;
     46  end process clk_en_proc;
     47 
     48    clock_gen_proc: process
     49  begin
     50    clk <= '0';
     51    wait for clock_period / 2;
     52    clk <= '1';
     53    wait for clock_period / 2;
     54  end process clock_gen_proc;
     55 
     56 
     57  ref_clock_gen_proc: process
    3558    begin
    36       refclk_in <= '0';
     59      refclk_i <= '0';
    3760      wait for REFCLK_PERIOD / 2;
    38       refclk_in <= '1';
     61      refclk_i <= '1';
    3962      wait for REFCLK_PERIOD / 2;
    40     end process clock_gen_proc;
     63    end process ref_clock_gen_proc;
    4164 
    4265END ARCHITECTURE beha;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd

    r10180 r10225  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 16:10:14 25.02.2011
    6 --
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     4--          by - daqct3.UNKNOWN (IHP110)
     5--          at - 18:33:01 02.03.2011
     6--
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    88--
    99LIBRARY ieee;
    … …  
    2020--
    2121-- Created:
    22 --          by - dneise.UNKNOWN (E5B-LABOR6)
    23 --          at - 16:10:15 25.02.2011
    24 --
    25 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     22--          by - daqct3.UNKNOWN (IHP110)
     23--          at - 18:33:01 02.03.2011
     24--
     25-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    2626--
    2727LIBRARY ieee;
    … …  
    182182   COMPONENT w5300_emulator
    183183   PORT (
    184       int  : OUT    std_logic  := '0';
     184      int  : OUT    std_logic  := '1';
    185185      addr : IN     std_logic_vector (9 DOWNTO 0);
    186186      data : INOUT  std_logic_vector (15 DOWNTO 0);

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/refclk_counter_tb_struct.vhd

    r10129 r10225  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (E5B-LABOR6)
    5 --          at - 09:29:21 04.02.2011
     4--          by - daqct3.UNKNOWN (IHP110)
     5--          at - 18:11:15 03.03.2011
    66--
    7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    88--
    99
    … …  
    2222--
    2323-- Created:
    24 --          by - dneise.UNKNOWN (E5B-LABOR6)
    25 --          at - 09:29:21 04.02.2011
     24--          by - daqct3.UNKNOWN (IHP110)
     25--          at - 18:11:15 03.03.2011
    2626--
    27 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
     27-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
    2828--
    2929LIBRARY ieee;
    … …  
    6464      alarm_refclk_too_low  : IN     std_logic ;
    6565      counter_result        : IN     std_logic_vector (11 DOWNTO 0);
     66      clk                   : OUT    std_logic ;
    6667      refclk_in             : OUT    std_logic
    67    );
    68    END COMPONENT;
    69    COMPONENT clock_generator
    70    GENERIC (
    71       clock_period : time := 20 ns;
    72       reset_time   : time := 50 ns
    73    );
    74    PORT (
    75       clk : OUT    std_logic  := '0';
    76       rst : OUT    std_logic  := '0'
    7768   );
    7869   END COMPONENT;
    … …  
    8273   FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
    8374   FOR ALL : REFCLK_counter_tester USE ENTITY FACT_FAD_TB_lib.REFCLK_counter_tester;
    84    FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
    8575   -- pragma synthesis_on
    8676
    … …  
    10292         alarm_refclk_too_low  => alarm_refclk_too_low,
    10393         counter_result        => counter_result,
     94         clk                   => clk,
    10495         refclk_in             => refclk_in
    105       );
    106    U_2 : clock_generator
    107       GENERIC MAP (
    108          clock_period => 20 ns,
    109          reset_time   => 50 ns
    110       )
    111       PORT MAP (
    112          clk => clk,
    113          rst => OPEN
    11496      );
    11597

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd

    r10180 r10225  
    1717ENTITY w5300_emulator IS
    1818   PORT(
    19                 int : out       std_logic := '0';
     19                  int : out     std_logic := '1';
    2020      addr : in     std_logic_vector (9 DOWNTO 0);
    2121      data : inout  std_logic_vector (15 DOWNTO 0);
    … …  
    4343  set_proc : process
    4444  begin
     45        FIFOR_CNT <= 0;
    4546    RSR_0 <= X"0000";
    4647    RSR_1 <= X"0000";
    47     wait for 250 us;
     48    wait for 150 us;
    4849    RSR_1 <= X"0001";
    49     wait for 200 us;
     50    wait for 100 us;
    5051    RSR_1 <= X"0002";
     52    wait for 500 us;
     53                FIFOR_CNT <= 1;
     54        wait for 100 us;
     55                FIFOR_CNT <= 2;
     56        wait for 200 us;
     57                FIFOR_CNT <= 3;
     58        wait for 200 ns;
     59                RSR_1 <= X"0000";
     60        wait for 2 ms;
     61                RSR_1 <= X"0002";
     62                FIFOR_CNT <= 2;
     63               
     64        wait for 6 ms;
     65        int <= '0';
     66         
     67--      wait for 1 ms;
     68--              RSR_1 <= X"0000";
     69--              FIFOR_CNT <= 3;
    5170    wait;
    5271  end process set_proc;
    … …  
    7392        if (FIFOR_CNT = 0) then
    7493          data_temp <= X"1800";
    75           FIFOR_CNT <= 1;
     94         
    7695        elsif (FIFOR_CNT = 1) then
    7796          data_temp <= X"2200";
    78           FIFOR_CNT <= 2;
     97         
    7998        elsif (FIFOR_CNT = 2) then
    8099          data_temp <= X"A000";
    81           FIFOR_CNT <= 3;
     100         
    82101
    83102          elsif (FIFOR_CNT = 3) then
    84                 data_temp <= X"B000";
     103                data_temp <= X"A000";
    85104          end if;
    86105      else
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