Changeset 10227 for firmware/FTM
- Timestamp:
- 03/04/11 17:42:32 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 23 added
- 5 edited
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FTM_central_control.vhd (added)
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FTM_top.vhd (modified) (13 diffs)
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FTM_top_tb.vhd (modified) (12 diffs)
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clock (added)
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clock/FTM_clk_gen.vhd (added)
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clock/FTM_dcm_40M_to_250M.vhd (added)
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clock/FTM_dcm_40M_to_250M.xaw (added)
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clock/FTM_dcm_40M_to_250M_arwz.ucf (added)
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clock/FTM_dcm_40M_to_50M.vhd (added)
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clock/FTM_dcm_40M_to_50M.xaw (added)
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clock/FTM_dcm_40M_to_50M_arwz.ucf (added)
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clock/xaw2vhdl.log (added)
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ethernet (added)
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ethernet/CRAM_4096_16b.ngc (added)
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ethernet/CRAM_4096_16b_CRAM_4096_16b_a.vhd (added)
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ethernet/DRAM_4096_16b.ngc (added)
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ethernet/DRAM_4096_16b_DRAM_4096_16b_a.vhd (added)
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ethernet/FRAM_4096_16b.ngc (added)
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ethernet/FRAM_4096_16b_FRAM_4096_16b_a.vhd (added)
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ethernet/cram_control_beha.vhd (added)
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ethernet/dram_control_beha.vhd (added)
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ethernet/eth_config_modul_beha.vhd (added)
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ethernet/ethernet_modul_beha.vhd (added)
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ethernet/fram_control_beha.vhd (added)
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ethernet/w5300_modul.vhd (added)
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ftm_board.ucf (modified) (15 diffs)
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ftm_definitions.vhd (modified) (9 diffs)
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ftu_control/FTM_ftu_control.vhd (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTM/FTM_top.vhd
r10067 r10227 25 25 use IEEE.STD_LOGIC_UNSIGNED.ALL; 26 26 27 library ftm_definitions; 28 USE ftm_definitions.ftm_array_types.all; 29 USE ftm_definitions.ftm_constants.all; 30 27 31 ---- Uncomment the following library declaration if instantiating 28 32 ---- any Xilinx primitives in this code. 29 --library UNISIM;30 --use UNISIM.VComponents.all;33 library UNISIM; 34 use UNISIM.VComponents.all; 31 35 32 36 … … 44 48 45 49 -- W5300 address bus 46 W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NOnet W_A0 because50 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because 47 51 -- the W5300 is operated in the 48 -- 16-bit mode 52 -- 16-bit mode 53 -- -> W_A<0> assigned to unconnected pin 49 54 50 55 -- W5300 control signals 51 56 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 52 57 -- W_CS is also routed to testpoint JP7 53 W_CS : out STD_LOGIC ;-- W5300 chip select58 W_CS : out STD_LOGIC := '1'; -- W5300 chip select 54 59 W_INT : IN STD_LOGIC; -- interrupt 55 W_RD : out STD_LOGIC ;-- read56 W_WR : out STD_LOGIC ;-- write57 W_RES : out STD_LOGIC ;-- reset W5300 chip60 W_RD : out STD_LOGIC := '1'; -- read 61 W_WR : out STD_LOGIC := '1'; -- write 62 W_RES : out STD_LOGIC := '1'; -- reset W5300 chip 58 63 59 64 -- W5300 buffer ready indicator 60 W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);65 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); 61 66 62 67 -- testpoints (T18) associated with the W5300 on IO-bank 1 63 W_T : inout STD_LOGIC_VECTOR(3 downto 0);68 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); 64 69 65 70 … … 69 74 -- on IO-Bank 1 70 75 ------------------------------------------------------------------------------- 71 S_CLK : out STD_LOGIC; -- SPI clock76 -- S_CLK : out STD_LOGIC; -- SPI clock 72 77 73 78 -- EEPROM … … 77 82 78 83 -- temperature sensors U45, U46, U48 and U49 79 SIO : inout STD_LOGIC; -- serial IO80 TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select84 -- SIO : inout STD_LOGIC; -- serial IO 85 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select 81 86 82 87 … … 84 89 -- on IO-Bank 2 85 90 ------------------------------------------------------------------------------- 86 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 087 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 188 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 289 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 391 -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 92 -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 93 -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 94 -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 90 95 91 96 … … 93 98 ------------------------------------------------------------------------------ 94 99 -- on IO-Bank 3 95 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input96 Veto : in STD_LOGIC; -- trigger veto input97 NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs100 -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input 101 -- Veto : in STD_LOGIC; -- trigger veto input 102 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs 98 103 99 104 -- on IO-Bank 0 100 105 -- alternative external clock input for FPGA 101 NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available106 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available 102 107 103 108 104 109 -- LEDs on IO-Banks 0 and 3 105 110 ------------------------------------------------------------------------------- 106 LED_red : out STD_LOGIC_VECTOR(3 downto 0); 111 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red 107 112 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow 108 113 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green … … 112 117 -- on IO-Bank 3 113 118 ------------------------------------------------------------------------------- 114 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock115 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable116 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data119 -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock 120 -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable 121 -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data 117 122 118 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization119 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for123 -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization 124 -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for 120 125 121 126 … … 137 142 138 143 Bus1_RxD_3 : in STD_LOGIC; -- crate 3 139 Bus1_TxD_3 : out STD_LOGIC ;144 Bus1_TxD_3 : out STD_LOGIC 140 145 141 146 142 147 -- Bus 2: Trigger-ID to FAD boards 143 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable144 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable145 146 Bus2_RxD_0 : in STD_LOGIC; -- crate 0147 Bus2_TxD_0 : out STD_LOGIC;148 149 Bus2_RxD_1 : in STD_LOGIC; -- crate 1150 Bus2_TxD_1 : out STD_LOGIC;151 152 Bus2_RxD_2 : in STD_LOGIC; -- crate 2153 Bus2_TxD_2 : out STD_LOGIC;154 155 Bus2_RxD_3 : in STD_LOGIC; -- crate 3156 Bus2_TxD_3 : out STD_LOGIC;148 -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable 149 -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable 150 151 -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 152 -- Bus2_TxD_0 : out STD_LOGIC; 153 154 -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 155 -- Bus2_TxD_1 : out STD_LOGIC; 156 157 -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 158 -- Bus2_TxD_2 : out STD_LOGIC; 159 160 -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 161 -- Bus2_TxD_3 : out STD_LOGIC; 157 162 158 163 … … 172 177 -- on IO-Bank 3 173 178 ------------------------------------------------------------------------------- 174 Crate_Res0 : out STD_LOGIC;175 Crate_Res1 : out STD_LOGIC;176 Crate_Res2 : out STD_LOGIC;177 Crate_Res3 : out STD_LOGIC;179 -- Crate_Res0 : out STD_LOGIC; 180 -- Crate_Res1 : out STD_LOGIC; 181 -- Crate_Res2 : out STD_LOGIC; 182 -- Crate_Res3 : out STD_LOGIC; 178 183 179 184 … … 181 186 -- on IO-Bank 3 182 187 ------------------------------------------------------------------------------- 183 Busy0 : in STD_LOGIC;184 Busy1 : in STD_LOGIC;185 Busy2 : in STD_LOGIC;186 Busy3 : in STD_LOGIC;188 -- Busy0 : in STD_LOGIC; 189 -- Busy1 : in STD_LOGIC; 190 -- Busy2 : in STD_LOGIC; 191 -- Busy3 : in STD_LOGIC; 187 192 188 193 … … 207 212 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage 208 213 ------------------------------------------------------------------------------- 209 RES_p : out STD_LOGIC; -- RES+ Reset210 RES_n : out STD_LOGIC; -- RES- IO-Bank 0211 212 TRG_p : out STD_LOGIC; -- TRG+ Trigger213 TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0214 215 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker216 TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2217 TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2214 -- RES_p : out STD_LOGIC; -- RES+ Reset 215 -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 216 217 -- TRG_p : out STD_LOGIC; -- TRG+ Trigger 218 -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 219 220 -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker 221 -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 222 -- TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 218 223 219 224 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA … … 225 230 -- to connector J13 226 231 -- for light pulsar in the mirror dish 227 Cal_0_p : out STD_LOGIC;228 Cal_0_n : out STD_LOGIC;229 Cal_1_p : out STD_LOGIC;230 Cal_1_n : out STD_LOGIC;231 Cal_2_p : out STD_LOGIC;232 Cal_2_n : out STD_LOGIC;233 Cal_3_p : out STD_LOGIC;234 Cal_3_n : out STD_LOGIC;232 -- Cal_0_p : out STD_LOGIC; 233 -- Cal_0_n : out STD_LOGIC; 234 -- Cal_1_p : out STD_LOGIC; 235 -- Cal_1_n : out STD_LOGIC; 236 -- Cal_2_p : out STD_LOGIC; 237 -- Cal_2_n : out STD_LOGIC; 238 -- Cal_3_p : out STD_LOGIC; 239 -- Cal_3_n : out STD_LOGIC; 235 240 236 241 -- to connector J12 237 242 -- for light pulsar inside shutter 238 Cal_4_p : out STD_LOGIC;239 Cal_4_n : out STD_LOGIC;240 Cal_5_p : out STD_LOGIC;241 Cal_5_n : out STD_LOGIC;242 Cal_6_p : out STD_LOGIC;243 Cal_6_n : out STD_LOGIC;244 Cal_7_p : out STD_LOGIC;245 Cal_7_n : out STD_LOGIC243 -- Cal_4_p : out STD_LOGIC; 244 -- Cal_4_n : out STD_LOGIC; 245 -- Cal_5_p : out STD_LOGIC; 246 -- Cal_5_n : out STD_LOGIC; 247 -- Cal_6_p : out STD_LOGIC; 248 -- Cal_6_n : out STD_LOGIC; 249 -- Cal_7_p : out STD_LOGIC; 250 -- Cal_7_n : out STD_LOGIC 246 251 247 252 … … 262 267 architecture Behavioral of FTM_top is 263 268 269 signal cc_R0_sig : std_logic_vector(31 DOWNTO 0); 270 signal cc_R1_sig : std_logic_vector(31 DOWNTO 0); 271 signal cc_R11_sig : std_logic_vector(31 DOWNTO 0); 272 signal cc_R13_sig : std_logic_vector(31 DOWNTO 0); 273 signal cc_R14_sig : std_logic_vector(31 DOWNTO 0); 274 signal cc_R15_sig : std_logic_vector(31 DOWNTO 0); 275 signal cc_R8_sig : std_logic_vector(31 DOWNTO 0); 276 signal cc_R9_sig : std_logic_vector(31 DOWNTO 0); 277 signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0); 278 signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0); 279 signal dead_time_sig : std_logic_vector(15 DOWNTO 0); 280 signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0); 281 signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0); 282 signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0); 283 signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0); 284 signal general_settings_sig : std_logic_vector(15 DOWNTO 0); 285 signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0); 286 signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0); 287 signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0); 288 signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0); 289 signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0); 290 signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0); 291 signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0); 292 signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0); 293 signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); 294 signal sd_busy_sig : std_logic; 295 signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); 296 signal sd_read_ftu_sig : std_logic; 297 signal sd_ready_sig : std_logic; 298 signal sd_started_ftu_sig : std_logic := '0'; 299 signal new_config_sig : std_logic := '0'; 300 signal config_started_sig : std_logic := '0'; 301 signal config_start_eth_sig : std_logic := '0'; 302 signal config_started_eth_sig : std_logic := '0'; 303 signal config_ready_eth_sig : std_logic := '0'; 304 signal config_started_ack_sig : std_logic := '0'; 305 signal ping_ftu_start_sig : std_logic := '0'; 306 signal ping_ftu_started_sig : std_logic := '0'; 307 signal ping_ftu_ready_sig : std_logic := '0'; 308 signal config_start_ftu_sig : std_logic := '0'; 309 signal config_started_ftu_sig : std_logic := '0'; 310 signal config_ready_ftu_sig : std_logic := '0'; 311 signal rates_ftu_start_sig : std_logic := '0'; 312 signal rates_ftu_started_sig : std_logic := '0'; 313 signal rates_ftu_ready_sig : std_logic := '0'; 314 signal fl_busy_sig : std_logic; 315 signal fl_ready_sig : std_logic; 316 signal fl_write_sig : std_logic := '0'; 317 signal fl_started_ftu_sig : std_logic := '0'; 318 signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); 319 signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); 320 signal ping_ftu_start_ftu_sig : std_logic := '0'; 321 signal ping_ftu_started1_sig : std_logic := '0'; 322 signal ping_ftu_ready1_sig : std_logic := '0'; 323 signal dd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); 324 signal dd_busy_sig : std_logic; 325 signal dd_data_in_ftu_sig : std_logic_vector(15 DOWNTO 0); 326 signal dd_ready_sig : std_logic; 327 signal dd_started_ftu_sig : std_logic := '0'; 328 signal dd_write_ftu_sig : std_logic; 329 signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); 330 signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); 331 332 signal clk_buf_sig : std_logic; 333 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider 334 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM 335 signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM 336 signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM 337 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked 338 339 signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up 340 341 signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); 342 343 component FTM_clk_gen 344 port( 345 clk : IN STD_LOGIC; 346 rst : IN STD_LOGIC; 347 clk_1 : OUT STD_LOGIC; 348 clk_50 : OUT STD_LOGIC; 349 clk_250 : OUT STD_LOGIC; 350 clk_250_ps : OUT STD_LOGIC; 351 ready : OUT STD_LOGIC 352 ); 353 end component; 354 355 component FTM_central_control 356 port( 357 clk : IN std_logic ; 358 new_config : IN std_logic ; 359 config_started : OUT std_logic := '0'; 360 config_started_ack : IN std_logic ; 361 config_start_eth : OUT std_logic := '0'; 362 config_started_eth : IN std_logic ; 363 config_ready_eth : IN std_logic ; 364 config_start_ftu : OUT std_logic := '0'; 365 config_started_ftu : IN std_logic ; 366 config_ready_ftu : IN std_logic ; 367 ping_ftu_start : IN std_logic ; 368 ping_ftu_started : OUT std_logic := '0'; 369 ping_ftu_ready : OUT std_logic := '0'; 370 ping_ftu_start_ftu : OUT std_logic := '0'; 371 ping_ftu_started_ftu : IN std_logic ; 372 ping_ftu_ready_ftu : IN std_logic 373 ); 374 end component; 375 376 component FTM_ftu_control 377 port( 378 clk_50MHz : in std_logic; 379 rx_en : out STD_LOGIC; 380 tx_en : out STD_LOGIC; 381 rx_d_0 : in STD_LOGIC; 382 tx_d_0 : out STD_LOGIC; 383 rx_d_1 : in STD_LOGIC; 384 tx_d_1 : out STD_LOGIC; 385 rx_d_2 : in STD_LOGIC; 386 tx_d_2 : out STD_LOGIC; 387 rx_d_3 : in STD_LOGIC; 388 tx_d_3 : out STD_LOGIC; 389 new_config : in std_logic; 390 ping_all : in std_logic; 391 read_rates : in std_logic; 392 read_rates_started : out std_logic := '0'; 393 read_rates_done : out std_logic := '0'; 394 new_config_started : out std_logic := '0'; 395 new_config_done : out std_logic := '0'; 396 ping_all_started : out std_logic := '0'; 397 ping_all_done : out std_logic := '0'; 398 ftu_active_cr0 : in std_logic_vector (15 downto 0); 399 ftu_active_cr1 : in std_logic_vector (15 downto 0); 400 ftu_active_cr2 : in std_logic_vector (15 downto 0); 401 ftu_active_cr3 : in std_logic_vector (15 downto 0); 402 static_RAM_busy : in std_logic; 403 static_RAM_started : in std_logic; 404 static_RAM_ready : in std_logic; 405 data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0'); 406 read_static_RAM : out std_logic := '0'; 407 addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0'); 408 dynamic_RAM_busy : in std_logic; 409 dynamic_RAM_started : in std_logic; 410 dynamic_RAM_ready : in std_logic; 411 data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0'); 412 write_dynamic_RAM : out std_logic := '0'; 413 addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0'); 414 FTUlist_RAM_busy : in std_logic; 415 FTUlist_RAM_started : in std_logic; 416 FTUlist_RAM_ready : in std_logic; 417 data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0'); 418 write_FTUlist_RAM : out std_logic := '0'; 419 addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0') 420 ); 421 end component; 422 423 component ethernet_modul 424 port( 425 wiz_reset : OUT std_logic := '1'; 426 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 427 wiz_data : INOUT std_logic_vector (15 DOWNTO 0); 428 wiz_cs : OUT std_logic := '1'; 429 wiz_wr : OUT std_logic := '1'; 430 wiz_rd : OUT std_logic := '1'; 431 wiz_int : IN std_logic ; 432 clk : IN std_logic ; 433 sd_ready : OUT std_logic ; 434 sd_busy : OUT std_logic ; 435 led : OUT std_logic_vector (7 DOWNTO 0); 436 sd_read_ftu : IN std_logic ; 437 sd_started_ftu : OUT std_logic := '0'; 438 cc_R0 : OUT std_logic_vector (31 DOWNTO 0); 439 cc_R1 : OUT std_logic_vector (31 DOWNTO 0); 440 cc_R11 : OUT std_logic_vector (31 DOWNTO 0); 441 cc_R13 : OUT std_logic_vector (31 DOWNTO 0); 442 cc_R14 : OUT std_logic_vector (31 DOWNTO 0); 443 cc_R15 : OUT std_logic_vector (31 DOWNTO 0); 444 cc_R8 : OUT std_logic_vector (31 DOWNTO 0); 445 cc_R9 : OUT std_logic_vector (31 DOWNTO 0); 446 coin_n_c : OUT std_logic_vector (15 DOWNTO 0); 447 coin_n_p : OUT std_logic_vector (15 DOWNTO 0); 448 dead_time : OUT std_logic_vector (15 DOWNTO 0); 449 general_settings : OUT std_logic_vector (15 DOWNTO 0); 450 lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); 451 lp1_delay : OUT std_logic_vector (15 DOWNTO 0); 452 lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); 453 lp2_delay : OUT std_logic_vector (15 DOWNTO 0); 454 lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); 455 lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); 456 timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); 457 trigger_delay : OUT std_logic_vector (15 DOWNTO 0); 458 sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 459 sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 460 ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); 461 ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); 462 ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); 463 ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); 464 new_config : OUT std_logic := '0'; 465 config_started : IN std_logic ; 466 config_start_eth : IN std_logic ; 467 config_started_eth : OUT std_logic := '0'; 468 config_ready_eth : OUT std_logic := '0'; 469 config_started_ack : OUT std_logic := '0'; 470 fl_busy : OUT std_logic ; 471 fl_ready : OUT std_logic ; 472 fl_write_ftu : IN std_logic ; 473 fl_started_ftu : OUT std_logic := '0'; 474 fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 475 fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); 476 ping_ftu_start : OUT std_logic := '0'; 477 ping_ftu_started : IN std_logic ; 478 ping_ftu_ready : IN std_logic ; 479 dd_write_ftu : IN std_logic ; 480 dd_started_ftu : OUT std_logic := '0'; 481 dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); 482 dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); 483 dd_busy : OUT std_logic ; 484 dd_ready : OUT std_logic ; 485 coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); 486 coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') 487 ); 488 end component; 489 264 490 begin 491 492 -- IBUFG: Single-ended global clock input buffer 493 -- Spartan-3A 494 -- Xilinx HDL Language Template, version 11.4 495 496 IBUFG_inst : IBUFG 497 generic map ( 498 IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, 499 -- "0"-"16" 500 IOSTANDARD => "DEFAULT") 501 port map ( 502 O => clk_buf_sig, -- Clock buffer output 503 I => clk -- Clock buffer input (connect directly to top-level port) 504 ); 505 506 Inst_FTM_clk_gen : FTM_clk_gen 507 port map( 508 clk => clk_buf_sig, 509 rst => reset_sig, 510 clk_1 => clk_1M_sig, 511 clk_50 => clk_50M_sig, 512 clk_250 => clk_250M_sig, 513 clk_250_ps => clk_250M_ps_sig, 514 ready => clk_ready_sig 515 ); 516 517 Inst_FTM_central_control : FTM_central_control 518 port map( 519 clk => clk_50M_sig, 520 new_config => new_config_sig, 521 config_started => config_started_sig, 522 config_started_ack => config_started_ack_sig, 523 config_start_eth => config_start_eth_sig, 524 config_started_eth => config_started_eth_sig, 525 config_ready_eth => config_ready_eth_sig, 526 config_start_ftu => config_start_ftu_sig, 527 config_started_ftu => config_started_ftu_sig, 528 config_ready_ftu => config_ready_ftu_sig, 529 ping_ftu_start => ping_ftu_start_sig, 530 ping_ftu_started => ping_ftu_started_sig, 531 ping_ftu_ready => ping_ftu_ready_sig, 532 ping_ftu_start_ftu => ping_ftu_start_ftu_sig, 533 ping_ftu_started_ftu => ping_ftu_started1_sig, 534 ping_ftu_ready_ftu => ping_ftu_ready1_sig 535 ); 536 537 Inst_FTM_ftu_control : FTM_ftu_control 538 port map( 539 clk_50MHz => clk_50M_sig, 540 rx_en => Bus1_Rx_En, 541 tx_en => Bus1_Tx_En, 542 rx_d_0 => Bus1_RxD_0, 543 tx_d_0 => Bus1_TxD_0, 544 rx_d_1 => Bus1_RxD_1, 545 tx_d_1 => Bus1_TxD_1, 546 rx_d_2 => Bus1_RxD_2, 547 tx_d_2 => Bus1_TxD_2, 548 rx_d_3 => Bus1_RxD_3, 549 tx_d_3 => Bus1_TxD_3, 550 new_config => config_start_ftu_sig, 551 ping_all => ping_ftu_start_ftu_sig, 552 read_rates => rates_ftu_start_sig, 553 read_rates_started => rates_ftu_started_sig, 554 read_rates_done => rates_ftu_ready_sig, 555 new_config_started => config_started_ftu_sig, 556 new_config_done => config_ready_ftu_sig, 557 ping_all_started => ping_ftu_started1_sig, 558 ping_all_done => ping_ftu_ready1_sig, 559 ftu_active_cr0 => ftu_active_cr0_sig, 560 ftu_active_cr1 => ftu_active_cr1_sig, 561 ftu_active_cr2 => ftu_active_cr2_sig, 562 ftu_active_cr3 => ftu_active_cr3_sig, 563 static_RAM_busy => sd_busy_sig, 564 static_RAM_started => sd_started_ftu_sig, 565 static_RAM_ready => sd_ready_sig, 566 data_static_RAM => sd_data_out_ftu_sig, 567 read_static_RAM => sd_read_ftu_sig, 568 addr_static_RAM => sd_addr_ftu_sig, 569 dynamic_RAM_busy => dd_busy_sig, 570 dynamic_RAM_started => dd_started_ftu_sig, 571 dynamic_RAM_ready => dd_ready_sig, 572 data_dynamic_RAM => dd_data_in_ftu_sig, 573 write_dynamic_RAM => dd_write_ftu_sig, 574 addr_dynamic_RAM => dd_addr_ftu_sig, 575 FTUlist_RAM_busy => fl_busy_sig, 576 FTUlist_RAM_started => fl_started_ftu_sig, 577 FTUlist_RAM_ready => fl_ready_sig, 578 data_FTUlist_RAM => fl_data_sig, 579 write_FTUlist_RAM => fl_write_sig, 580 addr_FTUlist_RAM => fl_addr_sig 581 ); 582 583 Inst_ethernet_modul : ethernet_modul 584 port map( 585 wiz_reset => W_RES, 586 wiz_addr => W_A, 587 wiz_data => W_D, 588 wiz_cs => W_CS, 589 wiz_wr => W_WR, 590 wiz_rd => W_RD, 591 wiz_int => W_INT, 592 clk => clk_50M_sig, 593 sd_ready => sd_ready_sig, 594 sd_busy => sd_busy_sig, 595 led => led_sig, 596 sd_read_ftu => sd_read_ftu_sig, 597 sd_started_ftu => sd_started_ftu_sig, 598 cc_R0 => cc_R0_sig, 599 cc_R1 => cc_R1_sig, 600 cc_R11 => cc_R11_sig, 601 cc_R13 => cc_R13_sig, 602 cc_R14 => cc_R14_sig, 603 cc_R15 => cc_R15_sig, 604 cc_R8 => cc_R8_sig, 605 cc_R9 => cc_R9_sig, 606 coin_n_c => coin_n_c_sig, 607 coin_n_p => coin_n_p_sig, 608 dead_time => dead_time_sig, 609 general_settings => general_settings_sig, 610 lp1_amplitude => lp1_amplitude_sig, 611 lp1_delay => lp1_delay_sig, 612 lp2_amplitude => lp2_amplitude_sig, 613 lp2_delay => lp2_delay_sig, 614 lp_pt_freq => lp_pt_freq_sig, 615 lp_pt_ratio => lp_pt_ratio_sig, 616 timemarker_delay => timemarker_delay_sig, 617 trigger_delay => trigger_delay_sig, 618 sd_addr_ftu => sd_addr_ftu_sig, 619 sd_data_out_ftu => sd_data_out_ftu_sig, 620 ftu_active_cr0 => ftu_active_cr0_sig, 621 ftu_active_cr1 => ftu_active_cr1_sig, 622 ftu_active_cr2 => ftu_active_cr2_sig, 623 ftu_active_cr3 => ftu_active_cr3_sig, 624 new_config => new_config_sig, 625 config_started => config_started_sig, 626 config_start_eth => config_start_eth_sig, 627 config_started_eth => config_started_eth_sig, 628 config_ready_eth => config_ready_eth_sig, 629 config_started_ack => config_started_ack_sig, 630 fl_busy => fl_busy_sig, 631 fl_ready => fl_ready_sig, 632 fl_write_ftu => fl_write_sig, 633 fl_started_ftu => fl_started_ftu_sig, 634 fl_addr_ftu => fl_addr_sig, 635 fl_data_in_ftu => fl_data_sig, 636 ping_ftu_start => ping_ftu_start_sig, 637 ping_ftu_started => ping_ftu_started_sig, 638 ping_ftu_ready => ping_ftu_ready_sig, 639 dd_write_ftu => dd_write_ftu_sig, 640 dd_started_ftu => dd_started_ftu_sig, 641 dd_data_in_ftu => dd_data_in_ftu_sig, 642 dd_addr_ftu => dd_addr_ftu_sig, 643 dd_busy => dd_busy_sig, 644 dd_ready => dd_ready_sig, 645 coin_win_c => coin_win_c_sig, 646 coin_win_p => coin_win_p_sig 647 ); 648 649 LED_red <= led_sig(3 downto 0); 650 LED_ye <= led_sig(5 downto 4); 651 LED_gn <= led_sig(7 downto 6); 265 652 266 653 end Behavioral; -
firmware/FTM/FTM_top_tb.vhd
r10127 r10227 53 53 54 54 -- W5300 address bus 55 W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NOnet W_A0 because55 W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because 56 56 -- the W5300 is operated in the 57 -- 16-bit mode 57 -- 16-bit mode 58 -- -> W_A<0> assigned to unconnected pin 58 59 59 60 -- W5300 control signals … … 67 68 68 69 -- W5300 buffer ready indicator 69 W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);70 -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); 70 71 71 72 -- testpoints (T18) associated with the W5300 72 W_T : inout STD_LOGIC_VECTOR(3 downto 0);73 -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); 73 74 74 75 … … 77 78 -- temperature sensors U45, U46, U48 and U49 (all MAX6662) 78 79 ------------------------------------------------------------------------------- 79 S_CLK : out STD_LOGIC; -- SPI clock80 -- S_CLK : out STD_LOGIC; -- SPI clock 80 81 81 82 -- EEPROM … … 85 86 86 87 -- temperature sensors U45, U46, U48 and U49 87 SIO : inout STD_LOGIC; -- serial IO88 TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select88 -- SIO : inout STD_LOGIC; -- serial IO 89 -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select 89 90 90 91 91 92 -- Trigger primitives inputs 92 93 ------------------------------------------------------------------------------- 93 Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 094 Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 195 Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 296 Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 394 -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 95 -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 96 -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 97 -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 97 98 98 99 99 100 -- NIM inputs 100 101 ------------------------------------------------------------------------------ 101 ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input102 Veto : in STD_LOGIC; -- trigger veto input103 NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs102 -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input 103 -- Veto : in STD_LOGIC; -- trigger veto input 104 -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs 104 105 105 106 -- alternative external clock input for FPGA 106 NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available107 -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available 107 108 108 109 … … 116 117 -- Clock conditioner LMK03000 117 118 ------------------------------------------------------------------------------- 118 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock119 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable120 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data119 -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock 120 -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable 121 -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data 121 122 122 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization123 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for123 -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization 124 -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for 124 125 125 126 … … 140 141 141 142 Bus1_RxD_3 : in STD_LOGIC; -- crate 3 142 Bus1_TxD_3 : out STD_LOGIC ;143 Bus1_TxD_3 : out STD_LOGIC 143 144 144 145 145 146 -- Bus 2: Trigger-ID to FAD boards 146 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable147 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable148 149 Bus2_RxD_0 : in STD_LOGIC; -- crate 0150 Bus2_TxD_0 : out STD_LOGIC;151 152 Bus2_RxD_1 : in STD_LOGIC; -- crate 1153 Bus2_TxD_1 : out STD_LOGIC;154 155 Bus2_RxD_2 : in STD_LOGIC; -- crate 2156 Bus2_TxD_2 : out STD_LOGIC;157 158 Bus2_RxD_3 : in STD_LOGIC; -- crate 3159 Bus2_TxD_3 : out STD_LOGIC;147 -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable 148 -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable 149 150 -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 151 -- Bus2_TxD_0 : out STD_LOGIC; 152 153 -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 154 -- Bus2_TxD_1 : out STD_LOGIC; 155 156 -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 157 -- Bus2_TxD_2 : out STD_LOGIC; 158 159 -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 160 -- Bus2_TxD_3 : out STD_LOGIC; 160 161 161 162 … … 174 175 -- Crate-Resets 175 176 ------------------------------------------------------------------------------- 176 Crate_Res0 : out STD_LOGIC;177 Crate_Res1 : out STD_LOGIC;178 Crate_Res2 : out STD_LOGIC;179 Crate_Res3 : out STD_LOGIC;177 -- Crate_Res0 : out STD_LOGIC; 178 -- Crate_Res1 : out STD_LOGIC; 179 -- Crate_Res2 : out STD_LOGIC; 180 -- Crate_Res3 : out STD_LOGIC; 180 181 181 182 182 183 -- Busy signals from the FAD boards 183 184 ------------------------------------------------------------------------------- 184 Busy0 : in STD_LOGIC;185 Busy1 : in STD_LOGIC;186 Busy2 : in STD_LOGIC;187 Busy3 : in STD_LOGIC;185 -- Busy0 : in STD_LOGIC; 186 -- Busy1 : in STD_LOGIC; 187 -- Busy2 : in STD_LOGIC; 188 -- Busy3 : in STD_LOGIC; 188 189 189 190 … … 207 208 -- LVDS output at the FPGA followed by LVDS to NIM conversion stage 208 209 ------------------------------------------------------------------------------- 209 RES_p : out STD_LOGIC; -- RES+ Reset210 RES_n : out STD_LOGIC; -- RES-211 212 TRG_p : out STD_LOGIC; -- TRG+ Trigger213 TRG_n : out STD_LOGIC; -- TRG-214 215 TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker216 TIM_Run_n : out STD_LOGIC; -- TIM_Run-217 TIM_Sel : out STD_LOGIC; -- Time Marker selector210 -- RES_p : out STD_LOGIC; -- RES+ Reset 211 -- RES_n : out STD_LOGIC; -- RES- 212 213 -- TRG_p : out STD_LOGIC; -- TRG+ Trigger 214 -- TRG_n : out STD_LOGIC; -- TRG- 215 216 -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker 217 -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- 218 -- TIM_Sel : out STD_LOGIC; -- Time Marker selector 218 219 219 220 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA … … 224 225 -- to connector J13 225 226 -- for light pulsar in the mirror dish 226 Cal_0_p : out STD_LOGIC;227 Cal_0_n : out STD_LOGIC;228 Cal_1_p : out STD_LOGIC;229 Cal_1_n : out STD_LOGIC;230 Cal_2_p : out STD_LOGIC;231 Cal_2_n : out STD_LOGIC;232 Cal_3_p : out STD_LOGIC;233 Cal_3_n : out STD_LOGIC;227 -- Cal_0_p : out STD_LOGIC; 228 -- Cal_0_n : out STD_LOGIC; 229 -- Cal_1_p : out STD_LOGIC; 230 -- Cal_1_n : out STD_LOGIC; 231 -- Cal_2_p : out STD_LOGIC; 232 -- Cal_2_n : out STD_LOGIC; 233 -- Cal_3_p : out STD_LOGIC; 234 -- Cal_3_n : out STD_LOGIC; 234 235 235 236 -- to connector J12 236 237 -- for light pulsar inside shutter 237 Cal_4_p : out STD_LOGIC;238 Cal_4_n : out STD_LOGIC;239 Cal_5_p : out STD_LOGIC;240 Cal_5_n : out STD_LOGIC;241 Cal_6_p : out STD_LOGIC;242 Cal_6_n : out STD_LOGIC;243 Cal_7_p : out STD_LOGIC;244 Cal_7_n : out STD_LOGIC238 -- Cal_4_p : out STD_LOGIC; 239 -- Cal_4_n : out STD_LOGIC; 240 -- Cal_5_p : out STD_LOGIC; 241 -- Cal_5_n : out STD_LOGIC; 242 -- Cal_6_p : out STD_LOGIC; 243 -- Cal_6_n : out STD_LOGIC; 244 -- Cal_7_p : out STD_LOGIC; 245 -- Cal_7_n : out STD_LOGIC 245 246 246 247 … … 291 292 292 293 --Outputs 293 signal W_A_sig : STD_LOGIC_VECTOR(9 downto 1);294 signal W_A_sig : STD_LOGIC_VECTOR(9 downto 0); 294 295 signal W_CS_sig : STD_LOGIC; 295 296 signal W_RD_sig : STD_LOGIC; … … 361 362 W_WR => W_WR_sig, 362 363 W_RES => W_RES_sig, 363 W_BRDY => W_BRDY_sig,364 W_T => W_T_sig,365 S_CLK => S_CLK_sig,366 SIO => SIO_sig,367 TS_CS => TS_CS_sig,368 Trig_Prim_A => Trig_Prim_A_sig,369 Trig_Prim_B => Trig_Prim_B_sig,370 Trig_Prim_C => Trig_Prim_C_sig,371 Trig_Prim_D => Trig_Prim_D_sig,372 ext_Trig => ext_Trig_sig,373 Veto => Veto_sig,374 NIM_In => NIM_In_sig,375 NIM_In3_GCLK => NIM_In3_GCLK_sig,364 -- W_BRDY => W_BRDY_sig, 365 -- W_T => W_T_sig, 366 -- S_CLK => S_CLK_sig, 367 -- SIO => SIO_sig, 368 -- TS_CS => TS_CS_sig, 369 -- Trig_Prim_A => Trig_Prim_A_sig, 370 -- Trig_Prim_B => Trig_Prim_B_sig, 371 -- Trig_Prim_C => Trig_Prim_C_sig, 372 -- Trig_Prim_D => Trig_Prim_D_sig, 373 -- ext_Trig => ext_Trig_sig, 374 -- Veto => Veto_sig, 375 -- NIM_In => NIM_In_sig, 376 -- NIM_In3_GCLK => NIM_In3_GCLK_sig, 376 377 LED_red => LED_red_sig, 377 378 LED_ye => LED_ye_sig, 378 379 LED_gn => LED_gn_sig, 379 CLK_Clk_Cond => CLK_Clk_Cond_sig,380 LE_Clk_Cond => LE_Clk_Cond_sig,381 DATA_Clk_Cond => DATA_Clk_Cond_sig,382 SYNC_Clk_Cond => SYNC_Clk_Cond_sig,383 LD_Clk_Cond => LD_Clk_Cond_sig,380 -- CLK_Clk_Cond => CLK_Clk_Cond_sig, 381 -- LE_Clk_Cond => LE_Clk_Cond_sig, 382 -- DATA_Clk_Cond => DATA_Clk_Cond_sig, 383 -- SYNC_Clk_Cond => SYNC_Clk_Cond_sig, 384 -- LD_Clk_Cond => LD_Clk_Cond_sig, 384 385 Bus1_Tx_En => Bus1_Tx_En_sig, 385 386 Bus1_Rx_En => Bus1_Rx_En_sig, … … 391 392 Bus1_TxD_2 => Bus1_TxD_2_sig, 392 393 Bus1_RxD_3 => Bus1_RxD_3_sig, 393 Bus1_TxD_3 => Bus1_TxD_3_sig ,394 Bus2_Tx_En => Bus2_Tx_En_sig,395 Bus2_Rx_En => Bus2_Rx_En_sig,396 Bus2_RxD_0 => Bus2_RxD_0_sig,397 Bus2_TxD_0 => Bus2_TxD_0_sig,398 Bus2_RxD_1 => Bus2_RxD_1_sig,399 Bus2_TxD_1 => Bus2_TxD_1_sig,400 Bus2_RxD_2 => Bus2_RxD_2_sig,401 Bus2_TxD_2 => Bus2_TxD_2_sig,402 Bus2_RxD_3 => Bus2_RxD_3_sig,403 Bus2_TxD_3 => Bus2_TxD_3_sig,404 Crate_Res0 => Crate_Res0_sig,405 Crate_Res1 => Crate_Res1_sig,406 Crate_Res2 => Crate_Res2_sig,407 Crate_Res3 => Crate_Res3_sig,408 Busy0 => Busy0_sig,409 Busy1 => Busy1_sig,410 Busy2 => Busy2_sig,411 Busy3 => Busy3_sig,412 RES_p => RES_p_sig,413 RES_n => RES_n_sig,414 TRG_p => TRG_p_sig,415 TRG_n => TRG_n_sig,416 TIM_Run_p => TIM_Run_p_sig,417 TIM_Run_n => TIM_Run_n_sig,418 TIM_Sel => TIM_Sel_sig,419 Cal_0_p => Cal_0_p_sig,420 Cal_0_n => Cal_0_n_sig,421 Cal_1_p => Cal_1_p_sig,422 Cal_1_n => Cal_1_n_sig,423 Cal_2_p => Cal_2_p_sig,424 Cal_2_n => Cal_2_n_sig,425 Cal_3_p => Cal_3_p_sig,426 Cal_3_n => Cal_3_n_sig,427 Cal_4_p => Cal_4_p_sig,428 Cal_4_n => Cal_4_n_sig,429 Cal_5_p => Cal_5_p_sig,430 Cal_5_n => Cal_5_n_sig,431 Cal_6_p => Cal_6_p_sig,432 Cal_6_n => Cal_6_n_sig,433 Cal_7_p => Cal_7_p_sig,434 Cal_7_n => Cal_7_n_sig394 Bus1_TxD_3 => Bus1_TxD_3_sig 395 -- Bus2_Tx_En => Bus2_Tx_En_sig, 396 -- Bus2_Rx_En => Bus2_Rx_En_sig, 397 -- Bus2_RxD_0 => Bus2_RxD_0_sig, 398 -- Bus2_TxD_0 => Bus2_TxD_0_sig, 399 -- Bus2_RxD_1 => Bus2_RxD_1_sig, 400 -- Bus2_TxD_1 => Bus2_TxD_1_sig, 401 -- Bus2_RxD_2 => Bus2_RxD_2_sig, 402 -- Bus2_TxD_2 => Bus2_TxD_2_sig, 403 -- Bus2_RxD_3 => Bus2_RxD_3_sig, 404 -- Bus2_TxD_3 => Bus2_TxD_3_sig, 405 -- Crate_Res0 => Crate_Res0_sig, 406 -- Crate_Res1 => Crate_Res1_sig, 407 -- Crate_Res2 => Crate_Res2_sig, 408 -- Crate_Res3 => Crate_Res3_sig, 409 -- Busy0 => Busy0_sig, 410 -- Busy1 => Busy1_sig, 411 -- Busy2 => Busy2_sig, 412 -- Busy3 => Busy3_sig, 413 -- RES_p => RES_p_sig, 414 -- RES_n => RES_n_sig, 415 -- TRG_p => TRG_p_sig, 416 -- TRG_n => TRG_n_sig, 417 -- TIM_Run_p => TIM_Run_p_sig, 418 -- TIM_Run_n => TIM_Run_n_sig, 419 -- TIM_Sel => TIM_Sel_sig, 420 -- Cal_0_p => Cal_0_p_sig, 421 -- Cal_0_n => Cal_0_n_sig, 422 -- Cal_1_p => Cal_1_p_sig, 423 -- Cal_1_n => Cal_1_n_sig, 424 -- Cal_2_p => Cal_2_p_sig, 425 -- Cal_2_n => Cal_2_n_sig, 426 -- Cal_3_p => Cal_3_p_sig, 427 -- Cal_3_n => Cal_3_n_sig, 428 -- Cal_4_p => Cal_4_p_sig, 429 -- Cal_4_n => Cal_4_n_sig, 430 -- Cal_5_p => Cal_5_p_sig, 431 -- Cal_5_n => Cal_5_n_sig, 432 -- Cal_6_p => Cal_6_p_sig, 433 -- Cal_6_n => Cal_6_n_sig, 434 -- Cal_7_p => Cal_7_p_sig, 435 -- Cal_7_n => Cal_7_n_sig 435 436 ); 436 437 -
firmware/FTM/ftm_board.ucf
r10067 r10227 5 5 # Pin location constraints 6 6 # 7 # by Patrick Vogler 8 # 18 August 2010 7 # by Patrick Vogler, 18 August 2010 8 # 9 # modified by Q. Weitzel, 01 March 2011 10 # (NET W_A<0> added and assigned to unconnected pin) 9 11 ######################################################## 10 12 … … 38 40 39 41 # W5300 address bus 40 NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because 41 NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode 42 NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet 42 NET W_A<0> LOC = U18 | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because 43 NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode 44 NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # (see W5300 datasheet) 45 NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin 43 46 NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # 44 47 NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # … … 58 61 59 62 # W5300 buffer ready indicator 60 NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #61 NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; #62 NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; #63 NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #63 # NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # 64 # NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # 65 # NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # 66 # NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # 64 67 65 68 # W5300 associated testpoints 66 NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; #67 NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #68 NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; #69 NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #69 # NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # 70 # NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # 71 # NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # 72 # NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # 70 73 71 74 … … 75 78 # on IO-Bank 1 76 79 ####################################################### 77 NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock80 # NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock 78 81 79 82 # EEPROM 80 NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in81 NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out82 NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in83 # NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in 84 # NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out 85 # NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in 83 86 84 87 # temperature sensors 85 NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO86 NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select087 NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select188 NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select289 NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select388 # NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO 89 # NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 90 # NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 91 # NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 92 # NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 90 93 91 94 … … 95 98 # crate 0 96 99 # crate A 97 NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>98 NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>99 NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>100 NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>101 NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>102 NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>103 NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>104 NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>105 NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>106 NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>100 # NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> 101 # NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> 102 # NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> 103 # NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> 104 # NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> 105 # NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> 106 # NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> 107 # NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> 108 # NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> 109 # NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> 107 110 108 111 # crate 1 109 112 # crate B 110 NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>111 NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>112 NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>113 NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>114 NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>115 NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>116 NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>117 NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>118 NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>119 NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>113 # NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> 114 # NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> 115 # NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> 116 # NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> 117 # NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> 118 # NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> 119 # NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> 120 # NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> 121 # NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> 122 # NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> 120 123 121 124 # crate 2 122 125 # crate C 123 NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>124 NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>125 NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>126 NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>127 NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>128 NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>129 NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>130 NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>131 NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>132 NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>126 # NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> 127 # NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> 128 # NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> 129 # NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> 130 # NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> 131 # NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> 132 # NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> 133 # NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> 134 # NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> 135 # NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> 133 136 134 137 # crate 3 135 138 # crate D 136 NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>137 NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>138 NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>139 NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>140 NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>141 NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>142 NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>143 NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>144 NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>145 NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>139 # NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> 140 # NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> 141 # NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> 142 # NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> 143 # NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> 144 # NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> 145 # NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> 146 # NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> 147 # NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> 148 # NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> 146 149 147 150 … … 149 152 ####################################################### 150 153 # on IO-Bank 3 151 NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; #152 NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; #153 NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; #154 NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; #155 NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; #156 NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; #154 # NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # 155 # NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # 156 # NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # 157 # NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # 158 # NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # 159 # NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # 157 160 158 161 # on IO-Bank 0 159 162 # input pin with global clock buffer available 160 NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33;163 # NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; 161 164 162 165 … … 182 185 # on IO-Bank 3 183 186 ####################################################### 184 NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3185 NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3186 NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3187 NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3188 NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3187 # NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 188 # NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 189 # NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 190 # NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 191 # NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 189 192 190 193 … … 214 217 215 218 # Bus 2: Trigger-ID to FAD boards 216 NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #217 NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #219 # NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 220 # NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 218 221 219 222 # crate 0 220 NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #221 NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #223 # NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 224 # NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 222 225 223 226 # crate 1 224 NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #225 NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #227 # NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 228 # NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 226 229 227 230 # crate 2 228 NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #229 NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #231 # NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 232 # NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 230 233 231 234 # crate 3 232 NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #233 NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #235 # NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 236 # NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 234 237 235 238 236 239 # auxiliary access 237 NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #238 NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #239 NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable240 NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID240 # NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 241 # NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 242 # NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable 243 # NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID 241 244 242 245 # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) 243 NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #244 NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #246 # NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 247 # NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 245 248 246 249 … … 248 251 # on IO-Bank 3 249 252 ####################################################### 250 NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #251 NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #252 NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #253 NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #253 # NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 254 # NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 255 # NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 256 # NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 254 257 255 258 … … 257 260 # on IO-Bank 3 258 261 ####################################################### 259 NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #260 NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #261 NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #262 NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #262 # NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 263 # NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 264 # NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 265 # NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 263 266 264 267 … … 269 272 ####################################################### 270 273 # calibration 271 NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+272 NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1-273 NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+274 NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2-274 # NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ 275 # NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- 276 # NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ 277 # NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- 275 278 276 279 # auxiliarry / spare NIM outputs 277 NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+278 NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-279 NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+280 NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-280 # NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ 281 # NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- 282 # NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ 283 # NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- 281 284 282 285 … … 285 288 # conversion stage 286 289 ####################################################### 287 NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset288 NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0289 290 NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger291 NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0292 293 NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker294 NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2295 296 NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2297 298 NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA290 # NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset 291 # NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 292 293 # NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger 294 # NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 295 296 # NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker 297 # NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 298 299 # NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 300 301 # NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA 299 302 300 303 … … 303 306 ####################################################### 304 307 # to connector J13 305 NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+306 NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-307 NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+308 NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-309 NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+310 NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-311 NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+312 NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-308 # NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ 309 # NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- 310 # NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ 311 # NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- 312 # NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ 313 # NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- 314 # NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ 315 # NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- 313 316 314 317 # to connector J12 315 NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+316 NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-317 NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+318 NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-319 NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+320 NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-321 NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+322 NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-318 # NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ 319 # NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- 320 # NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ 321 # NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- 322 # NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ 323 # NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- 324 # NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ 325 # NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- 323 326 324 327 … … 327 330 # Connector T7 328 331 # IO-Bank 0 329 NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; #330 NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; #331 NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; #332 NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; #332 # NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # 333 # NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # 334 # NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # 335 # NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # 333 336 334 337 # Connector T10 335 338 # IO-Bank 0 336 NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; #337 NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; #338 NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; #339 NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; #339 # NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # 340 # NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # 341 # NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # 342 # NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # 340 343 341 344 # on Connector T12 342 345 # IO-Bank 0 343 NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; #344 NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; #346 # NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # 347 # NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # 345 348 346 349 # on Connector T14 347 350 # IO-Bank 0 348 NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; #349 NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; #350 NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; #351 NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; #351 # NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # 352 # NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # 353 # NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # 354 # NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # 352 355 353 356 # on Connector T16 354 357 # IO-Bank 0 355 NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; #356 NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; #357 NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; #358 NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; #358 # NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # 359 # NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # 360 # NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # 361 # NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # 359 362 360 363 # on Connector T8 361 364 # IO-Bank 0 362 NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; #363 NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; #364 NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; #365 NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; #365 # NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # 366 # NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # 367 # NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # 368 # NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # 366 369 367 370 # on Connector T9 368 371 # IO-Bank 0 369 NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; #370 NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; #372 # NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # 373 # NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # 371 374 372 375 # on Connector T11 373 376 # IO-Bank 3 374 NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; #375 NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; #376 NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; #377 NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; #377 # NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # 378 # NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # 379 # NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # 380 # NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # 378 381 379 382 # on Connector T13 380 383 # IO-Bank 3 381 NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; #382 NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; #383 NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; #384 NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; #384 # NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # 385 # NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # 386 # NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # 387 # NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # 385 388 386 389 # on Connector T15 387 NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3388 NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only389 NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only390 # NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 391 # NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only 392 # NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only 390 393 391 394 … … 394 397 # all on 'input only' pins 395 398 ####################################################### 396 NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # 397 NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # 398 NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # 399 NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # 400 NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # 401 NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # 402 NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # 403 NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # 404 399 # NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # 400 # NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # 401 # NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # 402 # NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # 403 # NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # 404 # NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # 405 # NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # 406 # NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # -
firmware/FTM/ftm_definitions.vhd
r10179 r10227 19 19 -- modified: Patrick Vogler, February 17 2011 20 20 -- merged with library file from Dortmund, Q. Weitzel, February 24, 2011 21 -- 22 -- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...), 23 -- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined 21 24 ---------------------------------------------------------------------------------- 22 25 … … 53 56 use IEEE.STD_LOGIC_ARITH.ALL; 54 57 use IEEE.STD_LOGIC_UNSIGNED.ALL; 58 -- for HDL-Designer 59 -- LIBRARY FACT_FTM_lib; 60 -- use FACT_FTM_lib.ftm_array_types.all; 55 61 library ftm_definitions; 56 62 use ftm_definitions.ftm_array_types.all; 57 --use IEEE.NUMERIC_STD.ALL;63 use IEEE.NUMERIC_STD.ALL; 58 64 59 65 package ftm_constants is … … 69 75 constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz 70 76 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz 77 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1 71 78 72 79 --FTM address and firmware ID … … 77 84 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case 78 85 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods) 86 -- constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation 87 -- constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation 79 88 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!! 80 89 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol … … 166 175 167 176 -- FTU-list parameters 168 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249177 constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249 169 178 constant NO_OF_FTU_LIST_REG : integer := 6; 170 179 constant FTU_LIST_RAM_OFFSET : integer := 16#009#; … … 181 190 constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) 182 191 constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block 192 193 -- dynamic data block 194 constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"008"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block 183 195 184 196 -- addresses in static data block … … 212 224 constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B"; 213 225 constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C"; 226 constant SD_ADDR_coin_win_p : std_logic_vector := X"01D"; 227 constant SD_ADDR_coin_win_c : std_logic_vector := X"01E"; 214 228 constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; 215 229 constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; … … 221 235 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0); 222 236 type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0); 237 type sd_block_activeFTUlist_default_array_type is array (0 to (NO_OF_CRATES - 1)) of std_logic_vector (15 downto 0); 223 238 224 239 -- general default values … … 272 287 X"0001" -- Prescaling board x crate y 273 288 ); 289 290 --default values for active FTU lists 291 constant sd_block_activeFTUlist_default_array : sd_block_activeFTUlist_default_array_type := ( 292 X"0001", 293 X"0000", 294 X"0000", 295 X"0000" 296 ); 274 297 275 298 end ftm_constants; -
firmware/FTM/ftu_control/FTM_ftu_control.vhd
r10175 r10227 69 69 ping_all_done : out std_logic := '0'; 70 70 71 -- active FTU lists 72 ftu_active_cr0 : in std_logic_vector (15 downto 0); 73 ftu_active_cr1 : in std_logic_vector (15 downto 0); 74 ftu_active_cr2 : in std_logic_vector (15 downto 0); 75 ftu_active_cr3 : in std_logic_vector (15 downto 0); 76 71 77 -- communication with static (config) RAM 72 78 -- this RAM is only read by FTU_control … … 123 129 124 130 -- global signals after multiplexer 125 signal rx_en_sig : std_logic ;126 signal tx_en_sig : std_logic ;127 signal rx_valid_sig : std_logic ;128 signal tx_busy_sig : std_logic ;129 signal tx_start_sig : std_logic ;130 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) ;131 signal rx_en_sig : std_logic := '0'; 132 signal tx_en_sig : std_logic := '0'; 133 signal rx_valid_sig : std_logic := '0'; 134 signal tx_busy_sig : std_logic := '0'; 135 signal tx_start_sig : std_logic := '0'; 136 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); 131 137 132 138 -- signals for interpreter of FTU communication … … 190 196 191 197 -- various loop counters 192 signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0;198 --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0; 193 199 signal crate_cnt : integer range 0 to NO_OF_CRATES := 0; 194 200 signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0; … … 272 278 type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG, 273 279 PING, PING_END, FTU_LIST, RATES, 274 ACTIVE_LIST_1, ACTIVE_LIST_2, ACTIVE_LIST_3,275 280 READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3, 276 281 TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3, … … 435 440 end if; 436 441 437 when ACTIVE_LIST => -- loop over 4 crates to get active FTU list 438 if (active_FTU_list_cnt < NO_OF_CRATES) then 439 active_FTU_list_cnt <= active_FTU_list_cnt + 1; 440 FTM_ftu_rs485_control_State <= ACTIVE_LIST_1; 441 else 442 active_FTU_list_cnt <= 0; 443 FTM_ftu_rs485_control_State <= READ_CONFIG; 444 end if; 445 446 when ACTIVE_LIST_1 => 447 if (static_RAM_busy = '0') then 448 read_static_RAM <= '1'; 449 addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH); 450 FTM_ftu_rs485_control_State <= ACTIVE_LIST_2; 451 end if; 442 when ACTIVE_LIST => -- copy active FTU list from inputs to array 443 active_FTU_array_sig(0) <= ftu_active_cr0; 444 active_FTU_array_sig(1) <= ftu_active_cr1; 445 active_FTU_array_sig(2) <= ftu_active_cr2; 446 active_FTU_array_sig(3) <= ftu_active_cr3; 447 FTM_ftu_rs485_control_State <= READ_CONFIG; 448 449 -- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list 450 -- if (active_FTU_list_cnt < NO_OF_CRATES) then 451 -- active_FTU_list_cnt <= active_FTU_list_cnt + 1; 452 -- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1; 453 -- else 454 -- active_FTU_list_cnt <= 0; 455 -- FTM_ftu_rs485_control_State <= READ_CONFIG; 456 -- end if; 457 458 -- when ACTIVE_LIST_1 => 459 -- if (static_RAM_busy = '0') then 460 -- read_static_RAM <= '1'; 461 -- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH); 462 -- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2; 463 -- end if; 452 464 453 when ACTIVE_LIST_2 =>454 if (static_RAM_started = '1') then455 FTM_ftu_rs485_control_State <= ACTIVE_LIST_3;456 end if;465 -- when ACTIVE_LIST_2 => 466 -- if (static_RAM_started = '1') then 467 -- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3; 468 -- end if; 457 469 458 when ACTIVE_LIST_3 =>459 if (static_RAM_ready = '1') then460 active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM;461 read_static_RAM <= '0';462 FTM_ftu_rs485_control_State <= ACTIVE_LIST;463 end if;470 -- when ACTIVE_LIST_3 => 471 -- if (static_RAM_ready = '1') then 472 -- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM; 473 -- read_static_RAM <= '0'; 474 -- FTM_ftu_rs485_control_State <= ACTIVE_LIST; 475 -- end if; 464 476 465 477 when READ_CONFIG => -- read configuration of FTUs (one by one) … … 535 547 & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0) 536 548 & "00000000" & FIRMWARE_ID & FTM_ADDRESS 537 & "00" & conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)549 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) 538 550 & FTU_RS485_START_DELIM; 539 FTU_brd_add_sig <= conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);551 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); 540 552 FTU_command_sig <= "00000000"; 541 553 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; … … 552 564 & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0) 553 565 & "00000011" & FIRMWARE_ID & FTM_ADDRESS 554 & "00" & conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)566 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) 555 567 & FTU_RS485_START_DELIM; 556 FTU_brd_add_sig <= conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);568 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); 557 569 FTU_command_sig <= "00000011"; 558 570 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; … … 567 579 & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0) 568 580 & "00000110" & FIRMWARE_ID & FTM_ADDRESS 569 & "00" & conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)581 & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) 570 582 & FTU_RS485_START_DELIM; 571 FTU_brd_add_sig <= conv_std_logic_vector( FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);583 FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); 572 584 FTU_command_sig <= "00000110"; 573 585 FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; … … 735 747 write_FTUlist_RAM <= '1'; 736 748 addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET + 737 FTU_cnt* NO_OF_FTU_LIST_REG +749 (FTU_cnt - 1)* NO_OF_FTU_LIST_REG + 738 750 (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); 739 751 if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
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