 Timestamp:
 Mar 24, 2011, 4:38:45 PM (9 years ago)
 Location:
 firmware/FTM
 Files:

 2 edited
Legend:
 Unmodified
 Added
 Removed

firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10259 r10260 153 153 signal cc_R14_sig : std_logic_vector (31 downto 0); 154 154 signal cc_R15_sig : std_logic_vector (31 downto 0); 155 155 156 157 158 156 159 begin 157 160 … … 198 201 cc_R0_sig <= cc_R0; 199 202 cc_R1_sig <= cc_R1; 200 201 cc_R2_sig <= cc_R2; 202 cc_R3_sig <= cc_R3; 203 cc_R4_sig <= cc_R4; 204 cc_R5_sig <= cc_R5; 205 cc_R6_sig <= cc_R6; 206 cc_R7_sig <= cc_R7; 203 cc_R2_sig <= cc_R2_const; 204 cc_R3_sig <= cc_R3_const; 205 cc_R4_sig <= cc_R4_const; 206 cc_R5_sig <= cc_R5_const; 207 cc_R6_sig <= cc_R6_const; 208 cc_R7_sig <= cc_R7_const; 207 209 cc_R8_sig <= cc_R8; 208 209 210 cc_R9_sig <= cc_R9; 210 211 cc_R11_sig <= cc_R11; … … 216 217  bit 31 of register 0 217 218 clk_cond_array_sig(1) <= cc_R0_sig; 218 clk_cond_array_sig(2) <= cc_R1_sig; 219 clk_cond_array_sig(3) <= cc_R8_sig; 220 clk_cond_array_sig(4) <= cc_R9_sig; 221 clk_cond_array_sig(5) <= cc_R11_sig; 222 clk_cond_array_sig(6) <= cc_R13_sig; 223 clk_cond_array_sig(7) <= cc_R14_sig; 224 clk_cond_array_sig(8) <= cc_R15_sig; 219 clk_cond_array_sig(2) <= cc_R1_sig; 220 221 clk_cond_array_sig(3) <= cc_R2_sig;  unused channels 222 clk_cond_array_sig(4) <= cc_R3_sig; 223 clk_cond_array_sig(5) <= cc_R4_sig; 224 clk_cond_array_sig(6) <= cc_R5_sig; 225 clk_cond_array_sig(7) <= cc_R6_sig; 226 clk_cond_array_sig(8) <= cc_R7_sig; 227 228 clk_cond_array_sig(9) <= cc_R8_sig; 229 clk_cond_array_sig(10) <= cc_R9_sig; 230 clk_cond_array_sig(11) <= cc_R11_sig; 231 clk_cond_array_sig(12) <= cc_R13_sig; 232 clk_cond_array_sig(13) <= cc_R14_sig; 233 clk_cond_array_sig(14) <= cc_R15_sig; 225 234 226 235 
firmware/FTM/ftm_definitions.vhd
r10259 r10260 50 50 51 51  data array for clock conditioner interface 52 type clk_cond_array_type is array (0 to 1 3) of std_logic_vector (31 downto 0);52 type clk_cond_array_type is array (0 to 14) of std_logic_vector (31 downto 0); 53 53 54 54  network array types … … 113 113 constant LMK03000_Reset : std_logic_vector (31 downto 0) := x"80000000"; 114 114 constant LMK03000_REGISTER_WIDTH : integer := 32; 115 constant LMK03000_REGISTER_COUNT : integer := 9;  number of registers to be programmed in the LMK03000 including reset 115 constant LMK03000_REGISTER_COUNT : integer := 15;  number of registers to be programmed in the LMK03000 including reset 116 constant cc_R2_const : std_logic_vector := X"00000102";  unused 117 constant cc_R3_const : std_logic_vector := X"00000103";  channels 118 constant cc_R4_const : std_logic_vector := X"00000104"; 119 constant cc_R5_const : std_logic_vector := X"00000105"; 120 constant cc_R6_const : std_logic_vector := X"00000106"; 121 constant cc_R7_const : std_logic_vector := X"00000107"; 116 122 117 123  network settings Dortmund … … 249 255 250 256 251  Clock conditioner interface252 constant cc_R2_const : std_logic_vector := X"00000102";253 constant cc_R3_const : std_logic_vector := X"00000103";254 constant cc_R4_const : std_logic_vector := X"00000104";255 constant cc_R5_const : std_logic_vector := X"00000105";256 constant cc_R6_const : std_logic_vector := X"00000106";257 constant cc_R7_const : std_logic_vector := X"00000107";258 259 260 257  arrays for default values 261 258 type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL  1)) of std_logic_vector (15 downto 0); … … 327 324 328 325  Timing counter 329 constant tc_width : integer := 48;  width (number of bits) of timing counter330 constant zero : unsigned (tc_width  1 downto 0) := (others => '0');326  constant tc_width : integer := 48;  width (number of bits) of timing counter 327  constant zero : unsigned (tc_width  1 downto 0) := (others => '0'); 331 328 332 329 end ftm_constants;
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