- Timestamp:
- 04/08/11 14:26:50 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 4 edited
-
FTM_central_control.vhd (modified) (7 diffs)
-
FTM_top_tb.vhd (modified) (2 diffs)
-
ftm_definitions.vhd (modified) (2 diffs)
-
ftu_control/FTM_ftu_control.vhd (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/FTM_central_control.vhd
r10256 r10328 66 66 architecture Behavioral of FTM_central_control is 67 67 68 signal reset_scaler_sig : std_logic := '0'; 69 signal scaler_counts_sig : integer := 0; 70 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 68 signal reset_scaler_sig : std_logic := '0'; 69 signal reset_period_sig : std_logic := '0'; 70 signal scaler_counts_sig : integer := 0; 71 signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 72 signal period_finished_sig : std_logic := '0'; 73 signal wait_cnt_sig : integer range 0 to 10 := 0; 74 signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0'); 75 signal new_period_sig : std_logic := '0'; 76 signal new_period_ack_sig : std_logic := '0'; 77 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 71 78 72 79 type state_central_proc_type is (CP_INIT, 73 80 CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, 74 81 CP_CONFIG_CC, CP_CONFIG_CC_01, 75 CP_CONFIG_FTU, CP_CONFIG_FTU_01, CP_CONFIG_SCALER, 82 CP_CONFIG_FTU, CP_CONFIG_FTU_01, 83 CP_CONFIG_SCALER, CP_CONFIG_SCALER_01, 76 84 CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01, 77 85 CP_SEND_START, CP_SEND_END); … … 89 97 90 98 when CP_CONFIG_START => 91 reset_scaler_sig <= '1';92 99 if (config_started_ack = '1') then 93 100 config_started <= '0'; … … 96 103 97 104 when CP_CONFIG => 98 reset_scaler_sig <= '1';99 105 config_start_eth <= '1'; 100 106 if (config_started_eth = '1') then … … 133 139 state_central_proc <= CP_CONFIG_SCALER; 134 140 end if; 135 141 136 142 when CP_CONFIG_SCALER => 137 --if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then 138 --scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); 139 --else 140 --scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 141 --end if; 142 reset_scaler_sig <= '1'; 143 state_central_proc <= CP_IDLE; 144 143 prescaling_FTU01_sig <= prescaling_FTU01; 144 --reset_period_sig <= '1'; 145 state_central_proc <= CP_CONFIG_SCALER_01; 146 147 when CP_CONFIG_SCALER_01 => 148 --reset_period_sig <= '0'; 149 if wait_cnt_sig < 5 then 150 wait_cnt_sig <= wait_cnt_sig + 1; 151 reset_scaler_sig <= '1'; 152 state_central_proc <= CP_CONFIG_SCALER_01; 153 else 154 wait_cnt_sig <= 0; 155 reset_scaler_sig <= '0'; 156 state_central_proc <= CP_IDLE; 157 end if; 158 145 159 when CP_IDLE => 146 reset_scaler_sig <= '0';147 160 if (new_config = '1') then 148 161 config_started <= '1'; 149 162 state_central_proc <= CP_CONFIG_START; 150 163 elsif (ping_ftu_start = '1') then 151 --else152 164 ping_ftu_start_ftu <= '1'; 153 165 if (ping_ftu_started_ftu = '1') then … … 158 170 end if; 159 171 --elsif (scaler_counts_sig = scaler_period_sig) then 160 -- reset_scaler_sig <= '1'; 161 -- rates_ftu <= '1'; 162 -- state_central_proc <= CP_READ_RATES; 172 elsif (new_period_sig = '1') then 173 new_period_ack_sig <= '1'; 174 rates_ftu <= '1'; 175 state_central_proc <= CP_READ_RATES; 163 176 end if; 164 177 … … 173 186 174 187 when CP_READ_RATES => 175 reset_scaler_sig <= '0';188 new_period_ack_sig <= '0'; 176 189 if (rates_started_ftu = '1') then 177 190 rates_ftu <= '0'; … … 202 215 scaler_process: process(reset_scaler_sig, clk_scaler) 203 216 begin 204 if reset_scaler_sig = '1'then217 if (reset_scaler_sig = '1') then 205 218 scaler_counts_sig <= 0; 219 period_finished_sig <= '0'; 206 220 elsif rising_edge(clk_scaler) then 207 221 if (scaler_counts_sig < scaler_period_sig) then 208 222 scaler_counts_sig <= scaler_counts_sig + 1; 223 period_finished_sig <= '0'; 209 224 else 210 scaler_counts_sig <= scaler_counts_sig; 225 period_finished_sig <= '1'; 226 scaler_counts_sig <= 0; 211 227 end if; 212 228 end if; 213 229 end process scaler_process; 214 230 215 process(reset_scaler_sig, prescaling_FTU01) 216 begin 217 if rising_edge(reset_scaler_sig) then 218 if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then 219 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); 231 -- process(reset_period_sig) 232 -- begin 233 -- if rising_edge(reset_period_sig) then 234 -- if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then 235 -- scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); 236 -- else 237 -- scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 238 -- end if; 239 -- end if; 240 -- end process; 241 242 process(prescaling_FTU01_sig) 243 begin 244 if ((conv_integer(unsigned(prescaling_FTU01_sig))) mod 2 = 0) then 245 scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01_sig)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); 246 else 247 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01_sig)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 248 end if; 249 end process; 250 251 detect_period_finished: process(clk) 252 begin 253 if rising_edge(clk) then 254 new_period_sr_sig <= new_period_sr_sig(new_period_sr_sig'left - 1 downto 0) & period_finished_sig; 255 if(new_period_ack_sig = '1') then 256 new_period_sig <= '0'; 220 257 else 221 scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); 258 if (new_period_sr_sig(1 downto 0) = "01") then 259 new_period_sig <= '1'; 260 end if; 222 261 end if; 223 262 end if; 224 end process ;225 263 end process detect_period_finished; 264 226 265 end Behavioral; -
firmware/FTM/FTM_top_tb.vhd
r10256 r10328 117 117 -- Clock conditioner LMK03000 118 118 ------------------------------------------------------------------------------- 119 --CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock120 --LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable121 --DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data119 CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock 120 LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable 121 DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data 122 122 123 --SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization124 --LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for123 SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization 124 LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for 125 125 126 126 … … 379 379 LED_ye => LED_ye_sig, 380 380 LED_gn => LED_gn_sig, 381 --CLK_Clk_Cond => CLK_Clk_Cond_sig,382 --LE_Clk_Cond => LE_Clk_Cond_sig,383 --DATA_Clk_Cond => DATA_Clk_Cond_sig,384 --SYNC_Clk_Cond => SYNC_Clk_Cond_sig,385 --LD_Clk_Cond => LD_Clk_Cond_sig,381 CLK_Clk_Cond => CLK_Clk_Cond_sig, 382 LE_Clk_Cond => LE_Clk_Cond_sig, 383 DATA_Clk_Cond => DATA_Clk_Cond_sig, 384 SYNC_Clk_Cond => SYNC_Clk_Cond_sig, 385 LD_Clk_Cond => LD_Clk_Cond_sig, 386 386 Bus1_Tx_En => Bus1_Tx_En_sig, 387 387 Bus1_Rx_En => Bus1_Rx_En_sig, -
firmware/FTM/ftm_definitions.vhd
r10260 r10328 86 86 constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz 87 87 constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1 88 constant SCALER_FREQ_DIVIDER : integer := 1; -- for simulation, should normally be 1 88 --constant SCALER_FREQ_DIVIDER : integer := 10000; -- for simulation, should normally be 1 89 constant SCALER_FREQ_DIVIDER : integer := 1; 89 90 90 91 --FTM address and firmware ID … … 95 96 constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case 96 97 constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods) 97 -- 98 -- 98 --constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation 99 --constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation 99 100 constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!! 100 101 constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol -
firmware/FTM/ftu_control/FTM_ftu_control.vhd
r10256 r10328 916 916 FTM_ftu_rs485_control_State <= RATES; 917 917 else 918 retry_cnt <= 0; 918 919 FTU_cnt <= FTU_cnt; -- move on 919 920 FTM_ftu_rs485_control_State <= RATES;
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