Changeset 10500 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Timestamp:
- 04/29/11 14:55:16 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 5 edited
-
data_generator.vhd (modified) (4 diffs)
-
fad_board_struct.vhd (modified) (2 diffs)
-
fad_definitions.vhd (modified) (2 diffs)
-
fad_main_struct.vhd (modified) (11 diffs)
-
w5300_modul.vhd (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10462 r10500 75 75 76 76 -- EVT HEADER - part 6 77 runnumber : in std_logic_vector (31 downto 0); 77 78 timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us 78 79 … … 151 152 152 153 signal FTM_trigger_info_local_copy : std_logic_vector (55 downto 0) := (others => '0'); --7 byte 154 signal runnumber_local_copy : std_logic_vector (31 downto 0); 153 155 154 156 -- self configuration signals: … … 223 225 if (ram_write_ea = '1' and trigger_sr = "01") then 224 226 sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. 227 runnumber_local_copy <= runnumber; 225 228 trigger_veto <= '1'; 226 229 start_read_drs_stop_cell <= '1'; … … 290 293 when WRITE_TIMER => 291 294 data_out <= 292 X"0000"& -- 2times 16bit reserved for additional status info293 X"0000"&295 runnumber_local_copy(15 downto 0) & -- 2times 16bit reserved for additional status info 296 runnumber_local_copy(31 downto 16) & 294 297 timer_value(15 downto 0) & 295 298 timer_value(31 downto 16); -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10462 r10500 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 7:31:46 26.04.20115 -- at - 14:00:29 29.04.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 7:31:46 26.04.201178 -- at - 14:00:29 29.04.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10462 r10500 159 159 constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; 160 160 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 161 constant CMD_RESET_TRIGGER_ID : std_logic_vector := X"2A"; 161 162 162 163 constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode … … 166 167 constant CMD_TRIGGER : std_logic_vector := X"A0"; 167 168 constant CMD_TRIGGER_C : std_logic_vector := X"B0"; 169 170 168 171 169 172 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10462 r10500 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 1 7:31:44 26.04.20115 -- at - 14:00:28 29.04.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 1 7:31:45 26.04.201178 -- at - 14:00:29 29.04.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 121 121 SIGNAL cont_trigger : std_logic; 122 122 SIGNAL current_dac_array : dac_array_type := ( others => 0); 123 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd123 SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 124 124 SIGNAL data_generator_config_start : std_logic := '0'; 125 125 SIGNAL data_generator_config_valid : std_logic; 126 126 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 127 127 SIGNAL data_ram_empty : std_logic; 128 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off129 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off130 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off131 SIGNAL din1 : std_logic := '0'; -- default domino wave off128 SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off 129 SIGNAL denable_prim : std_logic := '0'; -- default domino wave off 130 SIGNAL denable_sig : std_logic := '0'; -- default domino wave off 131 SIGNAL din1 : std_logic := '0'; -- default domino wave off 132 132 SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); 133 133 SIGNAL dout : STD_LOGIC; … … 155 155 SIGNAL memory_manager_config_valid : std_logic; 156 156 SIGNAL package_length : std_logic_vector(15 DOWNTO 0); 157 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards158 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once159 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift157 SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards 158 SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once 159 SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift 160 160 SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); 161 161 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); … … 167 167 SIGNAL ready : STD_LOGIC := '0'; 168 168 SIGNAL rec_timeout_occured : std_logic := '0'; 169 SIGNAL reset : std_logic;170 169 SIGNAL reset_synch_i : std_logic; 170 SIGNAL reset_trigger_id : std_logic := '0'; 171 171 SIGNAL roi_max : roi_max_type; 172 172 SIGNAL roi_setting : roi_array_type; 173 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 173 SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte 174 SIGNAL runnumber : std_logic_vector(31 DOWNTO 0) := conv_std_logic_vector(0 ,31); 174 175 SIGNAL s_trigger : std_logic; 175 176 SIGNAL s_trigger_or_cont_trigger : std_logic; … … 332 333 dna : IN std_logic_vector (63 DOWNTO 0); 333 334 -- EVT HEADER - part 6 335 runnumber : IN std_logic_vector (31 DOWNTO 0); 334 336 timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us 335 337 trigger : IN std_logic ; … … 515 517 dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 516 518 roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 519 runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,31); 520 reset_trigger_id : OUT std_logic := '0'; 517 521 data_ram_empty : IN std_logic ; 518 522 ------------------------------------------------------------------------------ … … 600 604 denable <= denable_sig; 601 605 602 -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd'603 reset <= '0';604 605 606 -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' 606 607 reset_synch_i <= '0'; … … 746 747 TRG_GEN_div => c_trigger_mult, 747 748 dna => dna, 749 runnumber => runnumber, 748 750 timer_value => time, 749 751 trigger => trigger_out, … … 867 869 trigger_id => trigger_id, 868 870 trigger => trigger_out, 869 reset => reset ,871 reset => reset_trigger_id, 870 872 clk => CLK_25_PS_internal 871 873 ); … … 914 916 dac_setting => dac_setting, 915 917 roi_setting => roi_setting, 918 runnumber => runnumber, 919 reset_trigger_id => reset_trigger_id, 916 920 data_ram_empty => data_ram_empty, 917 921 MAC_jumper => D_T_in, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10462 r10500 48 48 dac_setting : out dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd 49 49 roi_setting : out roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd 50 51 data_ram_empty : IN std_logic; 50 51 runnumber : out std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,31); 52 reset_trigger_id : out std_logic := '0'; 53 54 data_ram_empty : IN std_logic; 52 55 53 56 ------------------------------------------------------------------------------ … … 184 187 185 188 signal config_addr : integer range 0 to 44; 186 type config_data_type is array (0 to 4 4) of std_logic_vector(15 downto 0);189 type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0); 187 190 signal config_setting : config_data_type := ( 188 191 -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY … … 197 200 X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs 198 201 X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs 199 X"0000" 202 X"0000", 203 X"0000", X"0000" 200 204 ); 201 205 … … 283 287 end generate dac_mapping; 284 288 c_trigger_mult <= config_setting(44); 289 290 runnumber <= config_setting(45) & config_setting(46); 285 291 286 292 trigger_enable <= trigger_enable_sig; … … 661 667 end case; 662 668 663 when CONFIG => 669 when CONFIG => -- Triggers are disabled here! 664 670 trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. 665 671 trigger_enable_sig <= '0'; --no triggers must occur, while configurating. 666 672 state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. 667 673 668 when WAIT_FOR_OLLI => 669 state_init <= WAIT_FOR_DATA_RAM_EMPTY; 674 when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. 675 state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN 670 676 671 677 … … 803 809 s_trigger <= '0'; 804 810 ps_do_phase_shift <= '0'; 811 reset_trigger_id <= '0'; 812 805 813 if (rx_packets_cnt > 0) then 806 814 rx_packets_cnt <= rx_packets_cnt - '1'; … … 882 890 ps_direction <= '0'; 883 891 state_read_data <= RD_5; 892 893 when CMD_RESET_TRIGGER_ID => 894 reset_trigger_id <= '1'; 895 state_read_data <= RD_5; 896 884 897 when CMD_WRITE => 885 898 config_addr <= conv_integer(data_read (7 downto 0)); … … 890 903 -- read data 891 904 892 -- these states are beeing pr ecessed, if the 'command' was a 'write command'905 -- these states are beeing processed, if the 'command' was a 'write command' 893 906 -- so it is assumed, that some data in config RAM changed, and we need full (re)config 894 907 when READ_COMMAND_DATA_SECTION => … … 907 920 if (config_addr < 36) then 908 921 update_of_rois <= '1'; 909 else 910 update_of_lessimportant <= '1'; 922 else 923 if (config_addr < 45 ) then 924 update_of_lessimportant <= '1'; 925 end if; 911 926 end if; 912 927 state_read_data <= RD_5;
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