Changeset 10779 for firmware/FTM
- Timestamp:
- 05/23/11 15:00:19 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 4 edited
-
FTM_central_control.vhd (modified) (10 diffs)
-
FTM_top.vhd (modified) (5 diffs)
-
Timing_counters/Timing_counter.vhd (modified) (5 diffs)
-
ftm_definitions.vhd (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/FTM_central_control.vhd
r10760 r10779 83 83 trigger_stop : out std_logic := '1'; 84 84 enable_ID_sending : out std_logic := '0'; 85 reset_timer : out std_logic := '0' 85 reset_timer : out std_logic := '0'; 86 crate_res_0 : out std_logic := '1'; 87 crate_res_1 : out std_logic := '1'; 88 crate_res_2 : out std_logic := '1'; 89 crate_res_3 : out std_logic := '1' 86 90 ); 87 91 end FTM_central_control; … … 99 103 signal new_period_ack_sig : std_logic := '0'; 100 104 signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; 105 signal reset_cnt_sig : integer range 0 to RESET_TIME := 0; 101 106 102 107 type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER, … … 108 113 CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, 109 114 CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, 110 CP_SEND_START, CP_SEND_END); 115 CP_SEND_START, CP_SEND_END, 116 CP_CRATE_RESET, CP_CRATE_RESET_ACK); 111 117 signal state_central_proc : state_central_proc_type := CP_INIT; 112 118 … … 124 130 when CP_INIT => -- wait for DCMs to lock 125 131 current_cc_state <= X"FFFF"; 126 --cc_state_test <= X"00";127 132 cc_state_test <= X"01"; 128 133 if (clk_ready = '1') then … … 250 255 if (new_config = '1') then 251 256 config_started <= '1'; 252 start_run_ack <= '1'; 257 start_run_ack <= '1'; --remove this line??? 253 258 state_central_proc <= CP_CONFIG_START; 254 259 elsif (ping_ftu_start = '1') then … … 274 279 state_central_proc <= CP_RUNNING; 275 280 end if; 281 elsif (crate_reset = '1') then 282 crate_reset_ack <= '1'; 283 state_central_proc <= CP_CRATE_RESET; 276 284 end if; 277 285 … … 317 325 enable_Id_sending <= '0'; 318 326 state_central_proc <= CP_RUNNING_02; 327 elsif (crate_reset = '1') then 328 crate_reset_ack <= '1'; 329 state_central_proc <= CP_CRATE_RESET_ACK; 319 330 end if; 320 331 … … 329 340 330 341 when CP_CONFIG_ACK => 331 current_cc_state <= FTM_STATE_CFG;332 342 cc_state_test <= X"11"; 333 343 if (config_started_ack = '1') then … … 335 345 state_central_proc <= CP_RUNNING_01; 336 346 end if; 337 347 338 348 when CP_PING => 339 349 cc_state_test <= X"12"; … … 392 402 end if; 393 403 404 when CP_CRATE_RESET_ACK => 405 cc_state_test <= X"18"; 406 if (crate_reset = '0') then 407 crate_reset_ack <= '0'; 408 state_central_proc <= CP_RUNNING_01; 409 end if; 410 411 when CP_CRATE_RESET => 412 cc_state_test <= X"19"; 413 if (crate_reset = '0') then 414 crate_reset_ack <= '0'; 415 state_central_proc <= CP_IDLE; 416 end if; 417 394 418 when others => 395 cc_state_test <= X"1 8";419 cc_state_test <= X"1A"; 396 420 397 421 end case; -
firmware/FTM/FTM_top.vhd
r10760 r10779 406 406 signal enable_ID_sending_sig : std_logic; 407 407 signal reset_timer_sig : std_logic; -- initialized in FTM_central_control 408 408 409 signal crate_res0_sig : std_logic; -- initialized in FTM_central_control 410 signal crate_res1_sig : std_logic; -- initialized in FTM_central_control 411 signal crate_res2_sig : std_logic; -- initialized in FTM_central_control 412 signal crate_res3_sig : std_logic; -- initialized in FTM_central_control 413 409 414 -- component FTM_clk_gen 410 415 -- port( … … 570 575 trigger_stop : out std_logic; 571 576 enable_ID_sending : out std_logic; 572 reset_timer : out std_logic 577 reset_timer : out std_logic; 578 crate_res_0 : out std_logic; 579 crate_res_1 : out std_logic; 580 crate_res_2 : out std_logic; 581 crate_res_3 : out std_logic 573 582 ); 574 583 end component; … … 967 976 trigger_stop => trigger_stop_sig, 968 977 enable_ID_sending => enable_ID_sending_sig, 969 reset_timer => reset_timer_sig 978 reset_timer => reset_timer_sig, 979 crate_res_0 => crate_res0_sig, 980 crate_res_1 => crate_res1_sig, 981 crate_res_2 => crate_res2_sig, 982 crate_res_3 => crate_res3_sig 970 983 ); 971 984 … … 1034 1047 rx_d_3 => Bus2_RxD_3, 1035 1048 tx_d_3 => Bus2_TxD_3, 1036 --enable_ID_sending => trigger_start_sig,1037 1049 enable_ID_sending => enable_ID_sending_sig, 1038 --enable_ID_sending => '1',1039 1050 TIM_source => general_settings_sig(0), 1040 1051 LP_settings => "0000", … … 1197 1208 TP( 7 downto 0) <= cc_state_test_sig; 1198 1209 1199 Crate_Res0 <= '1';1200 Crate_Res1 <= '1';1201 Crate_Res2 <= '1';1202 Crate_Res3 <= '1';1210 Crate_Res0 <= crate_res0_sig; 1211 Crate_Res1 <= crate_res1_sig; 1212 Crate_Res2 <= crate_res2_sig; 1213 Crate_Res3 <= crate_res3_sig; 1203 1214 1204 1215 end Behavioral; -
firmware/FTM/Timing_counters/Timing_counter.vhd
r10760 r10779 23 23 -- 24 24 -- May 18 2011 by Patrick Vogler 25 -- 26 -- May 20, 2011, by Q. Weitzel 27 -- counting was wrong by one clock cycle (1 us) 28 -- 29 -- May 23, 2011, by Q. Weitzel 30 -- counter reset changed from async to sync reset 31 -- reset, enable and read_counter removed from sensitity lists 32 -- 25 33 ---------------------------------------------------------------------------------- 26 34 … … 40 48 USE ftm_definitions.ftm_array_types.all; 41 49 USE ftm_definitions.ftm_constants.all; 42 43 50 44 51 … … 64 71 65 72 66 67 73 architecture Behavioral of Timing_counter is 68 74 … … 78 84 -- counting 79 85 ------------------------------------------------------------------------------- 80 count : process (clk, reset, enable) 81 begin 82 if reset = '1' then 83 counting <= (others => '0'); 84 precounting <= (others => '0'); 85 86 elsif rising_edge(clk) then 87 if enable = '1' then 88 precounting <= precounting + 1; 89 if (precounting = (PRECOUNT_DIVIDER - 1)) then 90 counting <= counting + 1; 91 precounting <= (others => '0'); 92 end if; 93 end if; 94 end if; 86 count : process (clk) 87 begin 88 89 if rising_edge(clk) then 90 if (reset = '1') then 91 counting <= (others => '0'); 92 precounting <= (others => '0'); 93 elsif enable = '1' then 94 precounting <= precounting + 1; 95 if (precounting = (PRECOUNT_DIVIDER - 1)) then 96 counting <= counting + 1; 97 precounting <= (others => '0'); 98 end if; 99 end if; 100 end if; 101 95 102 end process count; 96 97 103 98 104 -- read counter 99 105 ------------------------------------------------------------------------------- 100 readout_counter : process (clk , read_counter)106 readout_counter : process (clk) 101 107 begin 102 108 if rising_edge(clk) then … … 131 137 132 138 end Behavioral; 133 134 -
firmware/FTM/ftm_definitions.vhd
r10742 r10779 234 234 -- crate reset 235 235 constant CMD_CRESET : std_logic_vector := X"0020"; 236 236 constant RESET_TIME : integer := 1000; 237 237 238 -- start and end of package 238 239 constant FTM_PACKAGE_START : std_logic_vector := X"FB01";
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