Changeset 10883 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib
- Timestamp:
- 05/27/11 17:51:42 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib
- Files:
-
- 7 edited
-
hdl/fad_main_tb_struct.vhd (modified) (16 diffs)
-
hdl/trigger__generator_beha.vhd (modified) (1 diff)
-
hdl/w5300_emulator_beha.vhd (modified) (2 diffs)
-
hds/.cache.dat (modified) ( previous)
-
hds/.xrf/fad_main_tb_struct.xrf (modified) (1 diff)
-
hds/fad_main_tb/struct.bd (modified) (332 diffs)
-
hds/fad_main_tb/struct.bd.bak (modified) (352 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd
r10225 r10883 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 18:33:01 02.03.20115 -- at - 22:55:01 26.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 21 21 -- Created: 22 22 -- by - daqct3.UNKNOWN (IHP110) 23 -- at - 18:33:01 02.03.201123 -- at - 22:55:01 26.05.2011 24 24 -- 25 25 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 47 47 SIGNAL CLK_25_PS : std_logic; 48 48 SIGNAL CLK_50 : std_logic; 49 -- for debugging 50 SIGNAL DG_state : std_logic_vector(7 DOWNTO 0); 49 51 SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0); 52 SIGNAL FTM_RS485_rx_d : std_logic; 53 SIGNAL FTM_RS485_rx_en : std_logic; 54 SIGNAL FTM_RS485_tx_d : std_logic; 55 SIGNAL FTM_RS485_tx_en : std_logic; 50 56 SIGNAL REF_CLK : STD_LOGIC := '0'; 51 57 SIGNAL RSRLOAD : std_logic := '0'; … … 69 75 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 70 76 SIGNAL dac_cs : std_logic; 77 SIGNAL debug_data_ram_empty : std_logic; 78 SIGNAL debug_data_valid : std_logic; 71 79 SIGNAL denable : std_logic := '0'; -- default domino wave off 72 80 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); … … 74 82 SIGNAL green : std_logic; 75 83 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 84 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. 76 85 SIGNAL mosi : std_logic := '0'; 77 86 SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked … … 80 89 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 81 90 SIGNAL sio : std_logic; 91 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true 82 92 SIGNAL trigger : std_logic; 93 SIGNAL trigger_veto : std_logic := '1'; 94 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 83 95 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 84 96 SIGNAL wiz_cs : std_logic := '1'; … … 98 110 CLK : IN std_logic ; 99 111 D_T_in : IN std_logic_vector (1 DOWNTO 0); 112 FTM_RS485_rx_d : IN std_logic ; 100 113 SROUT_in_0 : IN std_logic ; 101 114 SROUT_in_1 : IN std_logic ; … … 113 126 CLK_25_PS : OUT std_logic ; 114 127 CLK_50 : OUT std_logic ; 128 -- for debugging 129 DG_state : OUT std_logic_vector (7 DOWNTO 0); 130 FTM_RS485_rx_en : OUT std_logic ; 131 FTM_RS485_tx_d : OUT std_logic ; 132 FTM_RS485_tx_en : OUT std_logic ; 115 133 RSRLOAD : OUT std_logic := '0'; 116 134 SRCLK : OUT std_logic := '0'; … … 122 140 counter_result : OUT std_logic_vector (11 DOWNTO 0); 123 141 dac_cs : OUT std_logic ; 142 debug_data_ram_empty : OUT std_logic ; 143 debug_data_valid : OUT std_logic ; 124 144 denable : OUT std_logic := '0'; -- default domino wave off 125 145 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); … … 127 147 green : OUT std_logic ; 128 148 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 149 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 129 150 mosi : OUT std_logic := '0'; 130 151 red : OUT std_logic ; 131 152 sclk : OUT std_logic ; 132 153 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 154 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 155 trigger_veto : OUT std_logic := '1'; 156 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 133 157 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 134 158 wiz_cs : OUT std_logic := '1'; … … 186 210 data : INOUT std_logic_vector (15 DOWNTO 0); 187 211 rd : IN std_logic ; 212 cs : IN std_logic ; 188 213 wr : IN std_logic 189 214 ); … … 237 262 CLK => clk, 238 263 D_T_in => D_T_in, 264 FTM_RS485_rx_d => FTM_RS485_rx_d, 239 265 SROUT_in_0 => SROUT_in_0, 240 266 SROUT_in_1 => SROUT_in_1, … … 252 278 CLK_25_PS => CLK_25_PS, 253 279 CLK_50 => CLK_50, 280 DG_state => DG_state, 281 FTM_RS485_rx_en => FTM_RS485_rx_en, 282 FTM_RS485_tx_d => FTM_RS485_tx_d, 283 FTM_RS485_tx_en => FTM_RS485_tx_en, 254 284 RSRLOAD => RSRLOAD, 255 285 SRCLK => SRCLK, … … 261 291 counter_result => counter_result, 262 292 dac_cs => dac_cs, 293 debug_data_ram_empty => debug_data_ram_empty, 294 debug_data_valid => debug_data_valid, 263 295 denable => denable, 264 296 drs_channel_id => drs_channel_id, … … 266 298 green => green, 267 299 led => led, 300 mem_manager_state => mem_manager_state, 268 301 mosi => mosi, 269 302 red => red, 270 303 sclk => sclk, 271 304 sensor_cs => sensor_cs, 305 socket_tx_free_out => socket_tx_free_out, 306 trigger_veto => trigger_veto, 307 w5300_state => w5300_state, 272 308 wiz_addr => wiz_addr, 273 309 wiz_cs => wiz_cs, … … 329 365 data => wiz_data, 330 366 rd => wiz_rd, 367 cs => wiz_cs, 331 368 wr => wiz_wr 332 369 ); -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd
r9912 r10883 34 34 trigger <= '0'; 35 35 wait for TRIGGER_RATE; 36 --trigger <= '1';36 trigger <= '1'; 37 37 wait for PULSE_WIDTH; 38 38 trigger <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd
r10240 r10883 49 49 wait for 150 us; 50 50 RSR_1 <= X"0001"; 51 wait for 100 us;51 wait for 500 us; 52 52 RSR_1 <= X"0002"; 53 wait for 500 us;53 wait for 1000 us; 54 54 FIFOR_CNT <= 1; 55 wait for 100 us; 55 wait for 1000 us; 56 RSR_1 <= X"0004"; 57 56 58 FIFOR_CNT <= 2; 57 wait for 200 us;59 wait for 40 us; 58 60 FIFOR_CNT <= 3; 59 wait for 200 ns; 61 62 wait for 200000 us; 60 63 RSR_1 <= X"0000"; 61 wait for 2ms;62 RSR_1 <= X"0002";63 FIFOR_CNT <= 2;64 -- wait for 1 ms; 65 -- RSR_1 <= X"0002"; 66 -- FIFOR_CNT <= 2; 64 67 65 wait for 6 ms;66 int <= '0';68 -- wait for 6 ms; 69 -- int <= '0'; 67 70 68 71 -- wait for 1 ms; … … 95 98 96 99 elsif (FIFOR_CNT = 1) then 97 data_temp <= X" 2200";100 data_temp <= X"A000"; 98 101 99 102 elsif (FIFOR_CNT = 2) then -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf
r10225 r10883 34 34 DESIGN fad_main_tb 35 35 VIEW struct.bd 36 GRAPHIC 1501,0 48 0 37 DESIGN fad_main_tb 38 VIEW struct.bd 39 GRAPHIC 2001,0 49 0 40 DESIGN fad_main_tb 41 VIEW struct.bd 42 GRAPHIC 855,0 50 0 43 DESIGN fad_main_tb 44 VIEW struct.bd 45 GRAPHIC 863,0 51 0 46 DESIGN fad_main_tb 47 VIEW struct.bd 48 GRAPHIC 1435,0 52 0 49 DESIGN fad_main_tb 50 VIEW struct.bd 51 GRAPHIC 871,0 53 0 52 DESIGN fad_main_tb 53 VIEW struct.bd 54 GRAPHIC 879,0 54 0 55 DESIGN fad_main_tb 56 VIEW struct.bd 57 GRAPHIC 887,0 55 0 58 DESIGN fad_main_tb 59 VIEW struct.bd 60 GRAPHIC 895,0 56 0 61 DESIGN fad_main_tb 62 VIEW struct.bd 63 GRAPHIC 568,0 57 0 64 DESIGN fad_main_tb 65 VIEW struct.bd 66 GRAPHIC 536,0 58 0 67 DESIGN fad_main_tb 68 VIEW struct.bd 69 GRAPHIC 544,0 59 0 70 DESIGN fad_main_tb 71 VIEW struct.bd 72 GRAPHIC 560,0 60 0 73 DESIGN fad_main_tb 74 VIEW struct.bd 75 GRAPHIC 528,0 61 0 76 DESIGN fad_main_tb 77 VIEW struct.bd 78 GRAPHIC 1483,0 62 0 79 DESIGN fad_main_tb 80 VIEW struct.bd 81 GRAPHIC 1475,0 63 0 82 DESIGN fad_main_tb 83 VIEW struct.bd 84 GRAPHIC 1443,0 64 0 85 DESIGN fad_main_tb 86 VIEW struct.bd 87 GRAPHIC 440,0 65 0 88 DESIGN fad_main_tb 89 VIEW struct.bd 90 GRAPHIC 284,0 66 0 91 DESIGN fad_main_tb 92 VIEW struct.bd 93 GRAPHIC 1467,0 67 0 94 DESIGN fad_main_tb 95 VIEW struct.bd 96 GRAPHIC 448,0 68 0 97 DESIGN fad_main_tb 98 VIEW struct.bd 99 GRAPHIC 799,0 69 0 100 DESIGN fad_main_tb 101 VIEW struct.bd 102 GRAPHIC 815,0 70 0 103 DESIGN fad_main_tb 104 VIEW struct.bd 105 GRAPHIC 839,0 71 0 106 DESIGN fad_main_tb 107 VIEW struct.bd 108 GRAPHIC 847,0 72 0 109 DESIGN fad_main_tb 110 VIEW struct.bd 111 GRAPHIC 1459,0 73 0 112 DESIGN fad_main_tb 113 VIEW struct.bd 114 GRAPHIC 775,0 74 0 115 DESIGN fad_main_tb 116 VIEW struct.bd 117 GRAPHIC 807,0 75 0 118 DESIGN fad_main_tb 119 VIEW struct.bd 120 GRAPHIC 1559,0 76 0 121 DESIGN fad_main_tb 122 VIEW struct.bd 123 GRAPHIC 1451,0 77 0 124 DESIGN fad_main_tb 125 VIEW struct.bd 126 GRAPHIC 378,0 78 0 127 DESIGN fad_main_tb 128 VIEW struct.bd 129 GRAPHIC 372,0 79 0 130 DESIGN fad_main_tb 131 VIEW struct.bd 132 GRAPHIC 384,0 80 0 133 DESIGN fad_main_tb 134 VIEW struct.bd 135 GRAPHIC 424,0 81 0 136 DESIGN fad_main_tb 137 VIEW struct.bd 138 GRAPHIC 316,0 82 0 139 DESIGN fad_main_tb 140 VIEW struct.bd 141 GRAPHIC 783,0 83 0 142 DESIGN fad_main_tb 143 VIEW struct.bd 144 GRAPHIC 322,0 84 0 145 DESIGN fad_main_tb 146 VIEW struct.bd 147 GRAPHIC 791,0 85 0 148 DESIGN fad_main_tb 149 VIEW struct.bd 150 GRAPHIC 328,0 86 0 151 DESIGN fad_main_tb 152 VIEW struct.bd 153 GRAPHIC 767,0 87 0 154 DESIGN fad_main_tb 155 VIEW struct.bd 156 GRAPHIC 334,0 88 0 157 DESIGN fad_main_tb 158 VIEW struct.bd 159 NO_GRAPHIC 89 160 DESIGN fad_main_tb 161 VIEW struct.bd 162 NO_GRAPHIC 90 36 GRAPHIC 2721,0 49 0 37 DESIGN fad_main_tb 38 VIEW struct.bd 39 GRAPHIC 1501,0 50 0 40 DESIGN fad_main_tb 41 VIEW struct.bd 42 GRAPHIC 2777,0 51 0 43 DESIGN fad_main_tb 44 VIEW struct.bd 45 GRAPHIC 2729,0 52 0 46 DESIGN fad_main_tb 47 VIEW struct.bd 48 GRAPHIC 2737,0 53 0 49 DESIGN fad_main_tb 50 VIEW struct.bd 51 GRAPHIC 2745,0 54 0 52 DESIGN fad_main_tb 53 VIEW struct.bd 54 GRAPHIC 2001,0 55 0 55 DESIGN fad_main_tb 56 VIEW struct.bd 57 GRAPHIC 855,0 56 0 58 DESIGN fad_main_tb 59 VIEW struct.bd 60 GRAPHIC 863,0 57 0 61 DESIGN fad_main_tb 62 VIEW struct.bd 63 GRAPHIC 1435,0 58 0 64 DESIGN fad_main_tb 65 VIEW struct.bd 66 GRAPHIC 871,0 59 0 67 DESIGN fad_main_tb 68 VIEW struct.bd 69 GRAPHIC 879,0 60 0 70 DESIGN fad_main_tb 71 VIEW struct.bd 72 GRAPHIC 887,0 61 0 73 DESIGN fad_main_tb 74 VIEW struct.bd 75 GRAPHIC 895,0 62 0 76 DESIGN fad_main_tb 77 VIEW struct.bd 78 GRAPHIC 568,0 63 0 79 DESIGN fad_main_tb 80 VIEW struct.bd 81 GRAPHIC 536,0 64 0 82 DESIGN fad_main_tb 83 VIEW struct.bd 84 GRAPHIC 544,0 65 0 85 DESIGN fad_main_tb 86 VIEW struct.bd 87 GRAPHIC 560,0 66 0 88 DESIGN fad_main_tb 89 VIEW struct.bd 90 GRAPHIC 528,0 67 0 91 DESIGN fad_main_tb 92 VIEW struct.bd 93 GRAPHIC 1483,0 68 0 94 DESIGN fad_main_tb 95 VIEW struct.bd 96 GRAPHIC 1475,0 69 0 97 DESIGN fad_main_tb 98 VIEW struct.bd 99 GRAPHIC 1443,0 70 0 100 DESIGN fad_main_tb 101 VIEW struct.bd 102 GRAPHIC 440,0 71 0 103 DESIGN fad_main_tb 104 VIEW struct.bd 105 GRAPHIC 284,0 72 0 106 DESIGN fad_main_tb 107 VIEW struct.bd 108 GRAPHIC 1467,0 73 0 109 DESIGN fad_main_tb 110 VIEW struct.bd 111 GRAPHIC 448,0 74 0 112 DESIGN fad_main_tb 113 VIEW struct.bd 114 GRAPHIC 799,0 75 0 115 DESIGN fad_main_tb 116 VIEW struct.bd 117 GRAPHIC 2705,0 76 0 118 DESIGN fad_main_tb 119 VIEW struct.bd 120 GRAPHIC 2713,0 77 0 121 DESIGN fad_main_tb 122 VIEW struct.bd 123 GRAPHIC 815,0 78 0 124 DESIGN fad_main_tb 125 VIEW struct.bd 126 GRAPHIC 839,0 79 0 127 DESIGN fad_main_tb 128 VIEW struct.bd 129 GRAPHIC 847,0 80 0 130 DESIGN fad_main_tb 131 VIEW struct.bd 132 GRAPHIC 1459,0 81 0 133 DESIGN fad_main_tb 134 VIEW struct.bd 135 GRAPHIC 775,0 82 0 136 DESIGN fad_main_tb 137 VIEW struct.bd 138 GRAPHIC 2753,0 83 0 139 DESIGN fad_main_tb 140 VIEW struct.bd 141 GRAPHIC 807,0 84 0 142 DESIGN fad_main_tb 143 VIEW struct.bd 144 GRAPHIC 1559,0 85 0 145 DESIGN fad_main_tb 146 VIEW struct.bd 147 GRAPHIC 1451,0 86 0 148 DESIGN fad_main_tb 149 VIEW struct.bd 150 GRAPHIC 378,0 87 0 151 DESIGN fad_main_tb 152 VIEW struct.bd 153 GRAPHIC 372,0 88 0 154 DESIGN fad_main_tb 155 VIEW struct.bd 156 GRAPHIC 384,0 89 0 157 DESIGN fad_main_tb 158 VIEW struct.bd 159 GRAPHIC 2942,0 90 0 160 DESIGN fad_main_tb 161 VIEW struct.bd 162 GRAPHIC 424,0 91 0 163 DESIGN fad_main_tb 164 VIEW struct.bd 165 GRAPHIC 2761,0 92 0 166 DESIGN fad_main_tb 167 VIEW struct.bd 168 GRAPHIC 2769,0 93 0 169 DESIGN fad_main_tb 170 VIEW struct.bd 171 GRAPHIC 316,0 94 0 172 DESIGN fad_main_tb 173 VIEW struct.bd 174 GRAPHIC 783,0 95 0 175 DESIGN fad_main_tb 176 VIEW struct.bd 177 GRAPHIC 322,0 96 0 178 DESIGN fad_main_tb 179 VIEW struct.bd 180 GRAPHIC 791,0 97 0 181 DESIGN fad_main_tb 182 VIEW struct.bd 183 GRAPHIC 328,0 98 0 184 DESIGN fad_main_tb 185 VIEW struct.bd 186 GRAPHIC 767,0 99 0 187 DESIGN fad_main_tb 188 VIEW struct.bd 189 GRAPHIC 334,0 100 0 190 DESIGN fad_main_tb 191 VIEW struct.bd 192 NO_GRAPHIC 101 193 DESIGN fad_main_tb 194 VIEW struct.bd 195 NO_GRAPHIC 102 163 196 LIBRARY FACT_FAD_lib 164 197 DESIGN @f@a@d_main 165 198 VIEW struct 166 GRAPHIC 233,0 92 0 167 DESIGN @f@a@d_main 168 VIEW symbol.sb 169 GRAPHIC 14,0 93 1 170 DESIGN @f@a@d_main 171 VIEW symbol.sb 172 GRAPHIC 1755,0 97 0 173 DESIGN @f@a@d_main 174 VIEW symbol.sb 175 GRAPHIC 5328,0 98 0 176 DESIGN @f@a@d_main 177 VIEW symbol.sb 178 GRAPHIC 2710,0 99 0 179 DESIGN @f@a@d_main 180 VIEW symbol.sb 181 GRAPHIC 2715,0 100 0 182 DESIGN @f@a@d_main 183 VIEW symbol.sb 184 GRAPHIC 2720,0 101 0 185 DESIGN @f@a@d_main 186 VIEW symbol.sb 187 GRAPHIC 2725,0 102 0 188 DESIGN @f@a@d_main 189 VIEW symbol.sb 190 GRAPHIC 2282,0 103 0 191 DESIGN @f@a@d_main 192 VIEW symbol.sb 193 GRAPHIC 1976,0 104 0 194 DESIGN @f@a@d_main 195 VIEW symbol.sb 196 GRAPHIC 923,0 105 0 197 DESIGN @f@a@d_main 198 VIEW symbol.sb 199 GRAPHIC 928,0 106 0 200 DESIGN @f@a@d_main 201 VIEW symbol.sb 202 GRAPHIC 5427,0 107 0 203 DESIGN @f@a@d_main 204 VIEW symbol.sb 205 GRAPHIC 5503,0 108 0 206 DESIGN @f@a@d_main 207 VIEW symbol.sb 208 GRAPHIC 464,0 109 0 209 DESIGN @f@a@d_main 210 VIEW symbol.sb 211 GRAPHIC 1062,0 110 0 212 DESIGN @f@a@d_main 213 VIEW symbol.sb 214 GRAPHIC 6704,0 111 0 215 DESIGN @f@a@d_main 216 VIEW symbol.sb 217 GRAPHIC 1389,0 112 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 1725,0 113 0 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 2987,0 114 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 2992,0 115 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 4780,0 116 0 230 DESIGN @f@a@d_main 231 VIEW symbol.sb 232 GRAPHIC 833,0 117 0 233 DESIGN @f@a@d_main 234 VIEW symbol.sb 235 GRAPHIC 5634,0 118 0 236 DESIGN @f@a@d_main 237 VIEW symbol.sb 238 GRAPHIC 5639,0 119 0 239 DESIGN @f@a@d_main 240 VIEW symbol.sb 241 GRAPHIC 4911,0 120 0 242 DESIGN @f@a@d_main 243 VIEW symbol.sb 244 GRAPHIC 5629,0 121 0 245 DESIGN @f@a@d_main 246 VIEW symbol.sb 247 GRAPHIC 3641,0 122 0 248 DESIGN @f@a@d_main 249 VIEW symbol.sb 250 GRAPHIC 4144,0 123 0 251 DESIGN @f@a@d_main 252 VIEW symbol.sb 253 GRAPHIC 2448,0 124 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 2453,0 125 0 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 4906,0 126 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 163,0 127 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 4067,0 128 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 4916,0 129 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 3631,0 130 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 3646,0 131 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 1037,0 132 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 1047,0 133 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 1057,0 134 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 135,0 135 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 1052,0 136 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 3636,0 137 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 1042,0 138 0 199 GRAPHIC 233,0 104 0 200 DESIGN @f@a@d_main 201 VIEW symbol.sb 202 GRAPHIC 14,0 105 1 203 DESIGN @f@a@d_main 204 VIEW symbol.sb 205 GRAPHIC 1755,0 109 0 206 DESIGN @f@a@d_main 207 VIEW symbol.sb 208 GRAPHIC 5328,0 110 0 209 DESIGN @f@a@d_main 210 VIEW symbol.sb 211 GRAPHIC 7621,0 111 0 212 DESIGN @f@a@d_main 213 VIEW symbol.sb 214 GRAPHIC 2710,0 112 0 215 DESIGN @f@a@d_main 216 VIEW symbol.sb 217 GRAPHIC 2715,0 113 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 2720,0 114 0 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 2725,0 115 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 2282,0 116 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 1976,0 117 0 230 DESIGN @f@a@d_main 231 VIEW symbol.sb 232 GRAPHIC 923,0 118 0 233 DESIGN @f@a@d_main 234 VIEW symbol.sb 235 GRAPHIC 928,0 119 0 236 DESIGN @f@a@d_main 237 VIEW symbol.sb 238 GRAPHIC 5427,0 120 0 239 DESIGN @f@a@d_main 240 VIEW symbol.sb 241 GRAPHIC 5503,0 121 0 242 DESIGN @f@a@d_main 243 VIEW symbol.sb 244 GRAPHIC 464,0 122 0 245 DESIGN @f@a@d_main 246 VIEW symbol.sb 247 GRAPHIC 1062,0 123 0 248 DESIGN @f@a@d_main 249 VIEW symbol.sb 250 GRAPHIC 6704,0 124 0 251 DESIGN @f@a@d_main 252 VIEW symbol.sb 253 GRAPHIC 1389,0 125 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 1725,0 126 0 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 8023,0 127 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 7631,0 129 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 7626,0 130 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 7636,0 131 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 2987,0 132 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 2992,0 133 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 4780,0 134 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 833,0 135 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 5634,0 136 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 5639,0 137 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 4911,0 138 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 5629,0 139 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 3641,0 140 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 7882,0 141 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 7887,0 142 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 4144,0 143 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 2448,0 144 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 2453,0 145 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 4906,0 146 0 314 DESIGN @f@a@d_main 315 VIEW symbol.sb 316 GRAPHIC 163,0 147 0 317 DESIGN @f@a@d_main 318 VIEW symbol.sb 319 GRAPHIC 7963,0 148 0 320 DESIGN @f@a@d_main 321 VIEW symbol.sb 322 GRAPHIC 4067,0 149 0 323 DESIGN @f@a@d_main 324 VIEW symbol.sb 325 GRAPHIC 4916,0 150 0 326 DESIGN @f@a@d_main 327 VIEW symbol.sb 328 GRAPHIC 3631,0 151 0 329 DESIGN @f@a@d_main 330 VIEW symbol.sb 331 GRAPHIC 3646,0 152 0 332 DESIGN @f@a@d_main 333 VIEW symbol.sb 334 GRAPHIC 8283,0 153 0 335 DESIGN @f@a@d_main 336 VIEW symbol.sb 337 GRAPHIC 7539,0 154 0 338 DESIGN @f@a@d_main 339 VIEW symbol.sb 340 GRAPHIC 7850,0 155 0 341 DESIGN @f@a@d_main 342 VIEW symbol.sb 343 GRAPHIC 1037,0 156 0 344 DESIGN @f@a@d_main 345 VIEW symbol.sb 346 GRAPHIC 1047,0 157 0 347 DESIGN @f@a@d_main 348 VIEW symbol.sb 349 GRAPHIC 1057,0 158 0 350 DESIGN @f@a@d_main 351 VIEW symbol.sb 352 GRAPHIC 135,0 159 0 353 DESIGN @f@a@d_main 354 VIEW symbol.sb 355 GRAPHIC 1052,0 160 0 356 DESIGN @f@a@d_main 357 VIEW symbol.sb 358 GRAPHIC 3636,0 161 0 359 DESIGN @f@a@d_main 360 VIEW symbol.sb 361 GRAPHIC 1042,0 162 0 296 362 LIBRARY FACT_FAD_TB_lib 297 363 DESIGN adc_emulator 298 364 VIEW @behavioral 299 GRAPHIC 508,0 1 410365 GRAPHIC 508,0 165 0 300 366 DESIGN adc_emulator 301 367 VIEW symbol.sb 302 GRAPHIC 14,0 1 421368 GRAPHIC 14,0 166 1 303 369 DESIGN adc_emulator 304 370 VIEW @behavioral 305 GRAPHIC 48,0 1 460371 GRAPHIC 48,0 170 0 306 372 DESIGN adc_emulator 307 373 VIEW @behavioral 308 GRAPHIC 53,0 1 470374 GRAPHIC 53,0 171 0 309 375 DESIGN adc_emulator 310 376 VIEW @behavioral 311 GRAPHIC 58,0 1 480377 GRAPHIC 58,0 172 0 312 378 DESIGN adc_emulator 313 379 VIEW @behavioral 314 GRAPHIC 63,0 1 490315 DESIGN fad_main_tb 316 VIEW struct.bd 317 GRAPHIC 274,0 1 520380 GRAPHIC 63,0 173 0 381 DESIGN fad_main_tb 382 VIEW struct.bd 383 GRAPHIC 274,0 176 0 318 384 DESIGN clock_generator 319 385 VIEW symbol.sb 320 GRAPHIC 14,0 1 531386 GRAPHIC 14,0 177 1 321 387 DESIGN clock_generator 322 388 VIEW @behavioral 323 GRAPHIC 48,0 1 580389 GRAPHIC 48,0 182 0 324 390 DESIGN clock_generator 325 391 VIEW @behavioral 326 GRAPHIC 53,0 1 590327 DESIGN fad_main_tb 328 VIEW struct.bd 329 GRAPHIC 362,0 1 620392 GRAPHIC 53,0 183 0 393 DESIGN fad_main_tb 394 VIEW struct.bd 395 GRAPHIC 362,0 186 0 330 396 DESIGN max6662_emulator 331 397 VIEW symbol.sb 332 GRAPHIC 14,0 1 631398 GRAPHIC 14,0 187 1 333 399 DESIGN max6662_emulator 334 400 VIEW beha 335 GRAPHIC 48,0 1 670401 GRAPHIC 48,0 191 0 336 402 DESIGN max6662_emulator 337 403 VIEW beha 338 GRAPHIC 53,0 1 680404 GRAPHIC 53,0 192 0 339 405 DESIGN max6662_emulator 340 406 VIEW beha 341 GRAPHIC 58,0 1 690342 DESIGN fad_main_tb 343 VIEW struct.bd 344 GRAPHIC 414,0 1 720407 GRAPHIC 58,0 193 0 408 DESIGN fad_main_tb 409 VIEW struct.bd 410 GRAPHIC 414,0 196 0 345 411 DESIGN trigger_generator 346 412 VIEW symbol.sb 347 GRAPHIC 14,0 1 731413 GRAPHIC 14,0 197 1 348 414 DESIGN trigger_generator 349 415 VIEW beha 350 GRAPHIC 48,0 1780351 DESIGN fad_main_tb 352 VIEW struct.bd 353 GRAPHIC 2336,0 1810416 GRAPHIC 48,0 202 0 417 DESIGN fad_main_tb 418 VIEW struct.bd 419 GRAPHIC 2336,0 205 0 354 420 DESIGN w5300_emulator 355 421 VIEW beha 356 GRAPHIC 163,0 1830422 GRAPHIC 163,0 207 0 357 423 DESIGN w5300_emulator 358 424 VIEW beha 359 GRAPHIC 48,0 1840425 GRAPHIC 48,0 208 0 360 426 DESIGN w5300_emulator 361 427 VIEW beha 362 GRAPHIC 53,0 1850428 GRAPHIC 53,0 209 0 363 429 DESIGN w5300_emulator 364 430 VIEW beha 365 GRAPHIC 58,0 1860431 GRAPHIC 58,0 210 0 366 432 DESIGN w5300_emulator 367 433 VIEW beha 368 GRAPHIC 63,0 187 0 434 GRAPHIC 286,0 211 0 435 DESIGN w5300_emulator 436 VIEW beha 437 GRAPHIC 63,0 212 0 369 438 LIBRARY FACT_FAD_TB_lib 370 439 DESIGN fad_main_tb 371 440 VIEW struct.bd 372 NO_GRAPHIC 190 373 DESIGN fad_main_tb 374 VIEW struct.bd 375 GRAPHIC 233,0 193 0 376 DESIGN fad_main_tb 377 VIEW struct.bd 378 GRAPHIC 508,0 194 0 379 DESIGN fad_main_tb 380 VIEW struct.bd 381 GRAPHIC 274,0 195 0 382 DESIGN fad_main_tb 383 VIEW struct.bd 384 GRAPHIC 362,0 196 0 385 DESIGN fad_main_tb 386 VIEW struct.bd 387 GRAPHIC 414,0 197 0 388 DESIGN fad_main_tb 389 VIEW struct.bd 390 GRAPHIC 2336,0 198 0 391 DESIGN fad_main_tb 392 VIEW struct.bd 393 NO_GRAPHIC 201 394 DESIGN fad_main_tb 395 VIEW struct.bd 396 GRAPHIC 430,0 204 0 397 DESIGN fad_main_tb 398 VIEW struct.bd 399 NO_GRAPHIC 208 400 DESIGN fad_main_tb 401 VIEW struct.bd 402 GRAPHIC 518,0 209 0 403 DESIGN fad_main_tb 404 VIEW struct.bd 405 NO_GRAPHIC 219 406 DESIGN fad_main_tb 407 VIEW struct.bd 408 GRAPHIC 1491,0 220 0 409 DESIGN fad_main_tb 410 VIEW struct.bd 411 NO_GRAPHIC 228 412 DESIGN fad_main_tb 413 VIEW struct.bd 414 NO_GRAPHIC 229 415 DESIGN fad_main_tb 416 VIEW struct.bd 417 GRAPHIC 233,0 231 0 418 DESIGN fad_main_tb 419 VIEW struct.bd 420 GRAPHIC 240,0 232 1 421 DESIGN fad_main_tb 422 VIEW struct.bd 423 GRAPHIC 286,0 236 0 424 DESIGN fad_main_tb 425 VIEW struct.bd 426 GRAPHIC 1503,0 237 0 427 DESIGN fad_main_tb 428 VIEW struct.bd 429 GRAPHIC 873,0 238 0 430 DESIGN fad_main_tb 431 VIEW struct.bd 432 GRAPHIC 881,0 239 0 433 DESIGN fad_main_tb 434 VIEW struct.bd 435 GRAPHIC 889,0 240 0 436 DESIGN fad_main_tb 437 VIEW struct.bd 438 GRAPHIC 897,0 241 0 439 DESIGN fad_main_tb 440 VIEW struct.bd 441 GRAPHIC 538,0 242 0 442 DESIGN fad_main_tb 443 VIEW struct.bd 444 GRAPHIC 530,0 243 0 445 DESIGN fad_main_tb 446 VIEW struct.bd 447 GRAPHIC 442,0 244 0 448 DESIGN fad_main_tb 449 VIEW struct.bd 450 GRAPHIC 450,0 245 0 451 DESIGN fad_main_tb 452 VIEW struct.bd 453 GRAPHIC 1529,0 246 0 454 DESIGN fad_main_tb 455 VIEW struct.bd 456 GRAPHIC 1561,0 247 0 457 DESIGN fad_main_tb 458 VIEW struct.bd 459 GRAPHIC 426,0 248 0 460 DESIGN fad_main_tb 461 VIEW struct.bd 462 GRAPHIC 793,0 249 0 463 DESIGN fad_main_tb 464 VIEW struct.bd 465 GRAPHIC 1684,0 250 0 466 DESIGN fad_main_tb 467 VIEW struct.bd 468 GRAPHIC 825,0 251 0 469 DESIGN fad_main_tb 470 VIEW struct.bd 471 GRAPHIC 833,0 252 0 472 DESIGN fad_main_tb 473 VIEW struct.bd 474 GRAPHIC 857,0 253 0 475 DESIGN fad_main_tb 476 VIEW struct.bd 477 GRAPHIC 865,0 254 0 478 DESIGN fad_main_tb 479 VIEW struct.bd 480 GRAPHIC 1437,0 255 0 481 DESIGN fad_main_tb 482 VIEW struct.bd 483 GRAPHIC 546,0 256 0 484 DESIGN fad_main_tb 485 VIEW struct.bd 486 GRAPHIC 1485,0 257 0 487 DESIGN fad_main_tb 488 VIEW struct.bd 489 GRAPHIC 1477,0 258 0 490 DESIGN fad_main_tb 491 VIEW struct.bd 492 GRAPHIC 1445,0 259 0 493 DESIGN fad_main_tb 494 VIEW struct.bd 495 GRAPHIC 1469,0 260 0 496 DESIGN fad_main_tb 497 VIEW struct.bd 498 GRAPHIC 801,0 261 0 499 DESIGN fad_main_tb 500 VIEW struct.bd 501 GRAPHIC 817,0 262 0 502 DESIGN fad_main_tb 503 VIEW struct.bd 504 GRAPHIC 841,0 263 0 505 DESIGN fad_main_tb 506 VIEW struct.bd 507 GRAPHIC 849,0 264 0 508 DESIGN fad_main_tb 509 VIEW struct.bd 510 GRAPHIC 1461,0 265 0 511 DESIGN fad_main_tb 512 VIEW struct.bd 513 GRAPHIC 777,0 266 0 514 DESIGN fad_main_tb 515 VIEW struct.bd 516 GRAPHIC 809,0 267 0 517 DESIGN fad_main_tb 518 VIEW struct.bd 519 GRAPHIC 1453,0 268 0 520 DESIGN fad_main_tb 521 VIEW struct.bd 522 GRAPHIC 380,0 269 0 523 DESIGN fad_main_tb 524 VIEW struct.bd 525 GRAPHIC 374,0 270 0 526 DESIGN fad_main_tb 527 VIEW struct.bd 528 GRAPHIC 318,0 271 0 529 DESIGN fad_main_tb 530 VIEW struct.bd 531 GRAPHIC 785,0 272 0 532 DESIGN fad_main_tb 533 VIEW struct.bd 534 GRAPHIC 330,0 273 0 535 DESIGN fad_main_tb 536 VIEW struct.bd 537 GRAPHIC 769,0 274 0 538 DESIGN fad_main_tb 539 VIEW struct.bd 540 GRAPHIC 336,0 275 0 541 DESIGN fad_main_tb 542 VIEW struct.bd 543 GRAPHIC 386,0 276 0 544 DESIGN fad_main_tb 545 VIEW struct.bd 546 GRAPHIC 324,0 277 0 547 DESIGN fad_main_tb 548 VIEW struct.bd 549 GRAPHIC 508,0 279 0 550 DESIGN fad_main_tb 551 VIEW struct.bd 552 GRAPHIC 515,0 280 1 553 DESIGN fad_main_tb 554 VIEW struct.bd 555 GRAPHIC 578,0 284 0 556 DESIGN fad_main_tb 557 VIEW struct.bd 558 GRAPHIC 570,0 285 0 559 DESIGN fad_main_tb 560 VIEW struct.bd 561 GRAPHIC 562,0 286 0 562 DESIGN fad_main_tb 563 VIEW struct.bd 564 GRAPHIC 554,0 287 0 565 DESIGN fad_main_tb 566 VIEW struct.bd 567 GRAPHIC 274,0 289 0 568 DESIGN fad_main_tb 569 VIEW struct.bd 570 GRAPHIC 281,0 290 1 571 DESIGN fad_main_tb 572 VIEW struct.bd 573 GRAPHIC 286,0 295 0 574 DESIGN fad_main_tb 575 VIEW struct.bd 576 GRAPHIC 1509,0 298 0 577 DESIGN fad_main_tb 578 VIEW struct.bd 579 GRAPHIC 1516,0 299 1 580 DESIGN fad_main_tb 581 VIEW struct.bd 582 GRAPHIC 1529,0 304 0 583 DESIGN fad_main_tb 584 VIEW struct.bd 585 GRAPHIC 362,0 307 0 586 DESIGN fad_main_tb 587 VIEW struct.bd 588 GRAPHIC 369,0 308 1 589 DESIGN fad_main_tb 590 VIEW struct.bd 591 GRAPHIC 380,0 312 0 592 DESIGN fad_main_tb 593 VIEW struct.bd 594 GRAPHIC 386,0 313 0 595 DESIGN fad_main_tb 596 VIEW struct.bd 597 GRAPHIC 374,0 314 0 598 DESIGN fad_main_tb 599 VIEW struct.bd 600 GRAPHIC 414,0 316 0 601 DESIGN fad_main_tb 602 VIEW struct.bd 603 GRAPHIC 421,0 317 1 604 DESIGN fad_main_tb 605 VIEW struct.bd 606 GRAPHIC 426,0 322 0 607 DESIGN fad_main_tb 608 VIEW struct.bd 609 GRAPHIC 2336,0 324 0 610 DESIGN fad_main_tb 611 VIEW struct.bd 612 GRAPHIC 793,0 326 0 613 DESIGN fad_main_tb 614 VIEW struct.bd 615 GRAPHIC 318,0 327 0 616 DESIGN fad_main_tb 617 VIEW struct.bd 618 GRAPHIC 324,0 328 0 619 DESIGN fad_main_tb 620 VIEW struct.bd 621 GRAPHIC 330,0 329 0 622 DESIGN fad_main_tb 623 VIEW struct.bd 624 GRAPHIC 336,0 330 0 625 DESIGN fad_main_tb 626 VIEW struct.bd 627 NO_GRAPHIC 333 441 NO_GRAPHIC 215 442 DESIGN fad_main_tb 443 VIEW struct.bd 444 GRAPHIC 233,0 218 0 445 DESIGN fad_main_tb 446 VIEW struct.bd 447 GRAPHIC 508,0 219 0 448 DESIGN fad_main_tb 449 VIEW struct.bd 450 GRAPHIC 274,0 220 0 451 DESIGN fad_main_tb 452 VIEW struct.bd 453 GRAPHIC 362,0 221 0 454 DESIGN fad_main_tb 455 VIEW struct.bd 456 GRAPHIC 414,0 222 0 457 DESIGN fad_main_tb 458 VIEW struct.bd 459 GRAPHIC 2336,0 223 0 460 DESIGN fad_main_tb 461 VIEW struct.bd 462 NO_GRAPHIC 226 463 DESIGN fad_main_tb 464 VIEW struct.bd 465 GRAPHIC 430,0 229 0 466 DESIGN fad_main_tb 467 VIEW struct.bd 468 NO_GRAPHIC 233 469 DESIGN fad_main_tb 470 VIEW struct.bd 471 GRAPHIC 518,0 234 0 472 DESIGN fad_main_tb 473 VIEW struct.bd 474 NO_GRAPHIC 244 475 DESIGN fad_main_tb 476 VIEW struct.bd 477 GRAPHIC 1491,0 245 0 478 DESIGN fad_main_tb 479 VIEW struct.bd 480 NO_GRAPHIC 253 481 DESIGN fad_main_tb 482 VIEW struct.bd 483 NO_GRAPHIC 254 484 DESIGN fad_main_tb 485 VIEW struct.bd 486 GRAPHIC 233,0 256 0 487 DESIGN fad_main_tb 488 VIEW struct.bd 489 GRAPHIC 240,0 257 1 490 DESIGN fad_main_tb 491 VIEW struct.bd 492 GRAPHIC 286,0 261 0 493 DESIGN fad_main_tb 494 VIEW struct.bd 495 GRAPHIC 1503,0 262 0 496 DESIGN fad_main_tb 497 VIEW struct.bd 498 GRAPHIC 2779,0 263 0 499 DESIGN fad_main_tb 500 VIEW struct.bd 501 GRAPHIC 873,0 264 0 502 DESIGN fad_main_tb 503 VIEW struct.bd 504 GRAPHIC 881,0 265 0 505 DESIGN fad_main_tb 506 VIEW struct.bd 507 GRAPHIC 889,0 266 0 508 DESIGN fad_main_tb 509 VIEW struct.bd 510 GRAPHIC 897,0 267 0 511 DESIGN fad_main_tb 512 VIEW struct.bd 513 GRAPHIC 538,0 268 0 514 DESIGN fad_main_tb 515 VIEW struct.bd 516 GRAPHIC 530,0 269 0 517 DESIGN fad_main_tb 518 VIEW struct.bd 519 GRAPHIC 442,0 270 0 520 DESIGN fad_main_tb 521 VIEW struct.bd 522 GRAPHIC 450,0 271 0 523 DESIGN fad_main_tb 524 VIEW struct.bd 525 GRAPHIC 1529,0 272 0 526 DESIGN fad_main_tb 527 VIEW struct.bd 528 GRAPHIC 1561,0 273 0 529 DESIGN fad_main_tb 530 VIEW struct.bd 531 GRAPHIC 426,0 274 0 532 DESIGN fad_main_tb 533 VIEW struct.bd 534 GRAPHIC 793,0 275 0 535 DESIGN fad_main_tb 536 VIEW struct.bd 537 GRAPHIC 1684,0 276 0 538 DESIGN fad_main_tb 539 VIEW struct.bd 540 GRAPHIC 825,0 277 0 541 DESIGN fad_main_tb 542 VIEW struct.bd 543 GRAPHIC 833,0 278 0 544 DESIGN fad_main_tb 545 VIEW struct.bd 546 GRAPHIC 2723,0 279 0 547 DESIGN fad_main_tb 548 VIEW struct.bd 549 GRAPHIC 2731,0 280 0 550 DESIGN fad_main_tb 551 VIEW struct.bd 552 GRAPHIC 2739,0 281 0 553 DESIGN fad_main_tb 554 VIEW struct.bd 555 GRAPHIC 2747,0 282 0 556 DESIGN fad_main_tb 557 VIEW struct.bd 558 GRAPHIC 857,0 283 0 559 DESIGN fad_main_tb 560 VIEW struct.bd 561 GRAPHIC 865,0 284 0 562 DESIGN fad_main_tb 563 VIEW struct.bd 564 GRAPHIC 1437,0 285 0 565 DESIGN fad_main_tb 566 VIEW struct.bd 567 GRAPHIC 546,0 286 0 568 DESIGN fad_main_tb 569 VIEW struct.bd 570 GRAPHIC 1485,0 287 0 571 DESIGN fad_main_tb 572 VIEW struct.bd 573 GRAPHIC 1477,0 288 0 574 DESIGN fad_main_tb 575 VIEW struct.bd 576 GRAPHIC 1445,0 289 0 577 DESIGN fad_main_tb 578 VIEW struct.bd 579 GRAPHIC 1469,0 290 0 580 DESIGN fad_main_tb 581 VIEW struct.bd 582 GRAPHIC 801,0 291 0 583 DESIGN fad_main_tb 584 VIEW struct.bd 585 GRAPHIC 2707,0 292 0 586 DESIGN fad_main_tb 587 VIEW struct.bd 588 GRAPHIC 2715,0 293 0 589 DESIGN fad_main_tb 590 VIEW struct.bd 591 GRAPHIC 817,0 294 0 592 DESIGN fad_main_tb 593 VIEW struct.bd 594 GRAPHIC 841,0 295 0 595 DESIGN fad_main_tb 596 VIEW struct.bd 597 GRAPHIC 849,0 296 0 598 DESIGN fad_main_tb 599 VIEW struct.bd 600 GRAPHIC 1461,0 297 0 601 DESIGN fad_main_tb 602 VIEW struct.bd 603 GRAPHIC 777,0 298 0 604 DESIGN fad_main_tb 605 VIEW struct.bd 606 GRAPHIC 2755,0 299 0 607 DESIGN fad_main_tb 608 VIEW struct.bd 609 GRAPHIC 809,0 300 0 610 DESIGN fad_main_tb 611 VIEW struct.bd 612 GRAPHIC 1453,0 301 0 613 DESIGN fad_main_tb 614 VIEW struct.bd 615 GRAPHIC 380,0 302 0 616 DESIGN fad_main_tb 617 VIEW struct.bd 618 GRAPHIC 374,0 303 0 619 DESIGN fad_main_tb 620 VIEW struct.bd 621 GRAPHIC 2944,0 304 0 622 DESIGN fad_main_tb 623 VIEW struct.bd 624 GRAPHIC 2763,0 305 0 625 DESIGN fad_main_tb 626 VIEW struct.bd 627 GRAPHIC 2771,0 306 0 628 DESIGN fad_main_tb 629 VIEW struct.bd 630 GRAPHIC 318,0 307 0 631 DESIGN fad_main_tb 632 VIEW struct.bd 633 GRAPHIC 785,0 308 0 634 DESIGN fad_main_tb 635 VIEW struct.bd 636 GRAPHIC 330,0 309 0 637 DESIGN fad_main_tb 638 VIEW struct.bd 639 GRAPHIC 769,0 310 0 640 DESIGN fad_main_tb 641 VIEW struct.bd 642 GRAPHIC 336,0 311 0 643 DESIGN fad_main_tb 644 VIEW struct.bd 645 GRAPHIC 386,0 312 0 646 DESIGN fad_main_tb 647 VIEW struct.bd 648 GRAPHIC 324,0 313 0 649 DESIGN fad_main_tb 650 VIEW struct.bd 651 GRAPHIC 508,0 315 0 652 DESIGN fad_main_tb 653 VIEW struct.bd 654 GRAPHIC 515,0 316 1 655 DESIGN fad_main_tb 656 VIEW struct.bd 657 GRAPHIC 578,0 320 0 658 DESIGN fad_main_tb 659 VIEW struct.bd 660 GRAPHIC 570,0 321 0 661 DESIGN fad_main_tb 662 VIEW struct.bd 663 GRAPHIC 562,0 322 0 664 DESIGN fad_main_tb 665 VIEW struct.bd 666 GRAPHIC 554,0 323 0 667 DESIGN fad_main_tb 668 VIEW struct.bd 669 GRAPHIC 274,0 325 0 670 DESIGN fad_main_tb 671 VIEW struct.bd 672 GRAPHIC 281,0 326 1 673 DESIGN fad_main_tb 674 VIEW struct.bd 675 GRAPHIC 286,0 331 0 676 DESIGN fad_main_tb 677 VIEW struct.bd 678 GRAPHIC 1509,0 334 0 679 DESIGN fad_main_tb 680 VIEW struct.bd 681 GRAPHIC 1516,0 335 1 682 DESIGN fad_main_tb 683 VIEW struct.bd 684 GRAPHIC 1529,0 340 0 685 DESIGN fad_main_tb 686 VIEW struct.bd 687 GRAPHIC 362,0 343 0 688 DESIGN fad_main_tb 689 VIEW struct.bd 690 GRAPHIC 369,0 344 1 691 DESIGN fad_main_tb 692 VIEW struct.bd 693 GRAPHIC 380,0 348 0 694 DESIGN fad_main_tb 695 VIEW struct.bd 696 GRAPHIC 386,0 349 0 697 DESIGN fad_main_tb 698 VIEW struct.bd 699 GRAPHIC 374,0 350 0 700 DESIGN fad_main_tb 701 VIEW struct.bd 702 GRAPHIC 414,0 352 0 703 DESIGN fad_main_tb 704 VIEW struct.bd 705 GRAPHIC 421,0 353 1 706 DESIGN fad_main_tb 707 VIEW struct.bd 708 GRAPHIC 426,0 358 0 709 DESIGN fad_main_tb 710 VIEW struct.bd 711 GRAPHIC 2336,0 360 0 712 DESIGN fad_main_tb 713 VIEW struct.bd 714 GRAPHIC 793,0 362 0 715 DESIGN fad_main_tb 716 VIEW struct.bd 717 GRAPHIC 318,0 363 0 718 DESIGN fad_main_tb 719 VIEW struct.bd 720 GRAPHIC 324,0 364 0 721 DESIGN fad_main_tb 722 VIEW struct.bd 723 GRAPHIC 330,0 365 0 724 DESIGN fad_main_tb 725 VIEW struct.bd 726 GRAPHIC 785,0 366 0 727 DESIGN fad_main_tb 728 VIEW struct.bd 729 GRAPHIC 336,0 367 0 730 DESIGN fad_main_tb 731 VIEW struct.bd 732 NO_GRAPHIC 370 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd
r10240 r10883 206 206 (vvPair 207 207 variable "date" 208 value " 04.03.2011"208 value "25.05.2011" 209 209 ) 210 210 (vvPair 211 211 variable "day" 212 value " Fr"212 value "Mi" 213 213 ) 214 214 (vvPair 215 215 variable "day_long" 216 value " Freitag"216 value "Mittwoch" 217 217 ) 218 218 (vvPair 219 219 variable "dd" 220 value " 04"220 value "25" 221 221 ) 222 222 (vvPair … … 278 278 (vvPair 279 279 variable "mm" 280 value "0 3"280 value "05" 281 281 ) 282 282 (vvPair … … 286 286 (vvPair 287 287 variable "month" 288 value "M rz"288 value "Mai" 289 289 ) 290 290 (vvPair 291 291 variable "month_long" 292 value "M ärz"292 value "Mai" 293 293 ) 294 294 (vvPair … … 354 354 (vvPair 355 355 variable "time" 356 value "1 1:37:19"356 value "17:24:50" 357 357 ) 358 358 (vvPair … … 406 406 bg "0,0,32768" 407 407 ) 408 xt "109200,97000,120 300,98000"408 xt "109200,97000,120000,98000" 409 409 st " 410 410 by %user on %dd %month %year … … 734 734 va (VaSet 735 735 ) 736 xt "10 4400,23500,108000,24500"736 xt "103800,23500,108000,24500" 737 737 st "wiz_reset" 738 738 ju 2 … … 745 745 n "wiz_reset" 746 746 t "std_logic" 747 o 39747 o 50 748 748 suid 2,0 749 749 i "'1'" … … 771 771 va (VaSet 772 772 ) 773 xt "10 4000,69500,108000,70500"773 xt "103600,69500,108000,70500" 774 774 st "led : (7:0)" 775 775 ju 2 … … 784 784 b "(7 DOWNTO 0)" 785 785 posAdd 0 786 o 3 1786 o 38 787 787 suid 7,0 788 788 i "(OTHERS => '0')" … … 810 810 va (VaSet 811 811 ) 812 xt "82000,31500,8 4800,32500"812 xt "82000,31500,85000,32500" 813 813 st "trigger" 814 814 blo "82000,32300" … … 821 821 preAdd 0 822 822 posAdd 0 823 o 1 3823 o 14 824 824 suid 18,0 825 825 ) … … 846 846 va (VaSet 847 847 ) 848 xt "82000,42500,85 200,43500"848 xt "82000,42500,85500,43500" 849 849 st "adc_oeb" 850 850 blo "82000,43300" … … 856 856 n "adc_oeb" 857 857 t "std_logic" 858 o 2 1858 o 26 859 859 suid 21,0 860 860 i "'1'" … … 882 882 va (VaSet 883 883 ) 884 xt "82000,33500,8 7900,34500"884 xt "82000,33500,88700,34500" 885 885 st "board_id : (3:0)" 886 886 blo "82000,34300" … … 892 892 t "std_logic_vector" 893 893 b "(3 DOWNTO 0)" 894 o 9894 o 10 895 895 suid 24,0 896 896 ) … … 917 917 va (VaSet 918 918 ) 919 xt "82000,34500,8 7700,35500"919 xt "82000,34500,88400,35500" 920 920 st "crate_id : (1:0)" 921 921 blo "82000,35300" … … 927 927 t "std_logic_vector" 928 928 b "(1 DOWNTO 0)" 929 o 1 0929 o 11 930 930 suid 25,0 931 931 ) … … 952 952 va (VaSet 953 953 ) 954 xt "10 2000,20500,108000,21500"954 xt "101100,20500,108000,21500" 955 955 st "wiz_addr : (9:0)" 956 956 ju 2 … … 964 964 t "std_logic_vector" 965 965 b "(9 DOWNTO 0)" 966 o 36966 o 47 967 967 suid 26,0 968 968 ) … … 989 989 va (VaSet 990 990 ) 991 xt "10 1700,21500,108000,22500"991 xt "100800,21500,108000,22500" 992 992 st "wiz_data : (15:0)" 993 993 ju 2 … … 1001 1001 t "std_logic_vector" 1002 1002 b "(15 DOWNTO 0)" 1003 o 421003 o 53 1004 1004 suid 27,0 1005 1005 ) … … 1026 1026 va (VaSet 1027 1027 ) 1028 xt "105 300,27500,108000,28500"1028 xt "105000,27500,108000,28500" 1029 1029 st "wiz_cs" 1030 1030 ju 2 … … 1037 1037 n "wiz_cs" 1038 1038 t "std_logic" 1039 o 371039 o 48 1040 1040 suid 28,0 1041 1041 i "'1'" … … 1063 1063 va (VaSet 1064 1064 ) 1065 xt "10 5300,25500,108000,26500"1065 xt "104800,25500,108000,26500" 1066 1066 st "wiz_wr" 1067 1067 ju 2 … … 1074 1074 n "wiz_wr" 1075 1075 t "std_logic" 1076 o 401076 o 51 1077 1077 suid 29,0 1078 1078 i "'1'" … … 1100 1100 va (VaSet 1101 1101 ) 1102 xt "10 5400,24500,108000,25500"1102 xt "104900,24500,108000,25500" 1103 1103 st "wiz_rd" 1104 1104 ju 2 … … 1111 1111 n "wiz_rd" 1112 1112 t "std_logic" 1113 o 381113 o 49 1114 1114 suid 30,0 1115 1115 i "'1'" … … 1137 1137 va (VaSet 1138 1138 ) 1139 xt "10 5300,26500,108000,27500"1139 xt "104800,26500,108000,27500" 1140 1140 st "wiz_int" 1141 1141 ju 2 … … 1147 1147 n "wiz_int" 1148 1148 t "std_logic" 1149 o 1 41149 o 15 1150 1150 suid 31,0 1151 1151 ) … … 1172 1172 va (VaSet 1173 1173 ) 1174 xt "82000,22500,86 500,23500"1174 xt "82000,22500,86800,23500" 1175 1175 st "CLK_25_PS" 1176 1176 blo "82000,23300" … … 1182 1182 n "CLK_25_PS" 1183 1183 t "std_logic" 1184 o 1 61184 o 17 1185 1185 suid 35,0 1186 1186 ) … … 1207 1207 va (VaSet 1208 1208 ) 1209 xt "82000,21500,85 100,22500"1209 xt "82000,21500,85300,22500" 1210 1210 st "CLK_50" 1211 1211 blo "82000,22300" … … 1219 1219 preAdd 0 1220 1220 posAdd 0 1221 o 1 71221 o 18 1222 1222 suid 37,0 1223 1223 ) … … 1278 1278 va (VaSet 1279 1279 ) 1280 xt "82000,41500,9 0000,42500"1280 xt "82000,41500,91300,42500" 1281 1281 st "adc_otr_array : (3:0)" 1282 1282 blo "82000,42300" … … 1288 1288 t "std_logic_vector" 1289 1289 b "(3 DOWNTO 0)" 1290 o 81290 o 9 1291 1291 suid 40,0 1292 1292 ) … … 1313 1313 va (VaSet 1314 1314 ) 1315 xt "82000,47500,8 7900,48500"1315 xt "82000,47500,88900,48500" 1316 1316 st "adc_data_array" 1317 1317 blo "82000,48300" … … 1322 1322 n "adc_data_array" 1323 1323 t "adc_data_array_type" 1324 o 71324 o 8 1325 1325 suid 41,0 1326 1326 ) … … 1347 1347 va (VaSet 1348 1348 ) 1349 xt "82000,61500,9 0500,62500"1349 xt "82000,61500,91500,62500" 1350 1350 st "drs_channel_id : (3:0)" 1351 1351 blo "82000,62300" … … 1358 1358 t "std_logic_vector" 1359 1359 b "(3 downto 0)" 1360 o 281360 o 35 1361 1361 suid 48,0 1362 1362 i "(others => '0')" … … 1384 1384 va (VaSet 1385 1385 ) 1386 xt "82000,66500,8 6300,67500"1386 xt "82000,66500,87200,67500" 1387 1387 st "drs_dwrite" 1388 1388 blo "82000,67300" … … 1394 1394 n "drs_dwrite" 1395 1395 t "std_logic" 1396 o 291396 o 36 1397 1397 suid 49,0 1398 1398 i "'1'" … … 1420 1420 va (VaSet 1421 1421 ) 1422 xt "82000,57500,87 400,58500"1422 xt "82000,57500,87800,58500" 1423 1423 st "SROUT_in_0" 1424 1424 blo "82000,58300" … … 1429 1429 n "SROUT_in_0" 1430 1430 t "std_logic" 1431 o 31431 o 4 1432 1432 suid 52,0 1433 1433 ) … … 1454 1454 va (VaSet 1455 1455 ) 1456 xt "82000,58500,87 400,59500"1456 xt "82000,58500,87700,59500" 1457 1457 st "SROUT_in_1" 1458 1458 blo "82000,59300" … … 1463 1463 n "SROUT_in_1" 1464 1464 t "std_logic" 1465 o 41465 o 5 1466 1466 suid 53,0 1467 1467 ) … … 1488 1488 va (VaSet 1489 1489 ) 1490 xt "82000,59500,87 400,60500"1490 xt "82000,59500,87800,60500" 1491 1491 st "SROUT_in_2" 1492 1492 blo "82000,60300" … … 1497 1497 n "SROUT_in_2" 1498 1498 t "std_logic" 1499 o 51499 o 6 1500 1500 suid 54,0 1501 1501 ) … … 1522 1522 va (VaSet 1523 1523 ) 1524 xt "82000,60500,87 400,61500"1524 xt "82000,60500,87800,61500" 1525 1525 st "SROUT_in_3" 1526 1526 blo "82000,61300" … … 1531 1531 n "SROUT_in_3" 1532 1532 t "std_logic" 1533 o 61533 o 7 1534 1534 suid 55,0 1535 1535 ) … … 1566 1566 n "RSRLOAD" 1567 1567 t "std_logic" 1568 o 181568 o 23 1569 1569 suid 56,0 1570 1570 i "'0'" … … 1592 1592 va (VaSet 1593 1593 ) 1594 xt "82000,64500,8 5000,65500"1594 xt "82000,64500,84900,65500" 1595 1595 st "SRCLK" 1596 1596 blo "82000,65300" … … 1602 1602 n "SRCLK" 1603 1603 t "std_logic" 1604 o 191604 o 24 1605 1605 suid 57,0 1606 1606 i "'0'" … … 1628 1628 va (VaSet 1629 1629 ) 1630 xt "106 300,50500,108000,51500"1630 xt "106100,50500,108000,51500" 1631 1631 st "sclk" 1632 1632 ju 2 … … 1639 1639 n "sclk" 1640 1640 t "std_logic" 1641 o 341641 o 42 1642 1642 suid 62,0 1643 1643 ) … … 1677 1677 preAdd 0 1678 1678 posAdd 0 1679 o 411679 o 52 1680 1680 suid 63,0 1681 1681 ) … … 1702 1702 va (VaSet 1703 1703 ) 1704 xt "105 200,39500,108000,40500"1704 xt "105000,39500,108000,40500" 1705 1705 st "dac_cs" 1706 1706 ju 2 … … 1713 1713 n "dac_cs" 1714 1714 t "std_logic" 1715 o 261715 o 31 1716 1716 suid 64,0 1717 1717 ) … … 1738 1738 va (VaSet 1739 1739 ) 1740 xt "101 500,41500,108000,42500"1740 xt "101000,41500,108000,42500" 1741 1741 st "sensor_cs : (3:0)" 1742 1742 ju 2 … … 1750 1750 t "std_logic_vector" 1751 1751 b "(3 DOWNTO 0)" 1752 o 351752 o 43 1753 1753 suid 65,0 1754 1754 ) … … 1786 1786 n "mosi" 1787 1787 t "std_logic" 1788 o 321788 o 40 1789 1789 suid 66,0 1790 1790 i "'0'" … … 1812 1812 va (VaSet 1813 1813 ) 1814 xt "82000,65500,85 000,66500"1814 xt "82000,65500,85200,66500" 1815 1815 st "denable" 1816 1816 blo "82000,66300" … … 1824 1824 eolc "-- default domino wave off" 1825 1825 posAdd 0 1826 o 271826 o 34 1827 1827 suid 67,0 1828 1828 i "'0'" … … 1850 1850 va (VaSet 1851 1851 ) 1852 xt "9 9400,73500,108000,74500"1852 xt "98000,73500,108000,74500" 1853 1853 st "alarm_refclk_too_high" 1854 1854 ju 2 … … 1861 1861 n "alarm_refclk_too_high" 1862 1862 t "std_logic" 1863 o 2 21863 o 27 1864 1864 suid 95,0 1865 1865 ) … … 1886 1886 va (VaSet 1887 1887 ) 1888 xt "9 9800,74500,108000,75500"1888 xt "98400,74500,108000,75500" 1889 1889 st "alarm_refclk_too_low" 1890 1890 ju 2 … … 1898 1898 t "std_logic" 1899 1899 posAdd 0 1900 o 2 31900 o 28 1901 1901 suid 96,0 1902 1902 ) … … 1923 1923 va (VaSet 1924 1924 ) 1925 xt "105 500,79500,108000,80500"1925 xt "105300,79500,108000,80500" 1926 1926 st "amber" 1927 1927 ju 2 … … 1934 1934 n "amber" 1935 1935 t "std_logic" 1936 o 2 41936 o 29 1937 1937 suid 87,0 1938 1938 ) … … 1959 1959 va (VaSet 1960 1960 ) 1961 xt "9 9400,76500,108000,77500"1961 xt "98400,76500,108000,77500" 1962 1962 st "counter_result : (11:0)" 1963 1963 ju 2 … … 1971 1971 t "std_logic_vector" 1972 1972 b "(11 DOWNTO 0)" 1973 o 251973 o 30 1974 1974 suid 94,0 1975 1975 ) … … 2031 2031 va (VaSet 2032 2032 ) 2033 xt "82000,75500,8 7100,76500"2033 xt "82000,75500,88100,76500" 2034 2034 st "drs_refclk_in" 2035 2035 blo "82000,76300" … … 2041 2041 t "std_logic" 2042 2042 eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 2043 o 1 12043 o 12 2044 2044 suid 92,0 2045 2045 ) … … 2077 2077 n "green" 2078 2078 t "std_logic" 2079 o 3 02079 o 37 2080 2080 suid 86,0 2081 2081 ) … … 2102 2102 va (VaSet 2103 2103 ) 2104 xt "82000,76500,88 100,77500"2104 xt "82000,76500,88700,77500" 2105 2105 st "plllock_in : (3:0)" 2106 2106 blo "82000,77300" … … 2113 2113 b "(3 DOWNTO 0)" 2114 2114 eolc "-- high level, if dominowave is running and DRS PLL locked" 2115 o 1 22115 o 13 2116 2116 suid 93,0 2117 2117 ) … … 2138 2138 va (VaSet 2139 2139 ) 2140 xt "106 500,78500,108000,79500"2140 xt "106300,78500,108000,79500" 2141 2141 st "red" 2142 2142 ju 2 … … 2149 2149 n "red" 2150 2150 t "std_logic" 2151 o 332151 o 41 2152 2152 suid 88,0 2153 2153 ) … … 2174 2174 va (VaSet 2175 2175 ) 2176 xt "82000,71500,8 5700,72500"2176 xt "82000,71500,86200,72500" 2177 2177 st "SRIN_out" 2178 2178 blo "82000,72300" … … 2184 2184 n "SRIN_out" 2185 2185 t "std_logic" 2186 o 2 02186 o 25 2187 2187 suid 85,0 2188 2188 i "'0'" … … 2221 2221 n "ADC_CLK" 2222 2222 t "std_logic" 2223 o 1 52223 o 16 2224 2224 suid 97,0 2225 ) 2226 ) 2227 ) 2228 *55 (CptPort 2229 uid 2651,0 2230 ps "OnEdgeStrategy" 2231 shape (Triangle 2232 uid 2652,0 2233 ro 90 2234 va (VaSet 2235 vasetType 1 2236 fg "0,65535,0" 2237 ) 2238 xt "109000,80625,109750,81375" 2239 ) 2240 tg (CPTG 2241 uid 2653,0 2242 ps "CptPortTextPlaceStrategy" 2243 stg "RightVerticalLayoutStrategy" 2244 f (Text 2245 uid 2654,0 2246 va (VaSet 2247 ) 2248 xt "97600,80500,108000,81500" 2249 st "debug_data_ram_empty" 2250 ju 2 2251 blo "108000,81300" 2252 ) 2253 ) 2254 thePort (LogicalPort 2255 m 1 2256 decl (Decl 2257 n "debug_data_ram_empty" 2258 t "std_logic" 2259 o 32 2260 suid 104,0 2261 ) 2262 ) 2263 ) 2264 *56 (CptPort 2265 uid 2655,0 2266 ps "OnEdgeStrategy" 2267 shape (Triangle 2268 uid 2656,0 2269 ro 90 2270 va (VaSet 2271 vasetType 1 2272 fg "0,65535,0" 2273 ) 2274 xt "109000,81625,109750,82375" 2275 ) 2276 tg (CPTG 2277 uid 2657,0 2278 ps "CptPortTextPlaceStrategy" 2279 stg "RightVerticalLayoutStrategy" 2280 f (Text 2281 uid 2658,0 2282 va (VaSet 2283 ) 2284 xt "100500,81500,108000,82500" 2285 st "debug_data_valid" 2286 ju 2 2287 blo "108000,82300" 2288 ) 2289 ) 2290 thePort (LogicalPort 2291 m 1 2292 decl (Decl 2293 n "debug_data_valid" 2294 t "std_logic" 2295 o 33 2296 suid 105,0 2297 ) 2298 ) 2299 ) 2300 *57 (CptPort 2301 uid 2659,0 2302 ps "OnEdgeStrategy" 2303 shape (Triangle 2304 uid 2660,0 2305 ro 90 2306 va (VaSet 2307 vasetType 1 2308 fg "0,65535,0" 2309 ) 2310 xt "109000,82625,109750,83375" 2311 ) 2312 tg (CPTG 2313 uid 2661,0 2314 ps "CptPortTextPlaceStrategy" 2315 stg "RightVerticalLayoutStrategy" 2316 f (Text 2317 uid 2662,0 2318 va (VaSet 2319 ) 2320 xt "101100,82500,108000,83500" 2321 st "DG_state : (7:0)" 2322 ju 2 2323 blo "108000,83300" 2324 ) 2325 ) 2326 thePort (LogicalPort 2327 m 1 2328 decl (Decl 2329 n "DG_state" 2330 t "std_logic_vector" 2331 b "(7 downto 0)" 2332 prec "-- for debugging" 2333 preAdd 0 2334 o 19 2335 suid 108,0 2336 ) 2337 ) 2338 ) 2339 *58 (CptPort 2340 uid 2663,0 2341 ps "OnEdgeStrategy" 2342 shape (Triangle 2343 uid 2664,0 2344 ro 90 2345 va (VaSet 2346 vasetType 1 2347 fg "0,65535,0" 2348 ) 2349 xt "80250,77625,81000,78375" 2350 ) 2351 tg (CPTG 2352 uid 2665,0 2353 ps "CptPortTextPlaceStrategy" 2354 stg "VerticalLayoutStrategy" 2355 f (Text 2356 uid 2666,0 2357 va (VaSet 2358 ) 2359 xt "82000,77500,90100,78500" 2360 st "FTM_RS485_rx_d" 2361 blo "82000,78300" 2362 ) 2363 ) 2364 thePort (LogicalPort 2365 decl (Decl 2366 n "FTM_RS485_rx_d" 2367 t "std_logic" 2368 o 3 2369 suid 99,0 2370 ) 2371 ) 2372 ) 2373 *59 (CptPort 2374 uid 2667,0 2375 ps "OnEdgeStrategy" 2376 shape (Triangle 2377 uid 2668,0 2378 ro 90 2379 va (VaSet 2380 vasetType 1 2381 fg "0,65535,0" 2382 ) 2383 xt "109000,83625,109750,84375" 2384 ) 2385 tg (CPTG 2386 uid 2669,0 2387 ps "CptPortTextPlaceStrategy" 2388 stg "RightVerticalLayoutStrategy" 2389 f (Text 2390 uid 2670,0 2391 va (VaSet 2392 ) 2393 xt "99600,83500,108000,84500" 2394 st "FTM_RS485_rx_en" 2395 ju 2 2396 blo "108000,84300" 2397 ) 2398 ) 2399 thePort (LogicalPort 2400 m 1 2401 decl (Decl 2402 n "FTM_RS485_rx_en" 2403 t "std_logic" 2404 o 20 2405 suid 101,0 2406 ) 2407 ) 2408 ) 2409 *60 (CptPort 2410 uid 2671,0 2411 ps "OnEdgeStrategy" 2412 shape (Triangle 2413 uid 2672,0 2414 ro 90 2415 va (VaSet 2416 vasetType 1 2417 fg "0,65535,0" 2418 ) 2419 xt "109000,84625,109750,85375" 2420 ) 2421 tg (CPTG 2422 uid 2673,0 2423 ps "CptPortTextPlaceStrategy" 2424 stg "RightVerticalLayoutStrategy" 2425 f (Text 2426 uid 2674,0 2427 va (VaSet 2428 ) 2429 xt "99900,84500,108000,85500" 2430 st "FTM_RS485_tx_d" 2431 ju 2 2432 blo "108000,85300" 2433 ) 2434 ) 2435 thePort (LogicalPort 2436 m 1 2437 decl (Decl 2438 n "FTM_RS485_tx_d" 2439 t "std_logic" 2440 o 21 2441 suid 100,0 2442 ) 2443 ) 2444 ) 2445 *61 (CptPort 2446 uid 2675,0 2447 ps "OnEdgeStrategy" 2448 shape (Triangle 2449 uid 2676,0 2450 ro 90 2451 va (VaSet 2452 vasetType 1 2453 fg "0,65535,0" 2454 ) 2455 xt "109000,85625,109750,86375" 2456 ) 2457 tg (CPTG 2458 uid 2677,0 2459 ps "CptPortTextPlaceStrategy" 2460 stg "RightVerticalLayoutStrategy" 2461 f (Text 2462 uid 2678,0 2463 va (VaSet 2464 ) 2465 xt "99600,85500,108000,86500" 2466 st "FTM_RS485_tx_en" 2467 ju 2 2468 blo "108000,86300" 2469 ) 2470 ) 2471 thePort (LogicalPort 2472 m 1 2473 decl (Decl 2474 n "FTM_RS485_tx_en" 2475 t "std_logic" 2476 o 22 2477 suid 102,0 2478 ) 2479 ) 2480 ) 2481 *62 (CptPort 2482 uid 2679,0 2483 ps "OnEdgeStrategy" 2484 shape (Triangle 2485 uid 2680,0 2486 ro 90 2487 va (VaSet 2488 vasetType 1 2489 fg "0,65535,0" 2490 ) 2491 xt "109000,86625,109750,87375" 2492 ) 2493 tg (CPTG 2494 uid 2681,0 2495 ps "CptPortTextPlaceStrategy" 2496 stg "RightVerticalLayoutStrategy" 2497 f (Text 2498 uid 2682,0 2499 va (VaSet 2500 ) 2501 xt "96600,86500,108000,87500" 2502 st "mem_manager_state : (3:0)" 2503 ju 2 2504 blo "108000,87300" 2505 ) 2506 ) 2507 thePort (LogicalPort 2508 lang 2 2509 m 1 2510 decl (Decl 2511 n "mem_manager_state" 2512 t "std_logic_vector" 2513 b "(3 DOWNTO 0)" 2514 eolc "-- state is encoded here ... useful for debugging." 2515 posAdd 0 2516 o 39 2517 suid 106,0 2518 ) 2519 ) 2520 ) 2521 *63 (CptPort 2522 uid 2683,0 2523 ps "OnEdgeStrategy" 2524 shape (Triangle 2525 uid 2684,0 2526 ro 90 2527 va (VaSet 2528 vasetType 1 2529 fg "0,65535,0" 2530 ) 2531 xt "109000,87625,109750,88375" 2532 ) 2533 tg (CPTG 2534 uid 2685,0 2535 ps "CptPortTextPlaceStrategy" 2536 stg "RightVerticalLayoutStrategy" 2537 f (Text 2538 uid 2686,0 2539 va (VaSet 2540 ) 2541 xt "102400,87500,108000,88500" 2542 st "trigger_veto" 2543 ju 2 2544 blo "108000,88300" 2545 ) 2546 ) 2547 thePort (LogicalPort 2548 m 1 2549 decl (Decl 2550 n "trigger_veto" 2551 t "std_logic" 2552 o 45 2553 suid 98,0 2554 i "'1'" 2555 ) 2556 ) 2557 ) 2558 *64 (CptPort 2559 uid 2687,0 2560 ps "OnEdgeStrategy" 2561 shape (Triangle 2562 uid 2688,0 2563 ro 90 2564 va (VaSet 2565 vasetType 1 2566 fg "0,65535,0" 2567 ) 2568 xt "109000,88625,109750,89375" 2569 ) 2570 tg (CPTG 2571 uid 2689,0 2572 ps "CptPortTextPlaceStrategy" 2573 stg "RightVerticalLayoutStrategy" 2574 f (Text 2575 uid 2690,0 2576 va (VaSet 2577 ) 2578 xt "99600,88500,108000,89500" 2579 st "w5300_state : (7:0)" 2580 ju 2 2581 blo "108000,89300" 2582 ) 2583 ) 2584 thePort (LogicalPort 2585 m 1 2586 decl (Decl 2587 n "w5300_state" 2588 t "std_logic_vector" 2589 b "(7 DOWNTO 0)" 2590 eolc "-- state is encoded here ... useful for debugging." 2591 posAdd 0 2592 o 46 2593 suid 103,0 2594 ) 2595 ) 2596 ) 2597 *65 (CptPort 2598 uid 2924,0 2599 ps "OnEdgeStrategy" 2600 shape (Triangle 2601 uid 2925,0 2602 ro 90 2603 va (VaSet 2604 vasetType 1 2605 fg "0,65535,0" 2606 ) 2607 xt "109000,89625,109750,90375" 2608 ) 2609 tg (CPTG 2610 uid 2926,0 2611 ps "CptPortTextPlaceStrategy" 2612 stg "RightVerticalLayoutStrategy" 2613 f (Text 2614 uid 2927,0 2615 va (VaSet 2616 ) 2617 xt "96100,89500,108000,90500" 2618 st "socket_tx_free_out : (16:0)" 2619 ju 2 2620 blo "108000,90300" 2621 ) 2622 ) 2623 thePort (LogicalPort 2624 m 1 2625 decl (Decl 2626 n "socket_tx_free_out" 2627 t "std_logic_vector" 2628 b "(16 DOWNTO 0)" 2629 eolc "-- 17bit value .. that's true" 2630 posAdd 0 2631 o 44 2632 suid 109,0 2225 2633 ) 2226 2634 ) … … 2235 2643 lineWidth 2 2236 2644 ) 2237 xt "81000,19000,109000, 81000"2645 xt "81000,19000,109000,91000" 2238 2646 ) 2239 2647 oxt "15000,-8000,43000,46000" … … 2243 2651 stg "VerticalLayoutStrategy" 2244 2652 textVec [ 2245 * 55(Text2653 *66 (Text 2246 2654 uid 236,0 2247 2655 va (VaSet … … 2253 2661 tm "BdLibraryNameMgr" 2254 2662 ) 2255 * 56(Text2663 *67 (Text 2256 2664 uid 237,0 2257 2665 va (VaSet … … 2263 2671 tm "CptNameMgr" 2264 2672 ) 2265 * 57(Text2673 *68 (Text 2266 2674 uid 238,0 2267 2675 va (VaSet … … 2305 2713 fg "49152,49152,49152" 2306 2714 ) 2307 xt "81250, 79250,82750,80750"2715 xt "81250,89250,82750,90750" 2308 2716 iconName "BlockDiagram.png" 2309 2717 iconMaskName "BlockDiagram.msk" … … 2315 2723 archFileType "UNKNOWN" 2316 2724 ) 2317 * 58(SaComponent2725 *69 (SaComponent 2318 2726 uid 274,0 2319 2727 optionalChildren [ 2320 * 59(CptPort2728 *70 (CptPort 2321 2729 uid 266,0 2322 2730 ps "OnEdgeStrategy" … … 2354 2762 ) 2355 2763 ) 2356 * 60(CptPort2764 *71 (CptPort 2357 2765 uid 270,0 2358 2766 ps "OnEdgeStrategy" … … 2407 2815 stg "VerticalLayoutStrategy" 2408 2816 textVec [ 2409 * 61(Text2817 *72 (Text 2410 2818 uid 277,0 2411 2819 va (VaSet … … 2417 2825 tm "BdLibraryNameMgr" 2418 2826 ) 2419 * 62(Text2827 *73 (Text 2420 2828 uid 278,0 2421 2829 va (VaSet … … 2427 2835 tm "CptNameMgr" 2428 2836 ) 2429 * 63(Text2837 *74 (Text 2430 2838 uid 279,0 2431 2839 va (VaSet … … 2486 2894 archFileType "UNKNOWN" 2487 2895 ) 2488 * 64(Net2896 *75 (Net 2489 2897 uid 284,0 2490 2898 decl (Decl … … 2501 2909 font "Courier New,8,0" 2502 2910 ) 2503 xt "-90000,41400,-68000,42200" 2504 st "SIGNAL clk : STD_LOGIC" 2505 ) 2506 ) 2507 *65 (Net 2911 xt "-90000,46200,-68000,47000" 2912 st "SIGNAL clk : STD_LOGIC 2913 " 2914 ) 2915 ) 2916 *76 (Net 2508 2917 uid 316,0 2509 2918 decl (Decl … … 2519 2928 font "Courier New,8,0" 2520 2929 ) 2521 xt "-90000,54200,-58500,55000" 2522 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)" 2523 ) 2524 ) 2525 *66 (Net 2930 xt "-90000,63800,-58500,64600" 2931 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0) 2932 " 2933 ) 2934 ) 2935 *77 (Net 2526 2936 uid 322,0 2527 2937 decl (Decl … … 2537 2947 font "Courier New,8,0" 2538 2948 ) 2539 xt "-90000,55800,-58000,56600" 2540 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)" 2541 ) 2542 ) 2543 *67 (Net 2949 xt "-90000,65400,-58000,66200" 2950 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0) 2951 " 2952 ) 2953 ) 2954 *78 (Net 2544 2955 uid 328,0 2545 2956 decl (Decl … … 2555 2966 font "Courier New,8,0" 2556 2967 ) 2557 xt "-90000,57400,-55000,58200" 2558 st "SIGNAL wiz_rd : std_logic := '1'" 2559 ) 2560 ) 2561 *68 (Net 2968 xt "-90000,67000,-55000,67800" 2969 st "SIGNAL wiz_rd : std_logic := '1' 2970 " 2971 ) 2972 ) 2973 *79 (Net 2562 2974 uid 334,0 2563 2975 decl (Decl … … 2573 2985 font "Courier New,8,0" 2574 2986 ) 2575 xt "-90000,59000,-55000,59800" 2576 st "SIGNAL wiz_wr : std_logic := '1'" 2577 ) 2578 ) 2579 *69 (SaComponent 2987 xt "-90000,68600,-55000,69400" 2988 st "SIGNAL wiz_wr : std_logic := '1' 2989 " 2990 ) 2991 ) 2992 *80 (SaComponent 2580 2993 uid 362,0 2581 2994 optionalChildren [ 2582 * 70(CptPort2995 *81 (CptPort 2583 2996 uid 350,0 2584 2997 ps "OnEdgeStrategy" … … 2616 3029 ) 2617 3030 ) 2618 * 71(CptPort3031 *82 (CptPort 2619 3032 uid 354,0 2620 3033 ps "OnEdgeStrategy" … … 2653 3066 ) 2654 3067 ) 2655 * 72(CptPort3068 *83 (CptPort 2656 3069 uid 358,0 2657 3070 ps "OnEdgeStrategy" … … 2707 3120 stg "VerticalLayoutStrategy" 2708 3121 textVec [ 2709 * 73(Text3122 *84 (Text 2710 3123 uid 365,0 2711 3124 va (VaSet … … 2717 3130 tm "BdLibraryNameMgr" 2718 3131 ) 2719 * 74(Text3132 *85 (Text 2720 3133 uid 366,0 2721 3134 va (VaSet … … 2727 3140 tm "CptNameMgr" 2728 3141 ) 2729 * 75(Text3142 *86 (Text 2730 3143 uid 367,0 2731 3144 va (VaSet … … 2781 3194 archFileType "UNKNOWN" 2782 3195 ) 2783 * 76(Net3196 *87 (Net 2784 3197 uid 372,0 2785 3198 decl (Decl … … 2795 3208 font "Courier New,8,0" 2796 3209 ) 2797 xt "-90000,51800,-58500,52600" 2798 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2799 ) 2800 ) 2801 *77 (Net 3210 xt "-90000,59000,-58500,59800" 3211 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3212 " 3213 ) 3214 ) 3215 *88 (Net 2802 3216 uid 378,0 2803 3217 decl (Decl … … 2812 3226 font "Courier New,8,0" 2813 3227 ) 2814 xt "-90000,51000,-68000,51800" 2815 st "SIGNAL sclk : std_logic" 2816 ) 2817 ) 2818 *78 (Net 3228 xt "-90000,58200,-68000,59000" 3229 st "SIGNAL sclk : std_logic 3230 " 3231 ) 3232 ) 3233 *89 (Net 2819 3234 uid 384,0 2820 3235 decl (Decl … … 2831 3246 font "Courier New,8,0" 2832 3247 ) 2833 xt "-90000,52600,-68000,53400" 2834 st "SIGNAL sio : std_logic" 2835 ) 2836 ) 2837 *79 (SaComponent 3248 xt "-90000,59800,-68000,60600" 3249 st "SIGNAL sio : std_logic 3250 " 3251 ) 3252 ) 3253 *90 (SaComponent 2838 3254 uid 414,0 2839 3255 optionalChildren [ 2840 * 80(CptPort3256 *91 (CptPort 2841 3257 uid 410,0 2842 3258 ps "OnEdgeStrategy" … … 2893 3309 stg "VerticalLayoutStrategy" 2894 3310 textVec [ 2895 * 81(Text3311 *92 (Text 2896 3312 uid 417,0 2897 3313 va (VaSet … … 2903 3319 tm "BdLibraryNameMgr" 2904 3320 ) 2905 * 82(Text3321 *93 (Text 2906 3322 uid 418,0 2907 3323 va (VaSet … … 2913 3329 tm "CptNameMgr" 2914 3330 ) 2915 * 83(Text3331 *94 (Text 2916 3332 uid 419,0 2917 3333 va (VaSet … … 2973 3389 archFileType "UNKNOWN" 2974 3390 ) 2975 * 84(Net3391 *95 (Net 2976 3392 uid 424,0 2977 3393 decl (Decl … … 2988 3404 font "Courier New,8,0" 2989 3405 ) 2990 xt "-90000,53400,-68000,54200" 2991 st "SIGNAL trigger : std_logic" 2992 ) 2993 ) 2994 *85 (HdlText 3406 xt "-90000,61400,-68000,62200" 3407 st "SIGNAL trigger : std_logic 3408 " 3409 ) 3410 ) 3411 *96 (HdlText 2995 3412 uid 430,0 2996 3413 optionalChildren [ 2997 * 86(EmbeddedText3414 *97 (EmbeddedText 2998 3415 uid 436,0 2999 3416 commentText (CommentText … … 3046 3463 stg "VerticalLayoutStrategy" 3047 3464 textVec [ 3048 * 87(Text3465 *98 (Text 3049 3466 uid 433,0 3050 3467 va (VaSet … … 3056 3473 tm "HdlTextNameMgr" 3057 3474 ) 3058 * 88(Text3475 *99 (Text 3059 3476 uid 434,0 3060 3477 va (VaSet … … 3082 3499 viewiconposition 0 3083 3500 ) 3084 * 89(Net3501 *100 (Net 3085 3502 uid 440,0 3086 3503 decl (Decl … … 3098 3515 font "Courier New,8,0" 3099 3516 ) 3100 xt "-90000,40600,-58500,41400" 3101 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 3102 ) 3103 ) 3104 *90 (Net 3517 xt "-90000,45400,-58500,46200" 3518 st "SIGNAL board_id : std_logic_vector(3 downto 0) 3519 " 3520 ) 3521 ) 3522 *101 (Net 3105 3523 uid 448,0 3106 3524 decl (Decl … … 3116 3534 font "Courier New,8,0" 3117 3535 ) 3118 xt "-90000,43000,-58500,43800" 3119 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 3120 ) 3121 ) 3122 *91 (SaComponent 3536 xt "-90000,47800,-58500,48600" 3537 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 3538 " 3539 ) 3540 ) 3541 *102 (SaComponent 3123 3542 uid 508,0 3124 3543 optionalChildren [ 3125 * 92(CptPort3544 *103 (CptPort 3126 3545 uid 489,0 3127 3546 ps "OnEdgeStrategy" … … 3159 3578 ) 3160 3579 ) 3161 * 93(CptPort3580 *104 (CptPort 3162 3581 uid 493,0 3163 3582 ps "OnEdgeStrategy" … … 3198 3617 ) 3199 3618 ) 3200 * 94(CptPort3619 *105 (CptPort 3201 3620 uid 497,0 3202 3621 ps "OnEdgeStrategy" … … 3236 3655 ) 3237 3656 ) 3238 * 95(CptPort3657 *106 (CptPort 3239 3658 uid 501,0 3240 3659 ps "OnEdgeStrategy" … … 3290 3709 stg "VerticalLayoutStrategy" 3291 3710 textVec [ 3292 * 96(Text3711 *107 (Text 3293 3712 uid 511,0 3294 3713 va (VaSet … … 3300 3719 tm "BdLibraryNameMgr" 3301 3720 ) 3302 * 97(Text3721 *108 (Text 3303 3722 uid 512,0 3304 3723 va (VaSet … … 3310 3729 tm "CptNameMgr" 3311 3730 ) 3312 * 98(Text3731 *109 (Text 3313 3732 uid 513,0 3314 3733 va (VaSet … … 3364 3783 archFileType "UNKNOWN" 3365 3784 ) 3366 * 99(HdlText3785 *110 (HdlText 3367 3786 uid 518,0 3368 3787 optionalChildren [ 3369 *1 00(EmbeddedText3788 *111 (EmbeddedText 3370 3789 uid 524,0 3371 3790 commentText (CommentText … … 3424 3843 stg "VerticalLayoutStrategy" 3425 3844 textVec [ 3426 *1 01(Text3845 *112 (Text 3427 3846 uid 521,0 3428 3847 va (VaSet … … 3434 3853 tm "HdlTextNameMgr" 3435 3854 ) 3436 *1 02(Text3855 *113 (Text 3437 3856 uid 522,0 3438 3857 va (VaSet … … 3460 3879 viewiconposition 0 3461 3880 ) 3462 *1 03(Net3881 *114 (Net 3463 3882 uid 528,0 3464 3883 decl (Decl … … 3474 3893 font "Courier New,8,0" 3475 3894 ) 3476 xt "-90000,37400,-58500,38200" 3477 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" 3478 ) 3479 ) 3480 *104 (Net 3895 xt "-90000,42200,-58500,43000" 3896 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0) 3897 " 3898 ) 3899 ) 3900 *115 (Net 3481 3901 uid 536,0 3482 3902 decl (Decl … … 3491 3911 font "Courier New,8,0" 3492 3912 ) 3493 xt "-90000,35000,-63000,35800" 3494 st "SIGNAL adc_data_array : adc_data_array_type" 3495 ) 3496 ) 3497 *105 (Net 3913 xt "-90000,39800,-63000,40600" 3914 st "SIGNAL adc_data_array : adc_data_array_type 3915 " 3916 ) 3917 ) 3918 *116 (Net 3498 3919 uid 544,0 3499 3920 decl (Decl … … 3510 3931 font "Courier New,8,0" 3511 3932 ) 3512 xt "-90000,35800,-68000,36600" 3513 st "SIGNAL adc_oeb : std_logic" 3514 ) 3515 ) 3516 *106 (Net 3933 xt "-90000,40600,-68000,41400" 3934 st "SIGNAL adc_oeb : std_logic 3935 " 3936 ) 3937 ) 3938 *117 (Net 3517 3939 uid 560,0 3518 3940 decl (Decl … … 3529 3951 font "Courier New,8,0" 3530 3952 ) 3531 xt "-90000,36600,-68000,37400" 3532 st "SIGNAL adc_otr : STD_LOGIC" 3533 ) 3534 ) 3535 *107 (Net 3953 xt "-90000,41400,-68000,42200" 3954 st "SIGNAL adc_otr : STD_LOGIC 3955 " 3956 ) 3957 ) 3958 *118 (Net 3536 3959 uid 568,0 3537 3960 decl (Decl … … 3549 3972 font "Courier New,8,0" 3550 3973 ) 3551 xt "-90000,34200,-58000,35000" 3552 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" 3553 ) 3554 ) 3555 *108 (Net 3974 xt "-90000,39000,-58000,39800" 3975 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0) 3976 " 3977 ) 3978 ) 3979 *119 (Net 3556 3980 uid 767,0 3557 3981 decl (Decl … … 3567 3991 font "Courier New,8,0" 3568 3992 ) 3569 xt "-90000,58200,-55000,59000" 3570 st "SIGNAL wiz_reset : std_logic := '1'" 3571 ) 3572 ) 3573 *109 (Net 3993 xt "-90000,67800,-55000,68600" 3994 st "SIGNAL wiz_reset : std_logic := '1' 3995 " 3996 ) 3997 ) 3998 *120 (Net 3574 3999 uid 775,0 3575 4000 decl (Decl … … 3587 4012 font "Courier New,8,0" 3588 4013 ) 3589 xt "-90000,47800,-49000,48600" 3590 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 3591 ) 3592 ) 3593 *110 (Net 4014 xt "-90000,54200,-49000,55000" 4015 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 4016 " 4017 ) 4018 ) 4019 *121 (Net 3594 4020 uid 783,0 3595 4021 decl (Decl … … 3605 4031 font "Courier New,8,0" 3606 4032 ) 3607 xt "-90000,55000,-55000,55800" 3608 st "SIGNAL wiz_cs : std_logic := '1'" 3609 ) 3610 ) 3611 *111 (Net 4033 xt "-90000,64600,-55000,65400" 4034 st "SIGNAL wiz_cs : std_logic := '1' 4035 " 4036 ) 4037 ) 4038 *122 (Net 3612 4039 uid 791,0 3613 4040 decl (Decl … … 3622 4049 font "Courier New,8,0" 3623 4050 ) 3624 xt "-90000,56600,-68000,57400" 3625 st "SIGNAL wiz_int : std_logic" 3626 ) 3627 ) 3628 *112 (Net 4051 xt "-90000,66200,-68000,67000" 4052 st "SIGNAL wiz_int : std_logic 4053 " 4054 ) 4055 ) 4056 *123 (Net 3629 4057 uid 799,0 3630 4058 decl (Decl … … 3639 4067 font "Courier New,8,0" 3640 4068 ) 3641 xt "-90000,43800,-68000,44600" 3642 st "SIGNAL dac_cs : std_logic" 3643 ) 3644 ) 3645 *113 (Net 4069 xt "-90000,48600,-68000,49400" 4070 st "SIGNAL dac_cs : std_logic 4071 " 4072 ) 4073 ) 4074 *124 (Net 3646 4075 uid 807,0 3647 4076 decl (Decl … … 3657 4086 font "Courier New,8,0" 3658 4087 ) 3659 xt "-90000,48600,-55000,49400" 3660 st "SIGNAL mosi : std_logic := '0'" 3661 ) 3662 ) 3663 *114 (Net 4088 xt "-90000,55800,-55000,56600" 4089 st "SIGNAL mosi : std_logic := '0' 4090 " 4091 ) 4092 ) 4093 *125 (Net 3664 4094 uid 815,0 3665 4095 decl (Decl … … 3677 4107 font "Courier New,8,0" 3678 4108 ) 3679 xt "-90000,44600,-41500,45400" 3680 st "SIGNAL denable : std_logic := '0' -- default domino wave off" 3681 ) 3682 ) 3683 *115 (Net 4109 xt "-90000,51000,-41500,51800" 4110 st "SIGNAL denable : std_logic := '0' -- default domino wave off 4111 " 4112 ) 4113 ) 4114 *126 (Net 3684 4115 uid 823,0 3685 4116 decl (Decl … … 3695 4126 ) 3696 4127 xt "-90000,25400,-68000,26200" 3697 st "SIGNAL CLK_25_PS : std_logic" 3698 ) 3699 ) 3700 *116 (Net 4128 st "SIGNAL CLK_25_PS : std_logic 4129 " 4130 ) 4131 ) 4132 *127 (Net 3701 4133 uid 831,0 3702 4134 decl (Decl … … 3712 4144 ) 3713 4145 xt "-90000,26200,-68000,27000" 3714 st "SIGNAL CLK_50 : std_logic" 3715 ) 3716 ) 3717 *117 (Net 4146 st "SIGNAL CLK_50 : std_logic 4147 " 4148 ) 4149 ) 4150 *128 (Net 3718 4151 uid 839,0 3719 4152 decl (Decl … … 3730 4163 font "Courier New,8,0" 3731 4164 ) 3732 xt "-90000,45400,-49000,46200" 3733 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 3734 ) 3735 ) 3736 *118 (Net 4165 xt "-90000,51800,-49000,52600" 4166 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 4167 " 4168 ) 4169 ) 4170 *129 (Net 3737 4171 uid 847,0 3738 4172 decl (Decl … … 3748 4182 font "Courier New,8,0" 3749 4183 ) 3750 xt "-90000,46200,-55000,47000" 3751 st "SIGNAL drs_dwrite : std_logic := '1'" 3752 ) 3753 ) 3754 *119 (Net 4184 xt "-90000,52600,-55000,53400" 4185 st "SIGNAL drs_dwrite : std_logic := '1' 4186 " 4187 ) 4188 ) 4189 *130 (Net 3755 4190 uid 855,0 3756 4191 decl (Decl … … 3766 4201 font "Courier New,8,0" 3767 4202 ) 3768 xt "-90000,28600,-55000,29400" 3769 st "SIGNAL RSRLOAD : std_logic := '0'" 3770 ) 3771 ) 3772 *120 (Net 4203 xt "-90000,33400,-55000,34200" 4204 st "SIGNAL RSRLOAD : std_logic := '0' 4205 " 4206 ) 4207 ) 4208 *131 (Net 3773 4209 uid 863,0 3774 4210 decl (Decl … … 3784 4220 font "Courier New,8,0" 3785 4221 ) 3786 xt "-90000,29400,-55000,30200" 3787 st "SIGNAL SRCLK : std_logic := '0'" 3788 ) 3789 ) 3790 *121 (Net 4222 xt "-90000,34200,-55000,35000" 4223 st "SIGNAL SRCLK : std_logic := '0' 4224 " 4225 ) 4226 ) 4227 *132 (Net 3791 4228 uid 871,0 3792 4229 decl (Decl … … 3801 4238 font "Courier New,8,0" 3802 4239 ) 3803 xt "-90000,31000,-68000,31800" 3804 st "SIGNAL SROUT_in_0 : std_logic" 3805 ) 3806 ) 3807 *122 (Net 4240 xt "-90000,35800,-68000,36600" 4241 st "SIGNAL SROUT_in_0 : std_logic 4242 " 4243 ) 4244 ) 4245 *133 (Net 3808 4246 uid 879,0 3809 4247 decl (Decl … … 3818 4256 font "Courier New,8,0" 3819 4257 ) 3820 xt "-90000,31800,-68000,32600" 3821 st "SIGNAL SROUT_in_1 : std_logic" 3822 ) 3823 ) 3824 *123 (Net 4258 xt "-90000,36600,-68000,37400" 4259 st "SIGNAL SROUT_in_1 : std_logic 4260 " 4261 ) 4262 ) 4263 *134 (Net 3825 4264 uid 887,0 3826 4265 decl (Decl … … 3835 4274 font "Courier New,8,0" 3836 4275 ) 3837 xt "-90000,32600,-68000,33400" 3838 st "SIGNAL SROUT_in_2 : std_logic" 3839 ) 3840 ) 3841 *124 (Net 4276 xt "-90000,37400,-68000,38200" 4277 st "SIGNAL SROUT_in_2 : std_logic 4278 " 4279 ) 4280 ) 4281 *135 (Net 3842 4282 uid 895,0 3843 4283 decl (Decl … … 3852 4292 font "Courier New,8,0" 3853 4293 ) 3854 xt "-90000,33400,-68000,34200" 3855 st "SIGNAL SROUT_in_3 : std_logic" 3856 ) 3857 ) 3858 *125 (Net 4294 xt "-90000,38200,-68000,39000" 4295 st "SIGNAL SROUT_in_3 : std_logic 4296 " 4297 ) 4298 ) 4299 *136 (Net 3859 4300 uid 1435,0 3860 4301 decl (Decl … … 3870 4311 font "Courier New,8,0" 3871 4312 ) 3872 xt "-90000,30200,-55000,31000" 3873 st "SIGNAL SRIN_out : std_logic := '0'" 3874 ) 3875 ) 3876 *126 (Net 4313 xt "-90000,35000,-55000,35800" 4314 st "SIGNAL SRIN_out : std_logic := '0' 4315 " 4316 ) 4317 ) 4318 *137 (Net 3877 4319 uid 1443,0 3878 4320 decl (Decl … … 3887 4329 font "Courier New,8,0" 3888 4330 ) 3889 xt "-90000,39800,-68000,40600" 3890 st "SIGNAL amber : std_logic" 3891 ) 3892 ) 3893 *127 (Net 4331 xt "-90000,44600,-68000,45400" 4332 st "SIGNAL amber : std_logic 4333 " 4334 ) 4335 ) 4336 *138 (Net 3894 4337 uid 1451,0 3895 4338 decl (Decl … … 3904 4347 font "Courier New,8,0" 3905 4348 ) 3906 xt "-90000,50200,-68000,51000" 3907 st "SIGNAL red : std_logic" 3908 ) 3909 ) 3910 *128 (Net 4349 xt "-90000,57400,-68000,58200" 4350 st "SIGNAL red : std_logic 4351 " 4352 ) 4353 ) 4354 *139 (Net 3911 4355 uid 1459,0 3912 4356 decl (Decl … … 3921 4365 font "Courier New,8,0" 3922 4366 ) 3923 xt "-90000,47000,-68000,47800" 3924 st "SIGNAL green : std_logic" 3925 ) 3926 ) 3927 *129 (Net 4367 xt "-90000,53400,-68000,54200" 4368 st "SIGNAL green : std_logic 4369 " 4370 ) 4371 ) 4372 *140 (Net 3928 4373 uid 1467,0 3929 4374 decl (Decl … … 3939 4384 font "Courier New,8,0" 3940 4385 ) 3941 xt "-90000,42200,-58000,43000" 3942 st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0)" 3943 ) 3944 ) 3945 *130 (Net 4386 xt "-90000,47000,-58000,47800" 4387 st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) 4388 " 4389 ) 4390 ) 4391 *141 (Net 3946 4392 uid 1475,0 3947 4393 decl (Decl … … 3957 4403 font "Courier New,8,0" 3958 4404 ) 3959 xt "-90000,39000,-68000,39800" 3960 st "SIGNAL alarm_refclk_too_low : std_logic" 3961 ) 3962 ) 3963 *131 (Net 4405 xt "-90000,43800,-68000,44600" 4406 st "SIGNAL alarm_refclk_too_low : std_logic 4407 " 4408 ) 4409 ) 4410 *142 (Net 3964 4411 uid 1483,0 3965 4412 decl (Decl … … 3974 4421 font "Courier New,8,0" 3975 4422 ) 3976 xt "-90000,38200,-68000,39000" 3977 st "SIGNAL alarm_refclk_too_high : std_logic" 3978 ) 3979 ) 3980 *132 (HdlText 4423 xt "-90000,43000,-68000,43800" 4424 st "SIGNAL alarm_refclk_too_high : std_logic 4425 " 4426 ) 4427 ) 4428 *143 (HdlText 3981 4429 uid 1491,0 3982 4430 optionalChildren [ 3983 *1 33(EmbeddedText4431 *144 (EmbeddedText 3984 4432 uid 1497,0 3985 4433 commentText (CommentText … … 4036 4484 stg "VerticalLayoutStrategy" 4037 4485 textVec [ 4038 *1 34(Text4486 *145 (Text 4039 4487 uid 1494,0 4040 4488 va (VaSet … … 4046 4494 tm "HdlTextNameMgr" 4047 4495 ) 4048 *1 35(Text4496 *146 (Text 4049 4497 uid 1495,0 4050 4498 va (VaSet … … 4072 4520 viewiconposition 0 4073 4521 ) 4074 *1 36(Net4522 *147 (Net 4075 4523 uid 1501,0 4076 4524 decl (Decl … … 4086 4534 font "Courier New,8,0" 4087 4535 ) 4088 xt "-90000,27000,-58500,27800" 4089 st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0)" 4090 ) 4091 ) 4092 *137 (SaComponent 4536 xt "-90000,28600,-58500,29400" 4537 st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0) 4538 " 4539 ) 4540 ) 4541 *148 (SaComponent 4093 4542 uid 1509,0 4094 4543 optionalChildren [ 4095 *1 38(CptPort4544 *149 (CptPort 4096 4545 uid 1519,0 4097 4546 ps "OnEdgeStrategy" … … 4129 4578 ) 4130 4579 ) 4131 *1 39(CptPort4580 *150 (CptPort 4132 4581 uid 1523,0 4133 4582 ps "OnEdgeStrategy" … … 4182 4631 stg "VerticalLayoutStrategy" 4183 4632 textVec [ 4184 *1 40(Text4633 *151 (Text 4185 4634 uid 1512,0 4186 4635 va (VaSet … … 4192 4641 tm "BdLibraryNameMgr" 4193 4642 ) 4194 *1 41(Text4643 *152 (Text 4195 4644 uid 1513,0 4196 4645 va (VaSet … … 4202 4651 tm "CptNameMgr" 4203 4652 ) 4204 *1 42(Text4653 *153 (Text 4205 4654 uid 1514,0 4206 4655 va (VaSet … … 4261 4710 archFileType "UNKNOWN" 4262 4711 ) 4263 *1 43(Net4712 *154 (Net 4264 4713 uid 1559,0 4265 4714 decl (Decl … … 4276 4725 font "Courier New,8,0" 4277 4726 ) 4278 xt "-90000,49400,-29000,50200" 4279 st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" 4280 ) 4281 ) 4282 *144 (Net 4727 xt "-90000,56600,-29000,57400" 4728 st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked 4729 " 4730 ) 4731 ) 4732 *155 (Net 4283 4733 uid 1682,0 4284 4734 lang 2 … … 4295 4745 ) 4296 4746 xt "-90000,24600,-68000,25400" 4297 st "SIGNAL ADC_CLK : std_logic" 4298 ) 4299 ) 4300 *145 (Net 4747 st "SIGNAL ADC_CLK : std_logic 4748 " 4749 ) 4750 ) 4751 *156 (Net 4301 4752 uid 2001,0 4302 4753 decl (Decl … … 4312 4763 font "Courier New,8,0" 4313 4764 ) 4314 xt "-90000,27800,-55000,28600" 4315 st "SIGNAL REF_CLK : STD_LOGIC := '0'" 4316 ) 4317 ) 4318 *146 (SaComponent 4765 xt "-90000,32600,-55000,33400" 4766 st "SIGNAL REF_CLK : STD_LOGIC := '0' 4767 " 4768 ) 4769 ) 4770 *157 (SaComponent 4319 4771 uid 2336,0 4320 4772 optionalChildren [ 4321 *1 47(CptPort4773 *158 (CptPort 4322 4774 uid 2315,0 4323 4775 ps "OnEdgeStrategy" … … 4356 4808 ) 4357 4809 ) 4358 *1 48(CptPort4810 *159 (CptPort 4359 4811 uid 2319,0 4360 4812 ps "OnEdgeStrategy" … … 4394 4846 ) 4395 4847 ) 4396 *1 49(CptPort4848 *160 (CptPort 4397 4849 uid 2323,0 4398 4850 ps "OnEdgeStrategy" … … 4430 4882 ) 4431 4883 ) 4432 *1 50(CptPort4884 *161 (CptPort 4433 4885 uid 2327,0 4434 4886 ps "OnEdgeStrategy" … … 4466 4918 ) 4467 4919 ) 4468 *1 51(CptPort4920 *162 (CptPort 4469 4921 uid 2331,0 4470 4922 ps "OnEdgeStrategy" … … 4502 4954 ) 4503 4955 ) 4504 *1 52(CptPort4956 *163 (CptPort 4505 4957 uid 2548,0 4506 4958 ps "OnEdgeStrategy" … … 4553 5005 stg "VerticalLayoutStrategy" 4554 5006 textVec [ 4555 *1 53(Text5007 *164 (Text 4556 5008 uid 2339,0 4557 5009 va (VaSet … … 4563 5015 tm "BdLibraryNameMgr" 4564 5016 ) 4565 *1 54(Text5017 *165 (Text 4566 5018 uid 2340,0 4567 5019 va (VaSet … … 4573 5025 tm "CptNameMgr" 4574 5026 ) 4575 *1 55(Text5027 *166 (Text 4576 5028 uid 2341,0 4577 5029 va (VaSet … … 4620 5072 archFileType "UNKNOWN" 4621 5073 ) 4622 *156 (Wire 5074 *167 (Net 5075 uid 2705,0 5076 decl (Decl 5077 n "debug_data_ram_empty" 5078 t "std_logic" 5079 o 45 5080 suid 53,0 5081 ) 5082 declText (MLText 5083 uid 2706,0 5084 va (VaSet 5085 font "Courier New,8,0" 5086 ) 5087 xt "-90000,49400,-68000,50200" 5088 st "SIGNAL debug_data_ram_empty : std_logic 5089 " 5090 ) 5091 ) 5092 *168 (Net 5093 uid 2713,0 5094 decl (Decl 5095 n "debug_data_valid" 5096 t "std_logic" 5097 o 46 5098 suid 54,0 5099 ) 5100 declText (MLText 5101 uid 2714,0 5102 va (VaSet 5103 font "Courier New,8,0" 5104 ) 5105 xt "-90000,50200,-68000,51000" 5106 st "SIGNAL debug_data_valid : std_logic 5107 " 5108 ) 5109 ) 5110 *169 (Net 5111 uid 2721,0 5112 decl (Decl 5113 n "DG_state" 5114 t "std_logic_vector" 5115 b "(7 downto 0)" 5116 prec "-- for debugging" 5117 preAdd 0 5118 o 47 5119 suid 55,0 5120 ) 5121 declText (MLText 5122 uid 2722,0 5123 va (VaSet 5124 font "Courier New,8,0" 5125 ) 5126 xt "-90000,27000,-58500,28600" 5127 st "-- for debugging 5128 SIGNAL DG_state : std_logic_vector(7 downto 0) 5129 " 5130 ) 5131 ) 5132 *170 (Net 5133 uid 2729,0 5134 decl (Decl 5135 n "FTM_RS485_rx_en" 5136 t "std_logic" 5137 o 48 5138 suid 56,0 5139 ) 5140 declText (MLText 5141 uid 2730,0 5142 va (VaSet 5143 font "Courier New,8,0" 5144 ) 5145 xt "-90000,30200,-68000,31000" 5146 st "SIGNAL FTM_RS485_rx_en : std_logic 5147 " 5148 ) 5149 ) 5150 *171 (Net 5151 uid 2737,0 5152 decl (Decl 5153 n "FTM_RS485_tx_d" 5154 t "std_logic" 5155 o 49 5156 suid 57,0 5157 ) 5158 declText (MLText 5159 uid 2738,0 5160 va (VaSet 5161 font "Courier New,8,0" 5162 ) 5163 xt "-90000,31000,-68000,31800" 5164 st "SIGNAL FTM_RS485_tx_d : std_logic 5165 " 5166 ) 5167 ) 5168 *172 (Net 5169 uid 2745,0 5170 decl (Decl 5171 n "FTM_RS485_tx_en" 5172 t "std_logic" 5173 o 50 5174 suid 58,0 5175 ) 5176 declText (MLText 5177 uid 2746,0 5178 va (VaSet 5179 font "Courier New,8,0" 5180 ) 5181 xt "-90000,31800,-68000,32600" 5182 st "SIGNAL FTM_RS485_tx_en : std_logic 5183 " 5184 ) 5185 ) 5186 *173 (Net 5187 uid 2753,0 5188 lang 2 5189 decl (Decl 5190 n "mem_manager_state" 5191 t "std_logic_vector" 5192 b "(3 DOWNTO 0)" 5193 eolc "-- state is encoded here ... useful for debugging." 5194 posAdd 0 5195 o 51 5196 suid 59,0 5197 ) 5198 declText (MLText 5199 uid 2754,0 5200 va (VaSet 5201 font "Courier New,8,0" 5202 ) 5203 xt "-90000,55000,-33000,55800" 5204 st "SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging. 5205 " 5206 ) 5207 ) 5208 *174 (Net 5209 uid 2761,0 5210 decl (Decl 5211 n "trigger_veto" 5212 t "std_logic" 5213 o 52 5214 suid 60,0 5215 i "'1'" 5216 ) 5217 declText (MLText 5218 uid 2762,0 5219 va (VaSet 5220 font "Courier New,8,0" 5221 ) 5222 xt "-90000,62200,-55000,63000" 5223 st "SIGNAL trigger_veto : std_logic := '1' 5224 " 5225 ) 5226 ) 5227 *175 (Net 5228 uid 2769,0 5229 decl (Decl 5230 n "w5300_state" 5231 t "std_logic_vector" 5232 b "(7 DOWNTO 0)" 5233 eolc "-- state is encoded here ... useful for debugging." 5234 posAdd 0 5235 o 53 5236 suid 61,0 5237 ) 5238 declText (MLText 5239 uid 2770,0 5240 va (VaSet 5241 font "Courier New,8,0" 5242 ) 5243 xt "-90000,63000,-33000,63800" 5244 st "SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging. 5245 " 5246 ) 5247 ) 5248 *176 (Net 5249 uid 2777,0 5250 decl (Decl 5251 n "FTM_RS485_rx_d" 5252 t "std_logic" 5253 o 54 5254 suid 62,0 5255 ) 5256 declText (MLText 5257 uid 2778,0 5258 va (VaSet 5259 font "Courier New,8,0" 5260 ) 5261 xt "-90000,29400,-68000,30200" 5262 st "SIGNAL FTM_RS485_rx_d : std_logic 5263 " 5264 ) 5265 ) 5266 *177 (Net 5267 uid 2942,0 5268 decl (Decl 5269 n "socket_tx_free_out" 5270 t "std_logic_vector" 5271 b "(16 DOWNTO 0)" 5272 eolc "-- 17bit value .. that's true" 5273 posAdd 0 5274 o 55 5275 suid 64,0 5276 ) 5277 declText (MLText 5278 uid 2943,0 5279 va (VaSet 5280 font "Courier New,8,0" 5281 ) 5282 xt "-90000,60600,-43000,61400" 5283 st "SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true 5284 " 5285 ) 5286 ) 5287 *178 (Wire 4623 5288 uid 286,0 4624 5289 shape (OrthoPolyLine … … 4633 5298 ] 4634 5299 ) 4635 start & 595300 start &70 4636 5301 end &27 4637 5302 sat 32 … … 4654 5319 ) 4655 5320 ) 4656 on & 644657 ) 4658 *1 57(Wire5321 on &75 5322 ) 5323 *179 (Wire 4659 5324 uid 318,0 4660 5325 shape (OrthoPolyLine … … 4671 5336 ) 4672 5337 start &19 4673 end &1 475338 end &158 4674 5339 sat 32 4675 5340 eat 32 … … 4692 5357 ) 4693 5358 ) 4694 on & 654695 ) 4696 *1 58(Wire5359 on &76 5360 ) 5361 *180 (Wire 4697 5362 uid 324,0 4698 5363 shape (OrthoPolyLine … … 4709 5374 ) 4710 5375 start &20 4711 end &1 485376 end &159 4712 5377 sat 32 4713 5378 eat 32 … … 4730 5395 ) 4731 5396 ) 4732 on & 664733 ) 4734 *1 59(Wire5397 on &77 5398 ) 5399 *181 (Wire 4735 5400 uid 330,0 4736 5401 shape (OrthoPolyLine … … 4746 5411 ) 4747 5412 start &23 4748 end &1 495413 end &160 4749 5414 sat 32 4750 5415 eat 32 … … 4766 5431 ) 4767 5432 ) 4768 on & 674769 ) 4770 *1 60(Wire5433 on &78 5434 ) 5435 *182 (Wire 4771 5436 uid 336,0 4772 5437 shape (OrthoPolyLine … … 4782 5447 ) 4783 5448 start &22 4784 end &1 505449 end &161 4785 5450 sat 32 4786 5451 eat 32 … … 4802 5467 ) 4803 5468 ) 4804 on & 684805 ) 4806 *1 61(Wire5469 on &79 5470 ) 5471 *183 (Wire 4807 5472 uid 374,0 4808 5473 shape (OrthoPolyLine … … 4821 5486 ) 4822 5487 start &41 4823 end & 725488 end &83 4824 5489 sat 32 4825 5490 eat 32 … … 4842 5507 ) 4843 5508 ) 4844 on & 764845 ) 4846 *1 62(Wire5509 on &87 5510 ) 5511 *184 (Wire 4847 5512 uid 380,0 4848 5513 shape (OrthoPolyLine … … 4858 5523 ) 4859 5524 start &38 4860 end & 705525 end &81 4861 5526 sat 32 4862 5527 eat 32 … … 4878 5543 ) 4879 5544 ) 4880 on & 774881 ) 4882 *1 63(Wire5545 on &88 5546 ) 5547 *185 (Wire 4883 5548 uid 386,0 4884 5549 shape (OrthoPolyLine … … 4894 5559 ) 4895 5560 start &39 4896 end & 715561 end &82 4897 5562 sat 32 4898 5563 eat 32 … … 4914 5579 ) 4915 5580 ) 4916 on & 784917 ) 4918 *1 64(Wire5581 on &89 5582 ) 5583 *186 (Wire 4919 5584 uid 426,0 4920 5585 shape (OrthoPolyLine … … 4929 5594 ] 4930 5595 ) 4931 start & 805596 start &91 4932 5597 end &15 4933 5598 sat 32 … … 4949 5614 ) 4950 5615 ) 4951 on & 844952 ) 4953 *1 65(Wire5616 on &95 5617 ) 5618 *187 (Wire 4954 5619 uid 442,0 4955 5620 shape (OrthoPolyLine … … 4968 5633 ) 4969 5634 start &17 4970 end & 855635 end &96 4971 5636 sat 32 4972 5637 eat 2 … … 4989 5654 ) 4990 5655 ) 4991 on & 894992 ) 4993 *1 66(Wire5656 on &100 5657 ) 5658 *188 (Wire 4994 5659 uid 450,0 4995 5660 shape (OrthoPolyLine … … 5008 5673 ) 5009 5674 start &18 5010 end & 855675 end &96 5011 5676 sat 32 5012 5677 eat 2 … … 5029 5694 ) 5030 5695 ) 5031 on & 905032 ) 5033 *1 67(Wire5696 on &101 5697 ) 5698 *189 (Wire 5034 5699 uid 530,0 5035 5700 shape (OrthoPolyLine … … 5048 5713 ) 5049 5714 start &28 5050 end & 995715 end &110 5051 5716 sat 32 5052 5717 eat 2 … … 5069 5734 ) 5070 5735 ) 5071 on &1 035072 ) 5073 *1 68(Wire5736 on &114 5737 ) 5738 *190 (Wire 5074 5739 uid 538,0 5075 5740 shape (OrthoPolyLine … … 5088 5753 ) 5089 5754 start &29 5090 end & 995755 end &110 5091 5756 sat 32 5092 5757 eat 2 … … 5109 5774 ) 5110 5775 ) 5111 on &1 045112 ) 5113 *1 69(Wire5776 on &115 5777 ) 5778 *191 (Wire 5114 5779 uid 546,0 5115 5780 shape (OrthoPolyLine … … 5127 5792 ) 5128 5793 start &16 5129 end & 995794 end &110 5130 5795 sat 32 5131 5796 eat 1 … … 5147 5812 ) 5148 5813 ) 5149 on &1 055150 ) 5151 *1 70(Wire5814 on &116 5815 ) 5816 *192 (Wire 5152 5817 uid 554,0 5153 5818 shape (OrthoPolyLine … … 5162 5827 ] 5163 5828 ) 5164 start & 995165 end & 955829 start &110 5830 end &106 5166 5831 sat 2 5167 5832 eat 32 … … 5182 5847 ) 5183 5848 ) 5184 on &1 055185 ) 5186 *1 71(Wire5849 on &116 5850 ) 5851 *193 (Wire 5187 5852 uid 562,0 5188 5853 shape (OrthoPolyLine … … 5197 5862 ] 5198 5863 ) 5199 start & 945200 end & 995864 start &105 5865 end &110 5201 5866 sat 32 5202 5867 eat 1 … … 5217 5882 ) 5218 5883 ) 5219 on &1 065220 ) 5221 *1 72(Wire5884 on &117 5885 ) 5886 *194 (Wire 5222 5887 uid 570,0 5223 5888 shape (OrthoPolyLine … … 5233 5898 ] 5234 5899 ) 5235 start & 935236 end & 995900 start &104 5901 end &110 5237 5902 sat 32 5238 5903 eat 1 … … 5254 5919 ) 5255 5920 ) 5256 on &1 075257 ) 5258 *1 73(Wire5921 on &118 5922 ) 5923 *195 (Wire 5259 5924 uid 578,0 5260 5925 shape (OrthoPolyLine … … 5269 5934 ] 5270 5935 ) 5271 start & 925936 start &103 5272 5937 sat 32 5273 5938 eat 16 … … 5288 5953 ) 5289 5954 ) 5290 on &1 445291 ) 5292 *1 74(Wire5955 on &155 5956 ) 5957 *196 (Wire 5293 5958 uid 769,0 5294 5959 shape (OrthoPolyLine … … 5323 5988 ) 5324 5989 ) 5325 on &1 085326 ) 5327 *1 75(Wire5990 on &119 5991 ) 5992 *197 (Wire 5328 5993 uid 777,0 5329 5994 shape (OrthoPolyLine … … 5360 6025 ) 5361 6026 ) 5362 on &1 095363 ) 5364 *1 76(Wire6027 on &120 6028 ) 6029 *198 (Wire 5365 6030 uid 785,0 5366 6031 shape (OrthoPolyLine … … 5376 6041 ) 5377 6042 start &21 5378 end &1 526043 end &163 5379 6044 sat 32 5380 6045 eat 32 … … 5396 6061 ) 5397 6062 ) 5398 on &1 105399 ) 5400 *1 77(Wire6063 on &121 6064 ) 6065 *199 (Wire 5401 6066 uid 793,0 5402 6067 shape (OrthoPolyLine … … 5411 6076 ] 5412 6077 ) 5413 start &1 516078 start &162 5414 6079 end &24 5415 6080 sat 32 … … 5432 6097 ) 5433 6098 ) 5434 on &1 115435 ) 5436 * 178(Wire6099 on &122 6100 ) 6101 *200 (Wire 5437 6102 uid 801,0 5438 6103 shape (OrthoPolyLine … … 5467 6132 ) 5468 6133 ) 5469 on &1 125470 ) 5471 * 179(Wire6134 on &123 6135 ) 6136 *201 (Wire 5472 6137 uid 809,0 5473 6138 shape (OrthoPolyLine … … 5502 6167 ) 5503 6168 ) 5504 on &1 135505 ) 5506 * 180(Wire6169 on &124 6170 ) 6171 *202 (Wire 5507 6172 uid 817,0 5508 6173 shape (OrthoPolyLine … … 5537 6202 ) 5538 6203 ) 5539 on &1 145540 ) 5541 * 181(Wire6204 on &125 6205 ) 6206 *203 (Wire 5542 6207 uid 825,0 5543 6208 shape (OrthoPolyLine … … 5572 6237 ) 5573 6238 ) 5574 on &1 155575 ) 5576 * 182(Wire6239 on &126 6240 ) 6241 *204 (Wire 5577 6242 uid 833,0 5578 6243 shape (OrthoPolyLine … … 5607 6272 ) 5608 6273 ) 5609 on &1 165610 ) 5611 * 183(Wire6274 on &127 6275 ) 6276 *205 (Wire 5612 6277 uid 841,0 5613 6278 shape (OrthoPolyLine … … 5644 6309 ) 5645 6310 ) 5646 on &1 175647 ) 5648 * 184(Wire6311 on &128 6312 ) 6313 *206 (Wire 5649 6314 uid 849,0 5650 6315 shape (OrthoPolyLine … … 5680 6345 ) 5681 6346 ) 5682 on &1 185683 ) 5684 * 185(Wire6347 on &129 6348 ) 6349 *207 (Wire 5685 6350 uid 857,0 5686 6351 shape (OrthoPolyLine … … 5715 6380 ) 5716 6381 ) 5717 on &1 195718 ) 5719 * 186(Wire6382 on &130 6383 ) 6384 *208 (Wire 5720 6385 uid 865,0 5721 6386 shape (OrthoPolyLine … … 5750 6415 ) 5751 6416 ) 5752 on &1 205753 ) 5754 * 187(Wire6417 on &131 6418 ) 6419 *209 (Wire 5755 6420 uid 873,0 5756 6421 shape (OrthoPolyLine … … 5785 6450 ) 5786 6451 ) 5787 on &1 215788 ) 5789 * 188(Wire6452 on &132 6453 ) 6454 *210 (Wire 5790 6455 uid 881,0 5791 6456 shape (OrthoPolyLine … … 5820 6485 ) 5821 6486 ) 5822 on &1 225823 ) 5824 * 189(Wire6487 on &133 6488 ) 6489 *211 (Wire 5825 6490 uid 889,0 5826 6491 shape (OrthoPolyLine … … 5855 6520 ) 5856 6521 ) 5857 on &1 235858 ) 5859 * 190(Wire6522 on &134 6523 ) 6524 *212 (Wire 5860 6525 uid 897,0 5861 6526 shape (OrthoPolyLine … … 5890 6555 ) 5891 6556 ) 5892 on &1 245893 ) 5894 * 191(Wire6557 on &135 6558 ) 6559 *213 (Wire 5895 6560 uid 1437,0 5896 6561 shape (OrthoPolyLine … … 5925 6590 ) 5926 6591 ) 5927 on &1 255928 ) 5929 * 192(Wire6592 on &136 6593 ) 6594 *214 (Wire 5930 6595 uid 1445,0 5931 6596 shape (OrthoPolyLine … … 5960 6625 ) 5961 6626 ) 5962 on &1 265963 ) 5964 * 193(Wire6627 on &137 6628 ) 6629 *215 (Wire 5965 6630 uid 1453,0 5966 6631 shape (OrthoPolyLine … … 5995 6660 ) 5996 6661 ) 5997 on &1 275998 ) 5999 * 194(Wire6662 on &138 6663 ) 6664 *216 (Wire 6000 6665 uid 1461,0 6001 6666 shape (OrthoPolyLine … … 6030 6695 ) 6031 6696 ) 6032 on &1 286033 ) 6034 * 195(Wire6697 on &139 6698 ) 6699 *217 (Wire 6035 6700 uid 1469,0 6036 6701 shape (OrthoPolyLine … … 6067 6732 ) 6068 6733 ) 6069 on &1 296070 ) 6071 * 196(Wire6734 on &140 6735 ) 6736 *218 (Wire 6072 6737 uid 1477,0 6073 6738 shape (OrthoPolyLine … … 6102 6767 ) 6103 6768 ) 6104 on &1 306105 ) 6106 * 197(Wire6769 on &141 6770 ) 6771 *219 (Wire 6107 6772 uid 1485,0 6108 6773 shape (OrthoPolyLine … … 6137 6802 ) 6138 6803 ) 6139 on &1 316140 ) 6141 * 198(Wire6804 on &142 6805 ) 6806 *220 (Wire 6142 6807 uid 1503,0 6143 6808 shape (OrthoPolyLine … … 6174 6839 ) 6175 6840 ) 6176 on &1 366177 ) 6178 * 199(Wire6841 on &147 6842 ) 6843 *221 (Wire 6179 6844 uid 1529,0 6180 6845 shape (OrthoPolyLine … … 6191 6856 ] 6192 6857 ) 6193 start &1 386858 start &149 6194 6859 end &49 6195 6860 sat 32 … … 6212 6877 ) 6213 6878 ) 6214 on &1 456215 ) 6216 *2 00(Wire6879 on &156 6880 ) 6881 *222 (Wire 6217 6882 uid 1533,0 6218 6883 shape (OrthoPolyLine … … 6227 6892 ] 6228 6893 ) 6229 start &1 326894 start &143 6230 6895 sat 2 6231 6896 eat 16 … … 6247 6912 ) 6248 6913 ) 6249 on &1 366250 ) 6251 *2 01(Wire6914 on &147 6915 ) 6916 *223 (Wire 6252 6917 uid 1561,0 6253 6918 shape (OrthoPolyLine … … 6284 6949 ) 6285 6950 ) 6286 on &1 436287 ) 6288 *2 02(Wire6951 on &154 6952 ) 6953 *224 (Wire 6289 6954 uid 1567,0 6290 6955 shape (OrthoPolyLine … … 6299 6964 ] 6300 6965 ) 6301 start &1 326966 start &143 6302 6967 sat 2 6303 6968 eat 16 … … 6319 6984 ) 6320 6985 ) 6321 on &1 436322 ) 6323 *2 03(Wire6986 on &154 6987 ) 6988 *225 (Wire 6324 6989 uid 1684,0 6325 6990 shape (OrthoPolyLine … … 6354 7019 ) 6355 7020 ) 6356 on &144 7021 on &155 7022 ) 7023 *226 (Wire 7024 uid 2707,0 7025 shape (OrthoPolyLine 7026 uid 2708,0 7027 va (VaSet 7028 vasetType 3 7029 ) 7030 xt "109750,81000,122000,81000" 7031 pts [ 7032 "109750,81000" 7033 "122000,81000" 7034 ] 7035 ) 7036 start &55 7037 sat 32 7038 eat 16 7039 st 0 7040 sf 1 7041 si 0 7042 tg (WTG 7043 uid 2711,0 7044 ps "ConnStartEndStrategy" 7045 stg "STSignalDisplayStrategy" 7046 f (Text 7047 uid 2712,0 7048 va (VaSet 7049 ) 7050 xt "111000,80000,121400,81000" 7051 st "debug_data_ram_empty" 7052 blo "111000,80800" 7053 tm "WireNameMgr" 7054 ) 7055 ) 7056 on &167 7057 ) 7058 *227 (Wire 7059 uid 2715,0 7060 shape (OrthoPolyLine 7061 uid 2716,0 7062 va (VaSet 7063 vasetType 3 7064 ) 7065 xt "109750,82000,120000,82000" 7066 pts [ 7067 "109750,82000" 7068 "120000,82000" 7069 ] 7070 ) 7071 start &56 7072 sat 32 7073 eat 16 7074 st 0 7075 sf 1 7076 si 0 7077 tg (WTG 7078 uid 2719,0 7079 ps "ConnStartEndStrategy" 7080 stg "STSignalDisplayStrategy" 7081 f (Text 7082 uid 2720,0 7083 va (VaSet 7084 ) 7085 xt "111000,81000,118500,82000" 7086 st "debug_data_valid" 7087 blo "111000,81800" 7088 tm "WireNameMgr" 7089 ) 7090 ) 7091 on &168 7092 ) 7093 *228 (Wire 7094 uid 2723,0 7095 shape (OrthoPolyLine 7096 uid 2724,0 7097 va (VaSet 7098 vasetType 3 7099 lineWidth 2 7100 ) 7101 xt "109750,83000,119000,83000" 7102 pts [ 7103 "109750,83000" 7104 "119000,83000" 7105 ] 7106 ) 7107 start &57 7108 sat 32 7109 eat 16 7110 sty 1 7111 st 0 7112 sf 1 7113 si 0 7114 tg (WTG 7115 uid 2727,0 7116 ps "ConnStartEndStrategy" 7117 stg "STSignalDisplayStrategy" 7118 f (Text 7119 uid 2728,0 7120 va (VaSet 7121 ) 7122 xt "111000,82000,117900,83000" 7123 st "DG_state : (7:0)" 7124 blo "111000,82800" 7125 tm "WireNameMgr" 7126 ) 7127 ) 7128 on &169 7129 ) 7130 *229 (Wire 7131 uid 2731,0 7132 shape (OrthoPolyLine 7133 uid 2732,0 7134 va (VaSet 7135 vasetType 3 7136 ) 7137 xt "109750,84000,120000,84000" 7138 pts [ 7139 "109750,84000" 7140 "120000,84000" 7141 ] 7142 ) 7143 start &59 7144 sat 32 7145 eat 16 7146 st 0 7147 sf 1 7148 si 0 7149 tg (WTG 7150 uid 2735,0 7151 ps "ConnStartEndStrategy" 7152 stg "STSignalDisplayStrategy" 7153 f (Text 7154 uid 2736,0 7155 va (VaSet 7156 ) 7157 xt "111000,83000,119400,84000" 7158 st "FTM_RS485_rx_en" 7159 blo "111000,83800" 7160 tm "WireNameMgr" 7161 ) 7162 ) 7163 on &170 7164 ) 7165 *230 (Wire 7166 uid 2739,0 7167 shape (OrthoPolyLine 7168 uid 2740,0 7169 va (VaSet 7170 vasetType 3 7171 ) 7172 xt "109750,85000,120000,85000" 7173 pts [ 7174 "109750,85000" 7175 "120000,85000" 7176 ] 7177 ) 7178 start &60 7179 sat 32 7180 eat 16 7181 st 0 7182 sf 1 7183 si 0 7184 tg (WTG 7185 uid 2743,0 7186 ps "ConnStartEndStrategy" 7187 stg "STSignalDisplayStrategy" 7188 f (Text 7189 uid 2744,0 7190 va (VaSet 7191 ) 7192 xt "111000,84000,119100,85000" 7193 st "FTM_RS485_tx_d" 7194 blo "111000,84800" 7195 tm "WireNameMgr" 7196 ) 7197 ) 7198 on &171 7199 ) 7200 *231 (Wire 7201 uid 2747,0 7202 shape (OrthoPolyLine 7203 uid 2748,0 7204 va (VaSet 7205 vasetType 3 7206 ) 7207 xt "109750,86000,120000,86000" 7208 pts [ 7209 "109750,86000" 7210 "120000,86000" 7211 ] 7212 ) 7213 start &61 7214 sat 32 7215 eat 16 7216 st 0 7217 sf 1 7218 si 0 7219 tg (WTG 7220 uid 2751,0 7221 ps "ConnStartEndStrategy" 7222 stg "STSignalDisplayStrategy" 7223 f (Text 7224 uid 2752,0 7225 va (VaSet 7226 ) 7227 xt "111000,85000,119400,86000" 7228 st "FTM_RS485_tx_en" 7229 blo "111000,85800" 7230 tm "WireNameMgr" 7231 ) 7232 ) 7233 on &172 7234 ) 7235 *232 (Wire 7236 uid 2755,0 7237 shape (OrthoPolyLine 7238 uid 2756,0 7239 va (VaSet 7240 vasetType 3 7241 lineWidth 2 7242 ) 7243 xt "109750,87000,123000,87000" 7244 pts [ 7245 "109750,87000" 7246 "123000,87000" 7247 ] 7248 ) 7249 start &62 7250 sat 32 7251 eat 16 7252 sty 1 7253 st 0 7254 sf 1 7255 si 0 7256 tg (WTG 7257 uid 2759,0 7258 ps "ConnStartEndStrategy" 7259 stg "STSignalDisplayStrategy" 7260 f (Text 7261 uid 2760,0 7262 va (VaSet 7263 ) 7264 xt "111000,86000,122400,87000" 7265 st "mem_manager_state : (3:0)" 7266 blo "111000,86800" 7267 tm "WireNameMgr" 7268 ) 7269 ) 7270 on &173 7271 ) 7272 *233 (Wire 7273 uid 2763,0 7274 shape (OrthoPolyLine 7275 uid 2764,0 7276 va (VaSet 7277 vasetType 3 7278 ) 7279 xt "109750,88000,118000,88000" 7280 pts [ 7281 "109750,88000" 7282 "118000,88000" 7283 ] 7284 ) 7285 start &63 7286 sat 32 7287 eat 16 7288 st 0 7289 sf 1 7290 si 0 7291 tg (WTG 7292 uid 2767,0 7293 ps "ConnStartEndStrategy" 7294 stg "STSignalDisplayStrategy" 7295 f (Text 7296 uid 2768,0 7297 va (VaSet 7298 ) 7299 xt "111000,87000,116600,88000" 7300 st "trigger_veto" 7301 blo "111000,87800" 7302 tm "WireNameMgr" 7303 ) 7304 ) 7305 on &174 7306 ) 7307 *234 (Wire 7308 uid 2771,0 7309 shape (OrthoPolyLine 7310 uid 2772,0 7311 va (VaSet 7312 vasetType 3 7313 lineWidth 2 7314 ) 7315 xt "109750,89000,120000,89000" 7316 pts [ 7317 "109750,89000" 7318 "120000,89000" 7319 ] 7320 ) 7321 start &64 7322 sat 32 7323 eat 16 7324 sty 1 7325 st 0 7326 sf 1 7327 si 0 7328 tg (WTG 7329 uid 2775,0 7330 ps "ConnStartEndStrategy" 7331 stg "STSignalDisplayStrategy" 7332 f (Text 7333 uid 2776,0 7334 va (VaSet 7335 ) 7336 xt "111000,88000,119400,89000" 7337 st "w5300_state : (7:0)" 7338 blo "111000,88800" 7339 tm "WireNameMgr" 7340 ) 7341 ) 7342 on &175 7343 ) 7344 *235 (Wire 7345 uid 2779,0 7346 shape (OrthoPolyLine 7347 uid 2780,0 7348 va (VaSet 7349 vasetType 3 7350 ) 7351 xt "74000,78000,80250,82000" 7352 pts [ 7353 "74000,82000" 7354 "80250,78000" 7355 ] 7356 ) 7357 end &58 7358 sat 16 7359 eat 32 7360 st 0 7361 sf 1 7362 si 0 7363 tg (WTG 7364 uid 2783,0 7365 ps "ConnStartEndStrategy" 7366 stg "STSignalDisplayStrategy" 7367 f (Text 7368 uid 2784,0 7369 va (VaSet 7370 ) 7371 xt "73000,80000,81100,81000" 7372 st "FTM_RS485_rx_d" 7373 blo "73000,80800" 7374 tm "WireNameMgr" 7375 ) 7376 ) 7377 on &176 7378 ) 7379 *236 (Wire 7380 uid 2944,0 7381 shape (OrthoPolyLine 7382 uid 2945,0 7383 va (VaSet 7384 vasetType 3 7385 lineWidth 2 7386 ) 7387 xt "109750,90000,124000,90000" 7388 pts [ 7389 "109750,90000" 7390 "124000,90000" 7391 ] 7392 ) 7393 start &65 7394 sat 32 7395 eat 16 7396 sty 1 7397 st 0 7398 sf 1 7399 si 0 7400 tg (WTG 7401 uid 2948,0 7402 ps "ConnStartEndStrategy" 7403 stg "STSignalDisplayStrategy" 7404 f (Text 7405 uid 2949,0 7406 va (VaSet 7407 ) 7408 xt "111000,89000,122900,90000" 7409 st "socket_tx_free_out : (16:0)" 7410 blo "111000,89800" 7411 tm "WireNameMgr" 7412 ) 7413 ) 7414 on &177 6357 7415 ) 6358 7416 ] … … 6368 7426 color "26368,26368,26368" 6369 7427 ) 6370 packageList *2 04(PackageList7428 packageList *237 (PackageList 6371 7429 uid 41,0 6372 7430 stg "VerticalLayoutStrategy" 6373 7431 textVec [ 6374 *2 05(Text7432 *238 (Text 6375 7433 uid 42,0 6376 7434 va (VaSet … … 6381 7439 blo "-87000,800" 6382 7440 ) 6383 *2 06(MLText7441 *239 (MLText 6384 7442 uid 43,0 6385 7443 va (VaSet … … 6404 7462 stg "VerticalLayoutStrategy" 6405 7463 textVec [ 6406 *2 07(Text7464 *240 (Text 6407 7465 uid 45,0 6408 7466 va (VaSet … … 6414 7472 blo "20000,800" 6415 7473 ) 6416 *2 08(Text7474 *241 (Text 6417 7475 uid 46,0 6418 7476 va (VaSet … … 6424 7482 blo "20000,1800" 6425 7483 ) 6426 *2 09(MLText7484 *242 (MLText 6427 7485 uid 47,0 6428 7486 va (VaSet … … 6434 7492 tm "BdCompilerDirectivesTextMgr" 6435 7493 ) 6436 *2 10(Text7494 *243 (Text 6437 7495 uid 48,0 6438 7496 va (VaSet … … 6444 7502 blo "20000,4800" 6445 7503 ) 6446 *2 11(MLText7504 *244 (MLText 6447 7505 uid 49,0 6448 7506 va (VaSet … … 6452 7510 tm "BdCompilerDirectivesTextMgr" 6453 7511 ) 6454 *2 12(Text7512 *245 (Text 6455 7513 uid 50,0 6456 7514 va (VaSet … … 6462 7520 blo "20000,5800" 6463 7521 ) 6464 *2 13(MLText7522 *246 (MLText 6465 7523 uid 51,0 6466 7524 va (VaSet … … 6473 7531 associable 1 6474 7532 ) 6475 windowSize "0, 0,1681,1030"6476 viewArea "6 0000,4200,152106,61908"7533 windowSize "0,20,1681,1050" 7534 viewArea "69200,38600,161306,94544" 6477 7535 cachedDiagramExtent "-92000,0,146000,98000" 6478 7536 pageSetupInfo (PageSetupInfo … … 6487 7545 hasePageBreakOrigin 1 6488 7546 pageBreakOrigin "-146000,0" 6489 lastUid 2 551,07547 lastUid 2951,0 6490 7548 defaultCommentText (CommentText 6491 7549 shape (Rectangle … … 6549 7607 stg "VerticalLayoutStrategy" 6550 7608 textVec [ 6551 *2 14(Text7609 *247 (Text 6552 7610 va (VaSet 6553 7611 font "Arial,8,1" … … 6558 7616 tm "BdLibraryNameMgr" 6559 7617 ) 6560 *2 15(Text7618 *248 (Text 6561 7619 va (VaSet 6562 7620 font "Arial,8,1" … … 6567 7625 tm "BlkNameMgr" 6568 7626 ) 6569 *2 16(Text7627 *249 (Text 6570 7628 va (VaSet 6571 7629 font "Arial,8,1" … … 6618 7676 stg "VerticalLayoutStrategy" 6619 7677 textVec [ 6620 *2 17(Text7678 *250 (Text 6621 7679 va (VaSet 6622 7680 font "Arial,8,1" … … 6626 7684 blo "550,4300" 6627 7685 ) 6628 *2 18(Text7686 *251 (Text 6629 7687 va (VaSet 6630 7688 font "Arial,8,1" … … 6634 7692 blo "550,5300" 6635 7693 ) 6636 *2 19(Text7694 *252 (Text 6637 7695 va (VaSet 6638 7696 font "Arial,8,1" … … 6683 7741 stg "VerticalLayoutStrategy" 6684 7742 textVec [ 6685 *2 20(Text7743 *253 (Text 6686 7744 va (VaSet 6687 7745 font "Arial,8,1" … … 6692 7750 tm "BdLibraryNameMgr" 6693 7751 ) 6694 *2 21(Text7752 *254 (Text 6695 7753 va (VaSet 6696 7754 font "Arial,8,1" … … 6701 7759 tm "CptNameMgr" 6702 7760 ) 6703 *2 22(Text7761 *255 (Text 6704 7762 va (VaSet 6705 7763 font "Arial,8,1" … … 6755 7813 stg "VerticalLayoutStrategy" 6756 7814 textVec [ 6757 *2 23(Text7815 *256 (Text 6758 7816 va (VaSet 6759 7817 font "Arial,8,1" … … 6763 7821 blo "500,4300" 6764 7822 ) 6765 *2 24(Text7823 *257 (Text 6766 7824 va (VaSet 6767 7825 font "Arial,8,1" … … 6771 7829 blo "500,5300" 6772 7830 ) 6773 *2 25(Text7831 *258 (Text 6774 7832 va (VaSet 6775 7833 font "Arial,8,1" … … 6816 7874 stg "VerticalLayoutStrategy" 6817 7875 textVec [ 6818 *2 26(Text7876 *259 (Text 6819 7877 va (VaSet 6820 7878 font "Arial,8,1" … … 6824 7882 blo "50,4300" 6825 7883 ) 6826 *2 27(Text7884 *260 (Text 6827 7885 va (VaSet 6828 7886 font "Arial,8,1" … … 6832 7890 blo "50,5300" 6833 7891 ) 6834 *2 28(Text7892 *261 (Text 6835 7893 va (VaSet 6836 7894 font "Arial,8,1" … … 6873 7931 stg "VerticalLayoutStrategy" 6874 7932 textVec [ 6875 *2 29(Text7933 *262 (Text 6876 7934 va (VaSet 6877 7935 font "Arial,8,1" … … 6882 7940 tm "HdlTextNameMgr" 6883 7941 ) 6884 *2 30(Text7942 *263 (Text 6885 7943 va (VaSet 6886 7944 font "Arial,8,1" … … 7285 8343 stg "VerticalLayoutStrategy" 7286 8344 textVec [ 7287 *2 31(Text8345 *264 (Text 7288 8346 va (VaSet 7289 8347 font "Arial,8,1" … … 7293 8351 blo "14100,20800" 7294 8352 ) 7295 *2 32(MLText8353 *265 (MLText 7296 8354 va (VaSet 7297 8355 ) … … 7345 8403 stg "VerticalLayoutStrategy" 7346 8404 textVec [ 7347 *2 33(Text8405 *266 (Text 7348 8406 va (VaSet 7349 8407 font "Arial,8,1" … … 7353 8411 blo "14100,20800" 7354 8412 ) 7355 *2 34(MLText8413 *267 (MLText 7356 8414 va (VaSet 7357 8415 ) … … 7497 8555 commonDM (CommonDM 7498 8556 ldm (LogicalDM 7499 suid 51,08557 suid 64,0 7500 8558 usingSuid 1 7501 emptyRow *2 35(LEmptyRow8559 emptyRow *268 (LEmptyRow 7502 8560 ) 7503 8561 uid 54,0 7504 8562 optionalChildren [ 7505 *2 36(RefLabelRowHdr7506 ) 7507 *2 37(TitleRowHdr7508 ) 7509 *2 38(FilterRowHdr7510 ) 7511 *2 39(RefLabelColHdr8563 *269 (RefLabelRowHdr 8564 ) 8565 *270 (TitleRowHdr 8566 ) 8567 *271 (FilterRowHdr 8568 ) 8569 *272 (RefLabelColHdr 7512 8570 tm "RefLabelColHdrMgr" 7513 8571 ) 7514 *2 40(RowExpandColHdr8572 *273 (RowExpandColHdr 7515 8573 tm "RowExpandColHdrMgr" 7516 8574 ) 7517 *2 41(GroupColHdr8575 *274 (GroupColHdr 7518 8576 tm "GroupColHdrMgr" 7519 8577 ) 7520 *2 42(NameColHdr8578 *275 (NameColHdr 7521 8579 tm "BlockDiagramNameColHdrMgr" 7522 8580 ) 7523 *2 43(ModeColHdr8581 *276 (ModeColHdr 7524 8582 tm "BlockDiagramModeColHdrMgr" 7525 8583 ) 7526 *2 44(TypeColHdr8584 *277 (TypeColHdr 7527 8585 tm "BlockDiagramTypeColHdrMgr" 7528 8586 ) 7529 *2 45(BoundsColHdr8587 *278 (BoundsColHdr 7530 8588 tm "BlockDiagramBoundsColHdrMgr" 7531 8589 ) 7532 *2 46(InitColHdr8590 *279 (InitColHdr 7533 8591 tm "BlockDiagramInitColHdrMgr" 7534 8592 ) 7535 *2 47(EolColHdr8593 *280 (EolColHdr 7536 8594 tm "BlockDiagramEolColHdrMgr" 7537 8595 ) 7538 *2 48(LeafLogPort8596 *281 (LeafLogPort 7539 8597 port (LogicalPort 7540 8598 m 4 … … 7550 8608 uid 340,0 7551 8609 ) 7552 *2 49(LeafLogPort8610 *282 (LeafLogPort 7553 8611 port (LogicalPort 7554 8612 m 4 … … 7563 8621 uid 342,0 7564 8622 ) 7565 *2 50(LeafLogPort8623 *283 (LeafLogPort 7566 8624 port (LogicalPort 7567 8625 m 4 … … 7576 8634 uid 344,0 7577 8635 ) 7578 *2 51(LeafLogPort8636 *284 (LeafLogPort 7579 8637 port (LogicalPort 7580 8638 m 4 … … 7589 8647 uid 346,0 7590 8648 ) 7591 *2 52(LeafLogPort8649 *285 (LeafLogPort 7592 8650 port (LogicalPort 7593 8651 m 4 … … 7602 8660 uid 348,0 7603 8661 ) 7604 *2 53(LeafLogPort8662 *286 (LeafLogPort 7605 8663 port (LogicalPort 7606 8664 m 4 … … 7615 8673 uid 404,0 7616 8674 ) 7617 *2 54(LeafLogPort8675 *287 (LeafLogPort 7618 8676 port (LogicalPort 7619 8677 m 4 … … 7627 8685 uid 406,0 7628 8686 ) 7629 *2 55(LeafLogPort8687 *288 (LeafLogPort 7630 8688 port (LogicalPort 7631 8689 m 4 … … 7641 8699 uid 408,0 7642 8700 ) 7643 *2 56(LeafLogPort8701 *289 (LeafLogPort 7644 8702 port (LogicalPort 7645 8703 m 4 … … 7655 8713 uid 456,0 7656 8714 ) 7657 *2 57(LeafLogPort8715 *290 (LeafLogPort 7658 8716 port (LogicalPort 7659 8717 m 4 … … 7670 8728 uid 458,0 7671 8729 ) 7672 *2 58(LeafLogPort8730 *291 (LeafLogPort 7673 8731 port (LogicalPort 7674 8732 m 4 … … 7683 8741 uid 460,0 7684 8742 ) 7685 *2 59(LeafLogPort8743 *292 (LeafLogPort 7686 8744 port (LogicalPort 7687 8745 m 4 … … 7696 8754 uid 584,0 7697 8755 ) 7698 *2 60(LeafLogPort8756 *293 (LeafLogPort 7699 8757 port (LogicalPort 7700 8758 m 4 … … 7708 8766 uid 586,0 7709 8767 ) 7710 *2 61(LeafLogPort8768 *294 (LeafLogPort 7711 8769 port (LogicalPort 7712 8770 m 4 … … 7722 8780 uid 588,0 7723 8781 ) 7724 *2 62(LeafLogPort8782 *295 (LeafLogPort 7725 8783 port (LogicalPort 7726 8784 m 4 … … 7736 8794 uid 590,0 7737 8795 ) 7738 *2 63(LeafLogPort8796 *296 (LeafLogPort 7739 8797 port (LogicalPort 7740 8798 m 4 … … 7751 8809 uid 592,0 7752 8810 ) 7753 *2 64(LeafLogPort8811 *297 (LeafLogPort 7754 8812 port (LogicalPort 7755 8813 m 4 … … 7764 8822 uid 903,0 7765 8823 ) 7766 *2 65(LeafLogPort8824 *298 (LeafLogPort 7767 8825 port (LogicalPort 7768 8826 m 4 … … 7779 8837 uid 905,0 7780 8838 ) 7781 *2 66(LeafLogPort8839 *299 (LeafLogPort 7782 8840 port (LogicalPort 7783 8841 m 4 … … 7792 8850 uid 907,0 7793 8851 ) 7794 * 267(LeafLogPort8852 *300 (LeafLogPort 7795 8853 port (LogicalPort 7796 8854 m 4 … … 7804 8862 uid 909,0 7805 8863 ) 7806 * 268(LeafLogPort8864 *301 (LeafLogPort 7807 8865 port (LogicalPort 7808 8866 m 4 … … 7816 8874 uid 911,0 7817 8875 ) 7818 * 269(LeafLogPort8876 *302 (LeafLogPort 7819 8877 port (LogicalPort 7820 8878 m 4 … … 7829 8887 uid 913,0 7830 8888 ) 7831 * 270(LeafLogPort8889 *303 (LeafLogPort 7832 8890 port (LogicalPort 7833 8891 m 4 … … 7844 8902 uid 915,0 7845 8903 ) 7846 * 271(LeafLogPort8904 *304 (LeafLogPort 7847 8905 port (LogicalPort 7848 8906 m 4 … … 7856 8914 uid 917,0 7857 8915 ) 7858 * 272(LeafLogPort8916 *305 (LeafLogPort 7859 8917 port (LogicalPort 7860 8918 m 4 … … 7868 8926 uid 919,0 7869 8927 ) 7870 * 273(LeafLogPort8928 *306 (LeafLogPort 7871 8929 port (LogicalPort 7872 8930 m 4 … … 7882 8940 uid 921,0 7883 8941 ) 7884 * 274(LeafLogPort8942 *307 (LeafLogPort 7885 8943 port (LogicalPort 7886 8944 m 4 … … 7895 8953 uid 923,0 7896 8954 ) 7897 * 275(LeafLogPort8955 *308 (LeafLogPort 7898 8956 port (LogicalPort 7899 8957 m 4 … … 7908 8966 uid 925,0 7909 8967 ) 7910 * 276(LeafLogPort8968 *309 (LeafLogPort 7911 8969 port (LogicalPort 7912 8970 m 4 … … 7921 8979 uid 927,0 7922 8980 ) 7923 * 277(LeafLogPort8981 *310 (LeafLogPort 7924 8982 port (LogicalPort 7925 8983 m 4 … … 7933 8991 uid 929,0 7934 8992 ) 7935 * 278(LeafLogPort8993 *311 (LeafLogPort 7936 8994 port (LogicalPort 7937 8995 m 4 … … 7945 9003 uid 931,0 7946 9004 ) 7947 * 279(LeafLogPort9005 *312 (LeafLogPort 7948 9006 port (LogicalPort 7949 9007 m 4 … … 7957 9015 uid 933,0 7958 9016 ) 7959 * 280(LeafLogPort9017 *313 (LeafLogPort 7960 9018 port (LogicalPort 7961 9019 m 4 … … 7969 9027 uid 935,0 7970 9028 ) 7971 * 281(LeafLogPort9029 *314 (LeafLogPort 7972 9030 port (LogicalPort 7973 9031 m 4 … … 7982 9040 uid 1541,0 7983 9041 ) 7984 * 282(LeafLogPort9042 *315 (LeafLogPort 7985 9043 port (LogicalPort 7986 9044 m 4 … … 7994 9052 uid 1543,0 7995 9053 ) 7996 * 283(LeafLogPort9054 *316 (LeafLogPort 7997 9055 port (LogicalPort 7998 9056 m 4 … … 8006 9064 uid 1545,0 8007 9065 ) 8008 * 284(LeafLogPort9066 *317 (LeafLogPort 8009 9067 port (LogicalPort 8010 9068 m 4 … … 8018 9076 uid 1547,0 8019 9077 ) 8020 * 285(LeafLogPort9078 *318 (LeafLogPort 8021 9079 port (LogicalPort 8022 9080 m 4 … … 8031 9089 uid 1549,0 8032 9090 ) 8033 * 286(LeafLogPort9091 *319 (LeafLogPort 8034 9092 port (LogicalPort 8035 9093 m 4 … … 8044 9102 uid 1551,0 8045 9103 ) 8046 * 287(LeafLogPort9104 *320 (LeafLogPort 8047 9105 port (LogicalPort 8048 9106 m 4 … … 8056 9114 uid 1553,0 8057 9115 ) 8058 * 288(LeafLogPort9116 *321 (LeafLogPort 8059 9117 port (LogicalPort 8060 9118 m 4 … … 8069 9127 uid 1555,0 8070 9128 ) 8071 * 289(LeafLogPort9129 *322 (LeafLogPort 8072 9130 port (LogicalPort 8073 9131 m 4 … … 8083 9141 uid 1575,0 8084 9142 ) 8085 * 290(LeafLogPort9143 *323 (LeafLogPort 8086 9144 port (LogicalPort 8087 9145 lang 2 … … 8096 9154 uid 1690,0 8097 9155 ) 8098 * 291(LeafLogPort9156 *324 (LeafLogPort 8099 9157 port (LogicalPort 8100 9158 m 4 … … 8109 9167 uid 2003,0 8110 9168 ) 9169 *325 (LeafLogPort 9170 port (LogicalPort 9171 m 4 9172 decl (Decl 9173 n "debug_data_ram_empty" 9174 t "std_logic" 9175 o 45 9176 suid 53,0 9177 ) 9178 ) 9179 uid 2785,0 9180 ) 9181 *326 (LeafLogPort 9182 port (LogicalPort 9183 m 4 9184 decl (Decl 9185 n "debug_data_valid" 9186 t "std_logic" 9187 o 46 9188 suid 54,0 9189 ) 9190 ) 9191 uid 2787,0 9192 ) 9193 *327 (LeafLogPort 9194 port (LogicalPort 9195 m 4 9196 decl (Decl 9197 n "DG_state" 9198 t "std_logic_vector" 9199 b "(7 downto 0)" 9200 prec "-- for debugging" 9201 preAdd 0 9202 o 47 9203 suid 55,0 9204 ) 9205 ) 9206 uid 2789,0 9207 ) 9208 *328 (LeafLogPort 9209 port (LogicalPort 9210 m 4 9211 decl (Decl 9212 n "FTM_RS485_rx_en" 9213 t "std_logic" 9214 o 48 9215 suid 56,0 9216 ) 9217 ) 9218 uid 2791,0 9219 ) 9220 *329 (LeafLogPort 9221 port (LogicalPort 9222 m 4 9223 decl (Decl 9224 n "FTM_RS485_tx_d" 9225 t "std_logic" 9226 o 49 9227 suid 57,0 9228 ) 9229 ) 9230 uid 2793,0 9231 ) 9232 *330 (LeafLogPort 9233 port (LogicalPort 9234 m 4 9235 decl (Decl 9236 n "FTM_RS485_tx_en" 9237 t "std_logic" 9238 o 50 9239 suid 58,0 9240 ) 9241 ) 9242 uid 2795,0 9243 ) 9244 *331 (LeafLogPort 9245 port (LogicalPort 9246 lang 2 9247 m 4 9248 decl (Decl 9249 n "mem_manager_state" 9250 t "std_logic_vector" 9251 b "(3 DOWNTO 0)" 9252 eolc "-- state is encoded here ... useful for debugging." 9253 posAdd 0 9254 o 51 9255 suid 59,0 9256 ) 9257 ) 9258 uid 2797,0 9259 ) 9260 *332 (LeafLogPort 9261 port (LogicalPort 9262 m 4 9263 decl (Decl 9264 n "trigger_veto" 9265 t "std_logic" 9266 o 52 9267 suid 60,0 9268 i "'1'" 9269 ) 9270 ) 9271 uid 2799,0 9272 ) 9273 *333 (LeafLogPort 9274 port (LogicalPort 9275 m 4 9276 decl (Decl 9277 n "w5300_state" 9278 t "std_logic_vector" 9279 b "(7 DOWNTO 0)" 9280 eolc "-- state is encoded here ... useful for debugging." 9281 posAdd 0 9282 o 53 9283 suid 61,0 9284 ) 9285 ) 9286 uid 2801,0 9287 ) 9288 *334 (LeafLogPort 9289 port (LogicalPort 9290 m 4 9291 decl (Decl 9292 n "FTM_RS485_rx_d" 9293 t "std_logic" 9294 o 54 9295 suid 62,0 9296 ) 9297 ) 9298 uid 2803,0 9299 ) 9300 *335 (LeafLogPort 9301 port (LogicalPort 9302 m 4 9303 decl (Decl 9304 n "socket_tx_free_out" 9305 t "std_logic_vector" 9306 b "(16 DOWNTO 0)" 9307 eolc "-- 17bit value .. that's true" 9308 posAdd 0 9309 o 55 9310 suid 64,0 9311 ) 9312 ) 9313 uid 2950,0 9314 ) 8111 9315 ] 8112 9316 ) … … 8116 9320 uid 67,0 8117 9321 optionalChildren [ 8118 * 292(Sheet9322 *336 (Sheet 8119 9323 sheetRow (SheetRow 8120 9324 headerVa (MVa … … 8133 9337 font "Tahoma,10,0" 8134 9338 ) 8135 emptyMRCItem * 293(MRCItem8136 litem &2 358137 pos 449339 emptyMRCItem *337 (MRCItem 9340 litem &268 9341 pos 55 8138 9342 dimension 20 8139 9343 ) 8140 9344 uid 69,0 8141 9345 optionalChildren [ 8142 * 294(MRCItem8143 litem &2 369346 *338 (MRCItem 9347 litem &269 8144 9348 pos 0 8145 9349 dimension 20 8146 9350 uid 70,0 8147 9351 ) 8148 * 295(MRCItem8149 litem &2 379352 *339 (MRCItem 9353 litem &270 8150 9354 pos 1 8151 9355 dimension 23 8152 9356 uid 71,0 8153 9357 ) 8154 * 296(MRCItem8155 litem &2 389358 *340 (MRCItem 9359 litem &271 8156 9360 pos 2 8157 9361 hidden 1 … … 8159 9363 uid 72,0 8160 9364 ) 8161 * 297(MRCItem8162 litem &2 489365 *341 (MRCItem 9366 litem &281 8163 9367 pos 0 8164 9368 dimension 20 8165 9369 uid 341,0 8166 9370 ) 8167 * 298(MRCItem8168 litem &2 499371 *342 (MRCItem 9372 litem &282 8169 9373 pos 1 8170 9374 dimension 20 8171 9375 uid 343,0 8172 9376 ) 8173 * 299(MRCItem8174 litem &2 509377 *343 (MRCItem 9378 litem &283 8175 9379 pos 2 8176 9380 dimension 20 8177 9381 uid 345,0 8178 9382 ) 8179 *3 00(MRCItem8180 litem &2 519383 *344 (MRCItem 9384 litem &284 8181 9385 pos 3 8182 9386 dimension 20 8183 9387 uid 347,0 8184 9388 ) 8185 *3 01(MRCItem8186 litem &2 529389 *345 (MRCItem 9390 litem &285 8187 9391 pos 4 8188 9392 dimension 20 8189 9393 uid 349,0 8190 9394 ) 8191 *3 02(MRCItem8192 litem &2 539395 *346 (MRCItem 9396 litem &286 8193 9397 pos 5 8194 9398 dimension 20 8195 9399 uid 405,0 8196 9400 ) 8197 *3 03(MRCItem8198 litem &2 549401 *347 (MRCItem 9402 litem &287 8199 9403 pos 6 8200 9404 dimension 20 8201 9405 uid 407,0 8202 9406 ) 8203 *3 04(MRCItem8204 litem &2 559407 *348 (MRCItem 9408 litem &288 8205 9409 pos 7 8206 9410 dimension 20 8207 9411 uid 409,0 8208 9412 ) 8209 *3 05(MRCItem8210 litem &2 569413 *349 (MRCItem 9414 litem &289 8211 9415 pos 8 8212 9416 dimension 20 8213 9417 uid 457,0 8214 9418 ) 8215 *3 06(MRCItem8216 litem &2 579419 *350 (MRCItem 9420 litem &290 8217 9421 pos 9 8218 9422 dimension 20 8219 9423 uid 459,0 8220 9424 ) 8221 *3 07(MRCItem8222 litem &2 589425 *351 (MRCItem 9426 litem &291 8223 9427 pos 10 8224 9428 dimension 20 8225 9429 uid 461,0 8226 9430 ) 8227 *3 08(MRCItem8228 litem &2 599431 *352 (MRCItem 9432 litem &292 8229 9433 pos 11 8230 9434 dimension 20 8231 9435 uid 585,0 8232 9436 ) 8233 *3 09(MRCItem8234 litem &2 609437 *353 (MRCItem 9438 litem &293 8235 9439 pos 12 8236 9440 dimension 20 8237 9441 uid 587,0 8238 9442 ) 8239 *3 10(MRCItem8240 litem &2 619443 *354 (MRCItem 9444 litem &294 8241 9445 pos 13 8242 9446 dimension 20 8243 9447 uid 589,0 8244 9448 ) 8245 *3 11(MRCItem8246 litem &2 629449 *355 (MRCItem 9450 litem &295 8247 9451 pos 14 8248 9452 dimension 20 8249 9453 uid 591,0 8250 9454 ) 8251 *3 12(MRCItem8252 litem &2 639455 *356 (MRCItem 9456 litem &296 8253 9457 pos 15 8254 9458 dimension 20 8255 9459 uid 593,0 8256 9460 ) 8257 *3 13(MRCItem8258 litem &2 649461 *357 (MRCItem 9462 litem &297 8259 9463 pos 16 8260 9464 dimension 20 8261 9465 uid 904,0 8262 9466 ) 8263 *3 14(MRCItem8264 litem &2 659467 *358 (MRCItem 9468 litem &298 8265 9469 pos 17 8266 9470 dimension 20 8267 9471 uid 906,0 8268 9472 ) 8269 *3 15(MRCItem8270 litem &2 669473 *359 (MRCItem 9474 litem &299 8271 9475 pos 18 8272 9476 dimension 20 8273 9477 uid 908,0 8274 9478 ) 8275 *3 16(MRCItem8276 litem & 2679479 *360 (MRCItem 9480 litem &300 8277 9481 pos 19 8278 9482 dimension 20 8279 9483 uid 910,0 8280 9484 ) 8281 *3 17(MRCItem8282 litem & 2689485 *361 (MRCItem 9486 litem &301 8283 9487 pos 20 8284 9488 dimension 20 8285 9489 uid 912,0 8286 9490 ) 8287 *3 18(MRCItem8288 litem & 2699491 *362 (MRCItem 9492 litem &302 8289 9493 pos 21 8290 9494 dimension 20 8291 9495 uid 914,0 8292 9496 ) 8293 *3 19(MRCItem8294 litem & 2709497 *363 (MRCItem 9498 litem &303 8295 9499 pos 22 8296 9500 dimension 20 8297 9501 uid 916,0 8298 9502 ) 8299 *3 20(MRCItem8300 litem & 2719503 *364 (MRCItem 9504 litem &304 8301 9505 pos 23 8302 9506 dimension 20 8303 9507 uid 918,0 8304 9508 ) 8305 *3 21(MRCItem8306 litem & 2729509 *365 (MRCItem 9510 litem &305 8307 9511 pos 24 8308 9512 dimension 20 8309 9513 uid 920,0 8310 9514 ) 8311 *3 22(MRCItem8312 litem & 2739515 *366 (MRCItem 9516 litem &306 8313 9517 pos 25 8314 9518 dimension 20 8315 9519 uid 922,0 8316 9520 ) 8317 *3 23(MRCItem8318 litem & 2749521 *367 (MRCItem 9522 litem &307 8319 9523 pos 26 8320 9524 dimension 20 8321 9525 uid 924,0 8322 9526 ) 8323 *3 24(MRCItem8324 litem & 2759527 *368 (MRCItem 9528 litem &308 8325 9529 pos 27 8326 9530 dimension 20 8327 9531 uid 926,0 8328 9532 ) 8329 *3 25(MRCItem8330 litem & 2769533 *369 (MRCItem 9534 litem &309 8331 9535 pos 28 8332 9536 dimension 20 8333 9537 uid 928,0 8334 9538 ) 8335 *3 26(MRCItem8336 litem & 2779539 *370 (MRCItem 9540 litem &310 8337 9541 pos 29 8338 9542 dimension 20 8339 9543 uid 930,0 8340 9544 ) 8341 *3 27(MRCItem8342 litem & 2789545 *371 (MRCItem 9546 litem &311 8343 9547 pos 30 8344 9548 dimension 20 8345 9549 uid 932,0 8346 9550 ) 8347 *3 28(MRCItem8348 litem & 2799551 *372 (MRCItem 9552 litem &312 8349 9553 pos 31 8350 9554 dimension 20 8351 9555 uid 934,0 8352 9556 ) 8353 *3 29(MRCItem8354 litem & 2809557 *373 (MRCItem 9558 litem &313 8355 9559 pos 32 8356 9560 dimension 20 8357 9561 uid 936,0 8358 9562 ) 8359 *3 30(MRCItem8360 litem & 2819563 *374 (MRCItem 9564 litem &314 8361 9565 pos 33 8362 9566 dimension 20 8363 9567 uid 1542,0 8364 9568 ) 8365 *3 31(MRCItem8366 litem & 2829569 *375 (MRCItem 9570 litem &315 8367 9571 pos 34 8368 9572 dimension 20 8369 9573 uid 1544,0 8370 9574 ) 8371 *3 32(MRCItem8372 litem & 2839575 *376 (MRCItem 9576 litem &316 8373 9577 pos 35 8374 9578 dimension 20 8375 9579 uid 1546,0 8376 9580 ) 8377 *3 33(MRCItem8378 litem & 2849581 *377 (MRCItem 9582 litem &317 8379 9583 pos 36 8380 9584 dimension 20 8381 9585 uid 1548,0 8382 9586 ) 8383 *3 34(MRCItem8384 litem & 2859587 *378 (MRCItem 9588 litem &318 8385 9589 pos 37 8386 9590 dimension 20 8387 9591 uid 1550,0 8388 9592 ) 8389 *3 35(MRCItem8390 litem & 2869593 *379 (MRCItem 9594 litem &319 8391 9595 pos 38 8392 9596 dimension 20 8393 9597 uid 1552,0 8394 9598 ) 8395 *3 36(MRCItem8396 litem & 2879599 *380 (MRCItem 9600 litem &320 8397 9601 pos 39 8398 9602 dimension 20 8399 9603 uid 1554,0 8400 9604 ) 8401 *3 37(MRCItem8402 litem & 2889605 *381 (MRCItem 9606 litem &321 8403 9607 pos 40 8404 9608 dimension 20 8405 9609 uid 1556,0 8406 9610 ) 8407 *3 38(MRCItem8408 litem & 2899611 *382 (MRCItem 9612 litem &322 8409 9613 pos 41 8410 9614 dimension 20 8411 9615 uid 1576,0 8412 9616 ) 8413 *3 39(MRCItem8414 litem & 2909617 *383 (MRCItem 9618 litem &323 8415 9619 pos 42 8416 9620 dimension 20 8417 9621 uid 1691,0 8418 9622 ) 8419 *3 40(MRCItem8420 litem & 2919623 *384 (MRCItem 9624 litem &324 8421 9625 pos 43 8422 9626 dimension 20 8423 9627 uid 2004,0 9628 ) 9629 *385 (MRCItem 9630 litem &325 9631 pos 44 9632 dimension 20 9633 uid 2786,0 9634 ) 9635 *386 (MRCItem 9636 litem &326 9637 pos 45 9638 dimension 20 9639 uid 2788,0 9640 ) 9641 *387 (MRCItem 9642 litem &327 9643 pos 46 9644 dimension 20 9645 uid 2790,0 9646 ) 9647 *388 (MRCItem 9648 litem &328 9649 pos 47 9650 dimension 20 9651 uid 2792,0 9652 ) 9653 *389 (MRCItem 9654 litem &329 9655 pos 48 9656 dimension 20 9657 uid 2794,0 9658 ) 9659 *390 (MRCItem 9660 litem &330 9661 pos 49 9662 dimension 20 9663 uid 2796,0 9664 ) 9665 *391 (MRCItem 9666 litem &331 9667 pos 50 9668 dimension 20 9669 uid 2798,0 9670 ) 9671 *392 (MRCItem 9672 litem &332 9673 pos 51 9674 dimension 20 9675 uid 2800,0 9676 ) 9677 *393 (MRCItem 9678 litem &333 9679 pos 52 9680 dimension 20 9681 uid 2802,0 9682 ) 9683 *394 (MRCItem 9684 litem &334 9685 pos 53 9686 dimension 20 9687 uid 2804,0 9688 ) 9689 *395 (MRCItem 9690 litem &335 9691 pos 54 9692 dimension 20 9693 uid 2951,0 8424 9694 ) 8425 9695 ] … … 8434 9704 uid 73,0 8435 9705 optionalChildren [ 8436 *3 41(MRCItem8437 litem &2 399706 *396 (MRCItem 9707 litem &272 8438 9708 pos 0 8439 9709 dimension 20 8440 9710 uid 74,0 8441 9711 ) 8442 *3 42(MRCItem8443 litem &2 419712 *397 (MRCItem 9713 litem &274 8444 9714 pos 1 8445 9715 dimension 50 8446 9716 uid 75,0 8447 9717 ) 8448 *3 43(MRCItem8449 litem &2 429718 *398 (MRCItem 9719 litem &275 8450 9720 pos 2 8451 9721 dimension 100 8452 9722 uid 76,0 8453 9723 ) 8454 *3 44(MRCItem8455 litem &2 439724 *399 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(FilterRowHdr 9778 ) 9779 *408 (RefLabelColHdr 8510 9780 tm "RefLabelColHdrMgr" 8511 9781 ) 8512 * 354(RowExpandColHdr9782 *409 (RowExpandColHdr 8513 9783 tm "RowExpandColHdrMgr" 8514 9784 ) 8515 * 355(GroupColHdr9785 *410 (GroupColHdr 8516 9786 tm "GroupColHdrMgr" 8517 9787 ) 8518 * 356(NameColHdr9788 *411 (NameColHdr 8519 9789 tm "GenericNameColHdrMgr" 8520 9790 ) 8521 * 357(TypeColHdr9791 *412 (TypeColHdr 8522 9792 tm "GenericTypeColHdrMgr" 8523 9793 ) 8524 * 358(InitColHdr9794 *413 (InitColHdr 8525 9795 tm "GenericValueColHdrMgr" 8526 9796 ) 8527 * 359(PragmaColHdr9797 *414 (PragmaColHdr 8528 9798 tm "GenericPragmaColHdrMgr" 8529 9799 ) 8530 * 360(EolColHdr9800 *415 (EolColHdr 8531 9801 tm "GenericEolColHdrMgr" 8532 9802 ) … … 8538 9808 uid 95,0 8539 9809 optionalChildren [ 8540 * 361(Sheet9810 *416 (Sheet 8541 9811 sheetRow (SheetRow 8542 9812 headerVa (MVa … … 8555 9825 font "Tahoma,10,0" 8556 9826 ) 8557 emptyMRCItem * 362(MRCItem8558 litem & 3499827 emptyMRCItem *417 (MRCItem 9828 litem &404 8559 9829 pos 0 8560 9830 dimension 20 … … 8562 9832 uid 97,0 8563 9833 optionalChildren [ 8564 * 363(MRCItem8565 litem & 3509834 *418 (MRCItem 9835 litem &405 8566 9836 pos 0 8567 9837 dimension 20 8568 9838 uid 98,0 8569 9839 ) 8570 * 364(MRCItem8571 litem & 3519840 *419 (MRCItem 9841 litem &406 8572 9842 pos 1 8573 9843 dimension 23 8574 9844 uid 99,0 8575 9845 ) 8576 * 365(MRCItem8577 litem & 3529846 *420 (MRCItem 9847 litem &407 8578 9848 pos 2 8579 9849 hidden 1 … … 8592 9862 uid 101,0 8593 9863 optionalChildren [ 8594 * 366(MRCItem8595 litem & 3539864 *421 (MRCItem 9865 litem &408 8596 9866 pos 0 8597 9867 dimension 20 8598 9868 uid 102,0 8599 9869 ) 8600 * 367(MRCItem8601 litem & 3559870 *422 (MRCItem 9871 litem &410 8602 9872 pos 1 8603 9873 dimension 50 8604 9874 uid 103,0 8605 9875 ) 8606 * 368(MRCItem8607 litem & 3569876 *423 (MRCItem 9877 litem &411 8608 9878 pos 2 8609 9879 dimension 100 8610 9880 uid 104,0 8611 9881 ) 8612 * 369(MRCItem8613 litem & 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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak
r10240 r10883 206 206 (vvPair 207 207 variable "date" 208 value " 02.03.2011"208 value "23.05.2011" 209 209 ) 210 210 (vvPair 211 211 variable "day" 212 value "M i"212 value "Mo" 213 213 ) 214 214 (vvPair 215 215 variable "day_long" 216 value "M ittwoch"216 value "Montag" 217 217 ) 218 218 (vvPair 219 219 variable "dd" 220 value " 02"220 value "23" 221 221 ) 222 222 (vvPair … … 278 278 (vvPair 279 279 variable "mm" 280 value "0 3"280 value "05" 281 281 ) 282 282 (vvPair … … 286 286 (vvPair 287 287 variable "month" 288 value "M rz"288 value "Mai" 289 289 ) 290 290 (vvPair 291 291 variable "month_long" 292 value "M ärz"292 value "Mai" 293 293 ) 294 294 (vvPair … … 354 354 (vvPair 355 355 variable "time" 356 value "1 5:31:34"356 value "18:19:57" 357 357 ) 358 358 (vvPair … … 406 406 bg "0,0,32768" 407 407 ) 408 xt "109200,97000,1 19000,98000"408 xt "109200,97000,120300,98000" 409 409 st " 410 410 by %user on %dd %month %year … … 437 437 bg "0,0,32768" 438 438 ) 439 xt "126200,93000,129 200,94000"439 xt "126200,93000,129500,94000" 440 440 st " 441 441 Project: … … 468 468 bg "0,0,32768" 469 469 ) 470 xt "109200,95000,1 19200,96000"470 xt "109200,95000,120100,96000" 471 471 st " 472 472 <enter diagram title here> … … 499 499 bg "0,0,32768" 500 500 ) 501 xt "105200,95000,107 300,96000"501 xt "105200,95000,107500,96000" 502 502 st " 503 503 Title: … … 530 530 bg "0,0,32768" 531 531 ) 532 xt "126200,94200,13 5400,95200"532 xt "126200,94200,136000,95200" 533 533 st " 534 534 <enter comments here> … … 560 560 bg "0,0,32768" 561 561 ) 562 xt "130200,93000,134 700,94000"562 xt "130200,93000,134900,94000" 563 563 st " 564 564 %project_name … … 590 590 fg "32768,0,0" 591 591 ) 592 xt "112 700,93000,118300,95000"592 xt "112450,93000,118550,95000" 593 593 st " 594 594 TU Dortmund … … 623 623 bg "0,0,32768" 624 624 ) 625 xt "105200,96000,107 300,97000"625 xt "105200,96000,107500,97000" 626 626 st " 627 627 Path: … … 654 654 bg "0,0,32768" 655 655 ) 656 xt "105200,97000,10 7900,98000"656 xt "105200,97000,108300,98000" 657 657 st " 658 658 Edited: … … 685 685 bg "0,0,32768" 686 686 ) 687 xt "109200,96000,12 3400,97000"687 xt "109200,96000,125800,97000" 688 688 st " 689 689 %library/%unit/%view … … 734 734 va (VaSet 735 735 ) 736 xt "10 4400,23500,108000,24500"736 xt "103800,23500,108000,24500" 737 737 st "wiz_reset" 738 738 ju 2 … … 745 745 n "wiz_reset" 746 746 t "std_logic" 747 o 39747 o 49 748 748 suid 2,0 749 749 i "'1'" … … 771 771 va (VaSet 772 772 ) 773 xt "10 4000,69500,108000,70500"773 xt "103600,69500,108000,70500" 774 774 st "led : (7:0)" 775 775 ju 2 … … 784 784 b "(7 DOWNTO 0)" 785 785 posAdd 0 786 o 3 1786 o 38 787 787 suid 7,0 788 788 i "(OTHERS => '0')" … … 810 810 va (VaSet 811 811 ) 812 xt "82000,31500,8 4800,32500"812 xt "82000,31500,85000,32500" 813 813 st "trigger" 814 814 blo "82000,32300" … … 821 821 preAdd 0 822 822 posAdd 0 823 o 1 3823 o 14 824 824 suid 18,0 825 825 ) … … 846 846 va (VaSet 847 847 ) 848 xt "82000,42500,85 200,43500"848 xt "82000,42500,85500,43500" 849 849 st "adc_oeb" 850 850 blo "82000,43300" … … 856 856 n "adc_oeb" 857 857 t "std_logic" 858 o 2 1858 o 26 859 859 suid 21,0 860 860 i "'1'" … … 882 882 va (VaSet 883 883 ) 884 xt "82000,33500,8 7900,34500"884 xt "82000,33500,88700,34500" 885 885 st "board_id : (3:0)" 886 886 blo "82000,34300" … … 892 892 t "std_logic_vector" 893 893 b "(3 DOWNTO 0)" 894 o 9894 o 10 895 895 suid 24,0 896 896 ) … … 917 917 va (VaSet 918 918 ) 919 xt "82000,34500,8 7700,35500"919 xt "82000,34500,88400,35500" 920 920 st "crate_id : (1:0)" 921 921 blo "82000,35300" … … 927 927 t "std_logic_vector" 928 928 b "(1 DOWNTO 0)" 929 o 1 0929 o 11 930 930 suid 25,0 931 931 ) … … 952 952 va (VaSet 953 953 ) 954 xt "10 2000,20500,108000,21500"954 xt "101100,20500,108000,21500" 955 955 st "wiz_addr : (9:0)" 956 956 ju 2 … … 964 964 t "std_logic_vector" 965 965 b "(9 DOWNTO 0)" 966 o 36966 o 46 967 967 suid 26,0 968 968 ) … … 989 989 va (VaSet 990 990 ) 991 xt "10 1700,21500,108000,22500"991 xt "100800,21500,108000,22500" 992 992 st "wiz_data : (15:0)" 993 993 ju 2 … … 1001 1001 t "std_logic_vector" 1002 1002 b "(15 DOWNTO 0)" 1003 o 421003 o 52 1004 1004 suid 27,0 1005 1005 ) … … 1026 1026 va (VaSet 1027 1027 ) 1028 xt "105 300,27500,108000,28500"1028 xt "105000,27500,108000,28500" 1029 1029 st "wiz_cs" 1030 1030 ju 2 … … 1037 1037 n "wiz_cs" 1038 1038 t "std_logic" 1039 o 371039 o 47 1040 1040 suid 28,0 1041 1041 i "'1'" … … 1063 1063 va (VaSet 1064 1064 ) 1065 xt "10 5300,25500,108000,26500"1065 xt "104800,25500,108000,26500" 1066 1066 st "wiz_wr" 1067 1067 ju 2 … … 1074 1074 n "wiz_wr" 1075 1075 t "std_logic" 1076 o 401076 o 50 1077 1077 suid 29,0 1078 1078 i "'1'" … … 1100 1100 va (VaSet 1101 1101 ) 1102 xt "10 5400,24500,108000,25500"1102 xt "104900,24500,108000,25500" 1103 1103 st "wiz_rd" 1104 1104 ju 2 … … 1111 1111 n "wiz_rd" 1112 1112 t "std_logic" 1113 o 381113 o 48 1114 1114 suid 30,0 1115 1115 i "'1'" … … 1137 1137 va (VaSet 1138 1138 ) 1139 xt "10 5300,26500,108000,27500"1139 xt "104800,26500,108000,27500" 1140 1140 st "wiz_int" 1141 1141 ju 2 … … 1147 1147 n "wiz_int" 1148 1148 t "std_logic" 1149 o 1 41149 o 15 1150 1150 suid 31,0 1151 1151 ) … … 1172 1172 va (VaSet 1173 1173 ) 1174 xt "82000,22500,86 500,23500"1174 xt "82000,22500,86800,23500" 1175 1175 st "CLK_25_PS" 1176 1176 blo "82000,23300" … … 1182 1182 n "CLK_25_PS" 1183 1183 t "std_logic" 1184 o 1 61184 o 17 1185 1185 suid 35,0 1186 1186 ) … … 1207 1207 va (VaSet 1208 1208 ) 1209 xt "82000,21500,85 100,22500"1209 xt "82000,21500,85300,22500" 1210 1210 st "CLK_50" 1211 1211 blo "82000,22300" … … 1219 1219 preAdd 0 1220 1220 posAdd 0 1221 o 1 71221 o 18 1222 1222 suid 37,0 1223 1223 ) … … 1278 1278 va (VaSet 1279 1279 ) 1280 xt "82000,41500,9 0000,42500"1280 xt "82000,41500,91300,42500" 1281 1281 st "adc_otr_array : (3:0)" 1282 1282 blo "82000,42300" … … 1288 1288 t "std_logic_vector" 1289 1289 b "(3 DOWNTO 0)" 1290 o 81290 o 9 1291 1291 suid 40,0 1292 1292 ) … … 1313 1313 va (VaSet 1314 1314 ) 1315 xt "82000,47500,8 7900,48500"1315 xt "82000,47500,88900,48500" 1316 1316 st "adc_data_array" 1317 1317 blo "82000,48300" … … 1322 1322 n "adc_data_array" 1323 1323 t "adc_data_array_type" 1324 o 71324 o 8 1325 1325 suid 41,0 1326 1326 ) … … 1347 1347 va (VaSet 1348 1348 ) 1349 xt "82000,61500,9 0500,62500"1349 xt "82000,61500,91500,62500" 1350 1350 st "drs_channel_id : (3:0)" 1351 1351 blo "82000,62300" … … 1358 1358 t "std_logic_vector" 1359 1359 b "(3 downto 0)" 1360 o 281360 o 35 1361 1361 suid 48,0 1362 1362 i "(others => '0')" … … 1384 1384 va (VaSet 1385 1385 ) 1386 xt "82000,66500,8 6300,67500"1386 xt "82000,66500,87200,67500" 1387 1387 st "drs_dwrite" 1388 1388 blo "82000,67300" … … 1394 1394 n "drs_dwrite" 1395 1395 t "std_logic" 1396 o 291396 o 36 1397 1397 suid 49,0 1398 1398 i "'1'" … … 1420 1420 va (VaSet 1421 1421 ) 1422 xt "82000,57500,87 400,58500"1422 xt "82000,57500,87800,58500" 1423 1423 st "SROUT_in_0" 1424 1424 blo "82000,58300" … … 1429 1429 n "SROUT_in_0" 1430 1430 t "std_logic" 1431 o 31431 o 4 1432 1432 suid 52,0 1433 1433 ) … … 1454 1454 va (VaSet 1455 1455 ) 1456 xt "82000,58500,87 400,59500"1456 xt "82000,58500,87700,59500" 1457 1457 st "SROUT_in_1" 1458 1458 blo "82000,59300" … … 1463 1463 n "SROUT_in_1" 1464 1464 t "std_logic" 1465 o 41465 o 5 1466 1466 suid 53,0 1467 1467 ) … … 1488 1488 va (VaSet 1489 1489 ) 1490 xt "82000,59500,87 400,60500"1490 xt "82000,59500,87800,60500" 1491 1491 st "SROUT_in_2" 1492 1492 blo "82000,60300" … … 1497 1497 n "SROUT_in_2" 1498 1498 t "std_logic" 1499 o 51499 o 6 1500 1500 suid 54,0 1501 1501 ) … … 1522 1522 va (VaSet 1523 1523 ) 1524 xt "82000,60500,87 400,61500"1524 xt "82000,60500,87800,61500" 1525 1525 st "SROUT_in_3" 1526 1526 blo "82000,61300" … … 1531 1531 n "SROUT_in_3" 1532 1532 t "std_logic" 1533 o 61533 o 7 1534 1534 suid 55,0 1535 1535 ) … … 1566 1566 n "RSRLOAD" 1567 1567 t "std_logic" 1568 o 181568 o 23 1569 1569 suid 56,0 1570 1570 i "'0'" … … 1592 1592 va (VaSet 1593 1593 ) 1594 xt "82000,64500,8 5000,65500"1594 xt "82000,64500,84900,65500" 1595 1595 st "SRCLK" 1596 1596 blo "82000,65300" … … 1602 1602 n "SRCLK" 1603 1603 t "std_logic" 1604 o 191604 o 24 1605 1605 suid 57,0 1606 1606 i "'0'" … … 1628 1628 va (VaSet 1629 1629 ) 1630 xt "106 300,50500,108000,51500"1630 xt "106100,50500,108000,51500" 1631 1631 st "sclk" 1632 1632 ju 2 … … 1639 1639 n "sclk" 1640 1640 t "std_logic" 1641 o 341641 o 42 1642 1642 suid 62,0 1643 1643 ) … … 1677 1677 preAdd 0 1678 1678 posAdd 0 1679 o 411679 o 51 1680 1680 suid 63,0 1681 1681 ) … … 1702 1702 va (VaSet 1703 1703 ) 1704 xt "105 200,39500,108000,40500"1704 xt "105000,39500,108000,40500" 1705 1705 st "dac_cs" 1706 1706 ju 2 … … 1713 1713 n "dac_cs" 1714 1714 t "std_logic" 1715 o 261715 o 31 1716 1716 suid 64,0 1717 1717 ) … … 1738 1738 va (VaSet 1739 1739 ) 1740 xt "101 500,41500,108000,42500"1740 xt "101000,41500,108000,42500" 1741 1741 st "sensor_cs : (3:0)" 1742 1742 ju 2 … … 1750 1750 t "std_logic_vector" 1751 1751 b "(3 DOWNTO 0)" 1752 o 351752 o 43 1753 1753 suid 65,0 1754 1754 ) … … 1786 1786 n "mosi" 1787 1787 t "std_logic" 1788 o 321788 o 40 1789 1789 suid 66,0 1790 1790 i "'0'" … … 1812 1812 va (VaSet 1813 1813 ) 1814 xt "82000,65500,85 000,66500"1814 xt "82000,65500,85200,66500" 1815 1815 st "denable" 1816 1816 blo "82000,66300" … … 1824 1824 eolc "-- default domino wave off" 1825 1825 posAdd 0 1826 o 271826 o 34 1827 1827 suid 67,0 1828 1828 i "'0'" … … 1850 1850 va (VaSet 1851 1851 ) 1852 xt "9 9400,73500,108000,74500"1852 xt "98000,73500,108000,74500" 1853 1853 st "alarm_refclk_too_high" 1854 1854 ju 2 … … 1861 1861 n "alarm_refclk_too_high" 1862 1862 t "std_logic" 1863 o 2 21863 o 27 1864 1864 suid 95,0 1865 1865 ) … … 1886 1886 va (VaSet 1887 1887 ) 1888 xt "9 9800,74500,108000,75500"1888 xt "98400,74500,108000,75500" 1889 1889 st "alarm_refclk_too_low" 1890 1890 ju 2 … … 1898 1898 t "std_logic" 1899 1899 posAdd 0 1900 o 2 31900 o 28 1901 1901 suid 96,0 1902 1902 ) … … 1923 1923 va (VaSet 1924 1924 ) 1925 xt "105 500,79500,108000,80500"1925 xt "105300,79500,108000,80500" 1926 1926 st "amber" 1927 1927 ju 2 … … 1934 1934 n "amber" 1935 1935 t "std_logic" 1936 o 2 41936 o 29 1937 1937 suid 87,0 1938 1938 ) … … 1959 1959 va (VaSet 1960 1960 ) 1961 xt "9 9400,76500,108000,77500"1961 xt "98400,76500,108000,77500" 1962 1962 st "counter_result : (11:0)" 1963 1963 ju 2 … … 1971 1971 t "std_logic_vector" 1972 1972 b "(11 DOWNTO 0)" 1973 o 251973 o 30 1974 1974 suid 94,0 1975 1975 ) … … 2031 2031 va (VaSet 2032 2032 ) 2033 xt "82000,75500,8 7100,76500"2033 xt "82000,75500,88100,76500" 2034 2034 st "drs_refclk_in" 2035 2035 blo "82000,76300" … … 2041 2041 t "std_logic" 2042 2042 eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 2043 o 1 12043 o 12 2044 2044 suid 92,0 2045 2045 ) … … 2077 2077 n "green" 2078 2078 t "std_logic" 2079 o 3 02079 o 37 2080 2080 suid 86,0 2081 2081 ) … … 2102 2102 va (VaSet 2103 2103 ) 2104 xt "82000,76500,88 100,77500"2104 xt "82000,76500,88700,77500" 2105 2105 st "plllock_in : (3:0)" 2106 2106 blo "82000,77300" … … 2113 2113 b "(3 DOWNTO 0)" 2114 2114 eolc "-- high level, if dominowave is running and DRS PLL locked" 2115 o 1 22115 o 13 2116 2116 suid 93,0 2117 2117 ) … … 2138 2138 va (VaSet 2139 2139 ) 2140 xt "106 500,78500,108000,79500"2140 xt "106300,78500,108000,79500" 2141 2141 st "red" 2142 2142 ju 2 … … 2149 2149 n "red" 2150 2150 t "std_logic" 2151 o 332151 o 41 2152 2152 suid 88,0 2153 2153 ) … … 2174 2174 va (VaSet 2175 2175 ) 2176 xt "82000,71500,8 5700,72500"2176 xt "82000,71500,86200,72500" 2177 2177 st "SRIN_out" 2178 2178 blo "82000,72300" … … 2184 2184 n "SRIN_out" 2185 2185 t "std_logic" 2186 o 2 02186 o 25 2187 2187 suid 85,0 2188 2188 i "'0'" … … 2221 2221 n "ADC_CLK" 2222 2222 t "std_logic" 2223 o 1 52223 o 16 2224 2224 suid 97,0 2225 ) 2226 ) 2227 ) 2228 *55 (CptPort 2229 uid 2651,0 2230 ps "OnEdgeStrategy" 2231 shape (Triangle 2232 uid 2652,0 2233 ro 90 2234 va (VaSet 2235 vasetType 1 2236 fg "0,65535,0" 2237 ) 2238 xt "109000,80625,109750,81375" 2239 ) 2240 tg (CPTG 2241 uid 2653,0 2242 ps "CptPortTextPlaceStrategy" 2243 stg "RightVerticalLayoutStrategy" 2244 f (Text 2245 uid 2654,0 2246 va (VaSet 2247 ) 2248 xt "97600,80500,108000,81500" 2249 st "debug_data_ram_empty" 2250 ju 2 2251 blo "108000,81300" 2252 ) 2253 ) 2254 thePort (LogicalPort 2255 m 1 2256 decl (Decl 2257 n "debug_data_ram_empty" 2258 t "std_logic" 2259 o 32 2260 suid 104,0 2261 ) 2262 ) 2263 ) 2264 *56 (CptPort 2265 uid 2655,0 2266 ps "OnEdgeStrategy" 2267 shape (Triangle 2268 uid 2656,0 2269 ro 90 2270 va (VaSet 2271 vasetType 1 2272 fg "0,65535,0" 2273 ) 2274 xt "109000,81625,109750,82375" 2275 ) 2276 tg (CPTG 2277 uid 2657,0 2278 ps "CptPortTextPlaceStrategy" 2279 stg "RightVerticalLayoutStrategy" 2280 f (Text 2281 uid 2658,0 2282 va (VaSet 2283 ) 2284 xt "100500,81500,108000,82500" 2285 st "debug_data_valid" 2286 ju 2 2287 blo "108000,82300" 2288 ) 2289 ) 2290 thePort (LogicalPort 2291 m 1 2292 decl (Decl 2293 n "debug_data_valid" 2294 t "std_logic" 2295 o 33 2296 suid 105,0 2297 ) 2298 ) 2299 ) 2300 *57 (CptPort 2301 uid 2659,0 2302 ps "OnEdgeStrategy" 2303 shape (Triangle 2304 uid 2660,0 2305 ro 90 2306 va (VaSet 2307 vasetType 1 2308 fg "0,65535,0" 2309 ) 2310 xt "109000,82625,109750,83375" 2311 ) 2312 tg (CPTG 2313 uid 2661,0 2314 ps "CptPortTextPlaceStrategy" 2315 stg "RightVerticalLayoutStrategy" 2316 f (Text 2317 uid 2662,0 2318 va (VaSet 2319 ) 2320 xt "101100,82500,108000,83500" 2321 st "DG_state : (7:0)" 2322 ju 2 2323 blo "108000,83300" 2324 ) 2325 ) 2326 thePort (LogicalPort 2327 m 1 2328 decl (Decl 2329 n "DG_state" 2330 t "std_logic_vector" 2331 b "(7 downto 0)" 2332 prec "-- for debugging" 2333 preAdd 0 2334 o 19 2335 suid 108,0 2336 ) 2337 ) 2338 ) 2339 *58 (CptPort 2340 uid 2663,0 2341 ps "OnEdgeStrategy" 2342 shape (Triangle 2343 uid 2664,0 2344 ro 90 2345 va (VaSet 2346 vasetType 1 2347 fg "0,65535,0" 2348 ) 2349 xt "80250,77625,81000,78375" 2350 ) 2351 tg (CPTG 2352 uid 2665,0 2353 ps "CptPortTextPlaceStrategy" 2354 stg "VerticalLayoutStrategy" 2355 f (Text 2356 uid 2666,0 2357 va (VaSet 2358 ) 2359 xt "82000,77500,90100,78500" 2360 st "FTM_RS485_rx_d" 2361 blo "82000,78300" 2362 ) 2363 ) 2364 thePort (LogicalPort 2365 decl (Decl 2366 n "FTM_RS485_rx_d" 2367 t "std_logic" 2368 o 3 2369 suid 99,0 2370 ) 2371 ) 2372 ) 2373 *59 (CptPort 2374 uid 2667,0 2375 ps "OnEdgeStrategy" 2376 shape (Triangle 2377 uid 2668,0 2378 ro 90 2379 va (VaSet 2380 vasetType 1 2381 fg "0,65535,0" 2382 ) 2383 xt "109000,83625,109750,84375" 2384 ) 2385 tg (CPTG 2386 uid 2669,0 2387 ps "CptPortTextPlaceStrategy" 2388 stg "RightVerticalLayoutStrategy" 2389 f (Text 2390 uid 2670,0 2391 va (VaSet 2392 ) 2393 xt "99600,83500,108000,84500" 2394 st "FTM_RS485_rx_en" 2395 ju 2 2396 blo "108000,84300" 2397 ) 2398 ) 2399 thePort (LogicalPort 2400 m 1 2401 decl (Decl 2402 n "FTM_RS485_rx_en" 2403 t "std_logic" 2404 o 20 2405 suid 101,0 2406 ) 2407 ) 2408 ) 2409 *60 (CptPort 2410 uid 2671,0 2411 ps "OnEdgeStrategy" 2412 shape (Triangle 2413 uid 2672,0 2414 ro 90 2415 va (VaSet 2416 vasetType 1 2417 fg "0,65535,0" 2418 ) 2419 xt "109000,84625,109750,85375" 2420 ) 2421 tg (CPTG 2422 uid 2673,0 2423 ps "CptPortTextPlaceStrategy" 2424 stg "RightVerticalLayoutStrategy" 2425 f (Text 2426 uid 2674,0 2427 va (VaSet 2428 ) 2429 xt "99900,84500,108000,85500" 2430 st "FTM_RS485_tx_d" 2431 ju 2 2432 blo "108000,85300" 2433 ) 2434 ) 2435 thePort (LogicalPort 2436 m 1 2437 decl (Decl 2438 n "FTM_RS485_tx_d" 2439 t "std_logic" 2440 o 21 2441 suid 100,0 2442 ) 2443 ) 2444 ) 2445 *61 (CptPort 2446 uid 2675,0 2447 ps "OnEdgeStrategy" 2448 shape (Triangle 2449 uid 2676,0 2450 ro 90 2451 va (VaSet 2452 vasetType 1 2453 fg "0,65535,0" 2454 ) 2455 xt "109000,85625,109750,86375" 2456 ) 2457 tg (CPTG 2458 uid 2677,0 2459 ps "CptPortTextPlaceStrategy" 2460 stg "RightVerticalLayoutStrategy" 2461 f (Text 2462 uid 2678,0 2463 va (VaSet 2464 ) 2465 xt "99600,85500,108000,86500" 2466 st "FTM_RS485_tx_en" 2467 ju 2 2468 blo "108000,86300" 2469 ) 2470 ) 2471 thePort (LogicalPort 2472 m 1 2473 decl (Decl 2474 n "FTM_RS485_tx_en" 2475 t "std_logic" 2476 o 22 2477 suid 102,0 2478 ) 2479 ) 2480 ) 2481 *62 (CptPort 2482 uid 2679,0 2483 ps "OnEdgeStrategy" 2484 shape (Triangle 2485 uid 2680,0 2486 ro 90 2487 va (VaSet 2488 vasetType 1 2489 fg "0,65535,0" 2490 ) 2491 xt "109000,86625,109750,87375" 2492 ) 2493 tg (CPTG 2494 uid 2681,0 2495 ps "CptPortTextPlaceStrategy" 2496 stg "RightVerticalLayoutStrategy" 2497 f (Text 2498 uid 2682,0 2499 va (VaSet 2500 ) 2501 xt "96600,86500,108000,87500" 2502 st "mem_manager_state : (3:0)" 2503 ju 2 2504 blo "108000,87300" 2505 ) 2506 ) 2507 thePort (LogicalPort 2508 lang 2 2509 m 1 2510 decl (Decl 2511 n "mem_manager_state" 2512 t "std_logic_vector" 2513 b "(3 DOWNTO 0)" 2514 eolc "-- state is encoded here ... useful for debugging." 2515 posAdd 0 2516 o 39 2517 suid 106,0 2518 ) 2519 ) 2520 ) 2521 *63 (CptPort 2522 uid 2683,0 2523 ps "OnEdgeStrategy" 2524 shape (Triangle 2525 uid 2684,0 2526 ro 90 2527 va (VaSet 2528 vasetType 1 2529 fg "0,65535,0" 2530 ) 2531 xt "109000,87625,109750,88375" 2532 ) 2533 tg (CPTG 2534 uid 2685,0 2535 ps "CptPortTextPlaceStrategy" 2536 stg "RightVerticalLayoutStrategy" 2537 f (Text 2538 uid 2686,0 2539 va (VaSet 2540 ) 2541 xt "102400,87500,108000,88500" 2542 st "trigger_veto" 2543 ju 2 2544 blo "108000,88300" 2545 ) 2546 ) 2547 thePort (LogicalPort 2548 m 1 2549 decl (Decl 2550 n "trigger_veto" 2551 t "std_logic" 2552 o 44 2553 suid 98,0 2554 i "'1'" 2555 ) 2556 ) 2557 ) 2558 *64 (CptPort 2559 uid 2687,0 2560 ps "OnEdgeStrategy" 2561 shape (Triangle 2562 uid 2688,0 2563 ro 90 2564 va (VaSet 2565 vasetType 1 2566 fg "0,65535,0" 2567 ) 2568 xt "109000,88625,109750,89375" 2569 ) 2570 tg (CPTG 2571 uid 2689,0 2572 ps "CptPortTextPlaceStrategy" 2573 stg "RightVerticalLayoutStrategy" 2574 f (Text 2575 uid 2690,0 2576 va (VaSet 2577 ) 2578 xt "99600,88500,108000,89500" 2579 st "w5300_state : (7:0)" 2580 ju 2 2581 blo "108000,89300" 2582 ) 2583 ) 2584 thePort (LogicalPort 2585 m 1 2586 decl (Decl 2587 n "w5300_state" 2588 t "std_logic_vector" 2589 b "(7 DOWNTO 0)" 2590 eolc "-- state is encoded here ... useful for debugging." 2591 posAdd 0 2592 o 45 2593 suid 103,0 2225 2594 ) 2226 2595 ) … … 2235 2604 lineWidth 2 2236 2605 ) 2237 xt "81000,19000,109000, 81000"2606 xt "81000,19000,109000,90000" 2238 2607 ) 2239 2608 oxt "15000,-8000,43000,46000" … … 2243 2612 stg "VerticalLayoutStrategy" 2244 2613 textVec [ 2245 * 55 (Text2614 *65 (Text 2246 2615 uid 236,0 2247 2616 va (VaSet … … 2253 2622 tm "BdLibraryNameMgr" 2254 2623 ) 2255 * 56 (Text2624 *66 (Text 2256 2625 uid 237,0 2257 2626 va (VaSet … … 2263 2632 tm "CptNameMgr" 2264 2633 ) 2265 * 57 (Text2634 *67 (Text 2266 2635 uid 238,0 2267 2636 va (VaSet … … 2305 2674 fg "49152,49152,49152" 2306 2675 ) 2307 xt "81250, 79250,82750,80750"2676 xt "81250,88250,82750,89750" 2308 2677 iconName "BlockDiagram.png" 2309 2678 iconMaskName "BlockDiagram.msk" … … 2315 2684 archFileType "UNKNOWN" 2316 2685 ) 2317 * 58 (SaComponent2686 *68 (SaComponent 2318 2687 uid 274,0 2319 2688 optionalChildren [ 2320 * 59 (CptPort2689 *69 (CptPort 2321 2690 uid 266,0 2322 2691 ps "OnEdgeStrategy" … … 2354 2723 ) 2355 2724 ) 2356 * 60 (CptPort2725 *70 (CptPort 2357 2726 uid 270,0 2358 2727 ps "OnEdgeStrategy" … … 2407 2776 stg "VerticalLayoutStrategy" 2408 2777 textVec [ 2409 * 61 (Text2778 *71 (Text 2410 2779 uid 277,0 2411 2780 va (VaSet … … 2417 2786 tm "BdLibraryNameMgr" 2418 2787 ) 2419 * 62 (Text2788 *72 (Text 2420 2789 uid 278,0 2421 2790 va (VaSet … … 2427 2796 tm "CptNameMgr" 2428 2797 ) 2429 * 63 (Text2798 *73 (Text 2430 2799 uid 279,0 2431 2800 va (VaSet … … 2486 2855 archFileType "UNKNOWN" 2487 2856 ) 2488 * 64 (Net2857 *74 (Net 2489 2858 uid 284,0 2490 2859 decl (Decl … … 2501 2870 font "Courier New,8,0" 2502 2871 ) 2503 xt "-90000,41400,-68000,42200" 2504 st "SIGNAL clk : STD_LOGIC" 2505 ) 2506 ) 2507 *65 (Net 2872 xt "-90000,46200,-68000,47000" 2873 st "SIGNAL clk : STD_LOGIC 2874 " 2875 ) 2876 ) 2877 *75 (Net 2508 2878 uid 316,0 2509 2879 decl (Decl … … 2519 2889 font "Courier New,8,0" 2520 2890 ) 2521 xt "-90000,54200,-58500,55000" 2522 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)" 2523 ) 2524 ) 2525 *66 (Net 2891 xt "-90000,63000,-58500,63800" 2892 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0) 2893 " 2894 ) 2895 ) 2896 *76 (Net 2526 2897 uid 322,0 2527 2898 decl (Decl … … 2537 2908 font "Courier New,8,0" 2538 2909 ) 2539 xt "-90000,55800,-58000,56600" 2540 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)" 2541 ) 2542 ) 2543 *67 (Net 2910 xt "-90000,64600,-58000,65400" 2911 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0) 2912 " 2913 ) 2914 ) 2915 *77 (Net 2544 2916 uid 328,0 2545 2917 decl (Decl … … 2555 2927 font "Courier New,8,0" 2556 2928 ) 2557 xt "-90000,57400,-55000,58200" 2558 st "SIGNAL wiz_rd : std_logic := '1'" 2559 ) 2560 ) 2561 *68 (Net 2929 xt "-90000,66200,-55000,67000" 2930 st "SIGNAL wiz_rd : std_logic := '1' 2931 " 2932 ) 2933 ) 2934 *78 (Net 2562 2935 uid 334,0 2563 2936 decl (Decl … … 2573 2946 font "Courier New,8,0" 2574 2947 ) 2575 xt "-90000,59000,-55000,59800" 2576 st "SIGNAL wiz_wr : std_logic := '1'" 2577 ) 2578 ) 2579 *69 (SaComponent 2948 xt "-90000,67800,-55000,68600" 2949 st "SIGNAL wiz_wr : std_logic := '1' 2950 " 2951 ) 2952 ) 2953 *79 (SaComponent 2580 2954 uid 362,0 2581 2955 optionalChildren [ 2582 * 70 (CptPort2956 *80 (CptPort 2583 2957 uid 350,0 2584 2958 ps "OnEdgeStrategy" … … 2616 2990 ) 2617 2991 ) 2618 * 71 (CptPort2992 *81 (CptPort 2619 2993 uid 354,0 2620 2994 ps "OnEdgeStrategy" … … 2653 3027 ) 2654 3028 ) 2655 * 72 (CptPort3029 *82 (CptPort 2656 3030 uid 358,0 2657 3031 ps "OnEdgeStrategy" … … 2707 3081 stg "VerticalLayoutStrategy" 2708 3082 textVec [ 2709 * 73 (Text3083 *83 (Text 2710 3084 uid 365,0 2711 3085 va (VaSet … … 2717 3091 tm "BdLibraryNameMgr" 2718 3092 ) 2719 * 74 (Text3093 *84 (Text 2720 3094 uid 366,0 2721 3095 va (VaSet … … 2727 3101 tm "CptNameMgr" 2728 3102 ) 2729 * 75 (Text3103 *85 (Text 2730 3104 uid 367,0 2731 3105 va (VaSet … … 2781 3155 archFileType "UNKNOWN" 2782 3156 ) 2783 * 76 (Net3157 *86 (Net 2784 3158 uid 372,0 2785 3159 decl (Decl … … 2795 3169 font "Courier New,8,0" 2796 3170 ) 2797 xt "-90000,51800,-58500,52600" 2798 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2799 ) 2800 ) 2801 *77 (Net 3171 xt "-90000,59000,-58500,59800" 3172 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 3173 " 3174 ) 3175 ) 3176 *87 (Net 2802 3177 uid 378,0 2803 3178 decl (Decl … … 2812 3187 font "Courier New,8,0" 2813 3188 ) 2814 xt "-90000,51000,-68000,51800" 2815 st "SIGNAL sclk : std_logic" 2816 ) 2817 ) 2818 *78 (Net 3189 xt "-90000,58200,-68000,59000" 3190 st "SIGNAL sclk : std_logic 3191 " 3192 ) 3193 ) 3194 *88 (Net 2819 3195 uid 384,0 2820 3196 decl (Decl … … 2831 3207 font "Courier New,8,0" 2832 3208 ) 2833 xt "-90000,52600,-68000,53400" 2834 st "SIGNAL sio : std_logic" 2835 ) 2836 ) 2837 *79 (SaComponent 3209 xt "-90000,59800,-68000,60600" 3210 st "SIGNAL sio : std_logic 3211 " 3212 ) 3213 ) 3214 *89 (SaComponent 2838 3215 uid 414,0 2839 3216 optionalChildren [ 2840 * 80 (CptPort3217 *90 (CptPort 2841 3218 uid 410,0 2842 3219 ps "OnEdgeStrategy" … … 2893 3270 stg "VerticalLayoutStrategy" 2894 3271 textVec [ 2895 * 81 (Text3272 *91 (Text 2896 3273 uid 417,0 2897 3274 va (VaSet … … 2903 3280 tm "BdLibraryNameMgr" 2904 3281 ) 2905 * 82 (Text3282 *92 (Text 2906 3283 uid 418,0 2907 3284 va (VaSet … … 2913 3290 tm "CptNameMgr" 2914 3291 ) 2915 * 83 (Text3292 *93 (Text 2916 3293 uid 419,0 2917 3294 va (VaSet … … 2973 3350 archFileType "UNKNOWN" 2974 3351 ) 2975 * 84 (Net3352 *94 (Net 2976 3353 uid 424,0 2977 3354 decl (Decl … … 2988 3365 font "Courier New,8,0" 2989 3366 ) 2990 xt "-90000,53400,-68000,54200" 2991 st "SIGNAL trigger : std_logic" 2992 ) 2993 ) 2994 *85 (HdlText 3367 xt "-90000,60600,-68000,61400" 3368 st "SIGNAL trigger : std_logic 3369 " 3370 ) 3371 ) 3372 *95 (HdlText 2995 3373 uid 430,0 2996 3374 optionalChildren [ 2997 * 86 (EmbeddedText3375 *96 (EmbeddedText 2998 3376 uid 436,0 2999 3377 commentText (CommentText … … 3015 3393 va (VaSet 3016 3394 ) 3017 xt "50200,45200, 60200,48200"3395 xt "50200,45200,58200,49200" 3018 3396 st " 3019 3397 -- eb_ID 1: hard-wired IDs … … 3046 3424 stg "VerticalLayoutStrategy" 3047 3425 textVec [ 3048 * 87 (Text3426 *97 (Text 3049 3427 uid 433,0 3050 3428 va (VaSet … … 3056 3434 tm "HdlTextNameMgr" 3057 3435 ) 3058 * 88 (Text3436 *98 (Text 3059 3437 uid 434,0 3060 3438 va (VaSet … … 3082 3460 viewiconposition 0 3083 3461 ) 3084 * 89 (Net3462 *99 (Net 3085 3463 uid 440,0 3086 3464 decl (Decl … … 3098 3476 font "Courier New,8,0" 3099 3477 ) 3100 xt "-90000,40600,-58500,41400" 3101 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 3102 ) 3103 ) 3104 *90 (Net 3478 xt "-90000,45400,-58500,46200" 3479 st "SIGNAL board_id : std_logic_vector(3 downto 0) 3480 " 3481 ) 3482 ) 3483 *100 (Net 3105 3484 uid 448,0 3106 3485 decl (Decl … … 3116 3495 font "Courier New,8,0" 3117 3496 ) 3118 xt "-90000,43000,-58500,43800" 3119 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 3120 ) 3121 ) 3122 *91 (SaComponent 3497 xt "-90000,47800,-58500,48600" 3498 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 3499 " 3500 ) 3501 ) 3502 *101 (SaComponent 3123 3503 uid 508,0 3124 3504 optionalChildren [ 3125 * 92 (CptPort3505 *102 (CptPort 3126 3506 uid 489,0 3127 3507 ps "OnEdgeStrategy" … … 3159 3539 ) 3160 3540 ) 3161 * 93 (CptPort3541 *103 (CptPort 3162 3542 uid 493,0 3163 3543 ps "OnEdgeStrategy" … … 3198 3578 ) 3199 3579 ) 3200 * 94 (CptPort3580 *104 (CptPort 3201 3581 uid 497,0 3202 3582 ps "OnEdgeStrategy" … … 3236 3616 ) 3237 3617 ) 3238 * 95 (CptPort3618 *105 (CptPort 3239 3619 uid 501,0 3240 3620 ps "OnEdgeStrategy" … … 3290 3670 stg "VerticalLayoutStrategy" 3291 3671 textVec [ 3292 * 96 (Text3672 *106 (Text 3293 3673 uid 511,0 3294 3674 va (VaSet … … 3300 3680 tm "BdLibraryNameMgr" 3301 3681 ) 3302 * 97 (Text3682 *107 (Text 3303 3683 uid 512,0 3304 3684 va (VaSet … … 3310 3690 tm "CptNameMgr" 3311 3691 ) 3312 * 98 (Text3692 *108 (Text 3313 3693 uid 513,0 3314 3694 va (VaSet … … 3364 3744 archFileType "UNKNOWN" 3365 3745 ) 3366 * 99 (HdlText3746 *109 (HdlText 3367 3747 uid 518,0 3368 3748 optionalChildren [ 3369 *1 00 (EmbeddedText3749 *110 (EmbeddedText 3370 3750 uid 524,0 3371 3751 commentText (CommentText … … 3387 3767 va (VaSet 3388 3768 ) 3389 xt "50200,57200,6 2100,66200"3769 xt "50200,57200,60900,67200" 3390 3770 st " 3391 3771 -- eb_adc 2: ADC routing … … 3424 3804 stg "VerticalLayoutStrategy" 3425 3805 textVec [ 3426 *1 01 (Text3806 *111 (Text 3427 3807 uid 521,0 3428 3808 va (VaSet … … 3434 3814 tm "HdlTextNameMgr" 3435 3815 ) 3436 *1 02 (Text3816 *112 (Text 3437 3817 uid 522,0 3438 3818 va (VaSet … … 3460 3840 viewiconposition 0 3461 3841 ) 3462 *1 03 (Net3842 *113 (Net 3463 3843 uid 528,0 3464 3844 decl (Decl … … 3474 3854 font "Courier New,8,0" 3475 3855 ) 3476 xt "-90000,37400,-58500,38200" 3477 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" 3478 ) 3479 ) 3480 *104 (Net 3856 xt "-90000,42200,-58500,43000" 3857 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0) 3858 " 3859 ) 3860 ) 3861 *114 (Net 3481 3862 uid 536,0 3482 3863 decl (Decl … … 3491 3872 font "Courier New,8,0" 3492 3873 ) 3493 xt "-90000,35000,-63000,35800" 3494 st "SIGNAL adc_data_array : adc_data_array_type" 3495 ) 3496 ) 3497 *105 (Net 3874 xt "-90000,39800,-63000,40600" 3875 st "SIGNAL adc_data_array : adc_data_array_type 3876 " 3877 ) 3878 ) 3879 *115 (Net 3498 3880 uid 544,0 3499 3881 decl (Decl … … 3510 3892 font "Courier New,8,0" 3511 3893 ) 3512 xt "-90000,35800,-68000,36600" 3513 st "SIGNAL adc_oeb : std_logic" 3514 ) 3515 ) 3516 *106 (Net 3894 xt "-90000,40600,-68000,41400" 3895 st "SIGNAL adc_oeb : std_logic 3896 " 3897 ) 3898 ) 3899 *116 (Net 3517 3900 uid 560,0 3518 3901 decl (Decl … … 3529 3912 font "Courier New,8,0" 3530 3913 ) 3531 xt "-90000,36600,-68000,37400" 3532 st "SIGNAL adc_otr : STD_LOGIC" 3533 ) 3534 ) 3535 *107 (Net 3914 xt "-90000,41400,-68000,42200" 3915 st "SIGNAL adc_otr : STD_LOGIC 3916 " 3917 ) 3918 ) 3919 *117 (Net 3536 3920 uid 568,0 3537 3921 decl (Decl … … 3549 3933 font "Courier New,8,0" 3550 3934 ) 3551 xt "-90000,34200,-58000,35000" 3552 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" 3553 ) 3554 ) 3555 *108 (Net 3935 xt "-90000,39000,-58000,39800" 3936 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0) 3937 " 3938 ) 3939 ) 3940 *118 (Net 3556 3941 uid 767,0 3557 3942 decl (Decl … … 3567 3952 font "Courier New,8,0" 3568 3953 ) 3569 xt "-90000,58200,-55000,59000" 3570 st "SIGNAL wiz_reset : std_logic := '1'" 3571 ) 3572 ) 3573 *109 (Net 3954 xt "-90000,67000,-55000,67800" 3955 st "SIGNAL wiz_reset : std_logic := '1' 3956 " 3957 ) 3958 ) 3959 *119 (Net 3574 3960 uid 775,0 3575 3961 decl (Decl … … 3587 3973 font "Courier New,8,0" 3588 3974 ) 3589 xt "-90000,47800,-49000,48600" 3590 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 3591 ) 3592 ) 3593 *110 (Net 3975 xt "-90000,54200,-49000,55000" 3976 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 3977 " 3978 ) 3979 ) 3980 *120 (Net 3594 3981 uid 783,0 3595 3982 decl (Decl … … 3605 3992 font "Courier New,8,0" 3606 3993 ) 3607 xt "-90000,55000,-55000,55800" 3608 st "SIGNAL wiz_cs : std_logic := '1'" 3609 ) 3610 ) 3611 *111 (Net 3994 xt "-90000,63800,-55000,64600" 3995 st "SIGNAL wiz_cs : std_logic := '1' 3996 " 3997 ) 3998 ) 3999 *121 (Net 3612 4000 uid 791,0 3613 4001 decl (Decl … … 3622 4010 font "Courier New,8,0" 3623 4011 ) 3624 xt "-90000,56600,-68000,57400" 3625 st "SIGNAL wiz_int : std_logic" 3626 ) 3627 ) 3628 *112 (Net 4012 xt "-90000,65400,-68000,66200" 4013 st "SIGNAL wiz_int : std_logic 4014 " 4015 ) 4016 ) 4017 *122 (Net 3629 4018 uid 799,0 3630 4019 decl (Decl … … 3639 4028 font "Courier New,8,0" 3640 4029 ) 3641 xt "-90000,43800,-68000,44600" 3642 st "SIGNAL dac_cs : std_logic" 3643 ) 3644 ) 3645 *113 (Net 4030 xt "-90000,48600,-68000,49400" 4031 st "SIGNAL dac_cs : std_logic 4032 " 4033 ) 4034 ) 4035 *123 (Net 3646 4036 uid 807,0 3647 4037 decl (Decl … … 3657 4047 font "Courier New,8,0" 3658 4048 ) 3659 xt "-90000,48600,-55000,49400" 3660 st "SIGNAL mosi : std_logic := '0'" 3661 ) 3662 ) 3663 *114 (Net 4049 xt "-90000,55800,-55000,56600" 4050 st "SIGNAL mosi : std_logic := '0' 4051 " 4052 ) 4053 ) 4054 *124 (Net 3664 4055 uid 815,0 3665 4056 decl (Decl … … 3677 4068 font "Courier New,8,0" 3678 4069 ) 3679 xt "-90000,44600,-41500,45400" 3680 st "SIGNAL denable : std_logic := '0' -- default domino wave off" 3681 ) 3682 ) 3683 *115 (Net 4070 xt "-90000,51000,-41500,51800" 4071 st "SIGNAL denable : std_logic := '0' -- default domino wave off 4072 " 4073 ) 4074 ) 4075 *125 (Net 3684 4076 uid 823,0 3685 4077 decl (Decl … … 3695 4087 ) 3696 4088 xt "-90000,25400,-68000,26200" 3697 st "SIGNAL CLK_25_PS : std_logic" 3698 ) 3699 ) 3700 *116 (Net 4089 st "SIGNAL CLK_25_PS : std_logic 4090 " 4091 ) 4092 ) 4093 *126 (Net 3701 4094 uid 831,0 3702 4095 decl (Decl … … 3712 4105 ) 3713 4106 xt "-90000,26200,-68000,27000" 3714 st "SIGNAL CLK_50 : std_logic" 3715 ) 3716 ) 3717 *117 (Net 4107 st "SIGNAL CLK_50 : std_logic 4108 " 4109 ) 4110 ) 4111 *127 (Net 3718 4112 uid 839,0 3719 4113 decl (Decl … … 3730 4124 font "Courier New,8,0" 3731 4125 ) 3732 xt "-90000,45400,-49000,46200" 3733 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 3734 ) 3735 ) 3736 *118 (Net 4126 xt "-90000,51800,-49000,52600" 4127 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 4128 " 4129 ) 4130 ) 4131 *128 (Net 3737 4132 uid 847,0 3738 4133 decl (Decl … … 3748 4143 font "Courier New,8,0" 3749 4144 ) 3750 xt "-90000,46200,-55000,47000" 3751 st "SIGNAL drs_dwrite : std_logic := '1'" 3752 ) 3753 ) 3754 *119 (Net 4145 xt "-90000,52600,-55000,53400" 4146 st "SIGNAL drs_dwrite : std_logic := '1' 4147 " 4148 ) 4149 ) 4150 *129 (Net 3755 4151 uid 855,0 3756 4152 decl (Decl … … 3766 4162 font "Courier New,8,0" 3767 4163 ) 3768 xt "-90000,28600,-55000,29400" 3769 st "SIGNAL RSRLOAD : std_logic := '0'" 3770 ) 3771 ) 3772 *120 (Net 4164 xt "-90000,33400,-55000,34200" 4165 st "SIGNAL RSRLOAD : std_logic := '0' 4166 " 4167 ) 4168 ) 4169 *130 (Net 3773 4170 uid 863,0 3774 4171 decl (Decl … … 3784 4181 font "Courier New,8,0" 3785 4182 ) 3786 xt "-90000,29400,-55000,30200" 3787 st "SIGNAL SRCLK : std_logic := '0'" 3788 ) 3789 ) 3790 *121 (Net 4183 xt "-90000,34200,-55000,35000" 4184 st "SIGNAL SRCLK : std_logic := '0' 4185 " 4186 ) 4187 ) 4188 *131 (Net 3791 4189 uid 871,0 3792 4190 decl (Decl … … 3801 4199 font "Courier New,8,0" 3802 4200 ) 3803 xt "-90000,31000,-68000,31800" 3804 st "SIGNAL SROUT_in_0 : std_logic" 3805 ) 3806 ) 3807 *122 (Net 4201 xt "-90000,35800,-68000,36600" 4202 st "SIGNAL SROUT_in_0 : std_logic 4203 " 4204 ) 4205 ) 4206 *132 (Net 3808 4207 uid 879,0 3809 4208 decl (Decl … … 3818 4217 font "Courier New,8,0" 3819 4218 ) 3820 xt "-90000,31800,-68000,32600" 3821 st "SIGNAL SROUT_in_1 : std_logic" 3822 ) 3823 ) 3824 *123 (Net 4219 xt "-90000,36600,-68000,37400" 4220 st "SIGNAL SROUT_in_1 : std_logic 4221 " 4222 ) 4223 ) 4224 *133 (Net 3825 4225 uid 887,0 3826 4226 decl (Decl … … 3835 4235 font "Courier New,8,0" 3836 4236 ) 3837 xt "-90000,32600,-68000,33400" 3838 st "SIGNAL SROUT_in_2 : std_logic" 3839 ) 3840 ) 3841 *124 (Net 4237 xt "-90000,37400,-68000,38200" 4238 st "SIGNAL SROUT_in_2 : std_logic 4239 " 4240 ) 4241 ) 4242 *134 (Net 3842 4243 uid 895,0 3843 4244 decl (Decl … … 3852 4253 font "Courier New,8,0" 3853 4254 ) 3854 xt "-90000,33400,-68000,34200" 3855 st "SIGNAL SROUT_in_3 : std_logic" 3856 ) 3857 ) 3858 *125 (Net 4255 xt "-90000,38200,-68000,39000" 4256 st "SIGNAL SROUT_in_3 : std_logic 4257 " 4258 ) 4259 ) 4260 *135 (Net 3859 4261 uid 1435,0 3860 4262 decl (Decl … … 3870 4272 font "Courier New,8,0" 3871 4273 ) 3872 xt "-90000,30200,-55000,31000" 3873 st "SIGNAL SRIN_out : std_logic := '0'" 3874 ) 3875 ) 3876 *126 (Net 4274 xt "-90000,35000,-55000,35800" 4275 st "SIGNAL SRIN_out : std_logic := '0' 4276 " 4277 ) 4278 ) 4279 *136 (Net 3877 4280 uid 1443,0 3878 4281 decl (Decl … … 3887 4290 font "Courier New,8,0" 3888 4291 ) 3889 xt "-90000,39800,-68000,40600" 3890 st "SIGNAL amber : std_logic" 3891 ) 3892 ) 3893 *127 (Net 4292 xt "-90000,44600,-68000,45400" 4293 st "SIGNAL amber : std_logic 4294 " 4295 ) 4296 ) 4297 *137 (Net 3894 4298 uid 1451,0 3895 4299 decl (Decl … … 3904 4308 font "Courier New,8,0" 3905 4309 ) 3906 xt "-90000,50200,-68000,51000" 3907 st "SIGNAL red : std_logic" 3908 ) 3909 ) 3910 *128 (Net 4310 xt "-90000,57400,-68000,58200" 4311 st "SIGNAL red : std_logic 4312 " 4313 ) 4314 ) 4315 *138 (Net 3911 4316 uid 1459,0 3912 4317 decl (Decl … … 3921 4326 font "Courier New,8,0" 3922 4327 ) 3923 xt "-90000,47000,-68000,47800" 3924 st "SIGNAL green : std_logic" 3925 ) 3926 ) 3927 *129 (Net 4328 xt "-90000,53400,-68000,54200" 4329 st "SIGNAL green : std_logic 4330 " 4331 ) 4332 ) 4333 *139 (Net 3928 4334 uid 1467,0 3929 4335 decl (Decl … … 3939 4345 font "Courier New,8,0" 3940 4346 ) 3941 xt "-90000,42200,-58000,43000" 3942 st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0)" 3943 ) 3944 ) 3945 *130 (Net 4347 xt "-90000,47000,-58000,47800" 4348 st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) 4349 " 4350 ) 4351 ) 4352 *140 (Net 3946 4353 uid 1475,0 3947 4354 decl (Decl … … 3957 4364 font "Courier New,8,0" 3958 4365 ) 3959 xt "-90000,39000,-68000,39800" 3960 st "SIGNAL alarm_refclk_too_low : std_logic" 3961 ) 3962 ) 3963 *131 (Net 4366 xt "-90000,43800,-68000,44600" 4367 st "SIGNAL alarm_refclk_too_low : std_logic 4368 " 4369 ) 4370 ) 4371 *141 (Net 3964 4372 uid 1483,0 3965 4373 decl (Decl … … 3974 4382 font "Courier New,8,0" 3975 4383 ) 3976 xt "-90000,38200,-68000,39000" 3977 st "SIGNAL alarm_refclk_too_high : std_logic" 3978 ) 3979 ) 3980 *132 (HdlText 4384 xt "-90000,43000,-68000,43800" 4385 st "SIGNAL alarm_refclk_too_high : std_logic 4386 " 4387 ) 4388 ) 4389 *142 (HdlText 3981 4390 uid 1491,0 3982 4391 optionalChildren [ 3983 *1 33 (EmbeddedText4392 *143 (EmbeddedText 3984 4393 uid 1497,0 3985 4394 commentText (CommentText … … 4001 4410 va (VaSet 4002 4411 ) 4003 xt "27200,72200, 39400,77200"4412 xt "27200,72200,40200,77200" 4004 4413 st " 4005 4414 … … 4036 4445 stg "VerticalLayoutStrategy" 4037 4446 textVec [ 4038 *1 34 (Text4447 *144 (Text 4039 4448 uid 1494,0 4040 4449 va (VaSet … … 4046 4455 tm "HdlTextNameMgr" 4047 4456 ) 4048 *1 35 (Text4457 *145 (Text 4049 4458 uid 1495,0 4050 4459 va (VaSet … … 4072 4481 viewiconposition 0 4073 4482 ) 4074 *1 36 (Net4483 *146 (Net 4075 4484 uid 1501,0 4076 4485 decl (Decl … … 4086 4495 font "Courier New,8,0" 4087 4496 ) 4088 xt "-90000,27000,-58500,27800" 4089 st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0)" 4090 ) 4091 ) 4092 *137 (SaComponent 4497 xt "-90000,28600,-58500,29400" 4498 st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0) 4499 " 4500 ) 4501 ) 4502 *147 (SaComponent 4093 4503 uid 1509,0 4094 4504 optionalChildren [ 4095 *1 38 (CptPort4505 *148 (CptPort 4096 4506 uid 1519,0 4097 4507 ps "OnEdgeStrategy" … … 4129 4539 ) 4130 4540 ) 4131 *1 39 (CptPort4541 *149 (CptPort 4132 4542 uid 1523,0 4133 4543 ps "OnEdgeStrategy" … … 4182 4592 stg "VerticalLayoutStrategy" 4183 4593 textVec [ 4184 *1 40 (Text4594 *150 (Text 4185 4595 uid 1512,0 4186 4596 va (VaSet … … 4192 4602 tm "BdLibraryNameMgr" 4193 4603 ) 4194 *1 41 (Text4604 *151 (Text 4195 4605 uid 1513,0 4196 4606 va (VaSet … … 4202 4612 tm "CptNameMgr" 4203 4613 ) 4204 *1 42 (Text4614 *152 (Text 4205 4615 uid 1514,0 4206 4616 va (VaSet … … 4261 4671 archFileType "UNKNOWN" 4262 4672 ) 4263 *1 43 (Net4673 *153 (Net 4264 4674 uid 1559,0 4265 4675 decl (Decl … … 4276 4686 font "Courier New,8,0" 4277 4687 ) 4278 xt "-90000,49400,-29000,50200" 4279 st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" 4280 ) 4281 ) 4282 *144 (Net 4688 xt "-90000,56600,-29000,57400" 4689 st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked 4690 " 4691 ) 4692 ) 4693 *154 (Net 4283 4694 uid 1682,0 4284 4695 lang 2 … … 4295 4706 ) 4296 4707 xt "-90000,24600,-68000,25400" 4297 st "SIGNAL ADC_CLK : std_logic" 4298 ) 4299 ) 4300 *145 (Net 4708 st "SIGNAL ADC_CLK : std_logic 4709 " 4710 ) 4711 ) 4712 *155 (Net 4301 4713 uid 2001,0 4302 4714 decl (Decl … … 4312 4724 font "Courier New,8,0" 4313 4725 ) 4314 xt "-90000,27800,-55000,28600" 4315 st "SIGNAL REF_CLK : STD_LOGIC := '0'" 4316 ) 4317 ) 4318 *146 (SaComponent 4726 xt "-90000,32600,-55000,33400" 4727 st "SIGNAL REF_CLK : STD_LOGIC := '0' 4728 " 4729 ) 4730 ) 4731 *156 (SaComponent 4319 4732 uid 2336,0 4320 4733 optionalChildren [ 4321 *1 47 (CptPort4734 *157 (CptPort 4322 4735 uid 2315,0 4323 4736 ps "OnEdgeStrategy" … … 4339 4752 va (VaSet 4340 4753 ) 4341 xt "124000,20500,12 8500,21500"4754 xt "124000,20500,129100,21500" 4342 4755 st "addr : (9:0)" 4343 4756 blo "124000,21300" … … 4356 4769 ) 4357 4770 ) 4358 *1 48 (CptPort4771 *158 (CptPort 4359 4772 uid 2319,0 4360 4773 ps "OnEdgeStrategy" … … 4376 4789 va (VaSet 4377 4790 ) 4378 xt "124000,21500,12 8800,22500"4791 xt "124000,21500,129400,22500" 4379 4792 st "data : (15:0)" 4380 4793 blo "124000,22300" … … 4394 4807 ) 4395 4808 ) 4396 *1 49 (CptPort4809 *159 (CptPort 4397 4810 uid 2323,0 4398 4811 ps "OnEdgeStrategy" … … 4414 4827 va (VaSet 4415 4828 ) 4416 xt "124000,24500,125 100,25500"4829 xt "124000,24500,125300,25500" 4417 4830 st "rd" 4418 4831 blo "124000,25300" … … 4430 4843 ) 4431 4844 ) 4432 *1 50 (CptPort4845 *160 (CptPort 4433 4846 uid 2327,0 4434 4847 ps "OnEdgeStrategy" … … 4450 4863 va (VaSet 4451 4864 ) 4452 xt "124000,25500,125 200,26500"4865 xt "124000,25500,125400,26500" 4453 4866 st "wr" 4454 4867 blo "124000,26300" … … 4461 4874 preAdd 0 4462 4875 posAdd 0 4463 o 54876 o 6 4464 4877 suid 4,0 4465 4878 ) 4466 4879 ) 4467 4880 ) 4468 *1 51 (CptPort4881 *161 (CptPort 4469 4882 uid 2331,0 4470 4883 ps "OnEdgeStrategy" … … 4486 4899 va (VaSet 4487 4900 ) 4488 xt "124000,26500,125 200,27500"4901 xt "124000,26500,125400,27500" 4489 4902 st "int" 4490 4903 blo "124000,27300" 4491 )4492 t (Text4493 uid 2335,04494 va (VaSet4495 )4496 xt "124000,27500,125200,28500"4497 st "'1'"4498 blo "124000,28300"4499 4904 ) 4500 4905 ) … … 4507 4912 suid 5,0 4508 4913 i "'1'" 4914 ) 4915 ) 4916 ) 4917 *162 (CptPort 4918 uid 2548,0 4919 ps "OnEdgeStrategy" 4920 shape (Triangle 4921 uid 2549,0 4922 ro 90 4923 va (VaSet 4924 vasetType 1 4925 fg "0,65535,0" 4926 ) 4927 xt "122250,27625,123000,28375" 4928 ) 4929 tg (CPTG 4930 uid 2550,0 4931 ps "CptPortTextPlaceStrategy" 4932 stg "VerticalLayoutStrategy" 4933 f (Text 4934 uid 2551,0 4935 va (VaSet 4936 ) 4937 xt "124000,27500,125200,28500" 4938 st "cs" 4939 blo "124000,28300" 4940 ) 4941 ) 4942 thePort (LogicalPort 4943 decl (Decl 4944 n "cs" 4945 t "std_logic" 4946 o 5 4947 suid 6,0 4509 4948 ) 4510 4949 ) … … 4527 4966 stg "VerticalLayoutStrategy" 4528 4967 textVec [ 4529 *1 52(Text4968 *163 (Text 4530 4969 uid 2339,0 4531 4970 va (VaSet … … 4537 4976 tm "BdLibraryNameMgr" 4538 4977 ) 4539 *1 53(Text4978 *164 (Text 4540 4979 uid 2340,0 4541 4980 va (VaSet … … 4547 4986 tm "CptNameMgr" 4548 4987 ) 4549 *1 54(Text4988 *165 (Text 4550 4989 uid 2341,0 4551 4990 va (VaSet … … 4591 5030 viewiconposition 0 4592 5031 portVis (PortSigDisplay 4593 sIVOD 14594 5032 ) 4595 5033 archFileType "UNKNOWN" 4596 5034 ) 4597 *155 (Wire 5035 *166 (Net 5036 uid 2705,0 5037 decl (Decl 5038 n "debug_data_ram_empty" 5039 t "std_logic" 5040 o 45 5041 suid 53,0 5042 ) 5043 declText (MLText 5044 uid 2706,0 5045 va (VaSet 5046 font "Courier New,8,0" 5047 ) 5048 xt "-90000,49400,-68000,50200" 5049 st "SIGNAL debug_data_ram_empty : std_logic 5050 " 5051 ) 5052 ) 5053 *167 (Net 5054 uid 2713,0 5055 decl (Decl 5056 n "debug_data_valid" 5057 t "std_logic" 5058 o 46 5059 suid 54,0 5060 ) 5061 declText (MLText 5062 uid 2714,0 5063 va (VaSet 5064 font "Courier New,8,0" 5065 ) 5066 xt "-90000,50200,-68000,51000" 5067 st "SIGNAL debug_data_valid : std_logic 5068 " 5069 ) 5070 ) 5071 *168 (Net 5072 uid 2721,0 5073 decl (Decl 5074 n "DG_state" 5075 t "std_logic_vector" 5076 b "(7 downto 0)" 5077 prec "-- for debugging" 5078 preAdd 0 5079 o 47 5080 suid 55,0 5081 ) 5082 declText (MLText 5083 uid 2722,0 5084 va (VaSet 5085 font "Courier New,8,0" 5086 ) 5087 xt "-90000,27000,-58500,28600" 5088 st "-- for debugging 5089 SIGNAL DG_state : std_logic_vector(7 downto 0) 5090 " 5091 ) 5092 ) 5093 *169 (Net 5094 uid 2729,0 5095 decl (Decl 5096 n "FTM_RS485_rx_en" 5097 t "std_logic" 5098 o 48 5099 suid 56,0 5100 ) 5101 declText (MLText 5102 uid 2730,0 5103 va (VaSet 5104 font "Courier New,8,0" 5105 ) 5106 xt "-90000,30200,-68000,31000" 5107 st "SIGNAL FTM_RS485_rx_en : std_logic 5108 " 5109 ) 5110 ) 5111 *170 (Net 5112 uid 2737,0 5113 decl (Decl 5114 n "FTM_RS485_tx_d" 5115 t "std_logic" 5116 o 49 5117 suid 57,0 5118 ) 5119 declText (MLText 5120 uid 2738,0 5121 va (VaSet 5122 font "Courier New,8,0" 5123 ) 5124 xt "-90000,31000,-68000,31800" 5125 st "SIGNAL FTM_RS485_tx_d : std_logic 5126 " 5127 ) 5128 ) 5129 *171 (Net 5130 uid 2745,0 5131 decl (Decl 5132 n "FTM_RS485_tx_en" 5133 t "std_logic" 5134 o 50 5135 suid 58,0 5136 ) 5137 declText (MLText 5138 uid 2746,0 5139 va (VaSet 5140 font "Courier New,8,0" 5141 ) 5142 xt "-90000,31800,-68000,32600" 5143 st "SIGNAL FTM_RS485_tx_en : std_logic 5144 " 5145 ) 5146 ) 5147 *172 (Net 5148 uid 2753,0 5149 lang 2 5150 decl (Decl 5151 n "mem_manager_state" 5152 t "std_logic_vector" 5153 b "(3 DOWNTO 0)" 5154 eolc "-- state is encoded here ... useful for debugging." 5155 posAdd 0 5156 o 51 5157 suid 59,0 5158 ) 5159 declText (MLText 5160 uid 2754,0 5161 va (VaSet 5162 font "Courier New,8,0" 5163 ) 5164 xt "-90000,55000,-33000,55800" 5165 st "SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging. 5166 " 5167 ) 5168 ) 5169 *173 (Net 5170 uid 2761,0 5171 decl (Decl 5172 n "trigger_veto" 5173 t "std_logic" 5174 o 52 5175 suid 60,0 5176 i "'1'" 5177 ) 5178 declText (MLText 5179 uid 2762,0 5180 va (VaSet 5181 font "Courier New,8,0" 5182 ) 5183 xt "-90000,61400,-55000,62200" 5184 st "SIGNAL trigger_veto : std_logic := '1' 5185 " 5186 ) 5187 ) 5188 *174 (Net 5189 uid 2769,0 5190 decl (Decl 5191 n "w5300_state" 5192 t "std_logic_vector" 5193 b "(7 DOWNTO 0)" 5194 eolc "-- state is encoded here ... useful for debugging." 5195 posAdd 0 5196 o 53 5197 suid 61,0 5198 ) 5199 declText (MLText 5200 uid 2770,0 5201 va (VaSet 5202 font "Courier New,8,0" 5203 ) 5204 xt "-90000,62200,-33000,63000" 5205 st "SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging. 5206 " 5207 ) 5208 ) 5209 *175 (Net 5210 uid 2777,0 5211 decl (Decl 5212 n "FTM_RS485_rx_d" 5213 t "std_logic" 5214 o 54 5215 suid 62,0 5216 ) 5217 declText (MLText 5218 uid 2778,0 5219 va (VaSet 5220 font "Courier New,8,0" 5221 ) 5222 xt "-90000,29400,-68000,30200" 5223 st "SIGNAL FTM_RS485_rx_d : std_logic 5224 " 5225 ) 5226 ) 5227 *176 (Wire 4598 5228 uid 286,0 4599 5229 shape (OrthoPolyLine … … 4608 5238 ] 4609 5239 ) 4610 start & 595240 start &69 4611 5241 end &27 4612 5242 sat 32 … … 4629 5259 ) 4630 5260 ) 4631 on & 644632 ) 4633 *1 56(Wire5261 on &74 5262 ) 5263 *177 (Wire 4634 5264 uid 318,0 4635 5265 shape (OrthoPolyLine … … 4646 5276 ) 4647 5277 start &19 4648 end &1 475278 end &157 4649 5279 sat 32 4650 5280 eat 32 … … 4667 5297 ) 4668 5298 ) 4669 on & 654670 ) 4671 *1 57(Wire5299 on &75 5300 ) 5301 *178 (Wire 4672 5302 uid 324,0 4673 5303 shape (OrthoPolyLine … … 4684 5314 ) 4685 5315 start &20 4686 end &1 485316 end &158 4687 5317 sat 32 4688 5318 eat 32 … … 4705 5335 ) 4706 5336 ) 4707 on & 664708 ) 4709 *1 58(Wire5337 on &76 5338 ) 5339 *179 (Wire 4710 5340 uid 330,0 4711 5341 shape (OrthoPolyLine … … 4721 5351 ) 4722 5352 start &23 4723 end &1 495353 end &159 4724 5354 sat 32 4725 5355 eat 32 … … 4741 5371 ) 4742 5372 ) 4743 on & 674744 ) 4745 *1 59(Wire5373 on &77 5374 ) 5375 *180 (Wire 4746 5376 uid 336,0 4747 5377 shape (OrthoPolyLine … … 4757 5387 ) 4758 5388 start &22 4759 end &1 505389 end &160 4760 5390 sat 32 4761 5391 eat 32 … … 4777 5407 ) 4778 5408 ) 4779 on & 684780 ) 4781 *1 60(Wire5409 on &78 5410 ) 5411 *181 (Wire 4782 5412 uid 374,0 4783 5413 shape (OrthoPolyLine … … 4796 5426 ) 4797 5427 start &41 4798 end & 725428 end &82 4799 5429 sat 32 4800 5430 eat 32 … … 4817 5447 ) 4818 5448 ) 4819 on & 764820 ) 4821 *1 61(Wire5449 on &86 5450 ) 5451 *182 (Wire 4822 5452 uid 380,0 4823 5453 shape (OrthoPolyLine … … 4833 5463 ) 4834 5464 start &38 4835 end & 705465 end &80 4836 5466 sat 32 4837 5467 eat 32 … … 4853 5483 ) 4854 5484 ) 4855 on & 774856 ) 4857 *1 62(Wire5485 on &87 5486 ) 5487 *183 (Wire 4858 5488 uid 386,0 4859 5489 shape (OrthoPolyLine … … 4869 5499 ) 4870 5500 start &39 4871 end & 715501 end &81 4872 5502 sat 32 4873 5503 eat 32 … … 4889 5519 ) 4890 5520 ) 4891 on & 784892 ) 4893 *1 63(Wire5521 on &88 5522 ) 5523 *184 (Wire 4894 5524 uid 426,0 4895 5525 shape (OrthoPolyLine … … 4904 5534 ] 4905 5535 ) 4906 start & 805536 start &90 4907 5537 end &15 4908 5538 sat 32 … … 4924 5554 ) 4925 5555 ) 4926 on & 844927 ) 4928 *1 64(Wire5556 on &94 5557 ) 5558 *185 (Wire 4929 5559 uid 442,0 4930 5560 shape (OrthoPolyLine … … 4943 5573 ) 4944 5574 start &17 4945 end & 855575 end &95 4946 5576 sat 32 4947 5577 eat 2 … … 4964 5594 ) 4965 5595 ) 4966 on & 894967 ) 4968 *1 65(Wire5596 on &99 5597 ) 5598 *186 (Wire 4969 5599 uid 450,0 4970 5600 shape (OrthoPolyLine … … 4983 5613 ) 4984 5614 start &18 4985 end & 855615 end &95 4986 5616 sat 32 4987 5617 eat 2 … … 5004 5634 ) 5005 5635 ) 5006 on & 905007 ) 5008 *1 66(Wire5636 on &100 5637 ) 5638 *187 (Wire 5009 5639 uid 530,0 5010 5640 shape (OrthoPolyLine … … 5023 5653 ) 5024 5654 start &28 5025 end & 995655 end &109 5026 5656 sat 32 5027 5657 eat 2 … … 5044 5674 ) 5045 5675 ) 5046 on &1 035047 ) 5048 *1 67(Wire5676 on &113 5677 ) 5678 *188 (Wire 5049 5679 uid 538,0 5050 5680 shape (OrthoPolyLine … … 5063 5693 ) 5064 5694 start &29 5065 end & 995695 end &109 5066 5696 sat 32 5067 5697 eat 2 … … 5084 5714 ) 5085 5715 ) 5086 on &1 045087 ) 5088 *1 68(Wire5716 on &114 5717 ) 5718 *189 (Wire 5089 5719 uid 546,0 5090 5720 shape (OrthoPolyLine … … 5102 5732 ) 5103 5733 start &16 5104 end & 995734 end &109 5105 5735 sat 32 5106 5736 eat 1 … … 5122 5752 ) 5123 5753 ) 5124 on &1 055125 ) 5126 *1 69(Wire5754 on &115 5755 ) 5756 *190 (Wire 5127 5757 uid 554,0 5128 5758 shape (OrthoPolyLine … … 5137 5767 ] 5138 5768 ) 5139 start & 995140 end & 955769 start &109 5770 end &105 5141 5771 sat 2 5142 5772 eat 32 … … 5157 5787 ) 5158 5788 ) 5159 on &1 055160 ) 5161 *1 70(Wire5789 on &115 5790 ) 5791 *191 (Wire 5162 5792 uid 562,0 5163 5793 shape (OrthoPolyLine … … 5172 5802 ] 5173 5803 ) 5174 start & 945175 end & 995804 start &104 5805 end &109 5176 5806 sat 32 5177 5807 eat 1 … … 5192 5822 ) 5193 5823 ) 5194 on &1 065195 ) 5196 *1 71(Wire5824 on &116 5825 ) 5826 *192 (Wire 5197 5827 uid 570,0 5198 5828 shape (OrthoPolyLine … … 5208 5838 ] 5209 5839 ) 5210 start & 935211 end & 995840 start &103 5841 end &109 5212 5842 sat 32 5213 5843 eat 1 … … 5229 5859 ) 5230 5860 ) 5231 on &1 075232 ) 5233 *1 72(Wire5861 on &117 5862 ) 5863 *193 (Wire 5234 5864 uid 578,0 5235 5865 shape (OrthoPolyLine … … 5244 5874 ] 5245 5875 ) 5246 start & 925876 start &102 5247 5877 sat 32 5248 5878 eat 16 … … 5263 5893 ) 5264 5894 ) 5265 on &1 445266 ) 5267 *1 73(Wire5895 on &154 5896 ) 5897 *194 (Wire 5268 5898 uid 769,0 5269 5899 shape (OrthoPolyLine … … 5298 5928 ) 5299 5929 ) 5300 on &1 085301 ) 5302 *1 74(Wire5930 on &118 5931 ) 5932 *195 (Wire 5303 5933 uid 777,0 5304 5934 shape (OrthoPolyLine … … 5335 5965 ) 5336 5966 ) 5337 on &1 095338 ) 5339 *1 75(Wire5967 on &119 5968 ) 5969 *196 (Wire 5340 5970 uid 785,0 5341 5971 shape (OrthoPolyLine … … 5344 5974 vasetType 3 5345 5975 ) 5346 xt "109750,28000,1 16000,28000"5976 xt "109750,28000,122250,28000" 5347 5977 pts [ 5348 5978 "109750,28000" 5349 "1 16000,28000"5979 "122250,28000" 5350 5980 ] 5351 5981 ) 5352 5982 start &21 5983 end &162 5353 5984 sat 32 5354 eat 165985 eat 32 5355 5986 st 0 5356 5987 sf 1 … … 5370 6001 ) 5371 6002 ) 5372 on &1 105373 ) 5374 *1 76(Wire6003 on &120 6004 ) 6005 *197 (Wire 5375 6006 uid 793,0 5376 6007 shape (OrthoPolyLine … … 5385 6016 ] 5386 6017 ) 5387 start &1 516018 start &161 5388 6019 end &24 5389 6020 sat 32 … … 5406 6037 ) 5407 6038 ) 5408 on &1 115409 ) 5410 *1 77(Wire6039 on &121 6040 ) 6041 *198 (Wire 5411 6042 uid 801,0 5412 6043 shape (OrthoPolyLine … … 5441 6072 ) 5442 6073 ) 5443 on &1 125444 ) 5445 *1 78(Wire6074 on &122 6075 ) 6076 *199 (Wire 5446 6077 uid 809,0 5447 6078 shape (OrthoPolyLine … … 5476 6107 ) 5477 6108 ) 5478 on &1 135479 ) 5480 * 179(Wire6109 on &123 6110 ) 6111 *200 (Wire 5481 6112 uid 817,0 5482 6113 shape (OrthoPolyLine … … 5511 6142 ) 5512 6143 ) 5513 on &1 145514 ) 5515 * 180(Wire6144 on &124 6145 ) 6146 *201 (Wire 5516 6147 uid 825,0 5517 6148 shape (OrthoPolyLine … … 5546 6177 ) 5547 6178 ) 5548 on &1 155549 ) 5550 * 181(Wire6179 on &125 6180 ) 6181 *202 (Wire 5551 6182 uid 833,0 5552 6183 shape (OrthoPolyLine … … 5581 6212 ) 5582 6213 ) 5583 on &1 165584 ) 5585 * 182(Wire6214 on &126 6215 ) 6216 *203 (Wire 5586 6217 uid 841,0 5587 6218 shape (OrthoPolyLine … … 5618 6249 ) 5619 6250 ) 5620 on &1 175621 ) 5622 * 183(Wire6251 on &127 6252 ) 6253 *204 (Wire 5623 6254 uid 849,0 5624 6255 shape (OrthoPolyLine … … 5654 6285 ) 5655 6286 ) 5656 on &1 185657 ) 5658 * 184(Wire6287 on &128 6288 ) 6289 *205 (Wire 5659 6290 uid 857,0 5660 6291 shape (OrthoPolyLine … … 5689 6320 ) 5690 6321 ) 5691 on &1 195692 ) 5693 * 185(Wire6322 on &129 6323 ) 6324 *206 (Wire 5694 6325 uid 865,0 5695 6326 shape (OrthoPolyLine … … 5724 6355 ) 5725 6356 ) 5726 on &1 205727 ) 5728 * 186(Wire6357 on &130 6358 ) 6359 *207 (Wire 5729 6360 uid 873,0 5730 6361 shape (OrthoPolyLine … … 5759 6390 ) 5760 6391 ) 5761 on &1 215762 ) 5763 * 187(Wire6392 on &131 6393 ) 6394 *208 (Wire 5764 6395 uid 881,0 5765 6396 shape (OrthoPolyLine … … 5794 6425 ) 5795 6426 ) 5796 on &1 225797 ) 5798 * 188(Wire6427 on &132 6428 ) 6429 *209 (Wire 5799 6430 uid 889,0 5800 6431 shape (OrthoPolyLine … … 5829 6460 ) 5830 6461 ) 5831 on &1 235832 ) 5833 * 189(Wire6462 on &133 6463 ) 6464 *210 (Wire 5834 6465 uid 897,0 5835 6466 shape (OrthoPolyLine … … 5864 6495 ) 5865 6496 ) 5866 on &1 245867 ) 5868 * 190(Wire6497 on &134 6498 ) 6499 *211 (Wire 5869 6500 uid 1437,0 5870 6501 shape (OrthoPolyLine … … 5899 6530 ) 5900 6531 ) 5901 on &1 255902 ) 5903 * 191(Wire6532 on &135 6533 ) 6534 *212 (Wire 5904 6535 uid 1445,0 5905 6536 shape (OrthoPolyLine … … 5934 6565 ) 5935 6566 ) 5936 on &1 265937 ) 5938 * 192(Wire6567 on &136 6568 ) 6569 *213 (Wire 5939 6570 uid 1453,0 5940 6571 shape (OrthoPolyLine … … 5969 6600 ) 5970 6601 ) 5971 on &1 275972 ) 5973 * 193(Wire6602 on &137 6603 ) 6604 *214 (Wire 5974 6605 uid 1461,0 5975 6606 shape (OrthoPolyLine … … 6004 6635 ) 6005 6636 ) 6006 on &1 286007 ) 6008 * 194(Wire6637 on &138 6638 ) 6639 *215 (Wire 6009 6640 uid 1469,0 6010 6641 shape (OrthoPolyLine … … 6041 6672 ) 6042 6673 ) 6043 on &1 296044 ) 6045 * 195(Wire6674 on &139 6675 ) 6676 *216 (Wire 6046 6677 uid 1477,0 6047 6678 shape (OrthoPolyLine … … 6076 6707 ) 6077 6708 ) 6078 on &1 306079 ) 6080 * 196(Wire6709 on &140 6710 ) 6711 *217 (Wire 6081 6712 uid 1485,0 6082 6713 shape (OrthoPolyLine … … 6111 6742 ) 6112 6743 ) 6113 on &1 316114 ) 6115 * 197(Wire6744 on &141 6745 ) 6746 *218 (Wire 6116 6747 uid 1503,0 6117 6748 shape (OrthoPolyLine … … 6148 6779 ) 6149 6780 ) 6150 on &1 366151 ) 6152 * 198(Wire6781 on &146 6782 ) 6783 *219 (Wire 6153 6784 uid 1529,0 6154 6785 shape (OrthoPolyLine … … 6165 6796 ] 6166 6797 ) 6167 start &1 386798 start &148 6168 6799 end &49 6169 6800 sat 32 … … 6186 6817 ) 6187 6818 ) 6188 on &1 456189 ) 6190 * 199(Wire6819 on &155 6820 ) 6821 *220 (Wire 6191 6822 uid 1533,0 6192 6823 shape (OrthoPolyLine … … 6201 6832 ] 6202 6833 ) 6203 start &1 326834 start &142 6204 6835 sat 2 6205 6836 eat 16 … … 6221 6852 ) 6222 6853 ) 6223 on &1 366224 ) 6225 *2 00(Wire6854 on &146 6855 ) 6856 *221 (Wire 6226 6857 uid 1561,0 6227 6858 shape (OrthoPolyLine … … 6258 6889 ) 6259 6890 ) 6260 on &1 436261 ) 6262 *2 01(Wire6891 on &153 6892 ) 6893 *222 (Wire 6263 6894 uid 1567,0 6264 6895 shape (OrthoPolyLine … … 6273 6904 ] 6274 6905 ) 6275 start &1 326906 start &142 6276 6907 sat 2 6277 6908 eat 16 … … 6293 6924 ) 6294 6925 ) 6295 on &1 436296 ) 6297 *2 02(Wire6926 on &153 6927 ) 6928 *223 (Wire 6298 6929 uid 1684,0 6299 6930 shape (OrthoPolyLine … … 6328 6959 ) 6329 6960 ) 6330 on &144 6961 on &154 6962 ) 6963 *224 (Wire 6964 uid 2707,0 6965 shape (OrthoPolyLine 6966 uid 2708,0 6967 va (VaSet 6968 vasetType 3 6969 ) 6970 xt "109750,81000,122000,81000" 6971 pts [ 6972 "109750,81000" 6973 "122000,81000" 6974 ] 6975 ) 6976 start &55 6977 sat 32 6978 eat 16 6979 st 0 6980 sf 1 6981 si 0 6982 tg (WTG 6983 uid 2711,0 6984 ps "ConnStartEndStrategy" 6985 stg "STSignalDisplayStrategy" 6986 f (Text 6987 uid 2712,0 6988 va (VaSet 6989 ) 6990 xt "111000,80000,121400,81000" 6991 st "debug_data_ram_empty" 6992 blo "111000,80800" 6993 tm "WireNameMgr" 6994 ) 6995 ) 6996 on &166 6997 ) 6998 *225 (Wire 6999 uid 2715,0 7000 shape (OrthoPolyLine 7001 uid 2716,0 7002 va (VaSet 7003 vasetType 3 7004 ) 7005 xt "109750,82000,120000,82000" 7006 pts [ 7007 "109750,82000" 7008 "120000,82000" 7009 ] 7010 ) 7011 start &56 7012 sat 32 7013 eat 16 7014 st 0 7015 sf 1 7016 si 0 7017 tg (WTG 7018 uid 2719,0 7019 ps "ConnStartEndStrategy" 7020 stg "STSignalDisplayStrategy" 7021 f (Text 7022 uid 2720,0 7023 va (VaSet 7024 ) 7025 xt "111000,81000,118500,82000" 7026 st "debug_data_valid" 7027 blo "111000,81800" 7028 tm "WireNameMgr" 7029 ) 7030 ) 7031 on &167 7032 ) 7033 *226 (Wire 7034 uid 2723,0 7035 shape (OrthoPolyLine 7036 uid 2724,0 7037 va (VaSet 7038 vasetType 3 7039 lineWidth 2 7040 ) 7041 xt "109750,83000,119000,83000" 7042 pts [ 7043 "109750,83000" 7044 "119000,83000" 7045 ] 7046 ) 7047 start &57 7048 sat 32 7049 eat 16 7050 sty 1 7051 st 0 7052 sf 1 7053 si 0 7054 tg (WTG 7055 uid 2727,0 7056 ps "ConnStartEndStrategy" 7057 stg "STSignalDisplayStrategy" 7058 f (Text 7059 uid 2728,0 7060 va (VaSet 7061 ) 7062 xt "111000,82000,117900,83000" 7063 st "DG_state : (7:0)" 7064 blo "111000,82800" 7065 tm "WireNameMgr" 7066 ) 7067 ) 7068 on &168 7069 ) 7070 *227 (Wire 7071 uid 2731,0 7072 shape (OrthoPolyLine 7073 uid 2732,0 7074 va (VaSet 7075 vasetType 3 7076 ) 7077 xt "109750,84000,120000,84000" 7078 pts [ 7079 "109750,84000" 7080 "120000,84000" 7081 ] 7082 ) 7083 start &59 7084 sat 32 7085 eat 16 7086 st 0 7087 sf 1 7088 si 0 7089 tg (WTG 7090 uid 2735,0 7091 ps "ConnStartEndStrategy" 7092 stg "STSignalDisplayStrategy" 7093 f (Text 7094 uid 2736,0 7095 va (VaSet 7096 ) 7097 xt "111000,83000,119400,84000" 7098 st "FTM_RS485_rx_en" 7099 blo "111000,83800" 7100 tm "WireNameMgr" 7101 ) 7102 ) 7103 on &169 7104 ) 7105 *228 (Wire 7106 uid 2739,0 7107 shape (OrthoPolyLine 7108 uid 2740,0 7109 va (VaSet 7110 vasetType 3 7111 ) 7112 xt "109750,85000,120000,85000" 7113 pts [ 7114 "109750,85000" 7115 "120000,85000" 7116 ] 7117 ) 7118 start &60 7119 sat 32 7120 eat 16 7121 st 0 7122 sf 1 7123 si 0 7124 tg (WTG 7125 uid 2743,0 7126 ps "ConnStartEndStrategy" 7127 stg "STSignalDisplayStrategy" 7128 f (Text 7129 uid 2744,0 7130 va (VaSet 7131 ) 7132 xt "111000,84000,119100,85000" 7133 st "FTM_RS485_tx_d" 7134 blo "111000,84800" 7135 tm "WireNameMgr" 7136 ) 7137 ) 7138 on &170 7139 ) 7140 *229 (Wire 7141 uid 2747,0 7142 shape (OrthoPolyLine 7143 uid 2748,0 7144 va (VaSet 7145 vasetType 3 7146 ) 7147 xt "109750,86000,120000,86000" 7148 pts [ 7149 "109750,86000" 7150 "120000,86000" 7151 ] 7152 ) 7153 start &61 7154 sat 32 7155 eat 16 7156 st 0 7157 sf 1 7158 si 0 7159 tg (WTG 7160 uid 2751,0 7161 ps "ConnStartEndStrategy" 7162 stg "STSignalDisplayStrategy" 7163 f (Text 7164 uid 2752,0 7165 va (VaSet 7166 ) 7167 xt "111000,85000,119400,86000" 7168 st "FTM_RS485_tx_en" 7169 blo "111000,85800" 7170 tm "WireNameMgr" 7171 ) 7172 ) 7173 on &171 7174 ) 7175 *230 (Wire 7176 uid 2755,0 7177 shape (OrthoPolyLine 7178 uid 2756,0 7179 va (VaSet 7180 vasetType 3 7181 lineWidth 2 7182 ) 7183 xt "109750,87000,123000,87000" 7184 pts [ 7185 "109750,87000" 7186 "123000,87000" 7187 ] 7188 ) 7189 start &62 7190 sat 32 7191 eat 16 7192 sty 1 7193 st 0 7194 sf 1 7195 si 0 7196 tg (WTG 7197 uid 2759,0 7198 ps "ConnStartEndStrategy" 7199 stg "STSignalDisplayStrategy" 7200 f (Text 7201 uid 2760,0 7202 va (VaSet 7203 ) 7204 xt "111000,86000,122400,87000" 7205 st "mem_manager_state : (3:0)" 7206 blo "111000,86800" 7207 tm "WireNameMgr" 7208 ) 7209 ) 7210 on &172 7211 ) 7212 *231 (Wire 7213 uid 2763,0 7214 shape (OrthoPolyLine 7215 uid 2764,0 7216 va (VaSet 7217 vasetType 3 7218 ) 7219 xt "109750,88000,118000,88000" 7220 pts [ 7221 "109750,88000" 7222 "118000,88000" 7223 ] 7224 ) 7225 start &63 7226 sat 32 7227 eat 16 7228 st 0 7229 sf 1 7230 si 0 7231 tg (WTG 7232 uid 2767,0 7233 ps "ConnStartEndStrategy" 7234 stg "STSignalDisplayStrategy" 7235 f (Text 7236 uid 2768,0 7237 va (VaSet 7238 ) 7239 xt "111000,87000,116600,88000" 7240 st "trigger_veto" 7241 blo "111000,87800" 7242 tm "WireNameMgr" 7243 ) 7244 ) 7245 on &173 7246 ) 7247 *232 (Wire 7248 uid 2771,0 7249 shape (OrthoPolyLine 7250 uid 2772,0 7251 va (VaSet 7252 vasetType 3 7253 lineWidth 2 7254 ) 7255 xt "109750,89000,120000,89000" 7256 pts [ 7257 "109750,89000" 7258 "120000,89000" 7259 ] 7260 ) 7261 start &64 7262 sat 32 7263 eat 16 7264 sty 1 7265 st 0 7266 sf 1 7267 si 0 7268 tg (WTG 7269 uid 2775,0 7270 ps "ConnStartEndStrategy" 7271 stg "STSignalDisplayStrategy" 7272 f (Text 7273 uid 2776,0 7274 va (VaSet 7275 ) 7276 xt "111000,88000,119400,89000" 7277 st "w5300_state : (7:0)" 7278 blo "111000,88800" 7279 tm "WireNameMgr" 7280 ) 7281 ) 7282 on &174 7283 ) 7284 *233 (Wire 7285 uid 2779,0 7286 shape (OrthoPolyLine 7287 uid 2780,0 7288 va (VaSet 7289 vasetType 3 7290 ) 7291 xt "74000,78000,80250,82000" 7292 pts [ 7293 "74000,82000" 7294 "80250,78000" 7295 ] 7296 ) 7297 end &58 7298 sat 16 7299 eat 32 7300 st 0 7301 sf 1 7302 si 0 7303 tg (WTG 7304 uid 2783,0 7305 ps "ConnStartEndStrategy" 7306 stg "STSignalDisplayStrategy" 7307 f (Text 7308 uid 2784,0 7309 va (VaSet 7310 ) 7311 xt "73000,80000,81100,81000" 7312 st "FTM_RS485_rx_d" 7313 blo "73000,80800" 7314 tm "WireNameMgr" 7315 ) 7316 ) 7317 on &175 6331 7318 ) 6332 7319 ] … … 6342 7329 color "26368,26368,26368" 6343 7330 ) 6344 packageList *2 03(PackageList7331 packageList *234 (PackageList 6345 7332 uid 41,0 6346 7333 stg "VerticalLayoutStrategy" 6347 7334 textVec [ 6348 *2 04(Text7335 *235 (Text 6349 7336 uid 42,0 6350 7337 va (VaSet … … 6355 7342 blo "-87000,800" 6356 7343 ) 6357 *2 05(MLText7344 *236 (MLText 6358 7345 uid 43,0 6359 7346 va (VaSet 6360 7347 ) 6361 xt "-87000,1000,-7 2500,11000"7348 xt "-87000,1000,-70900,11000" 6362 7349 st "LIBRARY ieee; 6363 7350 USE ieee.std_logic_1164.all; … … 6378 7365 stg "VerticalLayoutStrategy" 6379 7366 textVec [ 6380 *2 06(Text7367 *237 (Text 6381 7368 uid 45,0 6382 7369 va (VaSet … … 6388 7375 blo "20000,800" 6389 7376 ) 6390 *2 07(Text7377 *238 (Text 6391 7378 uid 46,0 6392 7379 va (VaSet … … 6398 7385 blo "20000,1800" 6399 7386 ) 6400 *2 08(MLText7387 *239 (MLText 6401 7388 uid 47,0 6402 7389 va (VaSet 6403 7390 isHidden 1 6404 7391 ) 6405 xt "20000,2000,2 7500,4000"7392 xt "20000,2000,28200,4000" 6406 7393 st "`resetall 6407 7394 `timescale 1ns/10ps" 6408 7395 tm "BdCompilerDirectivesTextMgr" 6409 7396 ) 6410 *2 09(Text7397 *240 (Text 6411 7398 uid 48,0 6412 7399 va (VaSet … … 6418 7405 blo "20000,4800" 6419 7406 ) 6420 *2 10(MLText7407 *241 (MLText 6421 7408 uid 49,0 6422 7409 va (VaSet … … 6426 7413 tm "BdCompilerDirectivesTextMgr" 6427 7414 ) 6428 *2 11(Text7415 *242 (Text 6429 7416 uid 50,0 6430 7417 va (VaSet … … 6436 7423 blo "20000,5800" 6437 7424 ) 6438 *2 12(MLText7425 *243 (MLText 6439 7426 uid 51,0 6440 7427 va (VaSet … … 6447 7434 associable 1 6448 7435 ) 6449 windowSize "0, 0,1681,1030"6450 viewArea "6 0000,4200,152106,60144"7436 windowSize "0,20,1681,1050" 7437 viewArea "69198,38598,161304,96306" 6451 7438 cachedDiagramExtent "-92000,0,146000,98000" 6452 7439 pageSetupInfo (PageSetupInfo … … 6461 7448 hasePageBreakOrigin 1 6462 7449 pageBreakOrigin "-146000,0" 6463 lastUid 2 446,07450 lastUid 2804,0 6464 7451 defaultCommentText (CommentText 6465 7452 shape (Rectangle … … 6476 7463 fg "0,0,32768" 6477 7464 ) 6478 xt "200,200,2 000,1200"7465 xt "200,200,2400,1200" 6479 7466 st " 6480 7467 Text … … 6523 7510 stg "VerticalLayoutStrategy" 6524 7511 textVec [ 6525 *2 13(Text7512 *244 (Text 6526 7513 va (VaSet 6527 7514 font "Arial,8,1" … … 6532 7519 tm "BdLibraryNameMgr" 6533 7520 ) 6534 *2 14(Text7521 *245 (Text 6535 7522 va (VaSet 6536 7523 font "Arial,8,1" … … 6541 7528 tm "BlkNameMgr" 6542 7529 ) 6543 *2 15(Text7530 *246 (Text 6544 7531 va (VaSet 6545 7532 font "Arial,8,1" … … 6592 7579 stg "VerticalLayoutStrategy" 6593 7580 textVec [ 6594 *2 16(Text7581 *247 (Text 6595 7582 va (VaSet 6596 7583 font "Arial,8,1" … … 6600 7587 blo "550,4300" 6601 7588 ) 6602 *2 17(Text7589 *248 (Text 6603 7590 va (VaSet 6604 7591 font "Arial,8,1" … … 6608 7595 blo "550,5300" 6609 7596 ) 6610 *2 18(Text7597 *249 (Text 6611 7598 va (VaSet 6612 7599 font "Arial,8,1" … … 6657 7644 stg "VerticalLayoutStrategy" 6658 7645 textVec [ 6659 *2 19(Text7646 *250 (Text 6660 7647 va (VaSet 6661 7648 font "Arial,8,1" … … 6666 7653 tm "BdLibraryNameMgr" 6667 7654 ) 6668 *2 20(Text7655 *251 (Text 6669 7656 va (VaSet 6670 7657 font "Arial,8,1" … … 6675 7662 tm "CptNameMgr" 6676 7663 ) 6677 *2 21(Text7664 *252 (Text 6678 7665 va (VaSet 6679 7666 font "Arial,8,1" … … 6729 7716 stg "VerticalLayoutStrategy" 6730 7717 textVec [ 6731 *2 22(Text7718 *253 (Text 6732 7719 va (VaSet 6733 7720 font "Arial,8,1" … … 6737 7724 blo "500,4300" 6738 7725 ) 6739 *2 23(Text7726 *254 (Text 6740 7727 va (VaSet 6741 7728 font "Arial,8,1" … … 6745 7732 blo "500,5300" 6746 7733 ) 6747 *2 24(Text7734 *255 (Text 6748 7735 va (VaSet 6749 7736 font "Arial,8,1" … … 6790 7777 stg "VerticalLayoutStrategy" 6791 7778 textVec [ 6792 *2 25(Text7779 *256 (Text 6793 7780 va (VaSet 6794 7781 font "Arial,8,1" … … 6798 7785 blo "50,4300" 6799 7786 ) 6800 *2 26(Text7787 *257 (Text 6801 7788 va (VaSet 6802 7789 font "Arial,8,1" … … 6806 7793 blo "50,5300" 6807 7794 ) 6808 *2 27(Text7795 *258 (Text 6809 7796 va (VaSet 6810 7797 font "Arial,8,1" … … 6847 7834 stg "VerticalLayoutStrategy" 6848 7835 textVec [ 6849 *2 28(Text7836 *259 (Text 6850 7837 va (VaSet 6851 7838 font "Arial,8,1" … … 6856 7843 tm "HdlTextNameMgr" 6857 7844 ) 6858 *2 29(Text7845 *260 (Text 6859 7846 va (VaSet 6860 7847 font "Arial,8,1" … … 6894 7881 va (VaSet 6895 7882 ) 6896 xt "200,200,2 000,1200"7883 xt "200,200,2400,1200" 6897 7884 st " 6898 7885 Text … … 7232 8219 va (VaSet 7233 8220 ) 7234 xt "0,-1100,12 600,-100"8221 xt "0,-1100,12900,-100" 7235 8222 st "g0: FOR i IN 0 TO n GENERATE" 7236 8223 tm "FrameTitleTextMgr" … … 7259 8246 stg "VerticalLayoutStrategy" 7260 8247 textVec [ 7261 *2 30(Text8248 *261 (Text 7262 8249 va (VaSet 7263 8250 font "Arial,8,1" … … 7267 8254 blo "14100,20800" 7268 8255 ) 7269 *2 31(MLText8256 *262 (MLText 7270 8257 va (VaSet 7271 8258 ) … … 7292 8279 va (VaSet 7293 8280 ) 7294 xt "0,-1100,7 400,-100"8281 xt "0,-1100,7700,-100" 7295 8282 st "b0: BLOCK (guard)" 7296 8283 tm "FrameTitleTextMgr" … … 7319 8306 stg "VerticalLayoutStrategy" 7320 8307 textVec [ 7321 *2 32(Text8308 *263 (Text 7322 8309 va (VaSet 7323 8310 font "Arial,8,1" … … 7327 8314 blo "14100,20800" 7328 8315 ) 7329 *2 33(MLText8316 *264 (MLText 7330 8317 va (VaSet 7331 8318 ) … … 7471 8458 commonDM (CommonDM 7472 8459 ldm (LogicalDM 7473 suid 51,08460 suid 62,0 7474 8461 usingSuid 1 7475 emptyRow *2 34(LEmptyRow8462 emptyRow *265 (LEmptyRow 7476 8463 ) 7477 8464 uid 54,0 7478 8465 optionalChildren [ 7479 *2 35(RefLabelRowHdr7480 ) 7481 *2 36(TitleRowHdr7482 ) 7483 *2 37(FilterRowHdr7484 ) 7485 *2 38(RefLabelColHdr8466 *266 (RefLabelRowHdr 8467 ) 8468 *267 (TitleRowHdr 8469 ) 8470 *268 (FilterRowHdr 8471 ) 8472 *269 (RefLabelColHdr 7486 8473 tm "RefLabelColHdrMgr" 7487 8474 ) 7488 *2 39(RowExpandColHdr8475 *270 (RowExpandColHdr 7489 8476 tm "RowExpandColHdrMgr" 7490 8477 ) 7491 *2 40(GroupColHdr8478 *271 (GroupColHdr 7492 8479 tm "GroupColHdrMgr" 7493 8480 ) 7494 *2 41(NameColHdr8481 *272 (NameColHdr 7495 8482 tm "BlockDiagramNameColHdrMgr" 7496 8483 ) 7497 *2 42(ModeColHdr8484 *273 (ModeColHdr 7498 8485 tm "BlockDiagramModeColHdrMgr" 7499 8486 ) 7500 *2 43(TypeColHdr8487 *274 (TypeColHdr 7501 8488 tm "BlockDiagramTypeColHdrMgr" 7502 8489 ) 7503 *2 44(BoundsColHdr8490 *275 (BoundsColHdr 7504 8491 tm "BlockDiagramBoundsColHdrMgr" 7505 8492 ) 7506 *2 45(InitColHdr8493 *276 (InitColHdr 7507 8494 tm "BlockDiagramInitColHdrMgr" 7508 8495 ) 7509 *2 46(EolColHdr8496 *277 (EolColHdr 7510 8497 tm "BlockDiagramEolColHdrMgr" 7511 8498 ) 7512 *2 47(LeafLogPort8499 *278 (LeafLogPort 7513 8500 port (LogicalPort 7514 8501 m 4 … … 7524 8511 uid 340,0 7525 8512 ) 7526 *2 48(LeafLogPort8513 *279 (LeafLogPort 7527 8514 port (LogicalPort 7528 8515 m 4 … … 7537 8524 uid 342,0 7538 8525 ) 7539 *2 49(LeafLogPort8526 *280 (LeafLogPort 7540 8527 port (LogicalPort 7541 8528 m 4 … … 7550 8537 uid 344,0 7551 8538 ) 7552 *2 50(LeafLogPort8539 *281 (LeafLogPort 7553 8540 port (LogicalPort 7554 8541 m 4 … … 7563 8550 uid 346,0 7564 8551 ) 7565 *2 51(LeafLogPort8552 *282 (LeafLogPort 7566 8553 port (LogicalPort 7567 8554 m 4 … … 7576 8563 uid 348,0 7577 8564 ) 7578 *2 52(LeafLogPort8565 *283 (LeafLogPort 7579 8566 port (LogicalPort 7580 8567 m 4 … … 7589 8576 uid 404,0 7590 8577 ) 7591 *2 53(LeafLogPort8578 *284 (LeafLogPort 7592 8579 port (LogicalPort 7593 8580 m 4 … … 7601 8588 uid 406,0 7602 8589 ) 7603 *2 54(LeafLogPort8590 *285 (LeafLogPort 7604 8591 port (LogicalPort 7605 8592 m 4 … … 7615 8602 uid 408,0 7616 8603 ) 7617 *2 55(LeafLogPort8604 *286 (LeafLogPort 7618 8605 port (LogicalPort 7619 8606 m 4 … … 7629 8616 uid 456,0 7630 8617 ) 7631 *2 56(LeafLogPort8618 *287 (LeafLogPort 7632 8619 port (LogicalPort 7633 8620 m 4 … … 7644 8631 uid 458,0 7645 8632 ) 7646 *2 57(LeafLogPort8633 *288 (LeafLogPort 7647 8634 port (LogicalPort 7648 8635 m 4 … … 7657 8644 uid 460,0 7658 8645 ) 7659 *2 58(LeafLogPort8646 *289 (LeafLogPort 7660 8647 port (LogicalPort 7661 8648 m 4 … … 7670 8657 uid 584,0 7671 8658 ) 7672 *2 59(LeafLogPort8659 *290 (LeafLogPort 7673 8660 port (LogicalPort 7674 8661 m 4 … … 7682 8669 uid 586,0 7683 8670 ) 7684 *2 60(LeafLogPort8671 *291 (LeafLogPort 7685 8672 port (LogicalPort 7686 8673 m 4 … … 7696 8683 uid 588,0 7697 8684 ) 7698 *2 61(LeafLogPort8685 *292 (LeafLogPort 7699 8686 port (LogicalPort 7700 8687 m 4 … … 7710 8697 uid 590,0 7711 8698 ) 7712 *2 62(LeafLogPort8699 *293 (LeafLogPort 7713 8700 port (LogicalPort 7714 8701 m 4 … … 7725 8712 uid 592,0 7726 8713 ) 7727 *2 63(LeafLogPort8714 *294 (LeafLogPort 7728 8715 port (LogicalPort 7729 8716 m 4 … … 7738 8725 uid 903,0 7739 8726 ) 7740 *2 64(LeafLogPort8727 *295 (LeafLogPort 7741 8728 port (LogicalPort 7742 8729 m 4 … … 7753 8740 uid 905,0 7754 8741 ) 7755 *2 65(LeafLogPort8742 *296 (LeafLogPort 7756 8743 port (LogicalPort 7757 8744 m 4 … … 7766 8753 uid 907,0 7767 8754 ) 7768 *2 66(LeafLogPort8755 *297 (LeafLogPort 7769 8756 port (LogicalPort 7770 8757 m 4 … … 7778 8765 uid 909,0 7779 8766 ) 7780 *2 67(LeafLogPort8767 *298 (LeafLogPort 7781 8768 port (LogicalPort 7782 8769 m 4 … … 7790 8777 uid 911,0 7791 8778 ) 7792 *2 68(LeafLogPort8779 *299 (LeafLogPort 7793 8780 port (LogicalPort 7794 8781 m 4 … … 7803 8790 uid 913,0 7804 8791 ) 7805 * 269(LeafLogPort8792 *300 (LeafLogPort 7806 8793 port (LogicalPort 7807 8794 m 4 … … 7818 8805 uid 915,0 7819 8806 ) 7820 * 270(LeafLogPort8807 *301 (LeafLogPort 7821 8808 port (LogicalPort 7822 8809 m 4 … … 7830 8817 uid 917,0 7831 8818 ) 7832 * 271(LeafLogPort8819 *302 (LeafLogPort 7833 8820 port (LogicalPort 7834 8821 m 4 … … 7842 8829 uid 919,0 7843 8830 ) 7844 * 272(LeafLogPort8831 *303 (LeafLogPort 7845 8832 port (LogicalPort 7846 8833 m 4 … … 7856 8843 uid 921,0 7857 8844 ) 7858 * 273(LeafLogPort8845 *304 (LeafLogPort 7859 8846 port (LogicalPort 7860 8847 m 4 … … 7869 8856 uid 923,0 7870 8857 ) 7871 * 274(LeafLogPort8858 *305 (LeafLogPort 7872 8859 port (LogicalPort 7873 8860 m 4 … … 7882 8869 uid 925,0 7883 8870 ) 7884 * 275(LeafLogPort8871 *306 (LeafLogPort 7885 8872 port (LogicalPort 7886 8873 m 4 … … 7895 8882 uid 927,0 7896 8883 ) 7897 * 276(LeafLogPort8884 *307 (LeafLogPort 7898 8885 port (LogicalPort 7899 8886 m 4 … … 7907 8894 uid 929,0 7908 8895 ) 7909 * 277(LeafLogPort8896 *308 (LeafLogPort 7910 8897 port (LogicalPort 7911 8898 m 4 … … 7919 8906 uid 931,0 7920 8907 ) 7921 * 278(LeafLogPort8908 *309 (LeafLogPort 7922 8909 port (LogicalPort 7923 8910 m 4 … … 7931 8918 uid 933,0 7932 8919 ) 7933 * 279(LeafLogPort8920 *310 (LeafLogPort 7934 8921 port (LogicalPort 7935 8922 m 4 … … 7943 8930 uid 935,0 7944 8931 ) 7945 * 280(LeafLogPort8932 *311 (LeafLogPort 7946 8933 port (LogicalPort 7947 8934 m 4 … … 7956 8943 uid 1541,0 7957 8944 ) 7958 * 281(LeafLogPort8945 *312 (LeafLogPort 7959 8946 port (LogicalPort 7960 8947 m 4 … … 7968 8955 uid 1543,0 7969 8956 ) 7970 * 282(LeafLogPort8957 *313 (LeafLogPort 7971 8958 port (LogicalPort 7972 8959 m 4 … … 7980 8967 uid 1545,0 7981 8968 ) 7982 * 283(LeafLogPort8969 *314 (LeafLogPort 7983 8970 port (LogicalPort 7984 8971 m 4 … … 7992 8979 uid 1547,0 7993 8980 ) 7994 * 284(LeafLogPort8981 *315 (LeafLogPort 7995 8982 port (LogicalPort 7996 8983 m 4 … … 8005 8992 uid 1549,0 8006 8993 ) 8007 * 285(LeafLogPort8994 *316 (LeafLogPort 8008 8995 port (LogicalPort 8009 8996 m 4 … … 8018 9005 uid 1551,0 8019 9006 ) 8020 * 286(LeafLogPort9007 *317 (LeafLogPort 8021 9008 port (LogicalPort 8022 9009 m 4 … … 8030 9017 uid 1553,0 8031 9018 ) 8032 * 287(LeafLogPort9019 *318 (LeafLogPort 8033 9020 port (LogicalPort 8034 9021 m 4 … … 8043 9030 uid 1555,0 8044 9031 ) 8045 * 288(LeafLogPort9032 *319 (LeafLogPort 8046 9033 port (LogicalPort 8047 9034 m 4 … … 8057 9044 uid 1575,0 8058 9045 ) 8059 * 289(LeafLogPort9046 *320 (LeafLogPort 8060 9047 port (LogicalPort 8061 9048 lang 2 … … 8070 9057 uid 1690,0 8071 9058 ) 8072 * 290(LeafLogPort9059 *321 (LeafLogPort 8073 9060 port (LogicalPort 8074 9061 m 4 … … 8083 9070 uid 2003,0 8084 9071 ) 9072 *322 (LeafLogPort 9073 port (LogicalPort 9074 m 4 9075 decl (Decl 9076 n "debug_data_ram_empty" 9077 t "std_logic" 9078 o 45 9079 suid 53,0 9080 ) 9081 ) 9082 uid 2785,0 9083 ) 9084 *323 (LeafLogPort 9085 port (LogicalPort 9086 m 4 9087 decl (Decl 9088 n "debug_data_valid" 9089 t "std_logic" 9090 o 46 9091 suid 54,0 9092 ) 9093 ) 9094 uid 2787,0 9095 ) 9096 *324 (LeafLogPort 9097 port (LogicalPort 9098 m 4 9099 decl (Decl 9100 n "DG_state" 9101 t "std_logic_vector" 9102 b "(7 downto 0)" 9103 prec "-- for debugging" 9104 preAdd 0 9105 o 47 9106 suid 55,0 9107 ) 9108 ) 9109 uid 2789,0 9110 ) 9111 *325 (LeafLogPort 9112 port (LogicalPort 9113 m 4 9114 decl (Decl 9115 n "FTM_RS485_rx_en" 9116 t "std_logic" 9117 o 48 9118 suid 56,0 9119 ) 9120 ) 9121 uid 2791,0 9122 ) 9123 *326 (LeafLogPort 9124 port (LogicalPort 9125 m 4 9126 decl (Decl 9127 n "FTM_RS485_tx_d" 9128 t "std_logic" 9129 o 49 9130 suid 57,0 9131 ) 9132 ) 9133 uid 2793,0 9134 ) 9135 *327 (LeafLogPort 9136 port (LogicalPort 9137 m 4 9138 decl (Decl 9139 n "FTM_RS485_tx_en" 9140 t "std_logic" 9141 o 50 9142 suid 58,0 9143 ) 9144 ) 9145 uid 2795,0 9146 ) 9147 *328 (LeafLogPort 9148 port (LogicalPort 9149 lang 2 9150 m 4 9151 decl (Decl 9152 n "mem_manager_state" 9153 t "std_logic_vector" 9154 b "(3 DOWNTO 0)" 9155 eolc "-- state is encoded here ... useful for debugging." 9156 posAdd 0 9157 o 51 9158 suid 59,0 9159 ) 9160 ) 9161 uid 2797,0 9162 ) 9163 *329 (LeafLogPort 9164 port (LogicalPort 9165 m 4 9166 decl (Decl 9167 n "trigger_veto" 9168 t "std_logic" 9169 o 52 9170 suid 60,0 9171 i "'1'" 9172 ) 9173 ) 9174 uid 2799,0 9175 ) 9176 *330 (LeafLogPort 9177 port (LogicalPort 9178 m 4 9179 decl (Decl 9180 n "w5300_state" 9181 t "std_logic_vector" 9182 b "(7 DOWNTO 0)" 9183 eolc "-- state is encoded here ... useful for debugging." 9184 posAdd 0 9185 o 53 9186 suid 61,0 9187 ) 9188 ) 9189 uid 2801,0 9190 ) 9191 *331 (LeafLogPort 9192 port (LogicalPort 9193 m 4 9194 decl (Decl 9195 n "FTM_RS485_rx_d" 9196 t "std_logic" 9197 o 54 9198 suid 62,0 9199 ) 9200 ) 9201 uid 2803,0 9202 ) 8085 9203 ] 8086 9204 ) … … 8090 9208 uid 67,0 8091 9209 optionalChildren [ 8092 * 291(Sheet9210 *332 (Sheet 8093 9211 sheetRow (SheetRow 8094 9212 headerVa (MVa … … 8107 9225 font "Tahoma,10,0" 8108 9226 ) 8109 emptyMRCItem * 292(MRCItem8110 litem &2 348111 pos 449227 emptyMRCItem *333 (MRCItem 9228 litem &265 9229 pos 54 8112 9230 dimension 20 8113 9231 ) 8114 9232 uid 69,0 8115 9233 optionalChildren [ 8116 * 293(MRCItem8117 litem &2 359234 *334 (MRCItem 9235 litem &266 8118 9236 pos 0 8119 9237 dimension 20 8120 9238 uid 70,0 8121 9239 ) 8122 * 294(MRCItem8123 litem &2 369240 *335 (MRCItem 9241 litem &267 8124 9242 pos 1 8125 9243 dimension 23 8126 9244 uid 71,0 8127 9245 ) 8128 * 295(MRCItem8129 litem &2 379246 *336 (MRCItem 9247 litem &268 8130 9248 pos 2 8131 9249 hidden 1 … … 8133 9251 uid 72,0 8134 9252 ) 8135 * 296(MRCItem8136 litem &2 479253 *337 (MRCItem 9254 litem &278 8137 9255 pos 0 8138 9256 dimension 20 8139 9257 uid 341,0 8140 9258 ) 8141 * 297(MRCItem8142 litem &2 489259 *338 (MRCItem 9260 litem &279 8143 9261 pos 1 8144 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