Changeset 11155
- Timestamp:
- 06/23/11 21:25:53 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
r10957 r11155 51 51 dwrite_enable_in : in std_logic; 52 52 denable_enable_in : in std_logic; 53 busy_enable_in : in std_logic; 54 trigger_enable_in : in std_logic; 55 cont_trigger_en_in : in std_logic; 56 socket_send_mode_in : in std_logic; 57 53 58 54 59 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... … … 275 280 DCM_ready_status & -- 1 bit 276 281 SPI_SCLK_enable_status &-- 1 bit 277 conv_std_logic_vector(0,5) & 282 busy_enable_in & 283 trigger_enable_in & 284 cont_trigger_en_in & 285 socket_send_mode_in& 286 conv_std_logic_vector(0,1) & 278 287 PACKAGE_VERSION & PACKAGE_SUB_VERSION & 279 288 package_length_sig & … … 450 459 state_sig <= X"20"; 451 460 if (data_cntr < roi_max_int (channel_id)) then 452 data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & 453 adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & 454 adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & 455 adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; 461 data_out <= 462 --DRS chip 3 LOW BYTE 463 (adc_otr(3) xor adc_data_array(3)(7)) & 464 (adc_otr(3) xor adc_data_array(3)(6)) & 465 (adc_otr(3) xor adc_data_array(3)(5)) & 466 (adc_otr(3) xor adc_data_array(3)(4)) & 467 (adc_otr(3) xor adc_data_array(3)(3)) & 468 (adc_otr(3) xor adc_data_array(3)(2)) & 469 (adc_otr(3) xor adc_data_array(3)(1)) & 470 (adc_otr(3) xor adc_data_array(3)(0)) & 471 --DRS chip 3 HIGH BYTE 472 adc_data_array(3)(11) & 473 adc_data_array(3)(11) & 474 adc_data_array(3)(11) & 475 adc_data_array(3)(11) & 476 (adc_otr(3) xor adc_data_array(3)(11)) & 477 (adc_otr(3) xor adc_data_array(3)(10)) & 478 (adc_otr(3) xor adc_data_array(3)(9)) & 479 (adc_otr(3) xor adc_data_array(3)(8)) & 480 --DRS chip 2 LOW BYTE 481 (adc_otr(2) xor adc_data_array(2)(7)) & 482 (adc_otr(2) xor adc_data_array(2)(6)) & 483 (adc_otr(2) xor adc_data_array(2)(5)) & 484 (adc_otr(2) xor adc_data_array(2)(4)) & 485 (adc_otr(2) xor adc_data_array(2)(3)) & 486 (adc_otr(2) xor adc_data_array(2)(2)) & 487 (adc_otr(2) xor adc_data_array(2)(1)) & 488 (adc_otr(2) xor adc_data_array(2)(0)) & 489 --DRS chip 2 HIGH BYTE 490 adc_data_array(2)(11) & 491 adc_data_array(2)(11) & 492 adc_data_array(2)(11) & 493 adc_data_array(2)(11) & 494 (adc_otr(2) xor adc_data_array(2)(11)) & 495 (adc_otr(2) xor adc_data_array(2)(10)) & 496 (adc_otr(2) xor adc_data_array(2)(9)) & 497 (adc_otr(2) xor adc_data_array(2)(8)) & 498 --DRS chip 1 LOW BYTE 499 (adc_otr(1) xor adc_data_array(1)(7)) & 500 (adc_otr(1) xor adc_data_array(1)(6)) & 501 (adc_otr(1) xor adc_data_array(1)(5)) & 502 (adc_otr(1) xor adc_data_array(1)(4)) & 503 (adc_otr(1) xor adc_data_array(1)(3)) & 504 (adc_otr(1) xor adc_data_array(1)(2)) & 505 (adc_otr(1) xor adc_data_array(1)(1)) & 506 (adc_otr(1) xor adc_data_array(1)(0)) & 507 --DRS chip 1 HIGH BYTE 508 adc_data_array(1)(11) & 509 adc_data_array(1)(11) & 510 adc_data_array(1)(11) & 511 adc_data_array(1)(11) & 512 (adc_otr(1) xor adc_data_array(1)(11)) & 513 (adc_otr(1) xor adc_data_array(1)(10)) & 514 (adc_otr(1) xor adc_data_array(1)(9)) & 515 (adc_otr(1) xor adc_data_array(1)(8)) & 516 --DRS chip 0 LOW BYTE 517 (adc_otr(0) xor adc_data_array(0)(7)) & 518 (adc_otr(0) xor adc_data_array(0)(6)) & 519 (adc_otr(0) xor adc_data_array(0)(5)) & 520 (adc_otr(0) xor adc_data_array(0)(4)) & 521 (adc_otr(0) xor adc_data_array(0)(3)) & 522 (adc_otr(0) xor adc_data_array(0)(2)) & 523 (adc_otr(0) xor adc_data_array(0)(1)) & 524 (adc_otr(0) xor adc_data_array(0)(0)) & 525 --DRS chip 0 HIGH BYTE 526 adc_data_array(0)(11) & 527 adc_data_array(0)(11) & 528 adc_data_array(0)(11) & 529 adc_data_array(0)(11) & 530 (adc_otr(0) xor adc_data_array(0)(11)) & 531 (adc_otr(0) xor adc_data_array(0)(10)) & 532 (adc_otr(0) xor adc_data_array(0)(9)) & 533 (adc_otr(0) xor adc_data_array(0)(8)) ; 534 535 --adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & 536 --adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & 537 --adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & 538 --adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; 456 539 457 540 addr_cntr <= addr_cntr + 1; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf
r10957 r11155 255 255 # LEDs 256 256 ####################################################### 257 NET AMBER_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; #schematic: LED_3 D3 AMBER258 NET GREEN_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN257 NET AMBER_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; 258 NET GREEN_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; 259 259 NET RED_LED LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2 RED 260 260 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r11122 r11155 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 21:52:14 22.06.20115 -- at - 13:24:39 23.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 76 76 -- Created: 77 77 -- by - daqct3.UNKNOWN (IHP110) 78 -- at - 21:52:15 22.06.201178 -- at - 13:24:39 23.06.2011 79 79 -- 80 80 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r11122 r11155 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 2";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"05"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 174 174 constant CMD_TRIGGER_S : std_logic_vector := X"20"; 175 175 176 constant CMD_BUSY_ON : std_logic_vector := X"24"; 177 constant CMD_BUSY_OFF : std_logic_vector := X"25"; 178 179 176 180 177 181 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r11122 r11155 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 21:52:13 22.06.20115 -- at - 13:24:37 23.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 83 83 -- Created: 84 84 -- by - daqct3.UNKNOWN (IHP110) 85 -- at - 21:52:14 22.06.201185 -- at - 13:24:38 23.06.2011 86 86 -- 87 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 126 126 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); 127 127 SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); 128 SIGNAL busy_enable : std_logic := '1'; 128 129 SIGNAL c_trigger_enable : std_logic := '0'; 129 130 SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); … … 148 149 SIGNAL dout5 : std_logic; 149 150 SIGNAL dout6 : std_logic; 151 SIGNAL dout7 : std_logic; 150 152 SIGNAL drs_clk_en : std_logic := '0'; 151 153 SIGNAL drs_read_s_cell : std_logic := '0'; … … 325 327 dwrite_enable_in : IN std_logic ; 326 328 denable_enable_in : IN std_logic ; 329 busy_enable_in : IN std_logic ; 327 330 -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... 328 331 -- during EVT header wrinting, this field is left out ... and only written into event header, … … 557 560 sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. 558 561 srclk_enable : OUT std_logic := '1'; -- default SRCLK on. 562 busy_enable : OUT std_logic := '1'; 559 563 ------------------------------------------------------------------------------ 560 564 … … 621 625 drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable; 622 626 627 -- ModuleWare code(v1.9) for instance 'and_6' of 'and' 628 trig_veto <= busy_enable AND dout7; 629 623 630 -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment' 624 631 denable <= denable_sig; … … 646 653 647 654 -- ModuleWare code(v1.9) for instance 'or_2' of 'or' 648 trig_veto<= trigger_veto1 OR dout5;655 dout7 <= trigger_veto1 OR dout5; 649 656 650 657 -- ModuleWare code(v1.9) for instance 'or_5' of 'or' … … 764 771 dwrite_enable_in => dwrite_enable_w5300, 765 772 denable_enable_in => denable_sig, 773 busy_enable_in => busy_enable, 766 774 FTM_RS485_ready => FTM_RS485_ready, 767 775 FTM_trigger_info => rs465_data, … … 966 974 sclk_enable => sclk_enable, 967 975 srclk_enable => srclk_enable, 976 busy_enable => busy_enable, 968 977 ps_direction => ps_direction, 969 978 ps_do_phase_shift => ps_do_phase_shift, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd
r11122 r11155 79 79 80 80 --red <= not red_loc; 81 red <= trigger_veto;81 red <= not trigger_veto; 82 82 83 83 additional_flasher_out <= flasher; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r11122 r11155 79 79 sclk_enable : out std_logic := '1'; -- default DWRITE HIGH. 80 80 srclk_enable : out std_logic := '1'; -- default SRCLK on. 81 busy_enable : out std_logic := '1'; 82 socket_send_mode_out : out std_logic; 81 83 ------------------------------------------------------------------------------ 82 84 … … 343 345 trigger_enable <= trigger_enable_sig; 344 346 347 socket_send_mode_out <= socket_send_mode; 345 348 346 349 w5300_proc : process (clk) … … 439 442 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. 440 443 when IR2_05 => 441 state_sig <= X"F7";444 state_sig <= X"F7"; 442 445 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 443 446 --par_data <= X"0010"; -- CLOSE … … 448 451 if (socket_cnt = 7) then 449 452 socket_cnt <= "000"; 450 state_interrupt_2 <= IR2_06; 453 --state_interrupt_2 <= IR2_06; 454 state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; 451 455 else 452 456 state_interrupt_2 <= IR2_01;
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