- Timestamp:
- 07/06/10 09:25:02 (14 years ago)
- Location:
- FPGA/FTU/test_firmware/FTU_test2
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r237 r238 108 108 109 109 -- FSM for dac control: second process 110 FSM_logic: process(state )110 FSM_logic: process(state, config_ready_sig) 111 111 begin 112 112 next_state <= state; -
FPGA/FTU/test_firmware/FTU_test2/FTU_test2_spi_distributor.vhd
r236 r238 35 35 36 36 signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; 37 signal dac_id_cnt : integer range 0 to 7:= 0;37 signal dac_id_cnt : integer range 0 to 4 := 0; 38 38 39 39 BEGIN … … 67 67 if (dac_config_ready = '1') then 68 68 dac_config_start <= '0'; 69 if (dac_id_cnt < 7) then 70 if (dac_id_cnt = 3) then 71 dac_id_cnt <= 7; 72 else 73 dac_id_cnt <= dac_id_cnt + 1; 74 end if; 69 if (dac_id_cnt < 4) then 70 dac_id_cnt <= dac_id_cnt + 1; 75 71 dac_config_start <= '1'; 76 72 spi_distr_state <= CONFIG_DAC;
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