- Timestamp:
- 07/06/10 09:25:02 (14 years ago)
- File:
-
- 1 edited
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FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r237 r238 108 108 109 109 -- FSM for dac control: second process 110 FSM_logic: process(state )110 FSM_logic: process(state, config_ready_sig) 111 111 begin 112 112 next_state <= state;
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