- Timestamp:
- 07/05/10 16:49:07 (14 years ago)
- File:
-
- 1 edited
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FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd
r236 r237 34 34 clk : IN STD_LOGIC; 35 35 reset : IN STD_LOGIC; 36 miso : IN STD_LOGIC;37 36 clr : OUT STD_LOGIC; 38 37 mosi : OUT STD_LOGIC; … … 70 69 signal reset_sig : std_logic; 71 70 72 signal miso_sig : std_logic;73 71 signal clr_sig : std_logic; 74 72 signal mosi_sig : std_logic := '0'; … … 95 93 reset_sig <= reset; 96 94 clk_sig <= clk; 97 miso_sig <= miso;98 95 mosi <= mosi_sig; 99 96 sck <= serial_clock_sig; … … 139 136 mosi => mosi_sig, 140 137 sclk => serial_clock_sig, 141 miso => miso_sig138 miso => open 142 139 ); 143 140
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