Ignore:
Timestamp:
07/16/10 16:25:44 (14 years ago)
Author:
dneise
Message:
DRS addresses may not be set via
sa 44 0 .. 31
Location:
FPGA/FAD/stable/FACT_FAD
Files:
21 edited

Legend:

Unmodified
Added
Removed

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD.hdp

    r246 r252  
     1[DesignChecker]
     2FACT_FAD_lib = $HDS_PROJECT_DIR\FACT_FAD_lib\designcheck
    13[ModelSim]
    24FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
    35FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
    4 secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip
     6secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    57simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    68unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
    … …  
    810XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
    911[QuestaSim]
    10 secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip
     12secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
    1113simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
    1214unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd

    r246 r252  
    3636      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
    3737      dac_array         : OUT    dac_array_type;
    38       roi_array         : OUT    roi_array_type
     38      roi_array         : OUT    roi_array_type;
     39      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
     40      drs_address_mode  : OUT    std_logic
    3941   );
    4042
    … …  
    5355  signal int_dac_array : dac_array_type := DEFAULT_DAC;
    5456  signal int_roi_array : roi_array_type := DEFAULT_ROI;
     57  signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR;
     58  signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE;
    5559
    5660BEGIN
    … …  
    6670       
    6771        when CTRL_INIT =>
     72          -- WRITES DEFAULT VALUES IN config ram
    6873          addr_cntr <= addr_cntr + 1;
    6974          ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH);
    … …  
    7681          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then
    7782            ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16);
     83          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
     84            ram_data_in <=  "0000" & "0000"
     85                            & "000" & conv_std_logic_vector(int_drs_address_mode, 1)
     86                            & int_drs_address;
    7887          else
    7988            ram_write_en <= "0";
    … …  
    8291     
    8392        when CTRL_IDLE =>
     93          --
    8494          addr_cntr <= 0;
    8595          ram_write_en <= "0";
    … …  
    119129            dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out);
    120130            ctrl_state <= CTRL_LOAD_ADDR;
    121           else
     131          elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then
     132             drs_address <= ram_data_out(3 downto 0);
     133             drs_address_mode <= ram_data_out(4);
     134             ctrl_state <= CTRL_LOAD_ADDR;
     135          else
    122136            addr_cntr <= 0;
    123137            config_started <= '0';

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd

    r246 r252  
    22--
    33-- Created:
    4 --          by - Benjamin Krumm.UNKNOWN (EEPC8)
    5 --          at - 12:04:03 23.06.2010
     4--          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
     5--          at - 14:46:37 12.07.2010
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2525      config_started    : OUT    std_logic  := '0';
    2626      dac_array         : OUT    dac_array_type;
     27      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
     28      drs_address_mode  : OUT    std_logic;
    2729      roi_array         : OUT    roi_array_type;
    2830      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
    … …  
    3739--
    3840-- Created:
    39 --          by - Benjamin Krumm.UNKNOWN (EEPC8)
    40 --          at - 12:04:03 23.06.2010
     41--          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
     42--          at - 14:46:37 12.07.2010
    4143--
    4244-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    9395      ram_write_en      : OUT    std_logic_vector (0 DOWNTO 0);
    9496      dac_array         : OUT    dac_array_type ;
    95       roi_array         : OUT    roi_array_type
     97      roi_array         : OUT    roi_array_type ;
     98      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
     99      drs_address_mode  : OUT    std_logic
    96100   );
    97101   END COMPONENT;
    … …  
    137141         ram_write_en      => ram_wren,
    138142         dac_array         => dac_array,
    139          roi_array         => roi_array
     143         roi_array         => roi_array,
     144         drs_address       => drs_address,
     145         drs_address_mode  => drs_address_mode
    140146      );
    141147

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf

    r246 r252  
    1010
    1111#Test Trigger input on 'Testpoint near W5300'
    12 #NET W_T<3> LOC  = R19 | IOSTANDARD=LVCMOS33;           #ok
    13 NET TEST_TRG LOC  = R19 | IOSTANDARD=LVCMOS33 | PULLUP;
     12#NET _TW<3> LOC  = R19 | IOSTANDARD=LVCMOS33;           #ok
     13NET TEST_TRG LOC  = R19 | IOSTANDARD=LVCMOS33;
    1414
    1515
    … …  
    229229NET A1_T<2> LOC  = AC12 | IOSTANDARD=LVCMOS33;          #ok
    230230NET A1_T<3> LOC  = AC14 | IOSTANDARD=LVCMOS33;          #ok
    231 #NET A1_T<4> LOC  = AC15 | IOSTANDARD=LVCMOS33;         #ok
     231NET A1_T<4> LOC  = AC15 | IOSTANDARD=LVCMOS33;          #ok
    232232#NET A1_T<5> LOC  = AB16 | IOSTANDARD=LVCMOS33;                 #ok
    233233#NET A1_T<6> LOC  = AC16 | IOSTANDARD=LVCMOS33;         #ok

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r246 r252  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    5 --          at - 12:42:19 02.07.2010
     4--          by - dneise.UNKNOWN (E5B-LABOR6)
     5--          at - 15:25:14 14.07.2010
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2727      W_INT      : IN     std_logic;
    2828      X_50M      : IN     STD_LOGIC;
    29       A1_T       : OUT    std_logic_vector (3 DOWNTO 0);
     29      A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0');
    3030      A_CLK      : OUT    std_logic_vector (3 DOWNTO 0);
    3131      D0_SRCLK   : OUT    STD_LOGIC;
    … …  
    7272--
    7373-- Created:
    74 --          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    75 --          at - 12:42:20 02.07.2010
     74--          by - dneise.UNKNOWN (E5B-LABOR6)
     75--          at - 15:25:14 14.07.2010
    7676--
    7777-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    9595   SIGNAL CLK_25_PS      : std_logic;
    9696   SIGNAL CLK_50         : std_logic;
    97    SIGNAL SRCLK          : std_logic := '0';
     97   SIGNAL SRCLK          : std_logic                    := '0';
    9898   SIGNAL TRG_OR         : std_logic;
    9999   SIGNAL adc_data_array : adc_data_array_type;
    100100   SIGNAL board_id       : std_logic_vector(3 DOWNTO 0);
    101101   SIGNAL crate_id       : std_logic_vector(1 DOWNTO 0);
     102   SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
    102103   SIGNAL dummy          : std_logic;
    103    SIGNAL not_TEST_TRG   : STD_LOGIC;
    104104   SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0);
    105    SIGNAL trigger_out    : STD_LOGIC := '0';
    106 
    107    -- Implicit buffer signal declarations
    108    SIGNAL RSRLOAD_internal : std_logic;
    109105
    110106
    … …  
    148144   );
    149145   END COMPONENT;
    150    COMPONENT debouncer
    151    GENERIC (
    152       WIDTH : INTEGER := 17
    153    );
    154    PORT (
    155       clk         : IN     STD_LOGIC ;
    156       --           rst : in  STD_LOGIC;
    157       trigger_in  : IN     STD_LOGIC ;
    158       trigger_out : OUT    STD_LOGIC  := '0'
    159    );
    160    END COMPONENT;
    161146
    162147   -- Optional embedded configurations
    163148   -- pragma synthesis_off
    164149   FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
    165    FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer;
    166150   -- pragma synthesis_on
    167151
    … …  
    228212   -- HDL Embedded Text Block 8 eb2
    229213   -- eb2 8                                       
    230    A1_T(0) <= dummy;
    231    A1_T(1) <= RSRLOAD_internal;
    232    A1_T(2) <= D0_SROUT;
    233    A1_T(3) <= D1_SROUT;
     214   A1_T(3 downto 0) <= drs_channel_id;
     215   D_A <= drs_channel_id;
     216   A1_T(4)  <= TRG_OR;
    234217
    235218
    … …  
    237220   DAC_CS <= dummy;
    238221
    239    -- ModuleWare code(v1.9) for instance 'I1' of 'inv'
    240    not_TEST_TRG <= NOT(TEST_TRG);
    241 
    242222   -- ModuleWare code(v1.9) for instance 'I2' of 'or'
    243    TRG_OR <= TRG OR trigger_out;
     223   TRG_OR <= TRG OR TEST_TRG;
    244224
    245225   -- Instance port mappings.
    … …  
    262242         CLK_25_PS      => CLK_25_PS,
    263243         CLK_50         => CLK_50,
    264          RSRLOAD        => RSRLOAD_internal,
     244         RSRLOAD        => RSRLOAD,
    265245         SRCLK          => SRCLK,
    266246         adc_oeb        => OE_ADC,
    267247         dac_cs         => dummy,
    268248         denable        => DENABLE,
    269          drs_channel_id => D_A,
     249         drs_channel_id => drs_channel_id,
    270250         drs_dwrite     => DWRITE,
    271251         led            => D_T,
    … …  
    281261         wiz_data       => W_D
    282262      );
    283    I_debouncer : debouncer
    284       GENERIC MAP (
    285          WIDTH => 17
    286       )
    287       PORT MAP (
    288          clk         => CLK_50,
    289          trigger_in  => not_TEST_TRG,
    290          trigger_out => trigger_out
    291       );
    292 
    293    -- Implicit buffered output assignments
    294    RSRLOAD <= RSRLOAD_internal;
    295263
    296264END struct;

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd

    r246 r252  
    104104  constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836);
    105105  --constant DEFAULT_DAC : dac_array_type := (others => 0);
     106 
     107  constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000";
     108  constant DEFAULT_DRSADDR_MODE : std_logic := '0';
     109
     110 
    106111
    107112-- Commands

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak

    r246 r252  
    5151        constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
    5252        constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
     53        constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
     54        constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
    5355        constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
    5456        constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
    … …  
    8082
    8183  constant LOG2_OF_RAM_SIZE_64B : integer := 15;
    82   constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B;
     84  --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B;
     85  constant RAM_SIZE_64B : integer := 24576;
    8386  constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4;
    8487
    … …  
    101104  constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836);
    102105  --constant DEFAULT_DAC : dac_array_type := (others => 0);
     106 
     107  constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0";
     108  constant DEFAULT_DRSADDR_MODE : std_logic := '0';
     109
     110 
    103111
    104112-- Commands

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r246 r252  
    33-- Created:
    44--          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    5 --          at - 12:42:19 02.07.2010
     5--          at - 14:46:38 12.07.2010
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    6060-- Created:
    6161--          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    62 --          at - 12:42:19 02.07.2010
     62--          at - 14:46:38 12.07.2010
    6363--
    6464-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    106106   SIGNAL dac_array              : dac_array_type;
    107107   SIGNAL data_out               : std_logic_vector(63 DOWNTO 0);
     108   SIGNAL drs_address            : std_logic_vector(3 DOWNTO 0)                 := (others => '0');
     109   SIGNAL drs_address_mode       : std_logic;
     110   SIGNAL drs_channel_internal   : std_logic_vector(3 DOWNTO 0)                 := (others => '0');
    108111   SIGNAL drs_clk_en             : std_logic                                    := '0';
    109112   SIGNAL drs_read_s_cell        : std_logic                                    := '0';
    … …  
    170173      config_started    : OUT    std_logic  := '0';
    171174      dac_array         : OUT    dac_array_type ;
     175      drs_address       : OUT    std_logic_vector (3 DOWNTO 0);
     176      drs_address_mode  : OUT    std_logic ;
    172177      roi_array         : OUT    roi_array_type ;
    173178      config_data       : INOUT  std_logic_vector (15 DOWNTO 0)
    … …  
    351356   drs_dwrite <= dwrite AND dwrite_enable;
    352357
     358   -- ModuleWare code(v1.9) for instance 'U_0' of 'mux'
     359   u_0combo_proc: PROCESS(drs_channel_internal, drs_address,
     360                          drs_address_mode)
     361   BEGIN
     362      CASE drs_address_mode IS
     363      WHEN '0' => drs_channel_id <= drs_channel_internal;
     364      WHEN '1' => drs_channel_id <= drs_address;
     365      WHEN OTHERS => drs_channel_id <= (OTHERS => 'X');
     366      END CASE;
     367   END PROCESS u_0combo_proc;
     368
    353369   -- Instance port mappings.
    354370   I_main_adc_buffer : adc_buffer
    … …  
    379395         config_started    => config_started_cu,
    380396         dac_array         => dac_array,
     397         drs_address       => drs_address,
     398         drs_address_mode  => drs_address_mode,
    381399         roi_array         => roi_array,
    382400         config_data       => config_data
    … …  
    429447         adc_oeb               => adc_oeb,
    430448         adc_otr               => adc_otr,
    431          drs_channel_id        => drs_channel_id,
     449         drs_channel_id        => drs_channel_internal,
    432450         drs_dwrite            => dwrite,
    433451         drs_clk_en            => drs_clk_en,

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf

    r246 r252  
    3737DESIGN control_unit
    3838VIEW symbol.sb
    39 GRAPHIC 155,0 26 0
    40 DESIGN control_unit
    41 VIEW symbol.sb
    42 GRAPHIC 150,0 27 0
    43 DESIGN control_unit
    44 VIEW symbol.sb
    45 GRAPHIC 1,0 30 0
    46 DESIGN control_unit
    47 VIEW symbol.sb
    48 GRAPHIC 1,0 31 0
    49 DESIGN control_unit
    50 VIEW struct.bd
    51 NO_GRAPHIC 34
    52 DESIGN control_unit
    53 VIEW struct.bd
    54 GRAPHIC 41,0 43 0
    55 DESIGN control_unit
    56 VIEW struct.bd
    57 NO_GRAPHIC 48
    58 DESIGN control_unit
    59 VIEW struct.bd
    60 GRAPHIC 0,0 51 2
    61 DESIGN control_unit
    62 VIEW struct.bd
    63 GRAPHIC 345,0 56 0
    64 DESIGN control_unit
    65 VIEW struct.bd
    66 GRAPHIC 333,0 57 0
    67 DESIGN control_unit
    68 VIEW struct.bd
    69 GRAPHIC 349,0 58 0
    70 DESIGN control_unit
    71 VIEW struct.bd
    72 GRAPHIC 329,0 59 0
    73 DESIGN control_unit
    74 VIEW struct.bd
    75 NO_GRAPHIC 60
    76 DESIGN control_unit
    77 VIEW struct.bd
    78 NO_GRAPHIC 61
     39GRAPHIC 521,0 26 0
     40DESIGN control_unit
     41VIEW symbol.sb
     42GRAPHIC 526,0 27 0
     43DESIGN control_unit
     44VIEW symbol.sb
     45GRAPHIC 155,0 28 0
     46DESIGN control_unit
     47VIEW symbol.sb
     48GRAPHIC 150,0 29 0
     49DESIGN control_unit
     50VIEW symbol.sb
     51GRAPHIC 1,0 32 0
     52DESIGN control_unit
     53VIEW symbol.sb
     54GRAPHIC 1,0 33 0
     55DESIGN control_unit
     56VIEW struct.bd
     57NO_GRAPHIC 36
     58DESIGN control_unit
     59VIEW struct.bd
     60GRAPHIC 41,0 45 0
     61DESIGN control_unit
     62VIEW struct.bd
     63NO_GRAPHIC 50
     64DESIGN control_unit
     65VIEW struct.bd
     66GRAPHIC 0,0 53 2
     67DESIGN control_unit
     68VIEW struct.bd
     69GRAPHIC 345,0 58 0
     70DESIGN control_unit
     71VIEW struct.bd
     72GRAPHIC 333,0 59 0
     73DESIGN control_unit
     74VIEW struct.bd
     75GRAPHIC 349,0 60 0
     76DESIGN control_unit
     77VIEW struct.bd
     78GRAPHIC 329,0 61 0
     79DESIGN control_unit
     80VIEW struct.bd
     81NO_GRAPHIC 62
     82DESIGN control_unit
     83VIEW struct.bd
     84NO_GRAPHIC 63
    7985LIBRARY FACT_FAD_lib
    8086DESIGN control@r@a@m_16bit_x256
    8187VIEW control@r@a@m_16bit_x256_a
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    83 DESIGN control@r@a@m_16bit_x256
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    93 VIEW control@r@a@m_16bit_x256_a
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    95 DESIGN control@r@a@m_16bit_x256
    96 VIEW control@r@a@m_16bit_x256_a
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    105 VIEW beha
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     89DESIGN control@r@a@m_16bit_x256
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     93VIEW control@r@a@m_16bit_x256_a
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     96VIEW control@r@a@m_16bit_x256_a
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     101DESIGN control@r@a@m_16bit_x256
     102VIEW control@r@a@m_16bit_x256_a
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     108VIEW symbol.sb
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     111VIEW beha
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     114VIEW beha
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     117VIEW beha
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     120VIEW beha
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     123VIEW beha
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     126VIEW beha
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     129VIEW beha
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     135VIEW beha
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    152164LIBRARY FACT_FAD_lib
    153165DESIGN control_unit
    154166VIEW struct.bd
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r246 r252  
    175175DESIGN @f@a@d_@board
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    178178DESIGN @f@a@d_@board
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    202202DESIGN @f@a@d_@board
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    214208LIBRARY FACT_FAD_lib
    215209DESIGN @f@a@d_main
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    329308LIBRARY FACT_FAD_lib
    330309DESIGN @f@a@d_@board
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

    r246 r252  
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    283292LIBRARY FACT_FAD_lib
    284293DESIGN adc_buffer
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    293302DESIGN clock_generator
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    302311DESIGN clock_generator
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     320DESIGN control_unit
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     323DESIGN control_unit
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     326DESIGN control_unit
     327VIEW symbol.sb
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     329DESIGN control_unit
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     353DESIGN control_unit
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     356DESIGN control_unit
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     359DESIGN @f@a@d_main
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     361GRAPHIC 8277,0 180 0
    347362DESIGN data@r@a@m_64b_16b_width14_5
    348363VIEW data@r@a@m_64b_16b_width14_5_a
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    382 GRAPHIC 58,0 193 0
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    387 VIEW @behavioral
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    393 VIEW @behavioral
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    396 VIEW @behavioral
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    400 GRAPHIC 963,0 199 0
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    402 VIEW @behavioral
    403 GRAPHIC 1127,0 200 0
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    405 VIEW @behavioral
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    408 VIEW @behavioral
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    410 DESIGN data_generator
    411 VIEW @behavioral
    412 GRAPHIC 1053,0 203 0
    413 DESIGN data_generator
    414 VIEW @behavioral
    415 GRAPHIC 1201,0 204 0
    416 DESIGN data_generator
    417 VIEW @behavioral
    418 GRAPHIC 1196,0 205 0
    419 DESIGN data_generator
    420 VIEW @behavioral
    421 GRAPHIC 1206,0 206 0
    422 DESIGN data_generator
    423 VIEW @behavioral
    424 GRAPHIC 473,0 207 0
    425 DESIGN data_generator
    426 VIEW @behavioral
    427 GRAPHIC 412,0 208 0
    428 DESIGN data_generator
    429 VIEW @behavioral
    430 GRAPHIC 1085,0 209 0
    431 DESIGN data_generator
    432 VIEW @behavioral
    433 GRAPHIC 1090,0 210 0
    434 DESIGN data_generator
    435 VIEW @behavioral
    436 GRAPHIC 1240,0 211 0
    437 DESIGN data_generator
    438 VIEW @behavioral
    439 GRAPHIC 526,0 212 0
    440 DESIGN data_generator
    441 VIEW @behavioral
    442 GRAPHIC 88,0 213 0
    443 DESIGN data_generator
    444 VIEW @behavioral
    445 GRAPHIC 285,0 214 0
    446 DESIGN data_generator
    447 VIEW @behavioral
    448 GRAPHIC 93,0 215 0
    449 DESIGN data_generator
    450 VIEW @behavioral
    451 GRAPHIC 98,0 216 0
    452 DESIGN data_generator
    453 VIEW @behavioral
    454 GRAPHIC 1018,0 217 0
    455 DESIGN data_generator
    456 VIEW @behavioral
    457 GRAPHIC 1164,0 218 0
    458 DESIGN data_generator
    459 VIEW @behavioral
    460 GRAPHIC 1159,0 219 0
    461 DESIGN data_generator
    462 VIEW @behavioral
    463 GRAPHIC 898,0 220 0
    464 DESIGN data_generator
    465 VIEW @behavioral
    466 GRAPHIC 637,0 221 0
    467 DESIGN data_generator
    468 VIEW @behavioral
    469 GRAPHIC 642,0 222 0
    470 DESIGN data_generator
    471 VIEW @behavioral
    472 GRAPHIC 676,0 223 0
    473 DESIGN data_generator
    474 VIEW @behavioral
    475 GRAPHIC 845,0 224 0
    476 DESIGN data_generator
    477 VIEW @behavioral
    478 GRAPHIC 681,0 225 0
    479 DESIGN data_generator
    480 VIEW @behavioral
    481 GRAPHIC 801,0 226 0
    482 DESIGN data_generator
    483 VIEW @behavioral
    484 GRAPHIC 806,0 227 0
    485 DESIGN data_generator
    486 VIEW @behavioral
    487 GRAPHIC 811,0 228 0
    488 DESIGN @f@a@d_main
    489 VIEW struct.bd
    490 GRAPHIC 4903,0 231 0
    491 DESIGN @f@a@d_main
    492 VIEW struct.bd
    493 NO_GRAPHIC 244
    494 DESIGN @f@a@d_main
    495 VIEW struct.bd
    496 GRAPHIC 2311,0 246 0
    497 DESIGN memory_manager
    498 VIEW symbol.sb
    499 GRAPHIC 14,0 247 1
    500 DESIGN memory_manager
    501 VIEW beha
    502 GRAPHIC 138,0 252 0
    503 DESIGN memory_manager
    504 VIEW beha
    505 GRAPHIC 194,0 253 0
    506 DESIGN memory_manager
    507 VIEW beha
    508 GRAPHIC 349,0 254 0
    509 DESIGN memory_manager
    510 VIEW beha
    511 GRAPHIC 569,0 255 0
    512 DESIGN memory_manager
    513 VIEW beha
    514 GRAPHIC 224,0 256 0
    515 DESIGN memory_manager
    516 VIEW beha
    517 GRAPHIC 254,0 257 0
    518 DESIGN memory_manager
    519 VIEW beha
    520 GRAPHIC 804,0 258 0
    521 DESIGN memory_manager
    522 VIEW beha
    523 GRAPHIC 433,0 259 0
    524 DESIGN memory_manager
    525 VIEW beha
    526 GRAPHIC 622,0 260 0
    527 DESIGN memory_manager
    528 VIEW beha
    529 GRAPHIC 289,0 261 0
    530 DESIGN memory_manager
    531 VIEW beha
    532 GRAPHIC 309,0 262 0
    533 DESIGN memory_manager
    534 VIEW beha
    535 GRAPHIC 284,0 263 0
    536 DESIGN memory_manager
    537 VIEW beha
    538 GRAPHIC 294,0 264 0
    539 DESIGN memory_manager
    540 VIEW beha
    541 GRAPHIC 304,0 265 0
    542 DESIGN memory_manager
    543 VIEW beha
    544 GRAPHIC 299,0 266 0
    545 DESIGN memory_manager
    546 VIEW beha
    547 GRAPHIC 379,0 267 0
    548 DESIGN memory_manager
    549 VIEW beha
    550 GRAPHIC 915,0 268 0
    551 DESIGN memory_manager
    552 VIEW beha
    553 GRAPHIC 51,0 269 0
    554 DESIGN @f@a@d_main
    555 VIEW struct.bd
    556 GRAPHIC 5793,0 272 0
     382GRAPHIC 78,0 188 0
     383DESIGN @f@a@d_main
     384VIEW struct.bd
     385GRAPHIC 1399,0 191 0
     386DESIGN data_generator
     387VIEW symbol.sb
     388GRAPHIC 14,0 192 1
     389DESIGN data_generator
     390VIEW @behavioral
     391GRAPHIC 48,0 196 0
     392DESIGN data_generator
     393VIEW @behavioral
     394GRAPHIC 53,0 197 0
     395DESIGN data_generator
     396VIEW @behavioral
     397GRAPHIC 58,0 198 0
     398DESIGN data_generator
     399VIEW @behavioral
     400GRAPHIC 73,0 199 0
     401DESIGN data_generator
     402VIEW @behavioral
     403GRAPHIC 78,0 200 0
     404DESIGN data_generator
     405VIEW @behavioral
     406GRAPHIC 402,0 201 0
     407DESIGN data_generator
     408VIEW @behavioral
     409GRAPHIC 407,0 202 0
     410DESIGN data_generator
     411VIEW @behavioral
     412GRAPHIC 1122,0 203 0
     413DESIGN data_generator
     414VIEW @behavioral
     415GRAPHIC 963,0 204 0
     416DESIGN data_generator
     417VIEW @behavioral
     418GRAPHIC 1127,0 205 0
     419DESIGN data_generator
     420VIEW @behavioral
     421GRAPHIC 1048,0 206 0
     422DESIGN data_generator
     423VIEW @behavioral
     424GRAPHIC 958,0 207 0
     425DESIGN data_generator
     426VIEW @behavioral
     427GRAPHIC 1053,0 208 0
     428DESIGN data_generator
     429VIEW @behavioral
     430GRAPHIC 1201,0 209 0
     431DESIGN data_generator
     432VIEW @behavioral
     433GRAPHIC 1196,0 210 0
     434DESIGN data_generator
     435VIEW @behavioral
     436GRAPHIC 1206,0 211 0
     437DESIGN data_generator
     438VIEW @behavioral
     439GRAPHIC 473,0 212 0
     440DESIGN data_generator
     441VIEW @behavioral
     442GRAPHIC 412,0 213 0
     443DESIGN data_generator
     444VIEW @behavioral
     445GRAPHIC 1085,0 214 0
     446DESIGN data_generator
     447VIEW @behavioral
     448GRAPHIC 1090,0 215 0
     449DESIGN data_generator
     450VIEW @behavioral
     451GRAPHIC 1240,0 216 0
     452DESIGN data_generator
     453VIEW @behavioral
     454GRAPHIC 526,0 217 0
     455DESIGN data_generator
     456VIEW @behavioral
     457GRAPHIC 88,0 218 0
     458DESIGN data_generator
     459VIEW @behavioral
     460GRAPHIC 285,0 219 0
     461DESIGN data_generator
     462VIEW @behavioral
     463GRAPHIC 93,0 220 0
     464DESIGN data_generator
     465VIEW @behavioral
     466GRAPHIC 98,0 221 0
     467DESIGN data_generator
     468VIEW @behavioral
     469GRAPHIC 1018,0 222 0
     470DESIGN data_generator
     471VIEW @behavioral
     472GRAPHIC 1164,0 223 0
     473DESIGN data_generator
     474VIEW @behavioral
     475GRAPHIC 1159,0 224 0
     476DESIGN data_generator
     477VIEW @behavioral
     478GRAPHIC 898,0 225 0
     479DESIGN data_generator
     480VIEW @behavioral
     481GRAPHIC 637,0 226 0
     482DESIGN data_generator
     483VIEW @behavioral
     484GRAPHIC 642,0 227 0
     485DESIGN data_generator
     486VIEW @behavioral
     487GRAPHIC 676,0 228 0
     488DESIGN data_generator
     489VIEW @behavioral
     490GRAPHIC 845,0 229 0
     491DESIGN data_generator
     492VIEW @behavioral
     493GRAPHIC 681,0 230 0
     494DESIGN data_generator
     495VIEW @behavioral
     496GRAPHIC 801,0 231 0
     497DESIGN data_generator
     498VIEW @behavioral
     499GRAPHIC 806,0 232 0
     500DESIGN data_generator
     501VIEW @behavioral
     502GRAPHIC 811,0 233 0
     503DESIGN @f@a@d_main
     504VIEW struct.bd
     505GRAPHIC 4903,0 236 0
     506DESIGN @f@a@d_main
     507VIEW struct.bd
     508NO_GRAPHIC 249
     509DESIGN @f@a@d_main
     510VIEW struct.bd
     511GRAPHIC 2311,0 251 0
     512DESIGN memory_manager
     513VIEW symbol.sb
     514GRAPHIC 14,0 252 1
     515DESIGN memory_manager
     516VIEW beha
     517GRAPHIC 138,0 257 0
     518DESIGN memory_manager
     519VIEW beha
     520GRAPHIC 194,0 258 0
     521DESIGN memory_manager
     522VIEW beha
     523GRAPHIC 349,0 259 0
     524DESIGN memory_manager
     525VIEW beha
     526GRAPHIC 569,0 260 0
     527DESIGN memory_manager
     528VIEW beha
     529GRAPHIC 224,0 261 0
     530DESIGN memory_manager
     531VIEW beha
     532GRAPHIC 254,0 262 0
     533DESIGN memory_manager
     534VIEW beha
     535GRAPHIC 804,0 263 0
     536DESIGN memory_manager
     537VIEW beha
     538GRAPHIC 433,0 264 0
     539DESIGN memory_manager
     540VIEW beha
     541GRAPHIC 622,0 265 0
     542DESIGN memory_manager
     543VIEW beha
     544GRAPHIC 289,0 266 0
     545DESIGN memory_manager
     546VIEW beha
     547GRAPHIC 309,0 267 0
     548DESIGN memory_manager
     549VIEW beha
     550GRAPHIC 284,0 268 0
     551DESIGN memory_manager
     552VIEW beha
     553GRAPHIC 294,0 269 0
     554DESIGN memory_manager
     555VIEW beha
     556GRAPHIC 304,0 270 0
     557DESIGN memory_manager
     558VIEW beha
     559GRAPHIC 299,0 271 0
     560DESIGN memory_manager
     561VIEW beha
     562GRAPHIC 379,0 272 0
     563DESIGN memory_manager
     564VIEW beha
     565GRAPHIC 915,0 273 0
     566DESIGN memory_manager
     567VIEW beha
     568GRAPHIC 51,0 274 0
     569DESIGN @f@a@d_main
     570VIEW struct.bd
     571GRAPHIC 5793,0 277 0
    557572DESIGN spi_interface
    558573VIEW symbol.sb
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     574GRAPHIC 1121,0 279 0
    560575DESIGN spi_interface
    561576VIEW symbol.sb
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     577GRAPHIC 326,0 280 0
    563578DESIGN spi_interface
    564579VIEW symbol.sb
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     580GRAPHIC 197,0 281 0
    566581DESIGN spi_interface
    567582VIEW symbol.sb
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     583GRAPHIC 321,0 282 0
    569584DESIGN spi_interface
    570585VIEW symbol.sb
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     586GRAPHIC 1198,0 283 0
    572587DESIGN spi_interface
    573588VIEW symbol.sb
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     589GRAPHIC 1017,0 284 0
    575590DESIGN spi_interface
    576591VIEW symbol.sb
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    578593DESIGN spi_interface
    579594VIEW symbol.sb
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     595GRAPHIC 126,0 286 0
    581596DESIGN spi_interface
    582597VIEW symbol.sb
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     598GRAPHIC 819,0 287 0
    584599DESIGN spi_interface
    585600VIEW symbol.sb
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     601GRAPHIC 1022,0 288 0
    587602DESIGN spi_interface
    588603VIEW symbol.sb
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     604GRAPHIC 824,0 289 0
    590605DESIGN spi_interface
    591606VIEW symbol.sb
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    593 DESIGN @f@a@d_main
    594 VIEW struct.bd
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     607GRAPHIC 1283,0 290 0
     608DESIGN @f@a@d_main
     609VIEW struct.bd
     610GRAPHIC 1768,0 293 0
    596611DESIGN trigger_counter
    597612VIEW beha
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     613GRAPHIC 48,0 295 0
    599614DESIGN trigger_counter
    600615VIEW beha
    601 GRAPHIC 53,0 291 0
     616GRAPHIC 53,0 296 0
    602617DESIGN trigger_counter
    603618VIEW beha
    604 GRAPHIC 148,0 292 0
    605 DESIGN @f@a@d_main
    606 VIEW struct.bd
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    608 DESIGN w5300_modul
    609 VIEW symbol.sb
    610 GRAPHIC 14,0 296 1
    611 DESIGN w5300_modul
    612 VIEW @behavioral
    613 GRAPHIC 48,0 300 0
    614 DESIGN w5300_modul
    615 VIEW @behavioral
    616 GRAPHIC 53,0 301 0
    617 DESIGN w5300_modul
    618 VIEW @behavioral
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    620 DESIGN w5300_modul
    621 VIEW @behavioral
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    623 DESIGN w5300_modul
    624 VIEW @behavioral
    625 GRAPHIC 68,0 304 0
    626 DESIGN w5300_modul
    627 VIEW @behavioral
    628 GRAPHIC 73,0 305 0
    629 DESIGN w5300_modul
    630 VIEW @behavioral
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    632 DESIGN w5300_modul
    633 VIEW @behavioral
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    635 DESIGN w5300_modul
    636 VIEW @behavioral
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    638 DESIGN w5300_modul
    639 VIEW @behavioral
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    641 DESIGN w5300_modul
    642 VIEW @behavioral
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    644 DESIGN w5300_modul
    645 VIEW @behavioral
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    647 DESIGN w5300_modul
    648 VIEW @behavioral
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    650 DESIGN w5300_modul
    651 VIEW @behavioral
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    653 DESIGN w5300_modul
    654 VIEW @behavioral
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    657 VIEW @behavioral
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    659 DESIGN w5300_modul
    660 VIEW @behavioral
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    662 DESIGN w5300_modul
    663 VIEW @behavioral
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    665 DESIGN w5300_modul
    666 VIEW @behavioral
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    668 DESIGN w5300_modul
    669 VIEW @behavioral
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    671 DESIGN w5300_modul
    672 VIEW @behavioral
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    675 VIEW @behavioral
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    677 DESIGN w5300_modul
    678 VIEW @behavioral
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    681 VIEW @behavioral
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    683 DESIGN w5300_modul
    684 VIEW @behavioral
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    686 DESIGN w5300_modul
    687 VIEW @behavioral
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    689 DESIGN w5300_modul
    690 VIEW @behavioral
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    693 VIEW @behavioral
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    696 VIEW @behavioral
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     619GRAPHIC 148,0 297 0
     620DESIGN @f@a@d_main
     621VIEW struct.bd
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     623DESIGN w5300_modul
     624VIEW symbol.sb
     625GRAPHIC 14,0 301 1
     626DESIGN w5300_modul
     627VIEW @behavioral
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     629DESIGN w5300_modul
     630VIEW @behavioral
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     636VIEW @behavioral
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     638DESIGN w5300_modul
     639VIEW @behavioral
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     641DESIGN w5300_modul
     642VIEW @behavioral
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     645VIEW @behavioral
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     647DESIGN w5300_modul
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     650DESIGN w5300_modul
     651VIEW @behavioral
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     654VIEW @behavioral
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     657VIEW @behavioral
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     678VIEW @behavioral
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     681VIEW @behavioral
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     705VIEW @behavioral
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     708VIEW @behavioral
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     710DESIGN w5300_modul
     711VIEW @behavioral
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    698713LIBRARY FACT_FAD_lib
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    703 VIEW struct.bd
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    721 VIEW struct.bd
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    723 DESIGN @f@a@d_main
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    730 VIEW struct.bd
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    732 DESIGN @f@a@d_main
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    735 DESIGN @f@a@d_main
    736 VIEW struct.bd
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     717DESIGN @f@a@d_main
     718VIEW struct.bd
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     720DESIGN @f@a@d_main
     721VIEW struct.bd
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     723DESIGN @f@a@d_main
     724VIEW struct.bd
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     726DESIGN @f@a@d_main
     727VIEW struct.bd
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     729DESIGN @f@a@d_main
     730VIEW struct.bd
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     732DESIGN @f@a@d_main
     733VIEW struct.bd
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     735DESIGN @f@a@d_main
     736VIEW struct.bd
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     738DESIGN @f@a@d_main
     739VIEW struct.bd
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     741DESIGN @f@a@d_main
     742VIEW struct.bd
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     744DESIGN @f@a@d_main
     745VIEW struct.bd
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    738747DESIGN @f@a@d_main
    739748VIEW struct.bd
    … …  
    741750DESIGN @f@a@d_main
    742751VIEW struct.bd
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    744 DESIGN @f@a@d_main
    745 VIEW struct.bd
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    747 DESIGN @f@a@d_main
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    763 VIEW struct.bd
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    772 VIEW struct.bd
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    775 VIEW struct.bd
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    778 VIEW struct.bd
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    781 VIEW struct.bd
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     951DESIGN @f@a@d_main
     952VIEW struct.bd
     953GRAPHIC 5962,0 444 0
     954DESIGN @f@a@d_main
     955VIEW struct.bd
     956GRAPHIC 5626,0 445 0
     957DESIGN @f@a@d_main
     958VIEW struct.bd
     959GRAPHIC 2778,0 446 0
     960DESIGN @f@a@d_main
     961VIEW struct.bd
     962GRAPHIC 5634,0 447 0
     963DESIGN @f@a@d_main
     964VIEW struct.bd
     965GRAPHIC 8577,0 448 0
     966DESIGN @f@a@d_main
     967VIEW struct.bd
     968GRAPHIC 6540,0 449 0
     969DESIGN @f@a@d_main
     970VIEW struct.bd
     971GRAPHIC 4401,0 450 0
     972DESIGN @f@a@d_main
     973VIEW struct.bd
     974GRAPHIC 4419,0 451 0
     975DESIGN @f@a@d_main
     976VIEW struct.bd
     977GRAPHIC 4743,0 452 0
     978DESIGN @f@a@d_main
     979VIEW struct.bd
     980GRAPHIC 4407,0 453 0
     981DESIGN @f@a@d_main
     982VIEW struct.bd
     983GRAPHIC 4903,0 455 0
     984DESIGN @f@a@d_main
     985VIEW struct.bd
     986GRAPHIC 4757,0 457 0
     987DESIGN @f@a@d_main
     988VIEW struct.bd
     989GRAPHIC 4401,0 458 0
     990DESIGN @f@a@d_main
     991VIEW struct.bd
     992GRAPHIC 4419,0 459 0
     993DESIGN @f@a@d_main
     994VIEW struct.bd
     995GRAPHIC 4671,0 460 0
     996DESIGN @f@a@d_main
     997VIEW struct.bd
     998GRAPHIC 4679,0 461 0
     999DESIGN @f@a@d_main
     1000VIEW struct.bd
     1001GRAPHIC 4687,0 462 0
     1002DESIGN @f@a@d_main
     1003VIEW struct.bd
     1004GRAPHIC 4695,0 463 0
     1005DESIGN @f@a@d_main
     1006VIEW struct.bd
     1007GRAPHIC 4407,0 464 0
     1008DESIGN @f@a@d_main
     1009VIEW struct.bd
     1010GRAPHIC 4743,0 465 0
     1011DESIGN @f@a@d_main
     1012VIEW struct.bd
     1013GRAPHIC 4948,0 466 0
     1014DESIGN @f@a@d_main
     1015VIEW struct.bd
     1016GRAPHIC 4962,0 467 0
     1017DESIGN @f@a@d_main
     1018VIEW struct.bd
     1019GRAPHIC 2311,0 469 0
     1020DESIGN @f@a@d_main
     1021VIEW struct.bd
     1022GRAPHIC 2318,0 470 1
     1023DESIGN @f@a@d_main
     1024VIEW struct.bd
     1025GRAPHIC 6082,0 475 0
     1026DESIGN @f@a@d_main
     1027VIEW struct.bd
     1028GRAPHIC 2588,0 476 0
     1029DESIGN @f@a@d_main
     1030VIEW struct.bd
     1031GRAPHIC 2582,0 477 0
     1032DESIGN @f@a@d_main
     1033VIEW struct.bd
     1034GRAPHIC 5168,0 478 0
     1035DESIGN @f@a@d_main
     1036VIEW struct.bd
     1037GRAPHIC 2576,0 479 0
     1038DESIGN @f@a@d_main
     1039VIEW struct.bd
     1040GRAPHIC 2594,0 480 0
     1041DESIGN @f@a@d_main
     1042VIEW struct.bd
     1043GRAPHIC 6018,0 481 0
     1044DESIGN @f@a@d_main
     1045VIEW struct.bd
     1046GRAPHIC 2600,0 482 0
     1047DESIGN @f@a@d_main
     1048VIEW struct.bd
     1049GRAPHIC 2642,0 483 0
     1050DESIGN @f@a@d_main
     1051VIEW struct.bd
     1052GRAPHIC 2488,0 484 0
     1053DESIGN @f@a@d_main
     1054VIEW struct.bd
     1055GRAPHIC 2482,0 485 0
     1056DESIGN @f@a@d_main
     1057VIEW struct.bd
     1058GRAPHIC 2494,0 486 0
     1059DESIGN @f@a@d_main
     1060VIEW struct.bd
     1061GRAPHIC 2476,0 487 0
     1062DESIGN @f@a@d_main
     1063VIEW struct.bd
     1064GRAPHIC 2506,0 488 0
     1065DESIGN @f@a@d_main
     1066VIEW struct.bd
     1067GRAPHIC 2500,0 489 0
     1068DESIGN @f@a@d_main
     1069VIEW struct.bd
     1070GRAPHIC 2470,0 490 0
     1071DESIGN @f@a@d_main
     1072VIEW struct.bd
     1073GRAPHIC 8416,0 491 0
     1074DESIGN @f@a@d_main
     1075VIEW struct.bd
     1076GRAPHIC 2299,0 492 0
     1077DESIGN @f@a@d_main
     1078VIEW struct.bd
     1079GRAPHIC 5793,0 494 0
     1080DESIGN @f@a@d_main
     1081VIEW struct.bd
     1082GRAPHIC 5805,0 496 0
     1083DESIGN @f@a@d_main
     1084VIEW struct.bd
     1085GRAPHIC 5745,0 497 0
     1086DESIGN @f@a@d_main
     1087VIEW struct.bd
     1088GRAPHIC 5146,0 498 0
     1089DESIGN @f@a@d_main
     1090VIEW struct.bd
     1091GRAPHIC 5404,0 499 0
     1092DESIGN @f@a@d_main
     1093VIEW struct.bd
     1094GRAPHIC 6008,0 500 0
     1095DESIGN @f@a@d_main
     1096VIEW struct.bd
     1097GRAPHIC 5829,0 501 0
     1098DESIGN @f@a@d_main
     1099VIEW struct.bd
     1100GRAPHIC 6160,0 502 0
     1101DESIGN @f@a@d_main
     1102VIEW struct.bd
     1103GRAPHIC 5813,0 503 0
     1104DESIGN @f@a@d_main
     1105VIEW struct.bd
     1106GRAPHIC 5480,0 504 0
     1107DESIGN @f@a@d_main
     1108VIEW struct.bd
     1109GRAPHIC 5837,0 505 0
     1110DESIGN @f@a@d_main
     1111VIEW struct.bd
     1112GRAPHIC 5474,0 506 0
     1113DESIGN @f@a@d_main
     1114VIEW struct.bd
     1115GRAPHIC 5821,0 507 0
     1116DESIGN @f@a@d_main
     1117VIEW struct.bd
     1118GRAPHIC 1768,0 509 0
     1119DESIGN @f@a@d_main
     1120VIEW struct.bd
     1121GRAPHIC 1983,0 511 0
     1122DESIGN @f@a@d_main
     1123VIEW struct.bd
     1124GRAPHIC 2876,0 512 0
     1125DESIGN @f@a@d_main
     1126VIEW struct.bd
     1127GRAPHIC 6276,0 513 0
     1128DESIGN @f@a@d_main
     1129VIEW struct.bd
     1130GRAPHIC 1606,0 515 0
     1131DESIGN @f@a@d_main
     1132VIEW struct.bd
     1133GRAPHIC 1613,0 516 1
     1134DESIGN @f@a@d_main
     1135VIEW struct.bd
     1136GRAPHIC 3888,0 520 0
     1137DESIGN @f@a@d_main
     1138VIEW struct.bd
     1139GRAPHIC 376,0 521 0
     1140DESIGN @f@a@d_main
     1141VIEW struct.bd
     1142GRAPHIC 384,0 522 0
     1143DESIGN @f@a@d_main
     1144VIEW struct.bd
     1145GRAPHIC 392,0 523 0
     1146DESIGN @f@a@d_main
     1147VIEW struct.bd
     1148GRAPHIC 400,0 524 0
     1149DESIGN @f@a@d_main
     1150VIEW struct.bd
     1151GRAPHIC 408,0 525 0
     1152DESIGN @f@a@d_main
     1153VIEW struct.bd
     1154GRAPHIC 5222,0 526 0
     1155DESIGN @f@a@d_main
     1156VIEW struct.bd
     1157GRAPHIC 424,0 527 0
     1158DESIGN @f@a@d_main
     1159VIEW struct.bd
     1160GRAPHIC 432,0 528 0
     1161DESIGN @f@a@d_main
     1162VIEW struct.bd
     1163GRAPHIC 2482,0 529 0
     1164DESIGN @f@a@d_main
     1165VIEW struct.bd
     1166GRAPHIC 2488,0 530 0
     1167DESIGN @f@a@d_main
     1168VIEW struct.bd
     1169GRAPHIC 370,0 531 0
     1170DESIGN @f@a@d_main
     1171VIEW struct.bd
     1172GRAPHIC 364,0 532 0
     1173DESIGN @f@a@d_main
     1174VIEW struct.bd
     1175GRAPHIC 2476,0 533 0
     1176DESIGN @f@a@d_main
     1177VIEW struct.bd
     1178GRAPHIC 8416,0 534 0
     1179DESIGN @f@a@d_main
     1180VIEW struct.bd
     1181GRAPHIC 2470,0 535 0
     1182DESIGN @f@a@d_main
     1183VIEW struct.bd
     1184GRAPHIC 2506,0 536 0
     1185DESIGN @f@a@d_main
     1186VIEW struct.bd
     1187GRAPHIC 2500,0 537 0
     1188DESIGN @f@a@d_main
     1189VIEW struct.bd
     1190GRAPHIC 2494,0 538 0
     1191DESIGN @f@a@d_main
     1192VIEW struct.bd
     1193GRAPHIC 5281,0 539 0
     1194DESIGN @f@a@d_main
     1195VIEW struct.bd
     1196GRAPHIC 5950,0 540 0
     1197DESIGN @f@a@d_main
     1198VIEW struct.bd
     1199GRAPHIC 5962,0 541 0
     1200DESIGN @f@a@d_main
     1201VIEW struct.bd
     1202GRAPHIC 5090,0 542 0
     1203DESIGN @f@a@d_main
     1204VIEW struct.bd
     1205GRAPHIC 5114,0 543 0
     1206DESIGN @f@a@d_main
     1207VIEW struct.bd
     1208GRAPHIC 5122,0 544 0
     1209DESIGN @f@a@d_main
     1210VIEW struct.bd
     1211GRAPHIC 5130,0 545 0
     1212DESIGN @f@a@d_main
     1213VIEW struct.bd
     1214GRAPHIC 5106,0 546 0
     1215DESIGN @f@a@d_main
     1216VIEW struct.bd
     1217GRAPHIC 6362,0 547 0
     1218DESIGN @f@a@d_main
     1219VIEW struct.bd
     1220GRAPHIC 6452,0 548 0
     1221DESIGN @f@a@d_main
     1222VIEW struct.bd
     1223GRAPHIC 6276,0 552 0
     1224DESIGN @f@a@d_main
     1225VIEW struct.bd
     1226GRAPHIC 3888,0 553 0
     1227DESIGN @f@a@d_main
     1228VIEW struct.bd
     1229NO_GRAPHIC 555

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r246 r252  
    4040)
    4141(Instance
    42 name "I_debouncer"
    43 duLibraryName "FACT_FAD_LIB"
    44 duName "debouncer"
    45 elements [
    46 (GiElement
    47 name "WIDTH"
    48 type "INTEGER"
    49 value "17"
    50 )
    51 ]
    52 mwi 0
    53 uid 6250,0
    54 )
    55 (Instance
    56 name "I1"
    57 duLibraryName "moduleware"
    58 duName "inv"
    59 elements [
    60 ]
    61 mwi 1
    62 uid 6539,0
    63 )
    64 (Instance
    6542name "I2"
    6643duLibraryName "moduleware"
    … …  
    128105(vvPair
    129106variable "HDLDir"
    130 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hdl"
     107value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    131108)
    132109(vvPair
    133110variable "HDSDir"
    134 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"
     111value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    135112)
    136113(vvPair
    137114variable "SideDataDesignDir"
    138 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     115value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    139116)
    140117(vvPair
    141118variable "SideDataUserDir"
    142 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     119value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    143120)
    144121(vvPair
    145122variable "SourceDir"
    146 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"
     123value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    147124)
    148125(vvPair
    … …  
    156133(vvPair
    157134variable "config"
    158 value "%(unit)_config"
     135value "%(unit)_%(view)_config"
    159136)
    160137(vvPair
    161138variable "d"
    162 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     139value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    163140)
    164141(vvPair
    165142variable "d_logical"
    166 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
     143value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    167144)
    168145(vvPair
    169146variable "date"
    170 value "24.06.2010"
     147value "14.07.2010"
    171148)
    172149(vvPair
    173150variable "day"
    174 value "Do"
     151value "Mi"
    175152)
    176153(vvPair
    177154variable "day_long"
    178 value "Donnerstag"
     155value "Mittwoch"
    179156)
    180157(vvPair
    181158variable "dd"
    182 value "24"
     159value "14"
    183160)
    184161(vvPair
    … …  
    208185(vvPair
    209186variable "host"
    210 value "EEPC8"
     187value "E5B-LABOR6"
    211188)
    212189(vvPair
    … …  
    219196)
    220197(vvPair
     198variable "library_downstream_HdsLintPlugin"
     199value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     200)
     201(vvPair
    221202variable "library_downstream_ISEPARInvoke"
    222203value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
    … …  
    236217(vvPair
    237218variable "mm"
    238 value "06"
     219value "07"
    239220)
    240221(vvPair
    … …  
    244225(vvPair
    245226variable "month"
    246 value "Jun"
     227value "Jul"
    247228)
    248229(vvPair
    249230variable "month_long"
    250 value "Juni"
     231value "Juli"
    251232)
    252233(vvPair
    253234variable "p"
    254 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     235value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    255236)
    256237(vvPair
    257238variable "p_logical"
    258 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     239value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    259240)
    260241(vvPair
    … …  
    280261(vvPair
    281262variable "task_ModelSimPath"
    282 value "$HDS_HOME/../Modeltech/win32"
     263value "<TBD>"
    283264)
    284265(vvPair
    … …  
    288269(vvPair
    289270variable "task_PrecisionRTLPath"
    290 value "$HDS_HOME/../Precision/Mgc_home/bin"
     271value "<TBD>"
    291272)
    292273(vvPair
    … …  
    312293(vvPair
    313294variable "time"
    314 value "14:18:44"
     295value "15:25:08"
    315296)
    316297(vvPair
    … …  
    320301(vvPair
    321302variable "user"
    322 value "Benjamin Krumm"
     303value "dneise"
    323304)
    324305(vvPair
    … …  
    364345bg "0,0,32768"
    365346)
    366 xt "99200,4000,108700,5000"
     347xt "99200,4000,108500,5000"
    367348st "
    368349by %user on %dd %month %year
    … …  
    20742055)
    20752056xt "39000,48000,67000,48800"
    2076 st "SIGNAL board_id       : std_logic_vector(3 downto 0)"
     2057st "SIGNAL board_id       : std_logic_vector(3 downto 0)
     2058"
    20772059)
    20782060)
    … …  
    20922074)
    20932075xt "39000,48800,67000,49600"
    2094 st "SIGNAL crate_id       : std_logic_vector(1 downto 0)"
     2076st "SIGNAL crate_id       : std_logic_vector(1 downto 0)
     2077"
    20952078)
    20962079)
    … …  
    24152398)
    24162399xt "39000,47200,62500,48000"
    2417 st "SIGNAL adc_data_array : adc_data_array_type"
     2400st "SIGNAL adc_data_array : adc_data_array_type
     2401"
    24182402)
    24192403)
    24202404*63 (Net
    2421 uid 2267,0
    2422 decl (Decl
    2423 n "CLK_50"
    2424 t "std_logic"
    2425 preAdd 0
    2426 posAdd 0
    2427 o 51
    2428 suid 54,0
    2429 )
    2430 declText (MLText
    2431 uid 2268,0
    2432 va (VaSet
    2433 font "Courier New,8,0"
    2434 )
    2435 xt "39000,44800,57000,45600"
    2436 st "SIGNAL CLK_50         : std_logic"
    2437 )
    2438 )
    2439 *64 (Net
    24402405uid 2407,0
    24412406decl (Decl
    … …  
    24522417)
    24532418xt "39000,31000,68000,31800"
    2454 st "RSRLOAD        : std_logic                      := '0'"
    2455 )
    2456 )
    2457 *65 (PortIoOut
     2419st "RSRLOAD        : std_logic                      := '0'
     2420"
     2421)
     2422)
     2423*64 (PortIoOut
    24582424uid 2415,0
    24592425shape (CompositeShape
    … …  
    25002466)
    25012467)
    2502 *66 (Net
     2468*65 (Net
    25032469uid 2421,0
    25042470decl (Decl
    … …  
    25152481)
    25162482xt "39000,45600,71500,46400"
    2517 st "SIGNAL SRCLK          : std_logic                      := '0'"
    2518 )
    2519 )
    2520 *67 (Net
     2483st "SIGNAL SRCLK          : std_logic                      := '0'
     2484"
     2485)
     2486)
     2487*66 (Net
    25212488uid 3019,0
    25222489decl (Decl
    … …  
    25332500)
    25342501xt "39000,51200,67000,52000"
    2535 st "SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0)"
    2536 )
    2537 )
    2538 *68 (Net
     2502st "SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0)
     2503"
     2504)
     2505)
     2506*67 (Net
    25392507uid 3025,0
    25402508decl (Decl
    … …  
    25502518)
    25512519xt "39000,19800,53500,20600"
    2552 st "DAC_CS         : std_logic"
    2553 )
    2554 )
    2555 *69 (PortIoOut
     2520st "DAC_CS         : std_logic
     2521"
     2522)
     2523)
     2524*68 (PortIoOut
    25562525uid 3153,0
    25572526shape (CompositeShape
    … …  
    25982567)
    25992568)
    2600 *70 (Net
     2569*69 (Net
    26012570uid 3216,0
    26022571decl (Decl
    … …  
    26142583)
    26152584xt "39000,14200,53500,15000"
    2616 st "X_50M          : STD_LOGIC"
    2617 )
    2618 )
    2619 *71 (Net
     2585st "X_50M          : STD_LOGIC
     2586"
     2587)
     2588)
     2589*70 (Net
    26202590uid 3226,0
    26212591decl (Decl
    … …  
    26312601)
    26322602xt "39000,12600,53500,13400"
    2633 st "TRG            : STD_LOGIC"
    2634 )
    2635 )
    2636 *72 (HdlText
     2603st "TRG            : STD_LOGIC
     2604"
     2605)
     2606)
     2607*71 (HdlText
    26372608uid 3248,0
    26382609optionalChildren [
    2639 *73 (EmbeddedText
     2610*72 (EmbeddedText
    26402611uid 3254,0
    26412612commentText (CommentText
    … …  
    26892660stg "VerticalLayoutStrategy"
    26902661textVec [
    2691 *74 (Text
     2662*73 (Text
    26922663uid 3251,0
    26932664va (VaSet
    … …  
    26992670tm "HdlTextNameMgr"
    27002671)
    2701 *75 (Text
     2672*74 (Text
    27022673uid 3252,0
    27032674va (VaSet
    … …  
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    46064609shape (CompositeShape
    … …  
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    46474650)
    4648 *146 (PortIoOut
     4651*145 (PortIoOut
    46494652uid 3722,0
    46504653shape (CompositeShape
    … …  
    46904693)
    46914694)
    4692 *147 (PortIoOut
     4695*146 (PortIoOut
    46934696uid 3728,0
    46944697shape (CompositeShape
    … …  
    47344737)
    47354738)
    4736 *148 (PortIoOut
     4739*147 (PortIoOut
    47374740uid 3734,0
    47384741shape (CompositeShape
    … …  
    47784781)
    47794782)
    4780 *149 (PortIoOut
     4783*148 (PortIoOut
    47814784uid 3740,0
    47824785shape (CompositeShape
    … …  
    48224825)
    48234826)
    4824 *150 (PortIoOut
     4827*149 (PortIoOut
    48254828uid 3746,0
    48264829shape (CompositeShape
    … …  
    48664869)
    48674870)
    4868 *151 (PortIoOut
     4871*150 (PortIoOut
    48694872uid 3752,0
    48704873shape (CompositeShape
    … …  
    49104913)
    49114914)
    4912 *152 (PortIoOut
     4915*151 (PortIoOut
    49134916uid 3758,0
    49144917shape (CompositeShape
    … …  
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    49554958)
    4956 *153 (Net
     4959*152 (Net
    49574960uid 3864,0
    49584961decl (Decl
    … …  
    49684971)
    49694972xt "39000,36600,53500,37400"
    4970 st "TRG_V          : std_logic"
    4971 )
    4972 )
    4973 *154 (Net
     4973st "TRG_V          : std_logic
     4974"
     4975)
     4976)
     4977*153 (Net
    49744978uid 3866,0
    49754979decl (Decl
    … …  
    49854989)
    49864990xt "39000,28600,53500,29400"
    4987 st "RS485_C_RE     : std_logic"
    4988 )
    4989 )
    4990 *155 (Net
     4991st "RS485_C_RE     : std_logic
     4992"
     4993)
     4994)
     4995*154 (Net
    49914996uid 3868,0
    49924997decl (Decl
    … …  
    50025007)
    50035008xt "39000,27800,53500,28600"
    5004 st "RS485_C_DE     : std_logic"
    5005 )
    5006 )
    5007 *156 (Net
     5009st "RS485_C_DE     : std_logic
     5010"
     5011)
     5012)
     5013*155 (Net
    50085014uid 3870,0
    50095015decl (Decl
    … …  
    50195025)
    50205026xt "39000,30200,53500,31000"
    5021 st "RS485_E_RE     : std_logic"
    5022 )
    5023 )
    5024 *157 (Net
     5027st "RS485_E_RE     : std_logic
     5028"
     5029)
     5030)
     5031*156 (Net
    50255032uid 3872,0
    50265033decl (Decl
    … …  
    50365043)
    50375044xt "39000,29400,53500,30200"
    5038 st "RS485_E_DE     : std_logic"
    5039 )
    5040 )
    5041 *158 (Net
     5045st "RS485_E_DE     : std_logic
     5046"
     5047)
     5048)
     5049*157 (Net
    50425050uid 3874,0
    50435051decl (Decl
    … …  
    50545062)
    50555063xt "39000,20600,68000,21400"
    5056 st "DENABLE        : std_logic                      := '0'"
    5057 )
    5058 )
    5059 *159 (Net
     5064st "DENABLE        : std_logic                      := '0'
     5065"
     5066)
     5067)
     5068*158 (Net
    50605069uid 3876,0
    50615070decl (Decl
    … …  
    50715080)
    50725081xt "39000,31800,53500,32600"
    5073 st "SRIN           : std_logic"
    5074 )
    5075 )
    5076 *160 (Net
     5082st "SRIN           : std_logic
     5083"
     5084)
     5085)
     5086*159 (Net
    50775087uid 3878,0
    50785088decl (Decl
    … …  
    50885098)
    50895099xt "39000,24600,53500,25400"
    5090 st "EE_CS          : std_logic"
    5091 )
    5092 )
    5093 *161 (Net
     5100st "EE_CS          : std_logic
     5101"
     5102)
     5103)
     5104*160 (Net
    50945105uid 3880,0
    50955106decl (Decl
    … …  
    51075118)
    51085119xt "39000,25400,74000,26200"
    5109 st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')"
    5110 )
    5111 )
    5112 *162 (PortIoOut
     5120st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')
     5121"
     5122)
     5123)
     5124*161 (PortIoOut
    51135125uid 3995,0
    51145126shape (CompositeShape
    … …  
    51555167)
    51565168)
    5157 *163 (PortIoOut
     5169*162 (PortIoOut
    51585170uid 4001,0
    51595171shape (CompositeShape
    … …  
    52005212)
    52015213)
    5202 *164 (PortIoOut
     5214*163 (PortIoOut
    52035215uid 4007,0
    52045216shape (CompositeShape
    … …  
    52455257)
    52465258)
    5247 *165 (PortIoOut
     5259*164 (PortIoOut
    52485260uid 4013,0
    52495261shape (CompositeShape
    … …  
    52905302)
    52915303)
    5292 *166 (PortIoOut
     5304*165 (PortIoOut
    52935305uid 4916,0
    52945306shape (CompositeShape
    … …  
    53345346)
    53355347)
    5336 *167 (Net
     5348*166 (Net
    53375349uid 5320,0
    53385350decl (Decl
    … …  
    53505362)
    53515363xt "39000,23000,74000,23800"
    5352 st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
    5353 )
    5354 )
    5355 *168 (PortIoIn
     5364st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')
     5365"
     5366)
     5367)
     5368*167 (PortIoIn
    53565369uid 5650,0
    53575370shape (CompositeShape
    … …  
    53665379sl 0
    53675380ro 270
    5368 xt "-30000,88625,-28500,89375"
     5381xt "9000,78625,10500,79375"
    53695382)
    53705383(Line
    … …  
    53725385sl 0
    53735386ro 270
    5374 xt "-28500,89000,-28000,89000"
    5375 pts [
    5376 "-28500,89000"
    5377 "-28000,89000"
     5387xt "10500,79000,11000,79000"
     5388pts [
     5389"10500,79000"
     5390"11000,79000"
    53785391]
    53795392)
    … …  
    53905403va (VaSet
    53915404)
    5392 xt "-35500,88500,-31000,89500"
     5405xt "3500,78500,8000,79500"
    53935406st "TEST_TRG"
    53945407ju 2
    5395 blo "-31000,89300"
     5408blo "8000,79300"
    53965409tm "WireNameMgr"
    53975410)
    53985411)
    53995412)
    5400 *169 (Net
     5413*168 (Net
    54015414uid 5662,0
    54025415decl (Decl
    … …  
    54125425)
    54135426xt "39000,11800,53500,12600"
    5414 st "TEST_TRG       : std_logic"
    5415 )
    5416 )
    5417 *170 (Net
     5427st "TEST_TRG       : std_logic
     5428"
     5429)
     5430)
     5431*169 (Net
    54185432uid 6138,0
    54195433decl (Decl
    … …  
    54295443)
    54305444xt "39000,46400,57000,47200"
    5431 st "SIGNAL TRG_OR         : std_logic"
    5432 )
    5433 )
    5434 *171 (SaComponent
    5435 uid 6250,0
    5436 optionalChildren [
    5437 *172 (CptPort
    5438 uid 6235,0
    5439 ps "OnEdgeStrategy"
    5440 shape (Triangle
    5441 uid 6236,0
    5442 ro 90
    5443 va (VaSet
    5444 vasetType 1
    5445 fg "0,65535,0"
    5446 )
    5447 xt "-11750,87625,-11000,88375"
    5448 )
    5449 tg (CPTG
    5450 uid 6237,0
    5451 ps "CptPortTextPlaceStrategy"
    5452 stg "VerticalLayoutStrategy"
    5453 f (Text
    5454 uid 6238,0
    5455 va (VaSet
    5456 )
    5457 xt "-10000,87500,-8700,88500"
    5458 st "clk"
    5459 blo "-10000,88300"
    5460 )
    5461 )
    5462 thePort (LogicalPort
    5463 decl (Decl
    5464 n "clk"
    5465 t "STD_LOGIC"
    5466 preAdd 0
    5467 posAdd 0
    5468 o 1
    5469 suid 1,0
    5470 )
    5471 )
    5472 )
    5473 *173 (CptPort
    5474 uid 6239,0
    5475 ps "OnEdgeStrategy"
    5476 shape (Triangle
    5477 uid 6240,0
    5478 ro 90
    5479 va (VaSet
    5480 vasetType 1
    5481 fg "0,65535,0"
    5482 )
    5483 xt "-11750,88625,-11000,89375"
    5484 )
    5485 tg (CPTG
    5486 uid 6241,0
    5487 ps "CptPortTextPlaceStrategy"
    5488 stg "VerticalLayoutStrategy"
    5489 f (Text
    5490 uid 6242,0
    5491 va (VaSet
    5492 )
    5493 xt "-10000,88500,-5800,89500"
    5494 st "trigger_in"
    5495 blo "-10000,89300"
    5496 )
    5497 )
    5498 thePort (LogicalPort
    5499 decl (Decl
    5500 n "trigger_in"
    5501 t "STD_LOGIC"
    5502 prec "--           rst : in  STD_LOGIC;"
    5503 preAdd 0
    5504 posAdd 0
    5505 o 2
    5506 suid 2,0
    5507 )
    5508 )
    5509 )
    5510 *174 (CptPort
    5511 uid 6243,0
    5512 ps "OnEdgeStrategy"
    5513 shape (Triangle
    5514 uid 6244,0
    5515 ro 90
    5516 va (VaSet
    5517 vasetType 1
    5518 fg "0,65535,0"
    5519 )
    5520 xt "1000,88625,1750,89375"
    5521 )
    5522 tg (CPTG
    5523 uid 6245,0
    5524 ps "CptPortTextPlaceStrategy"
    5525 stg "RightVerticalLayoutStrategy"
    5526 f (Text
    5527 uid 6246,0
    5528 va (VaSet
    5529 )
    5530 xt "-4600,88500,0,89500"
    5531 st "trigger_out"
    5532 ju 2
    5533 blo "0,89300"
    5534 )
    5535 )
    5536 thePort (LogicalPort
    5537 m 1
    5538 decl (Decl
    5539 n "trigger_out"
    5540 t "STD_LOGIC"
    5541 preAdd 0
    5542 posAdd 0
    5543 o 3
    5544 suid 3,0
    5545 i "'0'"
    5546 )
    5547 )
    5548 )
    5549 ]
    5550 shape (Rectangle
    5551 uid 6251,0
    5552 va (VaSet
    5553 vasetType 1
    5554 fg "0,65535,0"
    5555 lineColor "0,32896,0"
    5556 lineWidth 2
    5557 )
    5558 xt "-11000,87000,1000,92000"
    5559 )
    5560 oxt "25000,13000,37000,18000"
    5561 ttg (MlTextGroup
    5562 uid 6252,0
    5563 ps "CenterOffsetStrategy"
    5564 stg "VerticalLayoutStrategy"
    5565 textVec [
    5566 *175 (Text
    5567 uid 6253,0
    5568 va (VaSet
    5569 font "Arial,8,1"
    5570 )
    5571 xt "-10800,92000,-4200,93000"
    5572 st "FACT_FAD_LIB"
    5573 blo "-10800,92800"
    5574 tm "BdLibraryNameMgr"
    5575 )
    5576 *176 (Text
    5577 uid 6254,0
    5578 va (VaSet
    5579 font "Arial,8,1"
    5580 )
    5581 xt "-10800,93000,-6400,94000"
    5582 st "debouncer"
    5583 blo "-10800,93800"
    5584 tm "CptNameMgr"
    5585 )
    5586 *177 (Text
    5587 uid 6255,0
    5588 va (VaSet
    5589 font "Arial,8,1"
    5590 )
    5591 xt "-10800,94000,-5400,95000"
    5592 st "I_debouncer"
    5593 blo "-10800,94800"
    5594 tm "InstanceNameMgr"
    5595 )
    5596 ]
    5597 )
    5598 ga (GenericAssociation
    5599 uid 6256,0
    5600 ps "EdgeToEdgeStrategy"
    5601 matrix (Matrix
    5602 uid 6257,0
    5603 text (MLText
    5604 uid 6258,0
    5605 va (VaSet
    5606 font "Courier New,8,0"
    5607 )
    5608 xt "-11000,86200,4000,87000"
    5609 st "WIDTH = 17    ( INTEGER )  "
    5610 )
    5611 header ""
    5612 )
    5613 elements [
    5614 (GiElement
    5615 name "WIDTH"
    5616 type "INTEGER"
    5617 value "17"
    5618 )
    5619 ]
    5620 )
    5621 viewicon (ZoomableIcon
    5622 uid 6259,0
    5623 sl 0
    5624 va (VaSet
    5625 vasetType 1
    5626 fg "49152,49152,49152"
    5627 )
    5628 xt "-10750,90250,-9250,91750"
    5629 iconName "VhdlFileViewIcon.png"
    5630 iconMaskName "VhdlFileViewIcon.msk"
    5631 ftype 10
    5632 )
    5633 ordering 1
    5634 viewiconposition 0
    5635 portVis (PortSigDisplay
    5636 )
    5637 archFileType "UNKNOWN"
    5638 )
    5639 *178 (Net
    5640 uid 6278,0
    5641 decl (Decl
    5642 n "trigger_out"
    5643 t "STD_LOGIC"
    5644 preAdd 0
    5645 posAdd 0
    5646 o 60
    5647 suid 147,0
    5648 i "'0'"
    5649 )
    5650 declText (MLText
    5651 uid 6279,0
    5652 va (VaSet
    5653 font "Courier New,8,0"
    5654 )
    5655 xt "39000,52000,71500,52800"
    5656 st "SIGNAL trigger_out    : STD_LOGIC                      := '0'"
    5657 )
    5658 )
    5659 *179 (Net
    5660 uid 6326,0
    5661 decl (Decl
    5662 n "not_TEST_TRG"
    5663 t "STD_LOGIC"
    5664 o 58
    5665 suid 148,0
    5666 )
    5667 declText (MLText
    5668 uid 6327,0
    5669 va (VaSet
    5670 font "Courier New,8,0"
    5671 )
    5672 xt "39000,50400,57000,51200"
    5673 st "SIGNAL not_TEST_TRG   : STD_LOGIC"
    5674 )
    5675 )
    5676 *180 (MWC
    5677 uid 6539,0
    5678 optionalChildren [
    5679 *181 (CptPort
    5680 uid 6526,0
    5681 optionalChildren [
    5682 *182 (Line
    5683 uid 6530,0
    5684 layer 5
    5685 sl 0
    5686 va (VaSet
    5687 vasetType 3
    5688 )
    5689 xt "-22000,89000,-20999,89000"
    5690 pts [
    5691 "-22000,89000"
    5692 "-20999,89000"
    5693 ]
    5694 )
    5695 ]
    5696 ps "OnEdgeStrategy"
    5697 shape (Triangle
    5698 uid 6527,0
    5699 ro 90
    5700 va (VaSet
    5701 vasetType 1
    5702 isHidden 1
    5703 fg "0,65535,65535"
    5704 )
    5705 xt "-22750,88625,-22000,89375"
    5706 )
    5707 tg (CPTG
    5708 uid 6528,0
    5709 ps "CptPortTextPlaceStrategy"
    5710 stg "VerticalLayoutStrategy"
    5711 f (Text
    5712 uid 6529,0
    5713 sl 0
    5714 va (VaSet
    5715 isHidden 1
    5716 font "arial,8,0"
    5717 )
    5718 xt "-25000,88500,-23600,89500"
    5719 st "din"
    5720 blo "-25000,89300"
    5721 )
    5722 s (Text
    5723 uid 6548,0
    5724 sl 0
    5725 va (VaSet
    5726 font "arial,8,0"
    5727 )
    5728 xt "-25000,89500,-25000,89500"
    5729 blo "-25000,89500"
    5730 )
    5731 )
    5732 thePort (LogicalPort
    5733 decl (Decl
    5734 n "din"
    5735 t "std_logic"
    5736 o 11
    5737 suid 1,0
    5738 )
    5739 )
    5740 )
    5741 *183 (CptPort
    5742 uid 6531,0
    5743 optionalChildren [
    5744 *184 (Line
    5745 uid 6535,0
    5746 layer 5
    5747 sl 0
    5748 va (VaSet
    5749 vasetType 3
    5750 )
    5751 xt "-17249,89000,-17000,89000"
    5752 pts [
    5753 "-17000,89000"
    5754 "-17249,89000"
    5755 ]
    5756 )
    5757 *185 (Circle
    5758 uid 6536,0
    5759 va (VaSet
    5760 vasetType 1
    5761 fg "65535,65535,65535"
    5762 lineColor "26368,26368,26368"
    5763 )
    5764 xt "-17999,88625,-17249,89375"
    5765 radius 375
    5766 )
    5767 ]
    5768 ps "OnEdgeStrategy"
    5769 shape (Triangle
    5770 uid 6532,0
    5771 ro 90
    5772 va (VaSet
    5773 vasetType 1
    5774 isHidden 1
    5775 fg "0,65535,65535"
    5776 )
    5777 xt "-17000,88625,-16250,89375"
    5778 )
    5779 tg (CPTG
    5780 uid 6533,0
    5781 ps "CptPortTextPlaceStrategy"
    5782 stg "RightVerticalLayoutStrategy"
    5783 f (Text
    5784 uid 6534,0
    5785 sl 0
    5786 va (VaSet
    5787 isHidden 1
    5788 font "arial,8,0"
    5789 )
    5790 xt "-15050,88500,-13250,89500"
    5791 st "dout"
    5792 ju 2
    5793 blo "-13250,89300"
    5794 )
    5795 s (Text
    5796 uid 6549,0
    5797 sl 0
    5798 va (VaSet
    5799 font "arial,8,0"
    5800 )
    5801 xt "-13250,89500,-13250,89500"
    5802 ju 2
    5803 blo "-13250,89500"
    5804 )
    5805 )
    5806 thePort (LogicalPort
    5807 m 1
    5808 decl (Decl
    5809 n "dout"
    5810 t "STD_LOGIC"
    5811 o 58
    5812 suid 2,0
    5813 )
    5814 )
    5815 )
    5816 *186 (CommentGraphic
    5817 uid 6537,0
    5818 shape (CustomPolygon
    5819 pts [
    5820 "-21000,87000"
    5821 "-18000,89000"
    5822 "-21000,91000"
    5823 "-21000,87000"
    5824 ]
    5825 uid 6538,0
    5826 layer 0
    5827 sl 0
    5828 va (VaSet
    5829 vasetType 1
    5830 fg "0,65535,65535"
    5831 bg "0,65535,65535"
    5832 lineColor "26368,26368,26368"
    5833 )
    5834 xt "-21000,87000,-18000,91000"
    5835 )
    5836 oxt "7000,6000,10000,10000"
    5837 )
    5838 ]
    5839 shape (Rectangle
    5840 uid 6540,0
    5841 va (VaSet
    5842 vasetType 1
    5843 transparent 1
    5844 fg "0,65535,0"
    5845 lineColor "65535,65535,65535"
    5846 lineWidth -1
    5847 )
    5848 xt "-22000,87000,-17000,91000"
    5849 fos 1
    5850 )
    5851 showPorts 0
    5852 oxt "6000,6000,11000,10000"
    5853 ttg (MlTextGroup
    5854 uid 6541,0
    5855 ps "CenterOffsetStrategy"
    5856 stg "VerticalLayoutStrategy"
    5857 textVec [
    5858 *187 (Text
    5859 uid 6542,0
    5860 va (VaSet
    5861 isHidden 1
    5862 font "arial,8,0"
    5863 )
    5864 xt "-19650,89100,-14850,90100"
    5865 st "moduleware"
    5866 blo "-19650,89900"
    5867 )
    5868 *188 (Text
    5869 uid 6543,0
    5870 va (VaSet
    5871 font "arial,8,0"
    5872 )
    5873 xt "-19650,90100,-18350,91100"
    5874 st "inv"
    5875 blo "-19650,90900"
    5876 )
    5877 *189 (Text
    5878 uid 6544,0
    5879 va (VaSet
    5880 font "arial,8,0"
    5881 )
    5882 xt "-19650,91100,-18650,92100"
    5883 st "I1"
    5884 blo "-19650,91900"
    5885 tm "InstanceNameMgr"
    5886 )
    5887 ]
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    7836 xt "50250,68000,53350,69000"
    7837 st "CLK_50"
    7838 blo "50250,68800"
    7839 tm "WireNameMgr"
    7840 )
    7841 )
    7842 on &63
    7843 )
    7844 *261 (Wire
     7368on &108
     7369)
     7370*242 (Wire
    78457371uid 2409,0
    78467372shape (OrthoPolyLine
    … …  
    78567382)
    78577383start &36
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     7384end &64
    78597385sat 32
    78607386eat 32
    … …  
    78787404)
    78797405)
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    7881 )
    7882 *262 (Wire
     7406on &63
     7407)
     7408*243 (Wire
    78837409uid 2423,0
    78847410shape (OrthoPolyLine
    … …  
    78947420)
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    7896 end &94
     7422end &93
    78977423sat 32
    78987424eat 1
    … …  
    79167442)
    79177443)
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    7919 )
    7920 *263 (Wire
     7444on &65
     7445)
     7446*244 (Wire
    79217447uid 3009,0
    79227448shape (OrthoPolyLine
    … …  
    79327458)
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     7460end &126
    79357461sat 32
    79367462eat 32
    … …  
    79547480)
    79557481)
    7956 on &128
    7957 )
    7958 *264 (Wire
     7482on &127
     7483)
     7484*245 (Wire
    79597485uid 3015,0
    79607486shape (OrthoPolyLine
    … …  
    79707496)
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     7498end &135
    79737499sat 32
    79747500eat 32
    … …  
    79927518)
    79937519)
    7994 on &139
    7995 )
    7996 *265 (Wire
     7520on &138
     7521)
     7522*246 (Wire
    79977523uid 3021,0
    79987524shape (OrthoPolyLine
    … …  
    80097535)
    80107536start &40
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     7537end &114
    80127538sat 32
    80137539eat 1
    … …  
    80307556)
    80317557)
    8032 on &67
    8033 )
    8034 *266 (Wire
     7558on &66
     7559)
     7560*247 (Wire
    80357561uid 3027,0
    80367562shape (OrthoPolyLine
    … …  
    80457571]
    80467572)
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     7574end &113
    80497575ss 0
    80507576sat 32
    … …  
    80697595)
    80707596)
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    8072 )
    8073 *267 (Wire
     7597on &67
     7598)
     7599*248 (Wire
    80747600uid 3218,0
    80757601shape (OrthoPolyLine
    … …  
    80857611)
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     7613end &176
    80887614sat 32
    80897615eat 32
    … …  
    81077633)
    81087634)
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    8110 )
    8111 *268 (Wire
     7635on &70
     7636)
     7637*249 (Wire
    81127638uid 3260,0
    81137639shape (OrthoPolyLine
    … …  
    81237649]
    81247650)
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     7652end &71
    81277653sat 32
    81287654eat 2
    … …  
    81477673)
    81487674)
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    8150 )
    8151 *269 (Wire
     7675on &75
     7676)
     7677*250 (Wire
    81527678uid 3270,0
    81537679shape (OrthoPolyLine
    … …  
    81637689)
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     7691end &71
    81667692sat 32
    81677693eat 1
    … …  
    81837709)
    81847710)
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    8186 )
    8187 *270 (Wire
     7711on &76
     7712)
     7713*251 (Wire
    81887714uid 3318,0
    81897715shape (OrthoPolyLine
    … …  
    81997725]
    82007726)
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    8202 end &82
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     7728end &81
    82037729sat 32
    82047730eat 1
    … …  
    82237749)
    82247750)
    8225 on &90
    8226 )
    8227 *271 (Wire
     7751on &89
     7752)
     7753*252 (Wire
    82287754uid 3352,0
    82297755shape (OrthoPolyLine
    … …  
    82397765]
    82407766)
    8241 start &87
    8242 end &82
     7767start &86
     7768end &81
    82437769sat 32
    82447770eat 1
    … …  
    82637789)
    82647790)
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    8266 )
    8267 *272 (Wire
     7791on &90
     7792)
     7793*253 (Wire
    82687794uid 3360,0
    82697795shape (OrthoPolyLine
    … …  
    82797805]
    82807806)
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    8282 end &82
     7807start &87
     7808end &81
    82837809sat 32
    82847810eat 1
    … …  
    83037829)
    83047830)
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    8306 )
    8307 *273 (Wire
     7831on &91
     7832)
     7833*254 (Wire
    83087834uid 3368,0
    83097835shape (OrthoPolyLine
    … …  
    83197845]
    83207846)
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    8322 end &82
     7847start &88
     7848end &81
    83237849sat 32
    83247850eat 1
    … …  
    83437869)
    83447870)
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    8346 )
    8347 *274 (Wire
     7871on &92
     7872)
     7873*255 (Wire
    83487874uid 3430,0
    83497875shape (OrthoPolyLine
    … …  
    83587884]
    83597885)
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     7886start &161
     7887end &93
    83627888sat 32
    83637889eat 2
    … …  
    83817907)
    83827908)
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    8384 )
    8385 *275 (Wire
     7909on &97
     7910)
     7911*256 (Wire
    83867912uid 3438,0
    83877913shape (OrthoPolyLine
    … …  
    83967922]
    83977923)
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     7925end &93
    84007926sat 32
    84017927eat 2
    … …  
    84197945)
    84207946)
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    8422 )
    8423 *276 (Wire
     7947on &98
     7948)
     7949*257 (Wire
    84247950uid 3446,0
    84257951shape (OrthoPolyLine
    … …  
    84347960]
    84357961)
    8436 start &164
    8437 end &94
     7962start &163
     7963end &93
    84387964sat 32
    84397965eat 2
    … …  
    84577983)
    84587984)
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    8461 *277 (Wire
     7985on &99
     7986)
     7987*258 (Wire
    84627988uid 3454,0
    84637989shape (OrthoPolyLine
    … …  
    84727998]
    84737999)
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    8475 end &94
     8000start &164
     8001end &93
    84768002sat 32
    84778003eat 2
    … …  
    84958021)
    84968022)
    8497 on &101
    8498 )
    8499 *278 (Wire
     8023on &100
     8024)
     8025*259 (Wire
    85008026uid 3574,0
    85018027shape (OrthoPolyLine
    … …  
    85108036]
    85118037)
    8512 start &119
    8513 end &115
     8038start &118
     8039end &114
    85148040sat 32
    85158041eat 2
    … …  
    85338059)
    85348060)
    8535 on &123
    8536 )
    8537 *279 (Wire
     8061on &122
     8062)
     8063*260 (Wire
    85388064uid 3582,0
    85398065shape (OrthoPolyLine
    … …  
    85488074]
    85498075)
    8550 start &120
    8551 end &115
     8076start &119
     8077end &114
    85528078sat 32
    85538079eat 2
    … …  
    85718097)
    85728098)
    8573 on &124
    8574 )
    8575 *280 (Wire
     8099on &123
     8100)
     8101*261 (Wire
    85768102uid 3590,0
    85778103shape (OrthoPolyLine
    … …  
    85868112]
    85878113)
    8588 start &121
    8589 end &115
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     8115end &114
    85908116sat 32
    85918117eat 2
    … …  
    86098135)
    86108136)
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    8612 )
    8613 *281 (Wire
     8137on &124
     8138)
     8139*262 (Wire
    86148140uid 3598,0
    86158141shape (OrthoPolyLine
    … …  
    86248150]
    86258151)
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    8627 end &115
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     8153end &114
    86288154sat 32
    86298155eat 2
    … …  
    86478173)
    86488174)
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    8650 )
    8651 *282 (Wire
     8175on &125
     8176)
     8177*263 (Wire
    86528178uid 3682,0
    86538179shape (OrthoPolyLine
    … …  
    86638189)
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    8665 end &138
     8191end &137
    86668192sat 32
    86678193eat 32
    … …  
    86858211)
    86868212)
    8687 on &137
    8688 )
    8689 *283 (Wire
     8213on &136
     8214)
     8215*264 (Wire
    86908216uid 3778,0
    86918217shape (OrthoPolyLine
    … …  
    87008226]
    87018227)
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    8703 end &140
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     8229end &139
    87048230sat 32
    87058231eat 2
    … …  
    87238249)
    87248250)
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    8726 )
    8727 *284 (Wire
     8251on &152
     8252)
     8253*265 (Wire
    87288254uid 3786,0
    87298255shape (OrthoPolyLine
    … …  
    87388264]
    87398265)
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     8267end &139
    87428268sat 32
    87438269eat 2
    … …  
    87618287)
    87628288)
    8763 on &154
    8764 )
    8765 *285 (Wire
     8289on &153
     8290)
     8291*266 (Wire
    87668292uid 3794,0
    87678293shape (OrthoPolyLine
    … …  
    87768302]
    87778303)
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    8779 end &140
     8304start &145
     8305end &139
    87808306sat 32
    87818307eat 2
    … …  
    87998325)
    88008326)
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    8802 )
    8803 *286 (Wire
     8327on &154
     8328)
     8329*267 (Wire
    88048330uid 3802,0
    88058331shape (OrthoPolyLine
    … …  
    88148340]
    88158341)
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    8817 end &140
     8342start &146
     8343end &139
    88188344sat 32
    88198345eat 2
    … …  
    88378363)
    88388364)
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    8840 )
    8841 *287 (Wire
     8365on &155
     8366)
     8367*268 (Wire
    88428368uid 3810,0
    88438369shape (OrthoPolyLine
    … …  
    88528378]
    88538379)
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    8855 end &140
     8380start &147
     8381end &139
    88568382sat 32
    88578383eat 2
    … …  
    88758401)
    88768402)
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    8878 )
    8879 *288 (Wire
     8403on &156
     8404)
     8405*269 (Wire
    88808406uid 3826,0
    88818407shape (OrthoPolyLine
    … …  
    88908416]
    88918417)
    8892 start &150
    8893 end &140
     8418start &149
     8419end &139
    88948420sat 32
    88958421eat 2
    … …  
    89138439)
    89148440)
    8915 on &159
    8916 )
    8917 *289 (Wire
     8441on &158
     8442)
     8443*270 (Wire
    89188444uid 3834,0
    89198445shape (OrthoPolyLine
    … …  
    89288454]
    89298455)
    8930 start &151
    8931 end &140
     8456start &150
     8457end &139
    89328458sat 32
    89338459eat 2
    … …  
    89518477)
    89528478)
    8953 on &160
    8954 )
    8955 *290 (Wire
     8479on &159
     8480)
     8481*271 (Wire
    89568482uid 3842,0
    89578483shape (OrthoPolyLine
    … …  
    89678493]
    89688494)
    8969 start &152
    8970 end &140
     8495start &151
     8496end &139
    89718497sat 32
    89728498eat 2
    … …  
    89918517)
    89928518)
    8993 on &161
    8994 )
    8995 *291 (Wire
     8519on &160
     8520)
     8521*272 (Wire
    89968522uid 4942,0
    89978523shape (OrthoPolyLine
    … …  
    90088534)
    90098535start &14
    9010 end &166
     8536end &165
    90118537sat 32
    90128538eat 32
    … …  
    90318557)
    90328558)
    9033 on &167
    9034 )
    9035 *292 (Wire
     8559on &166
     8560)
     8561*273 (Wire
    90368562uid 6130,0
    90378563shape (OrthoPolyLine
    … …  
    90468572]
    90478573)
    9048 start &193
     8574start &173
    90498575end &15
    90508576sat 32
    … …  
    90678593)
    90688594)
    9069 on &170
    9070 )
    9071 *293 (Wire
    9072 uid 6288,0
    9073 shape (OrthoPolyLine
    9074 uid 6289,0
    9075 va (VaSet
    9076 vasetType 3
    9077 )
    9078 xt "1750,79000,13000,89000"
    9079 pts [
    9080 "1750,89000"
    9081 "9000,89000"
    9082 "9000,86000"
    9083 "9000,79000"
    9084 "13000,79000"
    9085 ]
    9086 )
    9087 start &174
    9088 end &191
    9089 sat 32
    9090 eat 32
    9091 st 0
    9092 sf 1
    9093 si 0
    9094 tg (WTG
    9095 uid 6294,0
    9096 ps "ConnStartEndStrategy"
    9097 stg "STSignalDisplayStrategy"
    9098 f (Text
    9099 uid 6295,0
    9100 va (VaSet
    9101 )
    9102 xt "4000,88000,8600,89000"
    9103 st "trigger_out"
    9104 blo "4000,88800"
    9105 tm "WireNameMgr"
    9106 )
    9107 )
    9108 on &178
    9109 )
    9110 *294 (Wire
     8595on &169
     8596)
     8597*274 (Wire
    91118598uid 6306,0
    91128599shape (OrthoPolyLine
    … …  
    91158602vasetType 3
    91168603)
    9117 xt "-28000,89000,-22000,89000"
    9118 pts [
    9119 "-28000,89000"
    9120 "-22000,89000"
    9121 ]
    9122 )
    9123 start &168
    9124 end &181
    9125 es 0
     8604xt "11000,79000,13000,79000"
     8605pts [
     8606"11000,79000"
     8607"13000,79000"
     8608]
     8609)
     8610start &167
     8611end &171
    91268612sat 32
    91278613eat 32
     8614stc 0
    91288615st 0
    91298616sf 1
    … …  
    91368623uid 6313,0
    91378624va (VaSet
    9138 )
    9139 xt "-26000,88000,-21500,89000"
     8625isHidden 1
     8626)
     8627xt "13000,78000,17500,79000"
    91408628st "TEST_TRG"
    9141 blo "-26000,88800"
     8629blo "13000,78800"
    91428630tm "WireNameMgr"
    91438631)
    91448632)
    9145 on &169
    9146 )
    9147 *295 (Wire
    9148 uid 6328,0
    9149 shape (OrthoPolyLine
    9150 uid 6329,0
    9151 va (VaSet
    9152 vasetType 3
    9153 )
    9154 xt "-17000,89000,-11750,89000"
    9155 pts [
    9156 "-17000,89000"
    9157 "-11750,89000"
    9158 ]
    9159 )
    9160 start &183
    9161 end &173
    9162 sat 32
    9163 eat 32
    9164 st 0
    9165 sf 1
    9166 si 0
    9167 tg (WTG
    9168 uid 6334,0
    9169 ps "ConnStartEndStrategy"
    9170 stg "STSignalDisplayStrategy"
    9171 f (Text
    9172 uid 6335,0
    9173 va (VaSet
    9174 )
    9175 xt "-18000,92000,-11700,93000"
    9176 st "not_TEST_TRG"
    9177 blo "-18000,92800"
    9178 tm "WireNameMgr"
    9179 )
    9180 )
    9181 on &179
    9182 )
    9183 *296 (Wire
     8633on &168
     8634)
     8635*275 (Wire
    91848636uid 6431,0
    91858637shape (OrthoPolyLine
    … …  
    91958647)
    91968648start &43
    9197 end &149
     8649end &148
    91988650sat 32
    91998651eat 32
    … …  
    92178669)
    92188670)
    9219 on &158
    9220 )
    9221 *297 (Wire
     8671on &157
     8672)
     8673*276 (Wire
    92228674uid 6787,0
    92238675shape (OrthoPolyLine
    … …  
    92338685]
    92348686)
    9235 start &213
    9236 end &217
     8687start &193
     8688end &197
    92378689sat 32
    92388690eat 1
    … …  
    92568708)
    92578709)
    9258 on &214
    9259 )
    9260 *298 (Wire
     8710on &194
     8711)
     8712*277 (Wire
    92618713uid 6880,0
    92628714shape (OrthoPolyLine
    … …  
    92728724]
    92738725)
    9274 start &217
    9275 end &215
     8726start &197
     8727end &195
    92768728sat 2
    92778729eat 32
    … …  
    92958747)
    92968748)
    9297 on &216
    9298 )
    9299 *299 (Wire
    9300 uid 7102,0
    9301 shape (OrthoPolyLine
    9302 uid 7103,0
    9303 va (VaSet
    9304 vasetType 3
    9305 )
    9306 xt "21000,132000,31000,132000"
    9307 pts [
    9308 "21000,132000"
    9309 "31000,132000"
    9310 ]
    9311 )
    9312 end &221
    9313 sat 16
    9314 eat 1
    9315 st 0
    9316 sf 1
    9317 si 0
    9318 tg (WTG
    9319 uid 7108,0
    9320 ps "ConnStartEndStrategy"
    9321 stg "STSignalDisplayStrategy"
    9322 f (Text
    9323 uid 7109,0
    9324 va (VaSet
    9325 )
    9326 xt "23000,131000,27600,132000"
    9327 st "D0_SROUT"
    9328 blo "23000,131800"
    9329 tm "WireNameMgr"
    9330 )
    9331 )
    9332 on &106
    9333 )
    9334 *300 (Wire
    9335 uid 7110,0
    9336 shape (OrthoPolyLine
    9337 uid 7111,0
    9338 va (VaSet
    9339 vasetType 3
    9340 )
    9341 xt "21000,133000,31000,133000"
    9342 pts [
    9343 "21000,133000"
    9344 "31000,133000"
    9345 ]
    9346 )
    9347 end &221
    9348 sat 16
    9349 eat 1
    9350 st 0
    9351 sf 1
    9352 si 0
    9353 tg (WTG
    9354 uid 7116,0
    9355 ps "ConnStartEndStrategy"
    9356 stg "STSignalDisplayStrategy"
    9357 f (Text
    9358 uid 7117,0
    9359 va (VaSet
    9360 )
    9361 xt "23000,132000,27600,133000"
    9362 st "D1_SROUT"
    9363 blo "23000,132800"
    9364 tm "WireNameMgr"
    9365 )
    9366 )
    9367 on &107
    9368 )
    9369 *301 (Wire
    9370 uid 7118,0
    9371 shape (OrthoPolyLine
    9372 uid 7119,0
    9373 va (VaSet
    9374 vasetType 3
    9375 )
    9376 xt "21000,134000,31000,134000"
    9377 pts [
    9378 "21000,134000"
    9379 "31000,134000"
    9380 ]
    9381 )
    9382 end &221
    9383 sat 16
    9384 eat 1
    9385 st 0
    9386 sf 1
    9387 si 0
    9388 tg (WTG
    9389 uid 7124,0
    9390 ps "ConnStartEndStrategy"
    9391 stg "STSignalDisplayStrategy"
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     8750)
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    … …  
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    … …  
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak

    r246 r252  
    2626instances [
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    … …  
    128105(vvPair
    129106variable "HDLDir"
    130 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl"
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    132109(vvPair
    133110variable "HDSDir"
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    135112)
    136113(vvPair
    137114variable "SideDataDesignDir"
    138 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
     115value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"
    139116)
    140117(vvPair
    141118variable "SideDataUserDir"
    142 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
     119value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"
    143120)
    144121(vvPair
    145122variable "SourceDir"
    146 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds"
     123value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    147124)
    148125(vvPair
    … …  
    160137(vvPair
    161138variable "d"
    162 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     139value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    163140)
    164141(vvPair
    165142variable "d_logical"
    166 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board"
     143value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    167144)
    168145(vvPair
    169146variable "date"
    170 value "22.06.2010"
     147value "14.07.2010"
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    172149(vvPair
    173150variable "day"
    174 value "Di"
     151value "Mi"
    175152)
    176153(vvPair
    177154variable "day_long"
    178 value "Dienstag"
     155value "Mittwoch"
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    180157(vvPair
    181158variable "dd"
    182 value "22"
     159value "14"
    183160)
    184161(vvPair
    … …  
    208185(vvPair
    209186variable "host"
    210 value "TU-CC4900F8C7D2"
     187value "E5B-LABOR6"
    211188)
    212189(vvPair
    … …  
    219196)
    220197(vvPair
     198variable "library_downstream_HdsLintPlugin"
     199value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     200)
     201(vvPair
    221202variable "library_downstream_ISEPARInvoke"
    222203value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
    … …  
    236217(vvPair
    237218variable "mm"
    238 value "06"
     219value "07"
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    240221(vvPair
    … …  
    244225(vvPair
    245226variable "month"
    246 value "Jun"
     227value "Jul"
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    248229(vvPair
    249230variable "month_long"
    250 value "Juni"
     231value "Juli"
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    252233(vvPair
    253234variable "p"
    254 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
     235value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"
    255236)
    256237(vvPair
    257238variable "p_logical"
    258 value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
     239value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"
    259240)
    260241(vvPair
    … …  
    312293(vvPair
    313294variable "time"
    314 value "11:16:21"
     295value "15:24:46"
    315296)
    316297(vvPair
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    … …  
    20832064t "std_logic_vector"
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    … …  
    24062387n "adc_data_array"
    24072388t "adc_data_array_type"
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    24202401*63 (Net
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    2439 *64 (Net
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    24432405t "std_logic"
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    25002462)
    25012463)
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     2464*65 (Net
    25032465uid 2421,0
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    25362498)
    25372499)
    2538 *68 (Net
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    25392501uid 3025,0
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     5026o 37
    50655027suid 132,0
    50665028)
    … …  
    50705032font "Courier New,8,0"
    50715033)
    5072 xt "39000,31800,53500,32600"
     5034xt "39000,32600,53500,33400"
    50735035st "SRIN           : std_logic"
    50745036)
    50755037)
    5076 *160 (Net
     5038*159 (Net
    50775039uid 3878,0
    50785040decl (Decl
    50795041n "EE_CS"
    50805042t "std_logic"
    5081 o 27
     5043o 28
    50825044suid 133,0
    50835045)
    … …  
    50875049font "Courier New,8,0"
    50885050)
    5089 xt "39000,24600,53500,25400"
     5051xt "39000,25400,53500,26200"
    50905052st "EE_CS          : std_logic"
    50915053)
    50925054)
    5093 *161 (Net
     5055*160 (Net
    50945056uid 3880,0
    50955057decl (Decl
    … …  
    50975059t "std_logic_vector"
    50985060b "( 2 DOWNTO 0 )"
    5099 o 28
     5061o 29
    51005062suid 134,0
    51015063i "(others => '1')"
    … …  
    51065068font "Courier New,8,0"
    51075069)
    5108 xt "39000,25400,74000,26200"
     5070xt "39000,26200,74000,27000"
    51095071st "LED            : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')"
    51105072)
    51115073)
    5112 *162 (PortIoOut
     5074*161 (PortIoOut
    51135075uid 3995,0
    51145076shape (CompositeShape
    … …  
    51555117)
    51565118)
    5157 *163 (PortIoOut
     5119*162 (PortIoOut
    51585120uid 4001,0
    51595121shape (CompositeShape
    … …  
    52005162)
    52015163)
    5202 *164 (PortIoOut
     5164*163 (PortIoOut
    52035165uid 4007,0
    52045166shape (CompositeShape
    … …  
    52455207)
    52465208)
    5247 *165 (PortIoOut
     5209*164 (PortIoOut
    52485210uid 4013,0
    52495211shape (CompositeShape
    … …  
    52905252)
    52915253)
    5292 *166 (PortIoOut
     5254*165 (PortIoOut
    52935255uid 4916,0
    52945256shape (CompositeShape
    … …  
    53345296)
    53355297)
    5336 *167 (Net
     5298*166 (Net
    53375299uid 5320,0
    53385300decl (Decl
    … …  
    53405302t "std_logic_vector"
    53415303b "(7 DOWNTO 0)"
    5342 o 25
     5304o 26
    53435305suid 141,0
    53445306i "(OTHERS => '0')"
    … …  
    53495311font "Courier New,8,0"
    53505312)
    5351 xt "39000,23000,74000,23800"
     5313xt "39000,23800,74000,24600"
    53525314st "D_T            : std_logic_vector(7 DOWNTO 0)   := (OTHERS => '0')"
    53535315)
    53545316)
    5355 *168 (PortIoIn
     5317*167 (PortIoIn
    53565318uid 5650,0
    53575319shape (CompositeShape
    … …  
    53665328sl 0
    53675329ro 270
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     5330xt "9000,78625,10500,79375"
    53695331)
    53705332(Line
    … …  
    53725334sl 0
    53735335ro 270
    5374 xt "-28500,89000,-28000,89000"
    5375 pts [
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    5377 "-28000,89000"
     5336xt "10500,79000,11000,79000"
     5337pts [
     5338"10500,79000"
     5339"11000,79000"
    53785340]
    53795341)
    … …  
    53905352va (VaSet
    53915353)
    5392 xt "-35500,88500,-31000,89500"
     5354xt "3500,78500,8000,79500"
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    53945356ju 2
    5395 blo "-31000,89300"
    5396 tm "WireNameMgr"
    5397 )
    5398 )
    5399 )
    5400 *169 (Net
     5357blo "8000,79300"
     5358tm "WireNameMgr"
     5359)
     5360)
     5361)
     5362*168 (Net
    54015363uid 5662,0
    54025364decl (Decl
    … …  
    54155377)
    54165378)
    5417 *170 (Net
     5379*169 (Net
    54185380uid 6138,0
    54195381decl (Decl
    54205382n "TRG_OR"
    54215383t "std_logic"
    5422 o 53
     5384o 54
    54235385suid 146,0
    54245386)
    … …  
    54285390font "Courier New,8,0"
    54295391)
    5430 xt "39000,46400,57000,47200"
     5392xt "39000,47200,57000,48000"
    54315393st "SIGNAL TRG_OR         : std_logic"
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    54335395)
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    5436 optionalChildren [
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    5441 uid 6236,0
    5442 ro 90
    5443 va (VaSet
    5444 vasetType 1
    5445 fg "0,65535,0"
    5446 )
    5447 xt "-11750,87625,-11000,88375"
    5448 )
    5449 tg (CPTG
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    5451 ps "CptPortTextPlaceStrategy"
    5452 stg "VerticalLayoutStrategy"
    5453 f (Text
    5454 uid 6238,0
    5455 va (VaSet
    5456 )
    5457 xt "-10000,87500,-8700,88500"
    5458 st "clk"
    5459 blo "-10000,88300"
    5460 )
    5461 )
    5462 thePort (LogicalPort
    5463 decl (Decl
    5464 n "clk"
    5465 t "STD_LOGIC"
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    5467 posAdd 0
    5468 o 1
    5469 suid 1,0
    5470 )
    5471 )
    5472 )
    5473 *173 (CptPort
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    5477 uid 6240,0
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    5480 vasetType 1
    5481 fg "0,65535,0"
    5482 )
    5483 xt "-11750,88625,-11000,89375"
    5484 )
    5485 tg (CPTG
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    5487 ps "CptPortTextPlaceStrategy"
    5488 stg "VerticalLayoutStrategy"
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    5490 uid 6242,0
    5491 va (VaSet
    5492 )
    5493 xt "-10000,88500,-5800,89500"
    5494 st "trigger_in"
    5495 blo "-10000,89300"
    5496 )
    5497 )
    5498 thePort (LogicalPort
    5499 decl (Decl
    5500 n "trigger_in"
    5501 t "STD_LOGIC"
    5502 prec "--           rst : in  STD_LOGIC;"
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    5504 posAdd 0
    5505 o 2
    5506 suid 2,0
    5507 )
    5508 )
    5509 )
    5510 *174 (CptPort
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    5512 ps "OnEdgeStrategy"
    5513 shape (Triangle
    5514 uid 6244,0
    5515 ro 90
    5516 va (VaSet
    5517 vasetType 1
    5518 fg "0,65535,0"
    5519 )
    5520 xt "1000,88625,1750,89375"
    5521 )
    5522 tg (CPTG
    5523 uid 6245,0
    5524 ps "CptPortTextPlaceStrategy"
    5525 stg "RightVerticalLayoutStrategy"
    5526 f (Text
    5527 uid 6246,0
    5528 va (VaSet
    5529 )
    5530 xt "-4600,88500,0,89500"
    5531 st "trigger_out"
    5532 ju 2
    5533 blo "0,89300"
    5534 )
    5535 )
    5536 thePort (LogicalPort
    5537 m 1
    5538 decl (Decl
    5539 n "trigger_out"
    5540 t "STD_LOGIC"
    5541 preAdd 0
    5542 posAdd 0
    5543 o 3
    5544 suid 3,0
    5545 i "'0'"
    5546 )
    5547 )
    5548 )
    5549 ]
    5550 shape (Rectangle
    5551 uid 6251,0
    5552 va (VaSet
    5553 vasetType 1
    5554 fg "0,65535,0"
    5555 lineColor "0,32896,0"
    5556 lineWidth 2
    5557 )
    5558 xt "-11000,87000,1000,92000"
    5559 )
    5560 oxt "25000,13000,37000,18000"
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    5563 ps "CenterOffsetStrategy"
    5564 stg "VerticalLayoutStrategy"
    5565 textVec [
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    5567 uid 6253,0
    5568 va (VaSet
    5569 font "Arial,8,1"
    5570 )
    5571 xt "-10800,92000,-4200,93000"
    5572 st "FACT_FAD_LIB"
    5573 blo "-10800,92800"
    5574 tm "BdLibraryNameMgr"
    5575 )
    5576 *176 (Text
    5577 uid 6254,0
    5578 va (VaSet
    5579 font "Arial,8,1"
    5580 )
    5581 xt "-10800,93000,-6400,94000"
    5582 st "debouncer"
    5583 blo "-10800,93800"
    5584 tm "CptNameMgr"
    5585 )
    5586 *177 (Text
    5587 uid 6255,0
    5588 va (VaSet
    5589 font "Arial,8,1"
    5590 )
    5591 xt "-10800,94000,-9800,95000"
    5592 st "I0"
    5593 blo "-10800,94800"
    5594 tm "InstanceNameMgr"
    5595 )
    5596 ]
    5597 )
    5598 ga (GenericAssociation
    5599 uid 6256,0
    5600 ps "EdgeToEdgeStrategy"
    5601 matrix (Matrix
    5602 uid 6257,0
    5603 text (MLText
    5604 uid 6258,0
    5605 va (VaSet
    5606 font "Courier New,8,0"
    5607 )
    5608 xt "-11000,86200,4000,87000"
    5609 st "WIDTH = 17    ( INTEGER )  "
    5610 )
    5611 header ""
    5612 )
    5613 elements [
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    5615 name "WIDTH"
    5616 type "INTEGER"
    5617 value "17"
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    5619 ]
    5620 )
    5621 viewicon (ZoomableIcon
    5622 uid 6259,0
    5623 sl 0
    5624 va (VaSet
    5625 vasetType 1
    5626 fg "49152,49152,49152"
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    5628 xt "-10750,90250,-9250,91750"
    5629 iconName "VhdlFileViewIcon.png"
    5630 iconMaskName "VhdlFileViewIcon.msk"
    5631 ftype 10
    5632 )
    5633 ordering 1
    5634 viewiconposition 0
    5635 portVis (PortSigDisplay
    5636 )
    5637 archFileType "UNKNOWN"
    5638 )
    5639 *178 (Net
    5640 uid 6278,0
    5641 decl (Decl
    5642 n "trigger_out"
    5643 t "STD_LOGIC"
    5644 preAdd 0
    5645 posAdd 0
    5646 o 60
    5647 suid 147,0
    5648 i "'0'"
    5649 )
    5650 declText (MLText
    5651 uid 6279,0
    5652 va (VaSet
    5653 font "Courier New,8,0"
    5654 )
    5655 xt "39000,52000,71500,52800"
    5656 st "SIGNAL trigger_out    : STD_LOGIC                      := '0'"
    5657 )
    5658 )
    5659 *179 (Net
    5660 uid 6326,0
    5661 decl (Decl
    5662 n "not_TEST_TRG"
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    5664 o 58
    5665 suid 148,0
    5666 )
    5667 declText (MLText
    5668 uid 6327,0
    5669 va (VaSet
    5670 font "Courier New,8,0"
    5671 )
    5672 xt "39000,50400,57000,51200"
    5673 st "SIGNAL not_TEST_TRG   : STD_LOGIC"
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    5675 )
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    5680 uid 6526,0
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    5684 layer 5
    5685 sl 0
    5686 va (VaSet
    5687 vasetType 3
    5688 )
    5689 xt "-22000,89000,-20999,89000"
    5690 pts [
    5691 "-22000,89000"
    5692 "-20999,89000"
    5693 ]
    5694 )
    5695 ]
    5696 ps "OnEdgeStrategy"
    5697 shape (Triangle
    5698 uid 6527,0
    5699 ro 90
    5700 va (VaSet
    5701 vasetType 1
    5702 isHidden 1
    5703 fg "0,65535,65535"
    5704 )
    5705 xt "-22750,88625,-22000,89375"
    5706 )
    5707 tg (CPTG
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    5709 ps "CptPortTextPlaceStrategy"
    5710 stg "VerticalLayoutStrategy"
    5711 f (Text
    5712 uid 6529,0
    5713 sl 0
    5714 va (VaSet
    5715 isHidden 1
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    5722 s (Text
    5723 uid 6548,0
    5724 sl 0
    5725 va (VaSet
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    5731 )
    5732 thePort (LogicalPort
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    5734 n "din"
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    5739 )
    5740 )
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    5753 "-17000,89000"
    5754 "-17249,89000"
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    5756 )
    5757 *185 (Circle
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    5759 va (VaSet
    5760 vasetType 1
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    5768 ps "OnEdgeStrategy"
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    5773 vasetType 1
    5774 isHidden 1
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    5779 tg (CPTG
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    5787 isHidden 1
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    5790 xt "-15050,88500,-13250,89500"
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     7343xt "21000,108000,51250,108000"
     7344pts [
     7345"21000,108000"
     7346"51250,108000"
     7347]
     7348)
     7349start &104
     7350end &35
     7351sat 32
     7352eat 32
     7353stc 0
     7354st 0
     7355sf 1
     7356si 0
     7357tg (WTG
     7358uid 1893,0
     7359ps "ConnStartEndStrategy"
     7360stg "STSignalDisplayStrategy"
     7361f (Text
     7362uid 1894,0
     7363va (VaSet
     7364isHidden 1
     7365)
     7366xt "22000,107000,26600,108000"
     7367st "D3_SROUT"
     7368blo "22000,107800"
     7369tm "WireNameMgr"
     7370)
     7371)
     7372on &108
     7373)
     7374*244 (Wire
     7375uid 2409,0
     7376shape (OrthoPolyLine
     7377uid 2410,0
     7378va (VaSet
     7379vasetType 3
     7380)
     7381xt "21000,111000,51250,111000"
     7382pts [
     7383"51250,111000"
     7384"21000,111000"
     7385]
     7386)
     7387start &36
     7388end &64
     7389sat 32
     7390eat 32
     7391stc 0
     7392st 0
     7393sf 1
     7394si 0
     7395tg (WTG
     7396uid 2413,0
     7397ps "ConnStartEndStrategy"
     7398stg "STSignalDisplayStrategy"
     7399f (Text
     7400uid 2414,0
     7401va (VaSet
     7402isHidden 1
     7403)
     7404xt "22000,110000,26200,111000"
     7405st "RSRLOAD"
     7406blo "22000,110800"
     7407tm "WireNameMgr"
     7408)
     7409)
     7410on &63
     7411)
     7412*245 (Wire
     7413uid 2423,0
     7414shape (OrthoPolyLine
     7415uid 2424,0
     7416va (VaSet
     7417vasetType 3
     7418)
     7419xt "32000,113000,51250,113000"
     7420pts [
     7421"51250,113000"
     7422"32000,113000"
     7423]
     7424)
     7425start &37
     7426end &93
     7427sat 32
     7428eat 1
     7429stc 0
     7430st 0
     7431sf 1
     7432si 0
     7433tg (WTG
     7434uid 2427,0
     7435ps "ConnStartEndStrategy"
     7436stg "STSignalDisplayStrategy"
     7437f (Text
     7438uid 2428,0
     7439va (VaSet
     7440isHidden 1
     7441)
     7442xt "66250,109000,69250,110000"
     7443st "SRCLK"
     7444blo "66250,109800"
     7445tm "WireNameMgr"
     7446)
     7447)
     7448on &65
     7449)
     7450*246 (Wire
     7451uid 3009,0
     7452shape (OrthoPolyLine
     7453uid 3010,0
     7454va (VaSet
     7455vasetType 3
     7456)
     7457xt "80750,98000,111000,98000"
     7458pts [
     7459"80750,98000"
     7460"111000,98000"
     7461]
     7462)
     7463start &39
     7464end &126
     7465sat 32
     7466eat 32
     7467stc 0
     7468st 0
     7469sf 1
     7470si 0
     7471tg (WTG
     7472uid 3011,0
     7473ps "ConnStartEndStrategy"
     7474stg "STSignalDisplayStrategy"
     7475f (Text
     7476uid 3012,0
     7477va (VaSet
     7478isHidden 1
     7479)
     7480xt "82000,97000,84800,98000"
     7481st "S_CLK"
     7482blo "82000,97800"
     7483tm "WireNameMgr"
     7484)
     7485)
     7486on &127
     7487)
     7488*247 (Wire
     7489uid 3015,0
     7490shape (OrthoPolyLine
     7491uid 3016,0
     7492va (VaSet
     7493vasetType 3
     7494)
     7495xt "80750,99000,111000,99000"
     7496pts [
     7497"80750,99000"
     7498"111000,99000"
     7499]
     7500)
     7501start &41
     7502end &135
     7503sat 32
     7504eat 32
     7505stc 0
     7506st 0
     7507sf 1
     7508si 0
     7509tg (WTG
     7510uid 3017,0
     7511ps "ConnStartEndStrategy"
     7512stg "STSignalDisplayStrategy"
     7513f (Text
     7514uid 3018,0
     7515va (VaSet
     7516isHidden 1
     7517)
     7518xt "82750,98000,85150,99000"
     7519st "MISO"
     7520blo "82750,98800"
     7521tm "WireNameMgr"
     7522)
     7523)
     7524on &138
     7525)
     7526*248 (Wire
     7527uid 3021,0
     7528shape (OrthoPolyLine
     7529uid 3022,0
     7530va (VaSet
     7531vasetType 3
     7532lineWidth 2
     7533)
     7534xt "80750,89000,100000,89000"
     7535pts [
     7536"80750,89000"
     7537"100000,89000"
     7538]
     7539)
     7540start &40
     7541end &114
     7542sat 32
     7543eat 1
     7544sty 1
     7545st 0
     7546sf 1
     7547si 0
     7548tg (WTG
     7549uid 3023,0
     7550ps "ConnStartEndStrategy"
     7551stg "STSignalDisplayStrategy"
     7552f (Text
     7553uid 3024,0
     7554va (VaSet
     7555)
     7556xt "92000,88000,98500,89000"
     7557st "sensor_cs : (3:0)"
     7558blo "92000,88800"
     7559tm "WireNameMgr"
     7560)
     7561)
     7562on &66
     7563)
     7564*249 (Wire
     7565uid 3027,0
     7566shape (OrthoPolyLine
     7567uid 3028,0
     7568va (VaSet
     7569vasetType 3
     7570)
     7571xt "94000,87000,111000,87000"
     7572pts [
     7573"94000,87000"
     7574"111000,87000"
     7575]
     7576)
     7577start &211
     7578end &113
     7579ss 0
     7580sat 32
     7581eat 32
     7582stc 0
     7583st 0
     7584sf 1
     7585si 0
     7586tg (WTG
     7587uid 3031,0
     7588ps "ConnStartEndStrategy"
     7589stg "STSignalDisplayStrategy"
     7590f (Text
     7591uid 3032,0
     7592va (VaSet
     7593isHidden 1
     7594)
     7595xt "95000,86000,98600,87000"
     7596st "DAC_CS"
     7597blo "95000,86800"
     7598tm "WireNameMgr"
     7599)
     7600)
     7601on &67
     7602)
     7603*250 (Wire
     7604uid 3218,0
     7605shape (OrthoPolyLine
     7606uid 3219,0
     7607va (VaSet
     7608vasetType 3
     7609)
     7610xt "11000,77000,13000,77000"
     7611pts [
     7612"11000,77000"
     7613"13000,77000"
     7614]
     7615)
     7616start &47
     7617end &176
     7618sat 32
     7619eat 32
     7620stc 0
     7621st 0
     7622sf 1
     7623si 0
     7624tg (WTG
     7625uid 3220,0
     7626ps "ConnStartEndStrategy"
     7627stg "STSignalDisplayStrategy"
     7628f (Text
     7629uid 3221,0
     7630va (VaSet
     7631isHidden 1
     7632)
     7633xt "22000,76000,24100,77000"
     7634st "TRG"
     7635blo "22000,76800"
     7636tm "WireNameMgr"
     7637)
     7638)
     7639on &70
     7640)
     7641*251 (Wire
     7642uid 3260,0
     7643shape (OrthoPolyLine
     7644uid 3261,0
     7645va (VaSet
     7646vasetType 3
     7647lineWidth 2
     7648)
     7649xt "21000,70000,24000,70000"
     7650pts [
     7651"21000,70000"
     7652"24000,70000"
     7653]
     7654)
     7655start &68
     7656end &71
     7657sat 32
     7658eat 2
     7659sty 1
     7660stc 0
     7661st 0
     7662sf 1
     7663si 0
     7664tg (WTG
     7665uid 3264,0
     7666ps "ConnStartEndStrategy"
     7667stg "STSignalDisplayStrategy"
     7668f (Text
     7669uid 3265,0
     7670va (VaSet
     7671isHidden 1
     7672)
     7673xt "23000,69000,25800,70000"
     7674st "A_CLK"
     7675blo "23000,69800"
     7676tm "WireNameMgr"
     7677)
     7678)
     7679on &75
     7680)
     7681*252 (Wire
     7682uid 3270,0
     7683shape (OrthoPolyLine
     7684uid 3271,0
     7685va (VaSet
     7686vasetType 3
     7687)
     7688xt "32000,70000,51250,70000"
     7689pts [
     7690"51250,70000"
     7691"32000,70000"
     7692]
     7693)
     7694start &25
     7695end &71
     7696sat 32
     7697eat 1
     7698st 0
     7699sf 1
     7700si 0
     7701tg (WTG
     7702uid 3274,0
     7703ps "ConnStartEndStrategy"
     7704stg "STSignalDisplayStrategy"
     7705f (Text
     7706uid 3275,0
     7707va (VaSet
     7708)
     7709xt "46000,69000,50500,70000"
     7710st "CLK_25_PS"
     7711blo "46000,69800"
     7712tm "WireNameMgr"
     7713)
     7714)
     7715on &76
     7716)
     7717*253 (Wire
     7718uid 3318,0
     7719shape (OrthoPolyLine
     7720uid 3319,0
     7721va (VaSet
     7722vasetType 3
     7723lineWidth 2
     7724)
     7725xt "21000,95000,24000,95000"
     7726pts [
     7727"21000,95000"
     7728"24000,95000"
     7729]
     7730)
     7731start &85
     7732end &81
     7733sat 32
     7734eat 1
     7735sty 1
     7736stc 0
     7737st 0
     7738sf 1
     7739si 0
     7740tg (WTG
     7741uid 3322,0
     7742ps "ConnStartEndStrategy"
     7743stg "STSignalDisplayStrategy"
     7744f (Text
     7745uid 3323,0
     7746va (VaSet
     7747isHidden 1
     7748)
     7749xt "23000,94000,25300,95000"
     7750st "A0_D"
     7751blo "23000,94800"
     7752tm "WireNameMgr"
     7753)
     7754)
     7755on &89
     7756)
     7757*254 (Wire
     7758uid 3352,0
     7759shape (OrthoPolyLine
     7760uid 3353,0
     7761va (VaSet
     7762vasetType 3
     7763lineWidth 2
     7764)
     7765xt "21000,96000,24000,96000"
     7766pts [
     7767"21000,96000"
     7768"24000,96000"
     7769]
     7770)
     7771start &86
     7772end &81
     7773sat 32
     7774eat 1
     7775sty 1
     7776stc 0
     7777st 0
     7778sf 1
     7779si 0
     7780tg (WTG
     7781uid 3356,0
     7782ps "ConnStartEndStrategy"
     7783stg "STSignalDisplayStrategy"
     7784f (Text
     7785uid 3357,0
     7786va (VaSet
     7787isHidden 1
     7788)
     7789xt "23000,95000,25300,96000"
     7790st "A1_D"
     7791blo "23000,95800"
     7792tm "WireNameMgr"
     7793)
     7794)
     7795on &90
     7796)
     7797*255 (Wire
     7798uid 3360,0
     7799shape (OrthoPolyLine
     7800uid 3361,0
     7801va (VaSet
     7802vasetType 3
     7803lineWidth 2
     7804)
     7805xt "21000,97000,24000,97000"
     7806pts [
     7807"21000,97000"
     7808"24000,97000"
     7809]
     7810)
     7811start &87
     7812end &81
     7813sat 32
     7814eat 1
     7815sty 1
     7816stc 0
     7817st 0
     7818sf 1
     7819si 0
     7820tg (WTG
     7821uid 3364,0
     7822ps "ConnStartEndStrategy"
     7823stg "STSignalDisplayStrategy"
     7824f (Text
     7825uid 3365,0
     7826va (VaSet
     7827isHidden 1
     7828)
     7829xt "23000,96000,25300,97000"
     7830st "A2_D"
     7831blo "23000,96800"
     7832tm "WireNameMgr"
     7833)
     7834)
     7835on &91
     7836)
     7837*256 (Wire
     7838uid 3368,0
     7839shape (OrthoPolyLine
     7840uid 3369,0
     7841va (VaSet
     7842vasetType 3
     7843lineWidth 2
     7844)
     7845xt "21000,98000,24000,98000"
     7846pts [
     7847"21000,98000"
     7848"24000,98000"
     7849]
     7850)
     7851start &88
     7852end &81
     7853sat 32
     7854eat 1
     7855sty 1
     7856stc 0
     7857st 0
     7858sf 1
     7859si 0
     7860tg (WTG
     7861uid 3372,0
     7862ps "ConnStartEndStrategy"
     7863stg "STSignalDisplayStrategy"
     7864f (Text
     7865uid 3373,0
     7866va (VaSet
     7867isHidden 1
     7868)
     7869xt "23000,97000,25300,98000"
     7870st "A3_D"
     7871blo "23000,97800"
     7872tm "WireNameMgr"
     7873)
     7874)
     7875on &92
     7876)
     7877*257 (Wire
     7878uid 3430,0
     7879shape (OrthoPolyLine
     7880uid 3431,0
     7881va (VaSet
     7882vasetType 3
     7883)
     7884xt "21000,113000,24000,113000"
     7885pts [
     7886"21000,113000"
     7887"24000,113000"
     7888]
     7889)
     7890start &161
     7891end &93
     7892sat 32
     7893eat 2
     7894stc 0
     7895st 0
     7896sf 1
     7897si 0
     7898tg (WTG
     7899uid 3434,0
     7900ps "ConnStartEndStrategy"
     7901stg "STSignalDisplayStrategy"
     7902f (Text
     7903uid 3435,0
     7904va (VaSet
     7905isHidden 1
     7906)
     7907xt "23000,112000,27400,113000"
     7908st "D0_SRCLK"
     7909blo "23000,112800"
     7910tm "WireNameMgr"
     7911)
     7912)
     7913on &97
     7914)
     7915*258 (Wire
     7916uid 3438,0
     7917shape (OrthoPolyLine
     7918uid 3439,0
     7919va (VaSet
     7920vasetType 3
     7921)
     7922xt "21000,114000,24000,114000"
     7923pts [
     7924"21000,114000"
     7925"24000,114000"
     7926]
     7927)
     7928start &162
     7929end &93
     7930sat 32
     7931eat 2
     7932stc 0
     7933st 0
     7934sf 1
     7935si 0
     7936tg (WTG
     7937uid 3442,0
     7938ps "ConnStartEndStrategy"
     7939stg "STSignalDisplayStrategy"
     7940f (Text
     7941uid 3443,0
     7942va (VaSet
     7943isHidden 1
     7944)
     7945xt "23000,113000,27400,114000"
     7946st "D1_SRCLK"
     7947blo "23000,113800"
     7948tm "WireNameMgr"
     7949)
     7950)
     7951on &98
     7952)
     7953*259 (Wire
     7954uid 3446,0
     7955shape (OrthoPolyLine
     7956uid 3447,0
     7957va (VaSet
     7958vasetType 3
     7959)
     7960xt "21000,115000,24000,115000"
     7961pts [
     7962"21000,115000"
     7963"24000,115000"
     7964]
     7965)
     7966start &163
     7967end &93
     7968sat 32
     7969eat 2
     7970stc 0
     7971st 0
     7972sf 1
     7973si 0
     7974tg (WTG
     7975uid 3450,0
     7976ps "ConnStartEndStrategy"
     7977stg "STSignalDisplayStrategy"
     7978f (Text
     7979uid 3451,0
     7980va (VaSet
     7981isHidden 1
     7982)
     7983xt "23000,114000,27400,115000"
     7984st "D2_SRCLK"
     7985blo "23000,114800"
     7986tm "WireNameMgr"
     7987)
     7988)
     7989on &99
     7990)
     7991*260 (Wire
     7992uid 3454,0
     7993shape (OrthoPolyLine
     7994uid 3455,0
     7995va (VaSet
     7996vasetType 3
     7997)
     7998xt "21000,116000,24000,116000"
     7999pts [
     8000"21000,116000"
     8001"24000,116000"
     8002]
     8003)
     8004start &164
     8005end &93
     8006sat 32
     8007eat 2
     8008stc 0
     8009st 0
     8010sf 1
     8011si 0
     8012tg (WTG
     8013uid 3458,0
     8014ps "ConnStartEndStrategy"
     8015stg "STSignalDisplayStrategy"
     8016f (Text
     8017uid 3459,0
     8018va (VaSet
     8019isHidden 1
     8020)
     8021xt "23000,115000,27400,116000"
     8022st "D3_SRCLK"
     8023blo "23000,115800"
     8024tm "WireNameMgr"
     8025)
     8026)
     8027on &100
     8028)
     8029*261 (Wire
     8030uid 3574,0
     8031shape (OrthoPolyLine
     8032uid 3575,0
     8033va (VaSet
     8034vasetType 3
     8035)
     8036xt "108000,89000,111000,89000"
     8037pts [
     8038"111000,89000"
     8039"108000,89000"
     8040]
     8041)
     8042start &118
     8043end &114
     8044sat 32
     8045eat 2
     8046stc 0
     8047st 0
     8048sf 1
     8049si 0
     8050tg (WTG
     8051uid 3578,0
     8052ps "ConnStartEndStrategy"
     8053stg "STSignalDisplayStrategy"
     8054f (Text
     8055uid 3579,0
     8056va (VaSet
     8057isHidden 1
     8058)
     8059xt "108000,88000,110800,89000"
     8060st "T0_CS"
     8061blo "108000,88800"
     8062tm "WireNameMgr"
     8063)
     8064)
     8065on &122
     8066)
     8067*262 (Wire
     8068uid 3582,0
     8069shape (OrthoPolyLine
     8070uid 3583,0
     8071va (VaSet
     8072vasetType 3
     8073)
     8074xt "108000,90000,111000,90000"
     8075pts [
     8076"111000,90000"
     8077"108000,90000"
     8078]
     8079)
     8080start &119
     8081end &114
     8082sat 32
     8083eat 2
     8084stc 0
     8085st 0
     8086sf 1
     8087si 0
     8088tg (WTG
     8089uid 3586,0
     8090ps "ConnStartEndStrategy"
     8091stg "STSignalDisplayStrategy"
     8092f (Text
     8093uid 3587,0
     8094va (VaSet
     8095isHidden 1
     8096)
     8097xt "108000,89000,110800,90000"
     8098st "T1_CS"
     8099blo "108000,89800"
     8100tm "WireNameMgr"
     8101)
     8102)
     8103on &123
     8104)
     8105*263 (Wire
     8106uid 3590,0
     8107shape (OrthoPolyLine
     8108uid 3591,0
     8109va (VaSet
     8110vasetType 3
     8111)
     8112xt "108000,91000,111000,91000"
     8113pts [
     8114"111000,91000"
     8115"108000,91000"
     8116]
     8117)
     8118start &120
     8119end &114
     8120sat 32
     8121eat 2
     8122stc 0
     8123st 0
     8124sf 1
     8125si 0
     8126tg (WTG
     8127uid 3594,0
     8128ps "ConnStartEndStrategy"
     8129stg "STSignalDisplayStrategy"
     8130f (Text
     8131uid 3595,0
     8132va (VaSet
     8133isHidden 1
     8134)
     8135xt "108000,90000,110800,91000"
     8136st "T2_CS"
     8137blo "108000,90800"
     8138tm "WireNameMgr"
     8139)
     8140)
     8141on &124
     8142)
     8143*264 (Wire
     8144uid 3598,0
     8145shape (OrthoPolyLine
     8146uid 3599,0
     8147va (VaSet
     8148vasetType 3
     8149)
     8150xt "108000,92000,111000,92000"
     8151pts [
     8152"111000,92000"
     8153"108000,92000"
     8154]
     8155)
     8156start &121
     8157end &114
     8158sat 32
     8159eat 2
     8160stc 0
     8161st 0
     8162sf 1
     8163si 0
     8164tg (WTG
     8165uid 3602,0
     8166ps "ConnStartEndStrategy"
     8167stg "STSignalDisplayStrategy"
     8168f (Text
     8169uid 3603,0
     8170va (VaSet
     8171isHidden 1
     8172)
     8173xt "108000,91000,110800,92000"
     8174st "T3_CS"
     8175blo "108000,91800"
     8176tm "WireNameMgr"
     8177)
     8178)
     8179on &125
     8180)
     8181*265 (Wire
     8182uid 3682,0
     8183shape (OrthoPolyLine
     8184uid 3683,0
     8185va (VaSet
     8186vasetType 3
     8187)
     8188xt "80750,100000,111000,100000"
     8189pts [
     8190"80750,100000"
     8191"111000,100000"
     8192]
     8193)
     8194start &42
     8195end &137
     8196sat 32
     8197eat 32
     8198stc 0
     8199st 0
     8200sf 1
     8201si 0
     8202tg (WTG
     8203uid 3686,0
     8204ps "ConnStartEndStrategy"
     8205stg "STSignalDisplayStrategy"
     8206f (Text
     8207uid 3687,0
     8208va (VaSet
     8209isHidden 1
     8210)
     8211xt "82000,99000,84400,100000"
     8212st "MOSI"
     8213blo "82000,99800"
     8214tm "WireNameMgr"
     8215)
     8216)
     8217on &136
     8218)
     8219*266 (Wire
     8220uid 3778,0
     8221shape (OrthoPolyLine
     8222uid 3779,0
     8223va (VaSet
     8224vasetType 3
     8225)
     8226xt "108000,103000,111000,103000"
     8227pts [
     8228"111000,103000"
     8229"108000,103000"
     8230]
     8231)
     8232start &143
     8233end &139
     8234sat 32
     8235eat 2
     8236stc 0
     8237st 0
     8238sf 1
     8239si 0
     8240tg (WTG
     8241uid 3782,0
     8242ps "ConnStartEndStrategy"
     8243stg "STSignalDisplayStrategy"
     8244f (Text
     8245uid 3783,0
     8246va (VaSet
     8247isHidden 1
     8248)
     8249xt "108000,102000,111000,103000"
     8250st "TRG_V"
     8251blo "108000,102800"
     8252tm "WireNameMgr"
     8253)
     8254)
     8255on &152
     8256)
     8257*267 (Wire
     8258uid 3786,0
     8259shape (OrthoPolyLine
     8260uid 3787,0
     8261va (VaSet
     8262vasetType 3
     8263)
     8264xt "108000,104000,111000,104000"
     8265pts [
     8266"111000,104000"
     8267"108000,104000"
     8268]
     8269)
     8270start &144
     8271end &139
     8272sat 32
     8273eat 2
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     8275st 0
     8276sf 1
     8277si 0
     8278tg (WTG
     8279uid 3790,0
     8280ps "ConnStartEndStrategy"
     8281stg "STSignalDisplayStrategy"
     8282f (Text
     8283uid 3791,0
     8284va (VaSet
     8285isHidden 1
     8286)
     8287xt "108000,103000,113600,104000"
     8288st "RS485_C_RE"
     8289blo "108000,103800"
     8290tm "WireNameMgr"
     8291)
     8292)
     8293on &153
     8294)
     8295*268 (Wire
     8296uid 3794,0
     8297shape (OrthoPolyLine
     8298uid 3795,0
     8299va (VaSet
     8300vasetType 3
     8301)
     8302xt "108000,105000,111000,105000"
     8303pts [
     8304"111000,105000"
     8305"108000,105000"
     8306]
     8307)
     8308start &145
     8309end &139
     8310sat 32
     8311eat 2
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     8313st 0
     8314sf 1
     8315si 0
     8316tg (WTG
     8317uid 3798,0
     8318ps "ConnStartEndStrategy"
     8319stg "STSignalDisplayStrategy"
     8320f (Text
     8321uid 3799,0
     8322va (VaSet
     8323isHidden 1
     8324)
     8325xt "108000,104000,113600,105000"
     8326st "RS485_C_DE"
     8327blo "108000,104800"
     8328tm "WireNameMgr"
     8329)
     8330)
     8331on &154
     8332)
     8333*269 (Wire
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     8335shape (OrthoPolyLine
     8336uid 3803,0
     8337va (VaSet
     8338vasetType 3
     8339)
     8340xt "108000,106000,111000,106000"
     8341pts [
     8342"111000,106000"
     8343"108000,106000"
     8344]
     8345)
     8346start &146
     8347end &139
     8348sat 32
     8349eat 2
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     8351st 0
     8352sf 1
     8353si 0
     8354tg (WTG
     8355uid 3806,0
     8356ps "ConnStartEndStrategy"
     8357stg "STSignalDisplayStrategy"
     8358f (Text
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     8360va (VaSet
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     8362)
     8363xt "108000,105000,113500,106000"
     8364st "RS485_E_RE"
     8365blo "108000,105800"
     8366tm "WireNameMgr"
     8367)
     8368)
     8369on &155
     8370)
     8371*270 (Wire
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     8373shape (OrthoPolyLine
     8374uid 3811,0
     8375va (VaSet
     8376vasetType 3
     8377)
     8378xt "108000,107000,111000,107000"
     8379pts [
     8380"111000,107000"
     8381"108000,107000"
     8382]
     8383)
     8384start &147
     8385end &139
     8386sat 32
     8387eat 2
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     8389st 0
     8390sf 1
     8391si 0
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     8393uid 3814,0
     8394ps "ConnStartEndStrategy"
     8395stg "STSignalDisplayStrategy"
     8396f (Text
     8397uid 3815,0
     8398va (VaSet
     8399isHidden 1
     8400)
     8401xt "108000,106000,113500,107000"
     8402st "RS485_E_DE"
     8403blo "108000,106800"
     8404tm "WireNameMgr"
     8405)
     8406)
     8407on &156
     8408)
     8409*271 (Wire
     8410uid 3826,0
     8411shape (OrthoPolyLine
     8412uid 3827,0
     8413va (VaSet
     8414vasetType 3
     8415)
     8416xt "108000,109000,111000,109000"
     8417pts [
     8418"111000,109000"
     8419"108000,109000"
     8420]
     8421)
     8422start &149
     8423end &139
     8424sat 32
     8425eat 2
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     8427st 0
     8428sf 1
     8429si 0
     8430tg (WTG
     8431uid 3830,0
     8432ps "ConnStartEndStrategy"
     8433stg "STSignalDisplayStrategy"
     8434f (Text
     8435uid 3831,0
     8436va (VaSet
     8437isHidden 1
     8438)
     8439xt "108000,108000,110300,109000"
     8440st "SRIN"
     8441blo "108000,108800"
     8442tm "WireNameMgr"
     8443)
     8444)
     8445on &158
     8446)
     8447*272 (Wire
     8448uid 3834,0
     8449shape (OrthoPolyLine
     8450uid 3835,0
     8451va (VaSet
     8452vasetType 3
     8453)
     8454xt "108000,110000,111000,110000"
     8455pts [
     8456"111000,110000"
     8457"108000,110000"
     8458]
     8459)
     8460start &150
     8461end &139
     8462sat 32
     8463eat 2
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     8465st 0
     8466sf 1
     8467si 0
     8468tg (WTG
     8469uid 3838,0
     8470ps "ConnStartEndStrategy"
     8471stg "STSignalDisplayStrategy"
     8472f (Text
     8473uid 3839,0
     8474va (VaSet
     8475isHidden 1
     8476)
     8477xt "108000,109000,110900,110000"
     8478st "EE_CS"
     8479blo "108000,109800"
     8480tm "WireNameMgr"
     8481)
     8482)
     8483on &159
     8484)
     8485*273 (Wire
     8486uid 3842,0
     8487shape (OrthoPolyLine
     8488uid 3843,0
     8489va (VaSet
     8490vasetType 3
     8491lineWidth 2
     8492)
     8493xt "108000,111000,111000,111000"
     8494pts [
     8495"111000,111000"
     8496"108000,111000"
     8497]
     8498)
     8499start &151
     8500end &139
     8501sat 32
     8502eat 2
     8503sty 1
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     8505st 0
     8506sf 1
     8507si 0
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     8509uid 3846,0
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     8511stg "STSignalDisplayStrategy"
     8512f (Text
     8513uid 3847,0
     8514va (VaSet
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     8516)
     8517xt "108000,110000,109900,111000"
     8518st "LED"
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     8520tm "WireNameMgr"
     8521)
     8522)
     8523on &160
     8524)
     8525*274 (Wire
     8526uid 4942,0
     8527shape (OrthoPolyLine
     8528uid 4943,0
     8529va (VaSet
     8530vasetType 3
     8531lineWidth 2
     8532)
     8533xt "80750,120000,111000,120000"
     8534pts [
     8535"80750,120000"
     8536"111000,120000"
     8537]
     8538)
     8539start &14
     8540end &165
    75908541sat 32
    75918542eat 32
    … …  
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     8549uid 4948,0
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    7602 uid 1838,0
     8553uid 4949,0
    76038554va (VaSet
    76048555isHidden 1
    76058556)
    7606 xt "22000,108000,23900,109000"
    7607 st "D_A"
    7608 blo "22000,108800"
    7609 tm "WireNameMgr"
    7610 )
    7611 )
    7612 on &111
    7613 )
    7614 *255 (Wire
    7615 uid 1841,0
     8557xt "82750,117000,84650,118000"
     8558st "D_T"
     8559blo "82750,117800"
     8560tm "WireNameMgr"
     8561)
     8562)
     8563on &166
     8564)
     8565*275 (Wire
     8566uid 6130,0
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    7617 uid 1842,0
     8568uid 6131,0
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    76198570vasetType 3
    76208571)
    7621 xt "21000,110000,51250,110000"
    7622 pts [
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    7624 "21000,110000"
    7625 ]
    7626 )
    7627 start &31
    7628 end &112
     8572xt "19000,78000,51250,78000"
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     8574"19000,78000"
     8575"51250,78000"
     8576]
     8577)
     8578start &173
     8579end &15
     8580sat 32
     8581eat 32
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     8583sf 1
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     8586uid 6136,0
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     8588stg "STSignalDisplayStrategy"
     8589f (Text
     8590uid 6137,0
     8591va (VaSet
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     8593xt "21000,77000,24700,78000"
     8594st "TRG_OR"
     8595blo "21000,77800"
     8596tm "WireNameMgr"
     8597)
     8598)
     8599on &169
     8600)
     8601*276 (Wire
     8602uid 6306,0
     8603shape (OrthoPolyLine
     8604uid 6307,0
     8605va (VaSet
     8606vasetType 3
     8607)
     8608xt "11000,79000,13000,79000"
     8609pts [
     8610"11000,79000"
     8611"13000,79000"
     8612]
     8613)
     8614start &167
     8615end &171
    76298616sat 32
    76308617eat 32
    … …  
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    76358622tg (WTG
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     8623uid 6312,0
    76378624ps "ConnStartEndStrategy"
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     8627uid 6313,0
    76418628va (VaSet
    76428629isHidden 1
    76438630)
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    7645 st "DWRITE"
    7646 blo "22000,109800"
    7647 tm "WireNameMgr"
    7648 )
    7649 )
    7650 on &113
    7651 )
    7652 *256 (Wire
    7653 uid 1865,0
     8631xt "13000,78000,17500,79000"
     8632st "TEST_TRG"
     8633blo "13000,78800"
     8634tm "WireNameMgr"
     8635)
     8636)
     8637on &168
     8638)
     8639*277 (Wire
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    7655 uid 1866,0
     8642uid 6432,0
    76568643va (VaSet
    76578644vasetType 3
    76588645)
    7659 xt "21000,105000,51250,105000"
    7660 pts [
    7661 "21000,105000"
    7662 "51250,105000"
    7663 ]
    7664 )
    7665 start &102
    7666 end &32
     8646xt "80750,121000,111000,121000"
     8647pts [
     8648"80750,121000"
     8649"111000,121000"
     8650]
     8651)
     8652start &43
     8653end &148
    76678654sat 32
    76688655eat 32
    … …  
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    76738660tg (WTG
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     8661uid 6435,0
    76758662ps "ConnStartEndStrategy"
    76768663stg "STSignalDisplayStrategy"
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    76798666va (VaSet
    76808667isHidden 1
    76818668)
    7682 xt "22000,104000,26600,105000"
    7683 st "D0_SROUT"
    7684 blo "22000,104800"
    7685 tm "WireNameMgr"
    7686 )
    7687 )
    7688 on &106
    7689 )
    7690 *257 (Wire
    7691 uid 1873,0
     8669xt "92000,120000,96000,121000"
     8670st "DENABLE"
     8671blo "92000,120800"
     8672tm "WireNameMgr"
     8673)
     8674)
     8675on &157
     8676)
     8677*278 (Wire
     8678uid 6787,0
    76928679shape (OrthoPolyLine
    7693 uid 1874,0
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    7698 pts [
    7699 "21000,106000"
    7700 "51250,106000"
    7701 ]
    7702 )
    7703 start &103
    7704 end &33
    7705 sat 32
    7706 eat 32
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    7708 st 0
    7709 sf 1
    7710 si 0
    7711 tg (WTG
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    7717 va (VaSet
    7718 isHidden 1
    7719 )
    7720 xt "22000,105000,26600,106000"
    7721 st "D1_SROUT"
    7722 blo "22000,105800"
    7723 tm "WireNameMgr"
    7724 )
    7725 )
    7726 on &107
    7727 )
    7728 *258 (Wire
    7729 uid 1881,0
    7730 shape (OrthoPolyLine
    7731 uid 1882,0
    7732 va (VaSet
    7733 vasetType 3
    7734 )
    7735 xt "21000,107000,51250,107000"
    7736 pts [
    7737 "21000,107000"
    7738 "51250,107000"
    7739 ]
    7740 )
    7741 start &104
    7742 end &34
    7743 sat 32
    7744 eat 32
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    7746 st 0
    7747 sf 1
    7748 si 0
    7749 tg (WTG
    7750 uid 1885,0
    7751 ps "ConnStartEndStrategy"
    7752 stg "STSignalDisplayStrategy"
    7753 f (Text
    7754 uid 1886,0
    7755 va (VaSet
    7756 isHidden 1
    7757 )
    7758 xt "22000,106000,26600,107000"
    7759 st "D2_SROUT"
    7760 blo "22000,106800"
    7761 tm "WireNameMgr"
    7762 )
    7763 )
    7764 on &108
    7765 )
    7766 *259 (Wire
    7767 uid 1889,0
    7768 shape (OrthoPolyLine
    7769 uid 1890,0
    7770 va (VaSet
    7771 vasetType 3
    7772 )
    7773 xt "21000,108000,51250,108000"
    7774 pts [
    7775 "21000,108000"
    7776 "51250,108000"
    7777 ]
    7778 )
    7779 start &105
    7780 end &35
    7781 sat 32
    7782 eat 32
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    7784 st 0
    7785 sf 1
    7786 si 0
    7787 tg (WTG
    7788 uid 1893,0
    7789 ps "ConnStartEndStrategy"
    7790 stg "STSignalDisplayStrategy"
    7791 f (Text
    7792 uid 1894,0
    7793 va (VaSet
    7794 isHidden 1
    7795 )
    7796 xt "22000,107000,26600,108000"
    7797 st "D3_SROUT"
    7798 blo "22000,107800"
    7799 tm "WireNameMgr"
    7800 )
    7801 )
    7802 on &109
    7803 )
    7804 *260 (Wire
    7805 uid 2269,0
    7806 shape (OrthoPolyLine
    7807 uid 2270,0
    7808 va (VaSet
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    7810 )
    7811 xt "-15000,69000,51250,88000"
    7812 pts [
    7813 "51250,69000"
    7814 "-15000,69000"
    7815 "-15000,88000"
    7816 "-11750,88000"
    7817 ]
    7818 )
    7819 start &26
    7820 end &172
    7821 sat 32
    7822 eat 32
    7823 stc 0
    7824 st 0
    7825 sf 1
    7826 si 0
    7827 tg (WTG
    7828 uid 2273,0
    7829 ps "ConnStartEndStrategy"
    7830 stg "STSignalDisplayStrategy"
    7831 f (Text
    7832 uid 2274,0
    7833 va (VaSet
    7834 isHidden 1
    7835 )
    7836 xt "50250,68000,53350,69000"
    7837 st "CLK_50"
    7838 blo "50250,68800"
    7839 tm "WireNameMgr"
    7840 )
    7841 )
    7842 on &63
    7843 )
    7844 *261 (Wire
    7845 uid 2409,0
    7846 shape (OrthoPolyLine
    7847 uid 2410,0
    7848 va (VaSet
    7849 vasetType 3
    7850 )
    7851 xt "21000,111000,51250,111000"
    7852 pts [
    7853 "51250,111000"
    7854 "21000,111000"
    7855 ]
    7856 )
    7857 start &36
    7858 end &65
    7859 sat 32
    7860 eat 32
    7861 stc 0
    7862 st 0
    7863 sf 1
    7864 si 0
    7865 tg (WTG
    7866 uid 2413,0
    7867 ps "ConnStartEndStrategy"
    7868 stg "STSignalDisplayStrategy"
    7869 f (Text
    7870 uid 2414,0
    7871 va (VaSet
    7872 isHidden 1
    7873 )
    7874 xt "22000,110000,26200,111000"
    7875 st "RSRLOAD"
    7876 blo "22000,110800"
    7877 tm "WireNameMgr"
    7878 )
    7879 )
    7880 on &64
    7881 )
    7882 *262 (Wire
    7883 uid 2423,0
    7884 shape (OrthoPolyLine
    7885 uid 2424,0
    7886 va (VaSet
    7887 vasetType 3
    7888 )
    7889 xt "32000,113000,51250,113000"
    7890 pts [
    7891 "51250,113000"
    7892 "32000,113000"
    7893 ]
    7894 )
    7895 start &37
    7896 end &94
    7897 sat 32
    7898 eat 1
    7899 stc 0
    7900 st 0
    7901 sf 1
    7902 si 0
    7903 tg (WTG
    7904 uid 2427,0
    7905 ps "ConnStartEndStrategy"
    7906 stg "STSignalDisplayStrategy"
    7907 f (Text
    7908 uid 2428,0
    7909 va (VaSet
    7910 isHidden 1
    7911 )
    7912 xt "66250,109000,69250,110000"
    7913 st "SRCLK"
    7914 blo "66250,109800"
    7915 tm "WireNameMgr"
    7916 )
    7917 )
    7918 on &66
    7919 )
    7920 *263 (Wire
    7921 uid 3009,0
    7922 shape (OrthoPolyLine
    7923 uid 3010,0
    7924 va (VaSet
    7925 vasetType 3
    7926 )
    7927 xt "80750,98000,111000,98000"
    7928 pts [
    7929 "80750,98000"
    7930 "111000,98000"
    7931 ]
    7932 )
    7933 start &39
    7934 end &127
    7935 sat 32
    7936 eat 32
    7937 stc 0
    7938 st 0
    7939 sf 1
    7940 si 0
    7941 tg (WTG
    7942 uid 3011,0
    7943 ps "ConnStartEndStrategy"
    7944 stg "STSignalDisplayStrategy"
    7945 f (Text
    7946 uid 3012,0
    7947 va (VaSet
    7948 isHidden 1
    7949 )
    7950 xt "82000,97000,84800,98000"
    7951 st "S_CLK"
    7952 blo "82000,97800"
    7953 tm "WireNameMgr"
    7954 )
    7955 )
    7956 on &128
    7957 )
    7958 *264 (Wire
    7959 uid 3015,0
    7960 shape (OrthoPolyLine
    7961 uid 3016,0
    7962 va (VaSet
    7963 vasetType 3
    7964 )
    7965 xt "80750,99000,111000,99000"
    7966 pts [
    7967 "80750,99000"
    7968 "111000,99000"
    7969 ]
    7970 )
    7971 start &41
    7972 end &136
    7973 sat 32
    7974 eat 32
    7975 stc 0
    7976 st 0
    7977 sf 1
    7978 si 0
    7979 tg (WTG
    7980 uid 3017,0
    7981 ps "ConnStartEndStrategy"
    7982 stg "STSignalDisplayStrategy"
    7983 f (Text
    7984 uid 3018,0
    7985 va (VaSet
    7986 isHidden 1
    7987 )
    7988 xt "82750,98000,85150,99000"
    7989 st "MISO"
    7990 blo "82750,98800"
    7991 tm "WireNameMgr"
    7992 )
    7993 )
    7994 on &139
    7995 )
    7996 *265 (Wire
    7997 uid 3021,0
    7998 shape (OrthoPolyLine
    7999 uid 3022,0
     8680uid 6788,0
    80008681va (VaSet
    80018682vasetType 3
    80028683lineWidth 2
    80038684)
    8004 xt "80750,89000,100000,89000"
    8005 pts [
    8006 "80750,89000"
    8007 "100000,89000"
    8008 ]
    8009 )
    8010 start &40
    8011 end &115
     8685xt "93000,132000,99000,132000"
     8686pts [
     8687"93000,132000"
     8688"99000,132000"
     8689]
     8690)
     8691start &193
     8692end &197
    80128693sat 32
    80138694eat 1
    … …  
    80178698si 0
    80188699tg (WTG
    8019 uid 3023,0
     8700uid 6791,0
    80208701ps "ConnStartEndStrategy"
    80218702stg "STSignalDisplayStrategy"
    80228703f (Text
    8023 uid 3024,0
    8024 va (VaSet
    8025 )
    8026 xt "92000,88000,98500,89000"
    8027 st "sensor_cs : (3:0)"
    8028 blo "92000,88800"
    8029 tm "WireNameMgr"
    8030 )
    8031 )
    8032 on &67
    8033 )
    8034 *266 (Wire
    8035 uid 3027,0
     8704uid 6792,0
     8705va (VaSet
     8706isHidden 1
     8707)
     8708xt "95000,131000,101800,132000"
     8709st "D_PLLLCK : (3:0)"
     8710blo "95000,131800"
     8711tm "WireNameMgr"
     8712)
     8713)
     8714on &194
     8715)
     8716*279 (Wire
     8717uid 6880,0
    80368718shape (OrthoPolyLine
    8037 uid 3028,0
    8038 va (VaSet
    8039 vasetType 3
    8040 )
    8041 xt "94000,87000,111000,87000"
    8042 pts [
    8043 "94000,87000"
    8044 "111000,87000"
    8045 ]
    8046 )
    8047 start &231
    8048 end &114
    8049 ss 0
    8050 sat 32
    8051 eat 32
    8052 stc 0
    8053 st 0
    8054 sf 1
    8055 si 0
    8056 tg (WTG
    8057 uid 3031,0
    8058 ps "ConnStartEndStrategy"
    8059 stg "STSignalDisplayStrategy"
    8060 f (Text
    8061 uid 3032,0
    8062 va (VaSet
    8063 isHidden 1
    8064 )
    8065 xt "95000,86000,98600,87000"
    8066 st "DAC_CS"
    8067 blo "95000,86800"
    8068 tm "WireNameMgr"
    8069 )
    8070 )
    8071 on &68
    8072 )
    8073 *267 (Wire
    8074 uid 3218,0
    8075 shape (OrthoPolyLine
    8076 uid 3219,0
    8077 va (VaSet
    8078 vasetType 3
    8079 )
    8080 xt "11000,77000,13000,77000"
    8081 pts [
    8082 "11000,77000"
    8083 "13000,77000"
    8084 ]
    8085 )
    8086 start &47
    8087 end &196
    8088 sat 32
    8089 eat 32
    8090 stc 0
    8091 st 0
    8092 sf 1
    8093 si 0
    8094 tg (WTG
    8095 uid 3220,0
    8096 ps "ConnStartEndStrategy"
    8097 stg "STSignalDisplayStrategy"
    8098 f (Text
    8099 uid 3221,0
    8100 va (VaSet
    8101 isHidden 1
    8102 )
    8103 xt "22000,76000,24100,77000"
    8104 st "TRG"
    8105 blo "22000,76800"
    8106 tm "WireNameMgr"
    8107 )
    8108 )
    8109 on &71
    8110 )
    8111 *268 (Wire
    8112 uid 3260,0
    8113 shape (OrthoPolyLine
    8114 uid 3261,0
     8719uid 6881,0
    81158720va (VaSet
    81168721vasetType 3
    81178722lineWidth 2
    81188723)
    8119 xt "21000,70000,24000,70000"
    8120 pts [
    8121 "21000,70000"
    8122 "24000,70000"
    8123 ]
    8124 )
    8125 start &69
    8126 end &72
    8127 sat 32
    8128 eat 2
     8724xt "102000,132000,109000,132000"
     8725pts [
     8726"102000,132000"
     8727"109000,132000"
     8728]
     8729)
     8730start &197
     8731end &195
     8732sat 2
     8733eat 32
    81298734sty 1
    8130 stc 0
    81318735st 0
    81328736sf 1
    81338737si 0
    81348738tg (WTG
    8135 uid 3264,0
     8739uid 6884,0
    81368740ps "ConnStartEndStrategy"
    81378741stg "STSignalDisplayStrategy"
    81388742f (Text
    8139 uid 3265,0
     8743uid 6885,0
    81408744va (VaSet
    81418745isHidden 1
    81428746)
    8143 xt "23000,69000,25800,70000"
    8144 st "A_CLK"
    8145 blo "23000,69800"
    8146 tm "WireNameMgr"
    8147 )
    8148 )
    8149 on &76
    8150 )
    8151 *269 (Wire
    8152 uid 3270,0
     8747xt "104000,131000,108900,132000"
     8748st "D_T2 : (3:0)"
     8749blo "104000,131800"
     8750tm "WireNameMgr"
     8751)
     8752)
     8753on &196
     8754)
     8755*280 (Wire
     8756uid 7144,0
    81538757shape (OrthoPolyLine
    8154 uid 3271,0
    8155 va (VaSet
    8156 vasetType 3
    8157 )
    8158 xt "32000,70000,51250,70000"
    8159 pts [
    8160 "51250,70000"
    8161 "32000,70000"
    8162 ]
    8163 )
    8164 start &25
    8165 end &72
    8166 sat 32
    8167 eat 1
    8168 st 0
    8169 sf 1
    8170 si 0
    8171 tg (WTG
    8172 uid 3274,0
    8173 ps "ConnStartEndStrategy"
    8174 stg "STSignalDisplayStrategy"
    8175 f (Text
    8176 uid 3275,0
    8177 va (VaSet
    8178 )
    8179 xt "46000,69000,50500,70000"
    8180 st "CLK_25_PS"
    8181 blo "46000,69800"
    8182 tm "WireNameMgr"
    8183 )
    8184 )
    8185 on &77
    8186 )
    8187 *270 (Wire
    8188 uid 3318,0
    8189 shape (OrthoPolyLine
    8190 uid 3319,0
     8758uid 7145,0
    81918759va (VaSet
    81928760vasetType 3
    81938761lineWidth 2
    81948762)
    8195 xt "21000,95000,24000,95000"
    8196 pts [
    8197 "21000,95000"
    8198 "24000,95000"
    8199 ]
    8200 )
    8201 start &86
    8202 end &82
    8203 sat 32
    8204 eat 1
    8205 sty 1
    8206 stc 0
    8207 st 0
    8208 sf 1
    8209 si 0
    8210 tg (WTG
    8211 uid 3322,0
    8212 ps "ConnStartEndStrategy"
    8213 stg "STSignalDisplayStrategy"
    8214 f (Text
    8215 uid 3323,0
    8216 va (VaSet
    8217 isHidden 1
    8218 )
    8219 xt "23000,94000,25300,95000"
    8220 st "A0_D"
    8221 blo "23000,94800"
    8222 tm "WireNameMgr"
    8223 )
    8224 )
    8225 on &90
    8226 )
    8227 *271 (Wire
    8228 uid 3352,0
    8229 shape (OrthoPolyLine
    8230 uid 3353,0
    8231 va (VaSet
    8232 vasetType 3
    8233 lineWidth 2
    8234 )
    8235 xt "21000,96000,24000,96000"
    8236 pts [
    8237 "21000,96000"
    8238 "24000,96000"
    8239 ]
    8240 )
    8241 start &87
    8242 end &82
    8243 sat 32
    8244 eat 1
    8245 sty 1
    8246 stc 0
    8247 st 0
    8248 sf 1
    8249 si 0
    8250 tg (WTG
    8251 uid 3356,0
    8252 ps "ConnStartEndStrategy"
    8253 stg "STSignalDisplayStrategy"
    8254 f (Text
    8255 uid 3357,0
    8256 va (VaSet
    8257 isHidden 1
    8258 )
    8259 xt "23000,95000,25300,96000"
    8260 st "A1_D"
    8261 blo "23000,95800"
    8262 tm "WireNameMgr"
    8263 )
    8264 )
    8265 on &91
    8266 )
    8267 *272 (Wire
    8268 uid 3360,0
    8269 shape (OrthoPolyLine
    8270 uid 3361,0
    8271 va (VaSet
    8272 vasetType 3
    8273 lineWidth 2
    8274 )
    8275 xt "21000,97000,24000,97000"
    8276 pts [
    8277 "21000,97000"
    8278 "24000,97000"
    8279 ]
    8280 )
    8281 start &88
    8282 end &82
    8283 sat 32
    8284 eat 1
    8285 sty 1
    8286 stc 0
    8287 st 0
    8288 sf 1
    8289 si 0
    8290 tg (WTG
    8291 uid 3364,0
    8292 ps "ConnStartEndStrategy"
    8293 stg "STSignalDisplayStrategy"
    8294 f (Text
    8295 uid 3365,0
    8296 va (VaSet
    8297 isHidden 1
    8298 )
    8299 xt "23000,96000,25300,97000"
    8300 st "A2_D"
    8301 blo "23000,96800"
    8302 tm "WireNameMgr"
    8303 )
    8304 )
    8305 on &92
    8306 )
    8307 *273 (Wire
    8308 uid 3368,0
    8309 shape (OrthoPolyLine
    8310 uid 3369,0
    8311 va (VaSet
    8312 vasetType 3
    8313 lineWidth 2
    8314 )
    8315 xt "21000,98000,24000,98000"
    8316 pts [
    8317 "21000,98000"
    8318 "24000,98000"
    8319 ]
    8320 )
    8321 start &89
    8322 end &82
    8323 sat 32
    8324 eat 1
    8325 sty 1
    8326 stc 0
    8327 st 0
    8328 sf 1
    8329 si 0
    8330 tg (WTG
    8331 uid 3372,0
    8332 ps "ConnStartEndStrategy"
    8333 stg "STSignalDisplayStrategy"
    8334 f (Text
    8335 uid 3373,0
    8336 va (VaSet
    8337 isHidden 1
    8338 )
    8339 xt "23000,97000,25300,98000"
    8340 st "A3_D"
    8341 blo "23000,97800"
    8342 tm "WireNameMgr"
    8343 )
    8344 )
    8345 on &93
    8346 )
    8347 *274 (Wire
    8348 uid 3430,0
    8349 shape (OrthoPolyLine
    8350 uid 3431,0
    8351 va (VaSet
    8352 vasetType 3
    8353 )
    8354 xt "21000,113000,24000,113000"
    8355 pts [
    8356 "21000,113000"
    8357 "24000,113000"
    8358 ]
    8359 )
    8360 start &162
    8361 end &94
    8362 sat 32
    8363 eat 2
    8364 stc 0
    8365 st 0
    8366 sf 1
    8367 si 0
    8368 tg (WTG
    8369 uid 3434,0
    8370 ps "ConnStartEndStrategy"
    8371 stg "STSignalDisplayStrategy"
    8372 f (Text
    8373 uid 3435,0
    8374 va (VaSet
    8375 isHidden 1
    8376 )
    8377 xt "23000,112000,27400,113000"
    8378 st "D0_SRCLK"
    8379 blo "23000,112800"
    8380 tm "WireNameMgr"
    8381 )
    8382 )
    8383 on &98
    8384 )
    8385 *275 (Wire
    8386 uid 3438,0
    8387 shape (OrthoPolyLine
    8388 uid 3439,0
    8389 va (VaSet
    8390 vasetType 3
    8391 )
    8392 xt "21000,114000,24000,114000"
    8393 pts [
    8394 "21000,114000"
    8395 "24000,114000"
    8396 ]
    8397 )
    8398 start &163
    8399 end &94
    8400 sat 32
    8401 eat 2
    8402 stc 0
    8403 st 0
    8404 sf 1
    8405 si 0
    8406 tg (WTG
    8407 uid 3442,0
    8408 ps "ConnStartEndStrategy"
    8409 stg "STSignalDisplayStrategy"
    8410 f (Text
    8411 uid 3443,0
    8412 va (VaSet
    8413 isHidden 1
    8414 )
    8415 xt "23000,113000,27400,114000"
    8416 st "D1_SRCLK"
    8417 blo "23000,113800"
    8418 tm "WireNameMgr"
    8419 )
    8420 )
    8421 on &99
    8422 )
    8423 *276 (Wire
    8424 uid 3446,0
    8425 shape (OrthoPolyLine
    8426 uid 3447,0
    8427 va (VaSet
    8428 vasetType 3
    8429 )
    8430 xt "21000,115000,24000,115000"
    8431 pts [
    8432 "21000,115000"
    8433 "24000,115000"
    8434 ]
    8435 )
    8436 start &164
    8437 end &94
    8438 sat 32
    8439 eat 2
    8440 stc 0
    8441 st 0
    8442 sf 1
    8443 si 0
    8444 tg (WTG
    8445 uid 3450,0
    8446 ps "ConnStartEndStrategy"
    8447 stg "STSignalDisplayStrategy"
    8448 f (Text
    8449 uid 3451,0
    8450 va (VaSet
    8451 isHidden 1
    8452 )
    8453 xt "23000,114000,27400,115000"
    8454 st "D2_SRCLK"
    8455 blo "23000,114800"
    8456 tm "WireNameMgr"
    8457 )
    8458 )
    8459 on &100
    8460 )
    8461 *277 (Wire
    8462 uid 3454,0
    8463 shape (OrthoPolyLine
    8464 uid 3455,0
    8465 va (VaSet
    8466 vasetType 3
    8467 )
    8468 xt "21000,116000,24000,116000"
    8469 pts [
    8470 "21000,116000"
    8471 "24000,116000"
    8472 ]
    8473 )
    8474 start &165
    8475 end &94
    8476 sat 32
    8477 eat 2
    8478 stc 0
    8479 st 0
    8480 sf 1
    8481 si 0
    8482 tg (WTG
    8483 uid 3458,0
    8484 ps "ConnStartEndStrategy"
    8485 stg "STSignalDisplayStrategy"
    8486 f (Text
    8487 uid 3459,0
    8488 va (VaSet
    8489 isHidden 1
    8490 )
    8491 xt "23000,115000,27400,116000"
    8492 st "D3_SRCLK"
    8493 blo "23000,115800"
    8494 tm "WireNameMgr"
    8495 )
    8496 )
    8497 on &101
    8498 )
    8499 *278 (Wire
    8500 uid 3574,0
    8501 shape (OrthoPolyLine
    8502 uid 3575,0
    8503 va (VaSet
    8504 vasetType 3
    8505 )
    8506 xt "108000,89000,111000,89000"
    8507 pts [
    8508 "111000,89000"
    8509 "108000,89000"
    8510 ]
    8511 )
    8512 start &119
    8513 end &115
    8514 sat 32
    8515 eat 2
    8516 stc 0
    8517 st 0
    8518 sf 1
    8519 si 0
    8520 tg (WTG
    8521 uid 3578,0
    8522 ps "ConnStartEndStrategy"
    8523 stg "STSignalDisplayStrategy"
    8524 f (Text
    8525 uid 3579,0
    8526 va (VaSet
    8527 isHidden 1
    8528 )
    8529 xt "108000,88000,110800,89000"
    8530 st "T0_CS"
    8531 blo "108000,88800"
    8532 tm "WireNameMgr"
    8533 )
    8534 )
    8535 on &123
    8536 )
    8537 *279 (Wire
    8538 uid 3582,0
    8539 shape (OrthoPolyLine
    8540 uid 3583,0
    8541 va (VaSet
    8542 vasetType 3
    8543 )
    8544 xt "108000,90000,111000,90000"
    8545 pts [
    8546 "111000,90000"
    8547 "108000,90000"
    8548 ]
    8549 )
    8550 start &120
    8551 end &115
    8552 sat 32
    8553 eat 2
    8554 stc 0
    8555 st 0
    8556 sf 1
    8557 si 0
    8558 tg (WTG
    8559 uid 3586,0
    8560 ps "ConnStartEndStrategy"
    8561 stg "STSignalDisplayStrategy"
    8562 f (Text
    8563 uid 3587,0
    8564 va (VaSet
    8565 isHidden 1
    8566 )
    8567 xt "108000,89000,110800,90000"
    8568 st "T1_CS"
    8569 blo "108000,89800"
    8570 tm "WireNameMgr"
    8571 )
    8572 )
    8573 on &124
    8574 )
    8575 *280 (Wire
    8576 uid 3590,0
    8577 shape (OrthoPolyLine
    8578 uid 3591,0
    8579 va (VaSet
    8580 vasetType 3
    8581 )
    8582 xt "108000,91000,111000,91000"
    8583 pts [
    8584 "111000,91000"
    8585 "108000,91000"
    8586 ]
    8587 )
    8588 start &121
    8589 end &115
    8590 sat 32
    8591 eat 2
    8592 stc 0
    8593 st 0
    8594 sf 1
    8595 si 0
    8596 tg (WTG
    8597 uid 3594,0
    8598 ps "ConnStartEndStrategy"
    8599 stg "STSignalDisplayStrategy"
    8600 f (Text
    8601 uid 3595,0
    8602 va (VaSet
    8603 isHidden 1
    8604 )
    8605 xt "108000,90000,110800,91000"
    8606 st "T2_CS"
    8607 blo "108000,90800"
    8608 tm "WireNameMgr"
    8609 )
    8610 )
    8611 on &125
    8612 )
    8613 *281 (Wire
    8614 uid 3598,0
    8615 shape (OrthoPolyLine
    8616 uid 3599,0
    8617 va (VaSet
    8618 vasetType 3
    8619 )
    8620 xt "108000,92000,111000,92000"
    8621 pts [
    8622 "111000,92000"
    8623 "108000,92000"
    8624 ]
    8625 )
    8626 start &122
    8627 end &115
    8628 sat 32
    8629 eat 2
    8630 stc 0
    8631 st 0
    8632 sf 1
    8633 si 0
    8634 tg (WTG
    8635 uid 3602,0
    8636 ps "ConnStartEndStrategy"
    8637 stg "STSignalDisplayStrategy"
    8638 f (Text
    8639 uid 3603,0
    8640 va (VaSet
    8641 isHidden 1
    8642 )
    8643 xt "108000,91000,110800,92000"
    8644 st "T3_CS"
    8645 blo "108000,91800"
    8646 tm "WireNameMgr"
    8647 )
    8648 )
    8649 on &126
    8650 )
    8651 *282 (Wire
    8652 uid 3682,0
    8653 shape (OrthoPolyLine
    8654 uid 3683,0
    8655 va (VaSet
    8656 vasetType 3
    8657 )
    8658 xt "80750,100000,111000,100000"
    8659 pts [
    8660 "80750,100000"
    8661 "111000,100000"
    8662 ]
    8663 )
    8664 start &42
    8665 end &138
    8666 sat 32
    8667 eat 32
    8668 stc 0
    8669 st 0
    8670 sf 1
    8671 si 0
    8672 tg (WTG
    8673 uid 3686,0
    8674 ps "ConnStartEndStrategy"
    8675 stg "STSignalDisplayStrategy"
    8676 f (Text
    8677 uid 3687,0
    8678 va (VaSet
    8679 isHidden 1
    8680 )
    8681 xt "82000,99000,84400,100000"
    8682 st "MOSI"
    8683 blo "82000,99800"
    8684 tm "WireNameMgr"
    8685 )
    8686 )
    8687 on &137
    8688 )
    8689 *283 (Wire
    8690 uid 3778,0
    8691 shape (OrthoPolyLine
    8692 uid 3779,0
    8693 va (VaSet
    8694 vasetType 3
    8695 )
    8696 xt "108000,103000,111000,103000"
    8697 pts [
    8698 "111000,103000"
    8699 "108000,103000"
    8700 ]
    8701 )
    8702 start &144
    8703 end &140
    8704 sat 32
    8705 eat 2
    8706 stc 0
    8707 st 0
    8708 sf 1
    8709 si 0
    8710 tg (WTG
    8711 uid 3782,0
    8712 ps "ConnStartEndStrategy"
    8713 stg "STSignalDisplayStrategy"
    8714 f (Text
    8715 uid 3783,0
    8716 va (VaSet
    8717 isHidden 1
    8718 )
    8719 xt "108000,102000,111000,103000"
    8720 st "TRG_V"
    8721 blo "108000,102800"
    8722 tm "WireNameMgr"
    8723 )
    8724 )
    8725 on &153
    8726 )
    8727 *284 (Wire
    8728 uid 3786,0
    8729 shape (OrthoPolyLine
    8730 uid 3787,0
    8731 va (VaSet
    8732 vasetType 3
    8733 )
    8734 xt "108000,104000,111000,104000"
    8735 pts [
    8736 "111000,104000"
    8737 "108000,104000"
    8738 ]
    8739 )
    8740 start &145
    8741 end &140
    8742 sat 32
    8743 eat 2
    8744 stc 0
    8745 st 0
    8746 sf 1
    8747 si 0
    8748 tg (WTG
    8749 uid 3790,0
    8750 ps "ConnStartEndStrategy"
    8751 stg "STSignalDisplayStrategy"
    8752 f (Text
    8753 uid 3791,0
    8754 va (VaSet
    8755 isHidden 1
    8756 )
    8757 xt "108000,103000,113600,104000"
    8758 st "RS485_C_RE"
    8759 blo "108000,103800"
    8760 tm "WireNameMgr"
    8761 )
    8762 )
    8763 on &154
    8764 )
    8765 *285 (Wire
    8766 uid 3794,0
    8767 shape (OrthoPolyLine
    8768 uid 3795,0
    8769 va (VaSet
    8770 vasetType 3
    8771 )
    8772 xt "108000,105000,111000,105000"
    8773 pts [
    8774 "111000,105000"
    8775 "108000,105000"
    8776 ]
    8777 )
    8778 start &146
    8779 end &140
    8780 sat 32
    8781 eat 2
    8782 stc 0
    8783 st 0
    8784 sf 1
    8785 si 0
    8786 tg (WTG
    8787 uid 3798,0
    8788 ps "ConnStartEndStrategy"
    8789 stg "STSignalDisplayStrategy"
    8790 f (Text
    8791 uid 3799,0
    8792 va (VaSet
    8793 isHidden 1
    8794 )
    8795 xt "108000,104000,113600,105000"
    8796 st "RS485_C_DE"
    8797 blo "108000,104800"
    8798 tm "WireNameMgr"
    8799 )
    8800 )
    8801 on &155
    8802 )
    8803 *286 (Wire
    8804 uid 3802,0
    8805 shape (OrthoPolyLine
    8806 uid 3803,0
    8807 va (VaSet
    8808 vasetType 3
    8809 )
    8810 xt "108000,106000,111000,106000"
    8811 pts [
    8812 "111000,106000"
    8813 "108000,106000"
    8814 ]
    8815 )
    8816 start &147
    8817 end &140
    8818 sat 32
    8819 eat 2
    8820 stc 0
    8821 st 0
    8822 sf 1
    8823 si 0
    8824 tg (WTG
    8825 uid 3806,0
    8826 ps "ConnStartEndStrategy"
    8827 stg "STSignalDisplayStrategy"
    8828 f (Text
    8829 uid 3807,0
    8830 va (VaSet
    8831 isHidden 1
    8832 )
    8833 xt "108000,105000,113500,106000"
    8834 st "RS485_E_RE"
    8835 blo "108000,105800"
    8836 tm "WireNameMgr"
    8837 )
    8838 )
    8839 on &156
    8840 )
    8841 *287 (Wire
    8842 uid 3810,0
    8843 shape (OrthoPolyLine
    8844 uid 3811,0
    8845 va (VaSet
    8846 vasetType 3
    8847 )
    8848 xt "108000,107000,111000,107000"
    8849 pts [
    8850 "111000,107000"
    8851 "108000,107000"
    8852 ]
    8853 )
    8854 start &148
    8855 end &140
    8856 sat 32
    8857 eat 2
    8858 stc 0
    8859 st 0
    8860 sf 1
    8861 si 0
    8862 tg (WTG
    8863 uid 3814,0
    8864 ps "ConnStartEndStrategy"
    8865 stg "STSignalDisplayStrategy"
    8866 f (Text
    8867 uid 3815,0
    8868 va (VaSet
    8869 isHidden 1
    8870 )
    8871 xt "108000,106000,113500,107000"
    8872 st "RS485_E_DE"
    8873 blo "108000,106800"
    8874 tm "WireNameMgr"
    8875 )
    8876 )
    8877 on &157
    8878 )
    8879 *288 (Wire
    8880 uid 3826,0
    8881 shape (OrthoPolyLine
    8882 uid 3827,0
    8883 va (VaSet
    8884 vasetType 3
    8885 )
    8886 xt "108000,109000,111000,109000"
    8887 pts [
    8888 "111000,109000"
    8889 "108000,109000"
    8890 ]
    8891 )
    8892 start &150
    8893 end &140
    8894 sat 32
    8895 eat 2
    8896 stc 0
    8897 st 0
    8898 sf 1
    8899 si 0
    8900 tg (WTG
    8901 uid 3830,0
    8902 ps "ConnStartEndStrategy"
    8903 stg "STSignalDisplayStrategy"
    8904 f (Text
    8905 uid 3831,0
    8906 va (VaSet
    8907 isHidden 1
    8908 )
    8909 xt "108000,108000,110300,109000"
    8910 st "SRIN"
    8911 blo "108000,108800"
    8912 tm "WireNameMgr"
    8913 )
    8914 )
    8915 on &159
    8916 )
    8917 *289 (Wire
    8918 uid 3834,0
    8919 shape (OrthoPolyLine
    8920 uid 3835,0
    8921 va (VaSet
    8922 vasetType 3
    8923 )
    8924 xt "108000,110000,111000,110000"
    8925 pts [
    8926 "111000,110000"
    8927 "108000,110000"
    8928 ]
    8929 )
    8930 start &151
    8931 end &140
    8932 sat 32
    8933 eat 2
    8934 stc 0
    8935 st 0
    8936 sf 1
    8937 si 0
    8938 tg (WTG
    8939 uid 3838,0
    8940 ps "ConnStartEndStrategy"
    8941 stg "STSignalDisplayStrategy"
    8942 f (Text
    8943 uid 3839,0
    8944 va (VaSet
    8945 isHidden 1
    8946 )
    8947 xt "108000,109000,110900,110000"
    8948 st "EE_CS"
    8949 blo "108000,109800"
    8950 tm "WireNameMgr"
    8951 )
    8952 )
    8953 on &160
    8954 )
    8955 *290 (Wire
    8956 uid 3842,0
    8957 shape (OrthoPolyLine
    8958 uid 3843,0
    8959 va (VaSet
    8960 vasetType 3
    8961 lineWidth 2
    8962 )
    8963 xt "108000,111000,111000,111000"
    8964 pts [
    8965 "111000,111000"
    8966 "108000,111000"
    8967 ]
    8968 )
    8969 start &152
    8970 end &140
    8971 sat 32
    8972 eat 2
    8973 sty 1
    8974 stc 0
    8975 st 0
    8976 sf 1
    8977 si 0
    8978 tg (WTG
    8979 uid 3846,0
    8980 ps "ConnStartEndStrategy"
    8981 stg "STSignalDisplayStrategy"
    8982 f (Text
    8983 uid 3847,0
    8984 va (VaSet
    8985 isHidden 1
    8986 )
    8987 xt "108000,110000,109900,111000"
    8988 st "LED"
    8989 blo "108000,110800"
    8990 tm "WireNameMgr"
    8991 )
    8992 )
    8993 on &161
    8994 )
    8995 *291 (Wire
    8996 uid 4942,0
    8997 shape (OrthoPolyLine
    8998 uid 4943,0
    8999 va (VaSet
    9000 vasetType 3
    9001 lineWidth 2
    9002 )
    9003 xt "80750,120000,111000,120000"
    9004 pts [
    9005 "80750,120000"
    9006 "111000,120000"
    9007 ]
    9008 )
    9009 start &14
    9010 end &166
    9011 sat 32
     8763xt "39000,132000,44000,132000"
     8764pts [
     8765"39000,132000"
     8766"44000,132000"
     8767]
     8768)
     8769start &201
     8770end &205
     8771sat 2
    90128772eat 32
    90138773sty 1
    9014 stc 0
    90158774st 0
    90168775sf 1
    90178776si 0
    90188777tg (WTG
    9019 uid 4948,0
     8778uid 7148,0
    90208779ps "ConnStartEndStrategy"
    90218780stg "STSignalDisplayStrategy"
    90228781f (Text
    9023 uid 4949,0
     8782uid 7149,0
    90248783va (VaSet
    90258784isHidden 1
    90268785)
    9027 xt "82750,117000,84650,118000"
    9028 st "D_T"
    9029 blo "82750,117800"
    9030 tm "WireNameMgr"
    9031 )
    9032 )
    9033 on &167
    9034 )
    9035 *292 (Wire
    9036 uid 6130,0
     8786xt "41000,131000,45800,132000"
     8787st "A1_T : (7:0)"
     8788blo "41000,131800"
     8789tm "WireNameMgr"
     8790)
     8791)
     8792on &206
     8793)
     8794*281 (Wire
     8795uid 7477,0
    90378796shape (OrthoPolyLine
    9038 uid 6131,0
     8797uid 7478,0
    90398798va (VaSet
    90408799vasetType 3
    90418800)
    9042 xt "19000,78000,51250,78000"
    9043 pts [
    9044 "19000,78000"
    9045 "51250,78000"
    9046 ]
    9047 )
    9048 start &193
    9049 end &15
    9050 sat 32
    9051 eat 32
    9052 st 0
    9053 sf 1
    9054 si 0
    9055 tg (WTG
    9056 uid 6136,0
    9057 ps "ConnStartEndStrategy"
    9058 stg "STSignalDisplayStrategy"
    9059 f (Text
    9060 uid 6137,0
    9061 va (VaSet
    9062 )
    9063 xt "21000,77000,24700,78000"
    9064 st "TRG_OR"
    9065 blo "21000,77800"
    9066 tm "WireNameMgr"
    9067 )
    9068 )
    9069 on &170
    9070 )
    9071 *293 (Wire
    9072 uid 6288,0
    9073 shape (OrthoPolyLine
    9074 uid 6289,0
    9075 va (VaSet
    9076 vasetType 3
    9077 )
    9078 xt "1750,79000,13000,89000"
    9079 pts [
    9080 "1750,89000"
    9081 "9000,89000"
    9082 "9000,86000"
    9083 "9000,79000"
    9084 "13000,79000"
    9085 ]
    9086 )
    9087 start &174
    9088 end &191
    9089 sat 32
    9090 eat 32
    9091 st 0
    9092 sf 1
    9093 si 0
    9094 tg (WTG
    9095 uid 6294,0
    9096 ps "ConnStartEndStrategy"
    9097 stg "STSignalDisplayStrategy"
    9098 f (Text
    9099 uid 6295,0
    9100 va (VaSet
    9101 )
    9102 xt "4000,88000,8600,89000"
    9103 st "trigger_out"
    9104 blo "4000,88800"
    9105 tm "WireNameMgr"
    9106 )
    9107 )
    9108 on &178
    9109 )
    9110 *294 (Wire
    9111 uid 6306,0
    9112 shape (OrthoPolyLine
    9113 uid 6307,0
    9114 va (VaSet
    9115 vasetType 3
    9116 )
    9117 xt "-28000,89000,-22000,89000"
    9118 pts [
    9119 "-28000,89000"
    9120 "-22000,89000"
    9121 ]
    9122 )
    9123 start &168
    9124 end &181
     8801xt "80750,87000,91000,87000"
     8802pts [
     8803"80750,87000"
     8804"91000,87000"
     8805]
     8806)
     8807start &38
     8808end &209
    91258809es 0
    91268810sat 32
    … …  
    91308814si 0
    91318815tg (WTG
    9132 uid 6312,0
     8816uid 7483,0
    91338817ps "ConnStartEndStrategy"
    91348818stg "STSignalDisplayStrategy"
    91358819f (Text
    9136 uid 6313,0
    9137 va (VaSet
    9138 )
    9139 xt "-26000,88000,-21500,89000"
    9140 st "TEST_TRG"
    9141 blo "-26000,88800"
    9142 tm "WireNameMgr"
    9143 )
    9144 )
    9145 on &169
    9146 )
    9147 *295 (Wire
    9148 uid 6328,0
     8820uid 7484,0
     8821va (VaSet
     8822)
     8823xt "83000,86000,85700,87000"
     8824st "dummy"
     8825blo "83000,86800"
     8826tm "WireNameMgr"
     8827)
     8828)
     8829on &207
     8830)
     8831*282 (Wire
     8832uid 8853,0
    91498833shape (OrthoPolyLine
    9150 uid 6329,0
    9151 va (VaSet
    9152 vasetType 3
    9153 )
    9154 xt "-17000,89000,-11750,89000"
    9155 pts [
    9156 "-17000,89000"
    9157 "-11750,89000"
    9158 ]
    9159 )
    9160 start &183
    9161 end &173
    9162 sat 32
    9163 eat 32
    9164 st 0
    9165 sf 1
    9166 si 0
    9167 tg (WTG
    9168 uid 6334,0
    9169 ps "ConnStartEndStrategy"
    9170 stg "STSignalDisplayStrategy"
    9171 f (Text
    9172 uid 6335,0
    9173 va (VaSet
    9174 )
    9175 xt "-18000,92000,-11700,93000"
    9176 st "not_TEST_TRG"
    9177 blo "-18000,92800"
    9178 tm "WireNameMgr"
    9179 )
    9180 )
    9181 on &179
    9182 )
    9183 *296 (Wire
    9184 uid 6431,0
    9185 shape (OrthoPolyLine
    9186 uid 6432,0
    9187 va (VaSet
    9188 vasetType 3
    9189 )
    9190 xt "80750,121000,111000,121000"
    9191 pts [
    9192 "80750,121000"
    9193 "111000,121000"
    9194 ]
    9195 )
    9196 start &43
    9197 end &149
    9198 sat 32
    9199 eat 32
    9200 stc 0
    9201 st 0
    9202 sf 1
    9203 si 0
    9204 tg (WTG
    9205 uid 6435,0
    9206 ps "ConnStartEndStrategy"
    9207 stg "STSignalDisplayStrategy"
    9208 f (Text
    9209 uid 6436,0
    9210 va (VaSet
    9211 isHidden 1
    9212 )
    9213 xt "92000,120000,96000,121000"
    9214 st "DENABLE"
    9215 blo "92000,120800"
    9216 tm "WireNameMgr"
    9217 )
    9218 )
    9219 on &158
    9220 )
    9221 *297 (Wire
    9222 uid 6787,0
    9223 shape (OrthoPolyLine
    9224 uid 6788,0
     8834uid 8854,0
    92258835va (VaSet
    92268836vasetType 3
    92278837lineWidth 2
    92288838)
    9229 xt "93000,132000,99000,132000"
    9230 pts [
    9231 "93000,132000"
    9232 "99000,132000"
    9233 ]
    9234 )
    9235 start &213
    9236 end &217
     8839xt "10000,109000,51250,132000"
     8840pts [
     8841"51250,109000"
     8842"10000,109000"
     8843"10000,132000"
     8844"31000,132000"
     8845]
     8846)
     8847start &30
     8848end &201
    92378849sat 32
    92388850eat 1
    … …  
    92428854si 0
    92438855tg (WTG
    9244 uid 6791,0
     8856uid 8857,0
    92458857ps "ConnStartEndStrategy"
    92468858stg "STSignalDisplayStrategy"
    92478859f (Text
    9248 uid 6792,0
    9249 va (VaSet
    9250 isHidden 1
    9251 )
    9252 xt "95000,131000,101800,132000"
    9253 st "D_PLLLCK : (3:0)"
    9254 blo "95000,131800"
    9255 tm "WireNameMgr"
    9256 )
    9257 )
    9258 on &214
    9259 )
    9260 *298 (Wire
    9261 uid 6880,0
     8860uid 8858,0
     8861va (VaSet
     8862)
     8863xt "42000,108000,50500,109000"
     8864st "drs_channel_id : (3:0)"
     8865blo "42000,108800"
     8866tm "WireNameMgr"
     8867)
     8868)
     8869on &221
     8870)
     8871*283 (Wire
     8872uid 9193,0
    92628873shape (OrthoPolyLine
    9263 uid 6881,0
     8874uid 9194,0
    92648875va (VaSet
    92658876vasetType 3
    92668877lineWidth 2
    92678878)
    9268 xt "102000,132000,109000,132000"
    9269 pts [
    9270 "102000,132000"
    9271 "109000,132000"
    9272 ]
    9273 )
    9274 start &217
    9275 end &215
    9276 sat 2
     8879xt "93000,136000,103000,136000"
     8880pts [
     8881"93000,136000"
     8882"103000,136000"
     8883]
     8884)
     8885sat 16
     8886eat 16
     8887sty 1
     8888st 0
     8889sf 1
     8890si 0
     8891tg (WTG
     8892uid 9199,0
     8893ps "ConnStartEndStrategy"
     8894stg "STSignalDisplayStrategy"
     8895f (Text
     8896uid 9200,0
     8897va (VaSet
     8898)
     8899xt "95000,135000,99800,136000"
     8900st "A0_T : (7:0)"
     8901blo "95000,135800"
     8902tm "WireNameMgr"
     8903)
     8904)
     8905on &222
     8906)
     8907*284 (Wire
     8908uid 9300,0
     8909shape (OrthoPolyLine
     8910uid 9301,0
     8911va (VaSet
     8912vasetType 3
     8913lineWidth 2
     8914)
     8915xt "54000,140000,64000,140000"
     8916pts [
     8917"54000,140000"
     8918"64000,140000"
     8919]
     8920)
     8921end &223
     8922sat 16
    92778923eat 32
    92788924sty 1
    … …  
    92818927si 0
    92828928tg (WTG
    9283 uid 6884,0
     8929uid 9304,0
    92848930ps "ConnStartEndStrategy"
    92858931stg "STSignalDisplayStrategy"
    92868932f (Text
    9287 uid 6885,0
     8933uid 9305,0
    92888934va (VaSet
    92898935isHidden 1
    92908936)
    9291 xt "104000,131000,108900,132000"
    9292 st "D_T2 : (3:0)"
    9293 blo "104000,131800"
    9294 tm "WireNameMgr"
    9295 )
    9296 )
    9297 on &216
    9298 )
    9299 *299 (Wire
    9300 uid 7102,0
     8937xt "56000,139000,60800,140000"
     8938st "A0_T : (7:0)"
     8939blo "56000,139800"
     8940tm "WireNameMgr"
     8941)
     8942)
     8943on &222
     8944)
     8945*285 (Wire
     8946uid 9492,0
    93018947shape (OrthoPolyLine
    9302 uid 7103,0
     8948uid 9493,0
    93038949va (VaSet
    93048950vasetType 3
    93058951)
    9306 xt "21000,132000,31000,132000"
    9307 pts [
    9308 "21000,132000"
    9309 "31000,132000"
    9310 ]
    9311 )
    9312 end &221
     8952xt "21000,135000,31000,135000"
     8953pts [
     8954"21000,135000"
     8955"31000,135000"
     8956]
     8957)
     8958end &201
    93138959sat 16
    93148960eat 1
    … …  
    93178963si 0
    93188964tg (WTG
    9319 uid 7108,0
     8965uid 9498,0
    93208966ps "ConnStartEndStrategy"
    93218967stg "STSignalDisplayStrategy"
    93228968f (Text
    9323 uid 7109,0
    9324 va (VaSet
    9325 )
    9326 xt "23000,131000,27600,132000"
    9327 st "D0_SROUT"
    9328 blo "23000,131800"
    9329 tm "WireNameMgr"
    9330 )
    9331 )
    9332 on &106
    9333 )
    9334 *300 (Wire
    9335 uid 7110,0
     8969uid 9499,0
     8970va (VaSet
     8971)
     8972xt "23000,134000,26700,135000"
     8973st "TRG_OR"
     8974blo "23000,134800"
     8975tm "WireNameMgr"
     8976)
     8977)
     8978on &169
     8979)
     8980*286 (Wire
     8981uid 9502,0
    93368982shape (OrthoPolyLine
    9337 uid 7111,0
     8983uid 9503,0
    93388984va (VaSet
    93398985vasetType 3
    93408986)
    9341 xt "21000,133000,31000,133000"
    9342 pts [
    9343 "21000,133000"
    9344 "31000,133000"
    9345 ]
    9346 )
    9347 end &221
    9348 sat 16
    9349 eat 1
     8987xt "46000,69000,51250,69000"
     8988pts [
     8989"51250,69000"
     8990"46000,69000"
     8991]
     8992)
     8993start &26
     8994sat 32
     8995eat 16
    93508996st 0
    93518997sf 1
    93528998si 0
    93538999tg (WTG
    9354 uid 7116,0
     9000uid 9506,0
    93559001ps "ConnStartEndStrategy"
    93569002stg "STSignalDisplayStrategy"
    93579003f (Text
    9358 uid 7117,0
    9359 va (VaSet
    9360 )
    9361 xt "23000,132000,27600,133000"
    9362 st "D1_SROUT"
    9363 blo "23000,132800"
    9364 tm "WireNameMgr"
    9365 )
    9366 )
    9367 on &107
    9368 )
    9369 *301 (Wire
    9370 uid 7118,0
    9371 shape (OrthoPolyLine
    9372 uid 7119,0
    9373 va (VaSet
    9374 vasetType 3
    9375 )
    9376 xt "21000,134000,31000,134000"
    9377 pts [
    9378 "21000,134000"
    9379 "31000,134000"
    9380 ]
    9381 )
    9382 end &221
    9383 sat 16
    9384 eat 1
    9385 st 0
    9386 sf 1
    9387 si 0
    9388 tg (WTG
    9389 uid 7124,0
    9390 ps "ConnStartEndStrategy"
    9391 stg "STSignalDisplayStrategy"
    9392 f (Text
    9393 uid 7125,0
    9394 va (VaSet
    9395 )
    9396 xt "23000,133000,27200,134000"
    9397 st "RSRLOAD"
    9398 blo "23000,133800"
    9399 tm "WireNameMgr"
    9400 )
    9401 )
    9402 on &64
    9403 )
    9404 *302 (Wire
    9405 uid 7144,0
    9406 shape (OrthoPolyLine
    9407 uid 7145,0
    9408 va (VaSet
    9409 vasetType 3
    9410 lineWidth 2
    9411 )
    9412 xt "39000,132000,44000,132000"
    9413 pts [
    9414 "39000,132000"
    9415 "44000,132000"
    9416 ]
    9417 )
    9418 start &221
    9419 end &225
    9420 sat 2
    9421 eat 32
    9422 sty 1
    9423 st 0
    9424 sf 1
    9425 si 0
    9426 tg (WTG
    9427 uid 7148,0
    9428 ps "ConnStartEndStrategy"
    9429 stg "STSignalDisplayStrategy"
    9430 f (Text
    9431 uid 7149,0
    9432 va (VaSet
    9433 isHidden 1
    9434 )
    9435 xt "41000,131000,45800,132000"
    9436 st "A1_T : (3:0)"
    9437 blo "41000,131800"
    9438 tm "WireNameMgr"
    9439 )
    9440 )
    9441 on &226
    9442 )
    9443 *303 (Wire
    9444 uid 7477,0
    9445 shape (OrthoPolyLine
    9446 uid 7478,0
    9447 va (VaSet
    9448 vasetType 3
    9449 )
    9450 xt "80750,87000,91000,87000"
    9451 pts [
    9452 "80750,87000"
    9453 "91000,87000"
    9454 ]
    9455 )
    9456 start &38
    9457 end &229
    9458 es 0
    9459 sat 32
    9460 eat 32
    9461 st 0
    9462 sf 1
    9463 si 0
    9464 tg (WTG
    9465 uid 7483,0
    9466 ps "ConnStartEndStrategy"
    9467 stg "STSignalDisplayStrategy"
    9468 f (Text
    9469 uid 7484,0
    9470 va (VaSet
    9471 )
    9472 xt "83000,86000,85700,87000"
    9473 st "dummy"
    9474 blo "83000,86800"
    9475 tm "WireNameMgr"
    9476 )
    9477 )
    9478 on &227
    9479 )
    9480 *304 (Wire
    9481 uid 7487,0
    9482 shape (OrthoPolyLine
    9483 uid 7488,0
    9484 va (VaSet
    9485 vasetType 3
    9486 )
    9487 xt "21000,135000,31000,135000"
    9488 pts [
    9489 "21000,135000"
    9490 "31000,135000"
    9491 ]
    9492 )
    9493 end &221
    9494 sat 16
    9495 eat 1
    9496 st 0
    9497 sf 1
    9498 si 0
    9499 tg (WTG
    9500 uid 7493,0
    9501 ps "ConnStartEndStrategy"
    9502 stg "STSignalDisplayStrategy"
    9503 f (Text
    9504 uid 7494,0
    9505 va (VaSet
    9506 )
    9507 xt "23000,134000,25700,135000"
    9508 st "dummy"
    9509 blo "23000,134800"
    9510 tm "WireNameMgr"
    9511 )
    9512 )
    9513 on &227
     9004uid 9507,0
     9005va (VaSet
     9006)
     9007xt "47000,68000,50100,69000"
     9008st "CLK_50"
     9009blo "47000,68800"
     9010tm "WireNameMgr"
     9011)
     9012)
     9013on &224
    95149014)
    95159015]
    … …  
    95259025color "26368,26368,26368"
    95269026)
    9527 packageList *305 (PackageList
     9027packageList *287 (PackageList
    95289028uid 41,0
    95299029stg "VerticalLayoutStrategy"
    95309030textVec [
    9531 *306 (Text
     9031*288 (Text
    95329032uid 42,0
    95339033va (VaSet
    … …  
    95389038blo "0,800"
    95399039)
    9540 *307 (MLText
     9040*289 (MLText
    95419041uid 43,0
    95429042va (VaSet
    … …  
    95599059stg "VerticalLayoutStrategy"
    95609060textVec [
    9561 *308 (Text
     9061*290 (Text
    95629062uid 45,0
    95639063va (VaSet
    … …  
    95699069blo "20000,800"
    95709070)
    9571 *309 (Text
     9071*291 (Text
    95729072uid 46,0
    95739073va (VaSet
    … …  
    95799079blo "20000,1800"
    95809080)
    9581 *310 (MLText
     9081*292 (MLText
    95829082uid 47,0
    95839083va (VaSet
    … …  
    95899089tm "BdCompilerDirectivesTextMgr"
    95909090)
    9591 *311 (Text
     9091*293 (Text
    95929092uid 48,0
    95939093va (VaSet
    … …  
    95999099blo "20000,4800"
    96009100)
    9601 *312 (MLText
     9101*294 (MLText
    96029102uid 49,0
    96039103va (VaSet
    … …  
    96079107tm "BdCompilerDirectivesTextMgr"
    96089108)
    9609 *313 (Text
     9109*295 (Text
    96109110uid 50,0
    96119111va (VaSet
    … …  
    96179117blo "20000,5800"
    96189118)
    9619 *314 (MLText
     9119*296 (MLText
    96209120uid 51,0
    96219121va (VaSet
    … …  
    96289128associable 1
    96299129)
    9630 windowSize "0,0,1281,1002"
    9631 viewArea "-23100,-5300,61780,62940"
    9632 cachedDiagramExtent "-35500,0,699000,450107"
     9130windowSize "0,22,1281,1024"
     9131viewArea "-13800,92200,71080,160440"
     9132cachedDiagramExtent "0,0,699000,450107"
    96339133pageSetupInfo (PageSetupInfo
    96349134ptrCmd ""
    … …  
    96419141)
    96429142hasePageBreakOrigin 1
    9643 pageBreakOrigin "-73000,0"
    9644 lastUid 8652,0
     9143pageBreakOrigin "0,0"
     9144lastUid 9715,0
    96459145defaultCommentText (CommentText
    96469146shape (Rectangle
    … …  
    97049204stg "VerticalLayoutStrategy"
    97059205textVec [
    9706 *315 (Text
     9206*297 (Text
    97079207va (VaSet
    97089208font "Arial,8,1"
    … …  
    97139213tm "BdLibraryNameMgr"
    97149214)
    9715 *316 (Text
     9215*298 (Text
    97169216va (VaSet
    97179217font "Arial,8,1"
    … …  
    97229222tm "BlkNameMgr"
    97239223)
    9724 *317 (Text
     9224*299 (Text
    97259225va (VaSet
    97269226font "Arial,8,1"
    … …  
    97739273stg "VerticalLayoutStrategy"
    97749274textVec [
    9775 *318 (Text
     9275*300 (Text
    97769276va (VaSet
    97779277font "Arial,8,1"
    … …  
    97819281blo "550,4300"
    97829282)
    9783 *319 (Text
     9283*301 (Text
    97849284va (VaSet
    97859285font "Arial,8,1"
    … …  
    97899289blo "550,5300"
    97909290)
    9791 *320 (Text
     9291*302 (Text
    97929292va (VaSet
    97939293font "Arial,8,1"
    … …  
    98389338stg "VerticalLayoutStrategy"
    98399339textVec [
    9840 *321 (Text
     9340*303 (Text
    98419341va (VaSet
    98429342font "Arial,8,1"
    … …  
    98479347tm "BdLibraryNameMgr"
    98489348)
    9849 *322 (Text
     9349*304 (Text
    98509350va (VaSet
    98519351font "Arial,8,1"
    … …  
    98569356tm "CptNameMgr"
    98579357)
    9858 *323 (Text
     9358*305 (Text
    98599359va (VaSet
    98609360font "Arial,8,1"
    … …  
    99109410stg "VerticalLayoutStrategy"
    99119411textVec [
    9912 *324 (Text
     9412*306 (Text
    99139413va (VaSet
    99149414font "Arial,8,1"
    … …  
    99189418blo "500,4300"
    99199419)
    9920 *325 (Text
     9420*307 (Text
    99219421va (VaSet
    99229422font "Arial,8,1"
    … …  
    99269426blo "500,5300"
    99279427)
    9928 *326 (Text
     9428*308 (Text
    99299429va (VaSet
    99309430font "Arial,8,1"
    … …  
    99719471stg "VerticalLayoutStrategy"
    99729472textVec [
    9973 *327 (Text
     9473*309 (Text
    99749474va (VaSet
    99759475font "Arial,8,1"
    … …  
    99799479blo "50,4300"
    99809480)
    9981 *328 (Text
     9481*310 (Text
    99829482va (VaSet
    99839483font "Arial,8,1"
    … …  
    99879487blo "50,5300"
    99889488)
    9989 *329 (Text
     9489*311 (Text
    99909490va (VaSet
    99919491font "Arial,8,1"
    … …  
    100289528stg "VerticalLayoutStrategy"
    100299529textVec [
    10030 *330 (Text
     9530*312 (Text
    100319531va (VaSet
    100329532font "Arial,8,1"
    … …  
    100379537tm "HdlTextNameMgr"
    100389538)
    10039 *331 (Text
     9539*313 (Text
    100409540va (VaSet
    100419541font "Arial,8,1"
    … …  
    104409940stg "VerticalLayoutStrategy"
    104419941textVec [
    10442 *332 (Text
     9942*314 (Text
    104439943va (VaSet
    104449944font "Arial,8,1"
    … …  
    104489948blo "14100,20800"
    104499949)
    10450 *333 (MLText
     9950*315 (MLText
    104519951va (VaSet
    104529952)
    … …  
    1050010000stg "VerticalLayoutStrategy"
    1050110001textVec [
    10502 *334 (Text
     10002*316 (Text
    1050310003va (VaSet
    1050410004font "Arial,8,1"
    … …  
    1050810008blo "14100,20800"
    1050910009)
    10510 *335 (MLText
     10010*317 (MLText
    1051110011va (VaSet
    1051210012)
    … …  
    1062610126font "Arial,8,1"
    1062710127)
    10628 xt "37000,43000,44100,44000"
     10128xt "37000,43800,44100,44800"
    1062910129st "Diagram Signals:"
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     10130blo "37000,44600"
    1063110131)
    1063210132postUserLabel (Text
    … …  
    1065210152commonDM (CommonDM
    1065310153ldm (LogicalDM
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     10154suid 163,0
    1065510155usingSuid 1
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     10156emptyRow *318 (LEmptyRow
    1065710157)
    1065810158uid 54,0
    1065910159optionalChildren [
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    10661 )
    10662 *338 (TitleRowHdr
    10663 )
    10664 *339 (FilterRowHdr
    10665 )
    10666 *340 (RefLabelColHdr
     10160*319 (RefLabelRowHdr
     10161)
     10162*320 (TitleRowHdr
     10163)
     10164*321 (FilterRowHdr
     10165)
     10166*322 (RefLabelColHdr
    1066710167tm "RefLabelColHdrMgr"
    1066810168)
    10669 *341 (RowExpandColHdr
     10169*323 (RowExpandColHdr
    1067010170tm "RowExpandColHdrMgr"
    1067110171)
    10672 *342 (GroupColHdr
     10172*324 (GroupColHdr
    1067310173tm "GroupColHdrMgr"
    1067410174)
    10675 *343 (NameColHdr
     10175*325 (NameColHdr
    1067610176tm "BlockDiagramNameColHdrMgr"
    1067710177)
    10678 *344 (ModeColHdr
     10178*326 (ModeColHdr
    1067910179tm "BlockDiagramModeColHdrMgr"
    1068010180)
    10681 *345 (TypeColHdr
     10181*327 (TypeColHdr
    1068210182tm "BlockDiagramTypeColHdrMgr"
    1068310183)
    10684 *346 (BoundsColHdr
     10184*328 (BoundsColHdr
    1068510185tm "BlockDiagramBoundsColHdrMgr"
    1068610186)
    10687 *347 (InitColHdr
     10187*329 (InitColHdr
    1068810188tm "BlockDiagramInitColHdrMgr"
    1068910189)
    10690 *348 (EolColHdr
     10190*330 (EolColHdr
    1069110191tm "BlockDiagramEolColHdrMgr"
    1069210192)
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     10193*331 (LeafLogPort
    1069410194port (LogicalPort
    1069510195m 4
    … …  
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     10202o 56
    1070310203suid 5,0
    1070410204)
    … …  
    1070610206uid 327,0
    1070710207)
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     10208*332 (LeafLogPort
    1070910209port (LogicalPort
    1071010210m 4
    … …  
    1071310213t "std_logic_vector"
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    10715 o 56
     10215o 57
    1071610216suid 6,0
    1071710217)
    … …  
    1071910219uid 329,0
    1072010220)
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     10221*333 (LeafLogPort
    1072210222port (LogicalPort
    1072310223m 4
    … …  
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     10227o 55
    1072810228suid 29,0
    1072910229)
    … …  
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     10233*334 (LeafLogPort
     10234port (LogicalPort
     10235m 1
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     10237n "RSRLOAD"
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     10240suid 57,0
     10241i "'0'"
     10242)
     10243)
     10244uid 2435,0
     10245)
     10246*335 (LeafLogPort
    1073410247port (LogicalPort
    1073510248m 4
    1073610249decl (Decl
    10737 n "CLK_50"
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    10739 preAdd 0
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    10741 o 51
    10742 suid 54,0
    10743 )
    10744 )
    10745 uid 2275,0
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    10747 *353 (LeafLogPort
    10748 port (LogicalPort
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    10751 n "RSRLOAD"
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    10755 i "'0'"
    10756 )
    10757 )
    10758 uid 2435,0
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    10760 *354 (LeafLogPort
    10761 port (LogicalPort
    10762 m 4
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    1076410250n "SRCLK"
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     10252o 53
    1076710253suid 58,0
    1076810254i "'0'"
    … …  
    1077110257uid 2437,0
    1077210258)
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     10259*336 (LeafLogPort
    1077410260port (LogicalPort
    1077510261m 4
    … …  
    1077810264t "std_logic_vector"
    1077910265b "(3 DOWNTO 0)"
    10780 o 59
     10266o 60
    1078110267suid 65,0
    1078210268)
    … …  
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     10272*337 (LeafLogPort
    1078710273port (LogicalPort
    1078810274m 1
    … …  
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    1079410280)
    … …  
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    1080010286decl (Decl
    … …  
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    1081310299decl (Decl
    … …  
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    1082310309port (LogicalPort
    1082410310m 1
    … …  
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    1083010316suid 71,0
    1083110317)
    … …  
    1083310319uid 3280,0
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     10321*341 (LeafLogPort
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    1083710323m 4
    … …  
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    1084310329)
    … …  
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    1084810334port (LogicalPort
    1084910335m 1
    … …  
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     10341o 31
    1085610342suid 73,0
    1085710343)
    … …  
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    1086310349decl (Decl
    … …  
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    … …  
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    1088410370)
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     10371*345 (LeafLogPort
    1088610372port (LogicalPort
    1088710373decl (Decl
    … …  
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    1089610382)
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     10383*346 (LeafLogPort
    1089810384port (LogicalPort
    1089910385decl (Decl
    … …  
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    1090810394)
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     10395*347 (LeafLogPort
    1091010396port (LogicalPort
    1091110397decl (Decl
    … …  
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    1092010406)
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     10407*348 (LeafLogPort
    1092210408port (LogicalPort
    1092310409m 1
    … …  
    1092510411n "D0_SRCLK"
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     10413o 18
    1092810414suid 87,0
    1092910415)
    … …  
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    1093210418)
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     10419*349 (LeafLogPort
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    1093510421m 1
    … …  
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     10425o 19
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    1094110427)
    … …  
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    1094410430)
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     10431*350 (LeafLogPort
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    … …  
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     10437o 20
    1095210438suid 89,0
    1095310439)
    … …  
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    1095610442)
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     10443*351 (LeafLogPort
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    … …  
    1096110447n "D3_SRCLK"
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     10449o 21
    1096410450suid 90,0
    1096510451)
    … …  
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    1096810454)
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     10455*352 (LeafLogPort
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    1097110457decl (Decl
    … …  
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    1097910465)
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     10466*353 (LeafLogPort
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    1098210468decl (Decl
    … …  
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    1099010476)
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     10477*354 (LeafLogPort
    1099210478port (LogicalPort
    1099310479decl (Decl
    … …  
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    1100110487)
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     10488*355 (LeafLogPort
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    1100410490decl (Decl
    … …  
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    1101210498)
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     10499*356 (LeafLogPort
    1101410500port (LogicalPort
    1101510501m 1
    … …  
    1101810504t "std_logic_vector"
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     10506o 25
    1102110507suid 95,0
    1102210508i "(others => '0')"
    … …  
    1102510511uid 3532,0
    1102610512)
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     10513*357 (LeafLogPort
    1102810514port (LogicalPort
    1102910515m 1
    … …  
    1103110517n "DWRITE"
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     10519o 24
    1103410520suid 96,0
    1103510521i "'0'"
    … …  
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    1103910525)
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     10526*358 (LeafLogPort
    1104110527port (LogicalPort
    1104210528m 1
    … …  
    1104410530n "T0_CS"
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     10532o 39
    1104710533suid 101,0
    1104810534)
    … …  
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    1105110537)
    11052 *378 (LeafLogPort
     10538*359 (LeafLogPort
    1105310539port (LogicalPort
    1105410540m 1
    … …  
    1105610542n "T1_CS"
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     10544o 40
    1105910545suid 102,0
    1106010546)
    … …  
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    1106310549)
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     10550*360 (LeafLogPort
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    1106610552m 1
    … …  
    1106810554n "T2_CS"
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     10556o 41
    1107110557suid 103,0
    1107210558)
    … …  
    1107410560uid 3650,0
    1107510561)
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     10562*361 (LeafLogPort
    1107710563port (LogicalPort
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    … …  
    1108010566n "T3_CS"
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     10568o 42
    1108310569suid 104,0
    1108410570)
    … …  
    1108610572uid 3652,0
    1108710573)
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     10574*362 (LeafLogPort
    1108910575port (LogicalPort
    1109010576m 1
    … …  
    1109210578n "S_CLK"
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     10580o 38
    1109510581suid 105,0
    1109610582)
    … …  
    1109810584uid 3654,0
    1109910585)
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     10586*363 (LeafLogPort
    1110110587port (LogicalPort
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    … …  
    1110510591t "std_logic_vector"
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     10593o 44
    1110810594suid 106,0
    1110910595)
    … …  
    1111110597uid 3656,0
    1111210598)
    11113 *383 (LeafLogPort
     10599*364 (LeafLogPort
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    … …  
    1111810604t "std_logic_vector"
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     10606o 50
    1112110607suid 107,0
    1112210608)
    … …  
    1112410610uid 3658,0
    1112510611)
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     10612*365 (LeafLogPort
    1112710613port (LogicalPort
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    … …  
    1113010616n "W_RES"
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     10618o 47
    1113310619suid 108,0
    1113410620i "'1'"
    … …  
    1113710623uid 3660,0
    1113810624)
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     10625*366 (LeafLogPort
    1114010626port (LogicalPort
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    … …  
    1114310629n "W_RD"
    1114410630t "std_logic"
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     10631o 46
    1114610632suid 109,0
    1114710633i "'1'"
    … …  
    1115010636uid 3662,0
    1115110637)
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     10638*367 (LeafLogPort
    1115310639port (LogicalPort
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    … …  
    1115610642n "W_WR"
    1115710643t "std_logic"
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     10644o 48
    1115910645suid 110,0
    1116010646i "'1'"
    … …  
    1116310649uid 3664,0
    1116410650)
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     10651*368 (LeafLogPort
    1116610652port (LogicalPort
    1116710653decl (Decl
    … …  
    1117410660uid 3666,0
    1117510661)
    11176 *388 (LeafLogPort
     10662*369 (LeafLogPort
    1117710663port (LogicalPort
    1117810664m 1
    … …  
    1118010666n "W_CS"
    1118110667t "std_logic"
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     10668o 45
    1118310669suid 112,0
    1118410670i "'1'"
    … …  
    1118710673uid 3668,0
    1118810674)
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     10675*370 (LeafLogPort
    1119010676port (LogicalPort
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    … …  
    1119310679n "MOSI"
    1119410680t "std_logic"
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     10681o 30
    1119610682suid 113,0
    1119710683i "'0'"
    … …  
    1120010686uid 3696,0
    1120110687)
    11202 *390 (LeafLogPort
     10688*371 (LeafLogPort
    1120310689port (LogicalPort
    1120410690m 2
    … …  
    1120810694preAdd 0
    1120910695posAdd 0
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     10696o 49
    1121110697suid 114,0
    1121210698)
    … …  
    1121410700uid 3698,0
    1121510701)
    11216 *391 (LeafLogPort
     10702*372 (LeafLogPort
    1121710703port (LogicalPort
    1121810704m 1
    … …  
    1122010706n "TRG_V"
    1122110707t "std_logic"
    11222 o 42
     10708o 43
    1122310709suid 126,0
    1122410710)
    … …  
    1122610712uid 3886,0
    1122710713)
    11228 *392 (LeafLogPort
     10714*373 (LeafLogPort
    1122910715port (LogicalPort
    1123010716m 1
    … …  
    1123210718n "RS485_C_RE"
    1123310719t "std_logic"
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     10720o 33
    1123510721suid 127,0
    1123610722)
    … …  
    1123810724uid 3888,0
    1123910725)
    11240 *393 (LeafLogPort
     10726*374 (LeafLogPort
    1124110727port (LogicalPort
    1124210728m 1
    … …  
    1124410730n "RS485_C_DE"
    1124510731t "std_logic"
    11246 o 31
     10732o 32
    1124710733suid 128,0
    1124810734)
    … …  
    1125010736uid 3890,0
    1125110737)
    11252 *394 (LeafLogPort
     10738*375 (LeafLogPort
    1125310739port (LogicalPort
    1125410740m 1
    … …  
    1125610742n "RS485_E_RE"
    1125710743t "std_logic"
    11258 o 34
     10744o 35
    1125910745suid 129,0
    1126010746)
    … …  
    1126210748uid 3892,0
    1126310749)
    11264 *395 (LeafLogPort
     10750*376 (LeafLogPort
    1126510751port (LogicalPort
    1126610752m 1
    … …  
    1126810754n "RS485_E_DE"
    1126910755t "std_logic"
    11270 o 33
     10756o 34
    1127110757suid 130,0
    1127210758)
    … …  
    1127410760uid 3894,0
    1127510761)
    11276 *396 (LeafLogPort
     10762*377 (LeafLogPort
    1127710763port (LogicalPort
    1127810764m 1
    … …  
    1128010766n "DENABLE"
    1128110767t "std_logic"
    11282 o 22
     10768o 23
    1128310769suid 131,0
    1128410770i "'0'"
    … …  
    1128710773uid 3896,0
    1128810774)
    11289 *397 (LeafLogPort
     10775*378 (LeafLogPort
    1129010776port (LogicalPort
    1129110777m 1
    … …  
    1129310779n "SRIN"
    1129410780t "std_logic"
    11295 o 36
     10781o 37
    1129610782suid 132,0
    1129710783)
    … …  
    1129910785uid 3898,0
    1130010786)
    11301 *398 (LeafLogPort
     10787*379 (LeafLogPort
    1130210788port (LogicalPort
    1130310789m 1
    … …  
    1130510791n "EE_CS"
    1130610792t "std_logic"
    11307 o 27
     10793o 28
    1130810794suid 133,0
    1130910795)
    … …  
    1131110797uid 3900,0
    1131210798)
    11313 *399 (LeafLogPort
     10799*380 (LeafLogPort
    1131410800port (LogicalPort
    1131510801m 1
    … …  
    1131810804t "std_logic_vector"
    1131910805b "( 2 DOWNTO 0 )"
    11320 o 28
     10806o 29
    1132110807suid 134,0
    1132210808i "(others => '1')"
    … …  
    1132510811uid 3902,0
    1132610812)
    11327 *400 (LeafLogPort
     10813*381 (LeafLogPort
    1132810814port (LogicalPort
    1132910815m 1
    … …  
    1133210818t "std_logic_vector"
    1133310819b "(7 DOWNTO 0)"
    11334 o 25
     10820o 26
    1133510821suid 141,0
    1133610822i "(OTHERS => '0')"
    … …  
    1133910825uid 5322,0
    1134010826)
    11341 *401 (LeafLogPort
     10827*382 (LeafLogPort
    1134210828port (LogicalPort
    1134310829decl (Decl
    … …  
    1135110837scheme 0
    1135210838)
    11353 *402 (LeafLogPort
     10839*383 (LeafLogPort
    1135410840port (LogicalPort
    1135510841m 4
    … …  
    1135710843n "TRG_OR"
    1135810844t "std_logic"
    11359 o 53
     10845o 54
    1136010846suid 146,0
    1136110847)
    … …  
    1136410850scheme 0
    1136510851)
    11366 *403 (LeafLogPort
    11367 port (LogicalPort
    11368 m 4
    11369 decl (Decl
    11370 n "trigger_out"
    11371 t "STD_LOGIC"
    11372 preAdd 0
    11373 posAdd 0
    11374 o 60
    11375 suid 147,0
    11376 i "'0'"
    11377 )
    11378 )
    11379 uid 6286,0
    11380 )
    11381 *404 (LeafLogPort
    11382 port (LogicalPort
    11383 m 4
    11384 decl (Decl
    11385 n "not_TEST_TRG"
    11386 t "STD_LOGIC"
    11387 o 58
    11388 suid 148,0
    11389 )
    11390 )
    11391 uid 6314,0
    11392 scheme 0
    11393 )
    11394 *405 (LeafLogPort
     10852*384 (LeafLogPort
    1139510853port (LogicalPort
    1139610854decl (Decl
    … …  
    1140510863scheme 0
    1140610864)
    11407 *406 (LeafLogPort
     10865*385 (LeafLogPort
    1140810866port (LogicalPort
    1140910867m 1
    … …  
    1141210870t "std_logic_vector"
    1141310871b "(3 DOWNTO 0)"
    11414 o 26
     10872o 27
    1141510873suid 154,0
    1141610874i "(others => '0')"
    … …  
    1142010878scheme 0
    1142110879)
    11422 *407 (LeafLogPort
     10880*386 (LeafLogPort
    1142310881port (LogicalPort
    1142410882m 1
    … …  
    1142610884n "A1_T"
    1142710885t "std_logic_vector"
    11428 b "(3 DOWNTO 0)"
    11429 o 15
     10886b "(7 DOWNTO 0)"
     10887o 16
    1143010888suid 155,0
     10889i "(OTHERS => '0')"
    1143110890)
    1143210891)
    … …  
    1143410893scheme 0
    1143510894)
    11436 *408 (LeafLogPort
     10895*387 (LeafLogPort
    1143710896port (LogicalPort
    1143810897m 4
    … …  
    1144010899n "dummy"
    1144110900t "std_logic"
    11442 o 60
     10901o 59
    1144310902suid 157,0
    1144410903)
    … …  
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    1144710906scheme 0
     10907)
     10908*388 (LeafLogPort
     10909port (LogicalPort
     10910m 4
     10911decl (Decl
     10912n "drs_channel_id"
     10913t "std_logic_vector"
     10914b "(3 downto 0)"
     10915o 58
     10916suid 159,0
     10917i "(others => '0')"
     10918)
     10919)
     10920uid 8875,0
     10921)
     10922*389 (LeafLogPort
     10923port (LogicalPort
     10924m 1
     10925decl (Decl
     10926n "A0_T"
     10927t "std_logic_vector"
     10928b "(7 DOWNTO 0)"
     10929o 15
     10930suid 162,0
     10931i "(OTHERS => '0')"
     10932)
     10933)
     10934uid 9191,0
     10935scheme 0
     10936)
     10937*390 (LeafLogPort
     10938port (LogicalPort
     10939m 4
     10940decl (Decl
     10941n "CLK_50"
     10942t "std_logic"
     10943o 52
     10944suid 163,0
     10945)
     10946)
     10947uid 9516,0
    1144810948)
    1144910949]
    … …  
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    1145510955optionalChildren [
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    1145710957sheetRow (SheetRow
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    … …  
    1147110971font "Tahoma,10,0"
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    … …  
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     10981litem &319
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    1148510985)
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     10987litem &320
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    1149110991)
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    1149510995hidden 1
    … …  
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    1149810998)
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     11001pos 50
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    1150411004)
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    11506 litem &350
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     11005*397 (MRCItem
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     11007pos 51
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    1151011010)
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     11012litem &333
     11013pos 52
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    1151511015uid 1492,0
    1151611016)
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    11518 litem &352
    11519 pos 47
    11520 dimension 20
    11521 uid 2276,0
    11522 )
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     11018litem &334
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    1152811022)
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     11023*400 (MRCItem
     11024litem &335
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    1153411028)
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     11029*401 (MRCItem
     11030litem &336
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     11035*402 (MRCItem
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    1154611040)
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     11041*403 (MRCItem
     11042litem &338
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    1155011044dimension 20
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    1155211046)
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     11047*404 (MRCItem
     11048litem &339
    1155511049pos 3
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    1155711051uid 3279,0
    1155811052)
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     11053*405 (MRCItem
     11054litem &340
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    1156411058)
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     11059*406 (MRCItem
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    1157011064)
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     11065*407 (MRCItem
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    1157611070)
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     11072litem &343
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    1158211076)
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    1158811082)
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    1159411088)
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     11089*411 (MRCItem
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    1160011094)
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     11095*412 (MRCItem
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    1161811112)
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    1163611130)
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    1164211136)
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    1164811142)
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    1165411148)
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    1167211166)
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     11168litem &359
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    1167811172)
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     11203*430 (MRCItem
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    1171111205pos 28
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     11210litem &366
    1171711211pos 29
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     11215*432 (MRCItem
     11216litem &367
    1172311217pos 30
    1172411218dimension 20
    1172511219uid 3665,0
    1172611220)
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     11221*433 (MRCItem
     11222litem &368
    1172911223pos 31
    1173011224dimension 20
    1173111225uid 3667,0
    1173211226)
    11733 *453 (MRCItem
    11734 litem &388
     11227*434 (MRCItem
     11228litem &369
    1173511229pos 32
    1173611230dimension 20
    1173711231uid 3669,0
    1173811232)
    11739 *454 (MRCItem
    11740 litem &389
     11233*435 (MRCItem
     11234litem &370
    1174111235pos 33
    1174211236dimension 20
    1174311237uid 3697,0
    1174411238)
    11745 *455 (MRCItem
    11746 litem &390
     11239*436 (MRCItem
     11240litem &371
    1174711241pos 34
    1174811242dimension 20
    1174911243uid 3699,0
    1175011244)
    11751 *456 (MRCItem
    11752 litem &391
     11245*437 (MRCItem
     11246litem &372
    1175311247pos 35
    1175411248dimension 20
    1175511249uid 3887,0
    1175611250)
    11757 *457 (MRCItem
    11758 litem &392
     11251*438 (MRCItem
     11252litem &373
    1175911253pos 36
    1176011254dimension 20
    1176111255uid 3889,0
    1176211256)
    11763 *458 (MRCItem
    11764 litem &393
     11257*439 (MRCItem
     11258litem &374
    1176511259pos 37
    1176611260dimension 20
    1176711261uid 3891,0
    1176811262)
    11769 *459 (MRCItem
    11770 litem &394
     11263*440 (MRCItem
     11264litem &375
    1177111265pos 38
    1177211266dimension 20
    1177311267uid 3893,0
    1177411268)
    11775 *460 (MRCItem
    11776 litem &395
     11269*441 (MRCItem
     11270litem &376
    1177711271pos 39
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    1177911273uid 3895,0
    1178011274)
    11781 *461 (MRCItem
    11782 litem &396
     11275*442 (MRCItem
     11276litem &377
    1178311277pos 40
    1178411278dimension 20
    1178511279uid 3897,0
    1178611280)
    11787 *462 (MRCItem
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     11281*443 (MRCItem
     11282litem &378
    1178911283pos 41
    1179011284dimension 20
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    1179211286)
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    11794 litem &398
     11287*444 (MRCItem
     11288litem &379
    1179511289pos 42
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    1179811292)
    11799 *464 (MRCItem
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     11293*445 (MRCItem
     11294litem &380
    1180111295pos 43
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    1180411298)
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    1181011304)
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    1181611310)
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     11313pos 56
    1182011314dimension 20
    1182111315uid 6129,0
    1182211316)
    11823 *468 (MRCItem
    11824 litem &403
    11825 pos 54
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    11827 uid 6287,0
    11828 )
    11829 *469 (MRCItem
    11830 litem &404
    11831 pos 55
    11832 dimension 20
    11833 uid 6315,0
    11834 )
    11835 *470 (MRCItem
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     11317*449 (MRCItem
     11318litem &384
     11319pos 46
    1183811320dimension 20
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    1184011322)
    11841 *471 (MRCItem
    11842 litem &406
     11323*450 (MRCItem
     11324litem &385
     11325pos 47
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     11327uid 6873,0
     11328)
     11329*451 (MRCItem
     11330litem &386
     11331pos 48
     11332dimension 20
     11333uid 7135,0
     11334)
     11335*452 (MRCItem
     11336litem &387
    1184311337pos 57
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    11845 uid 6873,0
    11846 )
    11847 *472 (MRCItem
    11848 litem &407
     11339uid 7474,0
     11340)
     11341*453 (MRCItem
     11342litem &388
    1184911343pos 58
    1185011344dimension 20
    11851 uid 7135,0
    11852 )
    11853 *473 (MRCItem
    11854 litem &408
     11345uid 8876,0
     11346)
     11347*454 (MRCItem
     11348litem &389
     11349pos 49
     11350dimension 20
     11351uid 9192,0
     11352)
     11353*455 (MRCItem
     11354litem &390
    1185511355pos 59
    1185611356dimension 20
    11857 uid 7474,0
     11357uid 9517,0
    1185811358)
    1185911359]
    … …  
    1186811368uid 73,0
    1186911369optionalChildren [
    11870 *474 (MRCItem
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    1187311373dimension 20
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    1187511375)
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     11377litem &324
    1187811378pos 1
    1187911379dimension 50
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    1188111381)
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    1188411384pos 2
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    1188711387)
    11888 *477 (MRCItem
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     11389litem &326
    1189011390pos 3
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    1189311393)
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     11395litem &327
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    11900 *479 (MRCItem
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     11401litem &328
    1190211402pos 5
    1190311403dimension 100
    1190411404uid 79,0
    1190511405)
    11906 *480 (MRCItem
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     11407litem &329
    1190811408pos 6
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    1191011410uid 80,0
    1191111411)
    11912 *481 (MRCItem
    11913 litem &348
     11412*463 (MRCItem
     11413litem &330
    1191411414pos 7
    1191511415dimension 80
    … …  
    1193111431genericsCommonDM (CommonDM
    1193211432ldm (LogicalDM
    11933 emptyRow *482 (LEmptyRow
     11433emptyRow *464 (LEmptyRow
    1193411434)
    1193511435uid 83,0
    1193611436optionalChildren [
    11937 *483 (RefLabelRowHdr
    11938 )
    11939 *484 (TitleRowHdr
    11940 )
    11941 *485 (FilterRowHdr
    11942 )
    11943 *486 (RefLabelColHdr
     11437*465 (RefLabelRowHdr
     11438)
     11439*466 (TitleRowHdr
     11440)
     11441*467 (FilterRowHdr
     11442)
     11443*468 (RefLabelColHdr
    1194411444tm "RefLabelColHdrMgr"
    1194511445)
    11946 *487 (RowExpandColHdr
     11446*469 (RowExpandColHdr
    1194711447tm "RowExpandColHdrMgr"
    1194811448)
    11949 *488 (GroupColHdr
     11449*470 (GroupColHdr
    1195011450tm "GroupColHdrMgr"
    1195111451)
    11952 *489 (NameColHdr
     11452*471 (NameColHdr
    1195311453tm "GenericNameColHdrMgr"
    1195411454)
    11955 *490 (TypeColHdr
     11455*472 (TypeColHdr
    1195611456tm "GenericTypeColHdrMgr"
    1195711457)
    11958 *491 (InitColHdr
     11458*473 (InitColHdr
    1195911459tm "GenericValueColHdrMgr"
    1196011460)
    11961 *492 (PragmaColHdr
     11461*474 (PragmaColHdr
    1196211462tm "GenericPragmaColHdrMgr"
    1196311463)
    11964 *493 (EolColHdr
     11464*475 (EolColHdr
    1196511465tm "GenericEolColHdrMgr"
    1196611466)
    … …  
    1197211472uid 95,0
    1197311473optionalChildren [
    11974 *494 (Sheet
     11474*476 (Sheet
    1197511475sheetRow (SheetRow
    1197611476headerVa (MVa
    … …  
    1198911489font "Tahoma,10,0"
    1199011490)
    11991 emptyMRCItem *495 (MRCItem
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     11491emptyMRCItem *477 (MRCItem
     11492litem &464
    1199311493pos 0
    1199411494dimension 20
    … …  
    1199611496uid 97,0
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    1200111501dimension 20
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    1200311503)
    12004 *497 (MRCItem
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     11504*479 (MRCItem
     11505litem &466
    1200611506pos 1
    1200711507dimension 23
    1200811508uid 99,0
    1200911509)
    12010 *498 (MRCItem
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     11511litem &467
    1201211512pos 2
    1201311513hidden 1
    … …  
    1202611526uid 101,0
    1202711527optionalChildren [
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     11528*481 (MRCItem
     11529litem &468
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    1203111531dimension 20
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    1203311533)
    12034 *500 (MRCItem
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     11534*482 (MRCItem
     11535litem &470
    1203611536pos 1
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    1203911539)
    12040 *501 (MRCItem
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     11540*483 (MRCItem
     11541litem &471
    1204211542pos 2
    1204311543dimension 100
    1204411544uid 104,0
    1204511545)
    12046 *502 (MRCItem
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     11547litem &472
    1204811548pos 3
    1204911549dimension 100
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    1205111551)
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     11553litem &473
    1205411554pos 4
    1205511555dimension 50
    1205611556uid 106,0
    1205711557)
    12058 *504 (MRCItem
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     11559litem &474
    1206011560pos 5
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    1206311563)
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    1206611566pos 6
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb

    r246 r252  
    2121commonDM (CommonDM
    2222ldm (LogicalDM
    23 suid 66,0
     23suid 67,0
    2424usingSuid 1
    2525emptyRow *1 (LEmptyRow
    … …  
    659659n "A1_T"
    660660t "std_logic_vector"
    661 b "(3 DOWNTO 0)"
     661b "(7 DOWNTO 0)"
    662662o 15
    663663suid 66,0
     664i "(OTHERS => '0')"
    664665)
    665666)
    … …  
    12391240(vvPair
    12401241variable "HDLDir"
    1241 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hdl"
     1242value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    12421243)
    12431244(vvPair
    12441245variable "HDSDir"
    1245 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds"
     1246value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    12461247)
    12471248(vvPair
    12481249variable "SideDataDesignDir"
    1249 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
     1250value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"
    12501251)
    12511252(vvPair
    12521253variable "SideDataUserDir"
    1253 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
     1254value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"
    12541255)
    12551256(vvPair
    12561257variable "SourceDir"
    1257 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds"
     1258value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    12581259)
    12591260(vvPair
    … …  
    12711272(vvPair
    12721273variable "d"
    1273 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board"
     1274value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"
    12741275)
    12751276(vvPair
    12761277variable "d_logical"
    1277 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board"
     1278value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"
    12781279)
    12791280(vvPair
    12801281variable "date"
    1281 value "16.06.2010"
     1282value "14.07.2010"
    12821283)
    12831284(vvPair
    … …  
    12911292(vvPair
    12921293variable "dd"
    1293 value "16"
     1294value "14"
    12941295)
    12951296(vvPair
    … …  
    13191320(vvPair
    13201321variable "host"
    1321 value "TU-CC4900F8C7D2"
     1322value "E5B-LABOR6"
    13221323)
    13231324(vvPair
    … …  
    13301331)
    13311332(vvPair
     1333variable "library_downstream_HdsLintPlugin"
     1334value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck"
     1335)
     1336(vvPair
    13321337variable "library_downstream_ISEPARInvoke"
    13331338value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
    … …  
    13471352(vvPair
    13481353variable "mm"
    1349 value "06"
     1354value "07"
    13501355)
    13511356(vvPair
    … …  
    13551360(vvPair
    13561361variable "month"
    1357 value "Jun"
     1362value "Jul"
    13581363)
    13591364(vvPair
    13601365variable "month_long"
    1361 value "Juni"
     1366value "Juli"
    13621367)
    13631368(vvPair
    13641369variable "p"
    1365 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
     1370value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"
    13661371)
    13671372(vvPair
    13681373variable "p_logical"
    1369 value "C:\\FPGA_projects\\FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
     1374value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"
    13701375)
    13711376(vvPair
    … …  
    14231428(vvPair
    14241429variable "time"
    1425 value "15:30:04"
     1430value "15:25:08"
    14261431)
    14271432(vvPair
    … …  
    15001505)
    15011506xt "44000,29200,76000,30000"
    1502 st "RSRLOAD    : OUT    std_logic                       := '0' ;"
     1507st "RSRLOAD    : OUT    std_logic                       := '0' ;
     1508"
    15031509)
    15041510thePort (LogicalPort
    … …  
    15451551)
    15461552xt "44000,12400,61500,13200"
    1547 st "X_50M      : IN     STD_LOGIC  ;"
     1553st "X_50M      : IN     STD_LOGIC  ;
     1554"
    15481555)
    15491556thePort (LogicalPort
    … …  
    15901597)
    15911598xt "44000,10800,61500,11600"
    1592 st "TRG        : IN     STD_LOGIC  ;"
     1599st "TRG        : IN     STD_LOGIC  ;
     1600"
    15931601)
    15941602thePort (LogicalPort
    … …  
    16341642)
    16351643xt "44000,14000,71500,14800"
    1636 st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;"
     1644st "A_CLK      : OUT    std_logic_vector (3 downto 0) ;
     1645"
    16371646)
    16381647thePort (LogicalPort
    … …  
    16801689)
    16811690xt "44000,25200,61500,26000"
    1682 st "OE_ADC     : OUT    STD_LOGIC  ;"
     1691st "OE_ADC     : OUT    STD_LOGIC  ;
     1692"
    16831693)
    16841694thePort (LogicalPort
    … …  
    17261736)
    17271737xt "44000,5200,71500,6000"
    1728 st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;"
     1738st "A_OTR      : IN     std_logic_vector (3 DOWNTO 0) ;
     1739"
    17291740)
    17301741thePort (LogicalPort
    … …  
    17701781)
    17711782xt "44000,2000,72000,2800"
    1772 st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1783st "A0_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1784"
    17731785)
    17741786thePort (LogicalPort
    … …  
    18141826)
    18151827xt "44000,2800,72000,3600"
    1816 st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1828st "A1_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1829"
    18171830)
    18181831thePort (LogicalPort
    … …  
    18581871)
    18591872xt "44000,3600,72000,4400"
    1860 st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1873st "A2_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1874"
    18611875)
    18621876thePort (LogicalPort
    … …  
    19021916)
    19031917xt "44000,4400,72000,5200"
    1904 st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;"
     1918st "A3_D       : IN     std_logic_vector (11 DOWNTO 0) ;
     1919"
    19051920)
    19061921thePort (LogicalPort
    … …  
    19471962)
    19481963xt "44000,14800,61500,15600"
    1949 st "D0_SRCLK   : OUT    STD_LOGIC  ;"
     1964st "D0_SRCLK   : OUT    STD_LOGIC  ;
     1965"
    19501966)
    19511967thePort (LogicalPort
    … …  
    19922008)
    19932009xt "44000,15600,61500,16400"
    1994 st "D1_SRCLK   : OUT    STD_LOGIC  ;"
     2010st "D1_SRCLK   : OUT    STD_LOGIC  ;
     2011"
    19952012)
    19962013thePort (LogicalPort
    … …  
    20372054)
    20382055xt "44000,16400,61500,17200"
    2039 st "D2_SRCLK   : OUT    STD_LOGIC  ;"
     2056st "D2_SRCLK   : OUT    STD_LOGIC  ;
     2057"
    20402058)
    20412059thePort (LogicalPort
    … …  
    20822100)
    20832101xt "44000,17200,61500,18000"
    2084 st "D3_SRCLK   : OUT    STD_LOGIC  ;"
     2102st "D3_SRCLK   : OUT    STD_LOGIC  ;
     2103"
    20852104)
    20862105thePort (LogicalPort
    … …  
    21262145)
    21272146xt "44000,6000,61500,6800"
    2128 st "D0_SROUT   : IN     std_logic  ;"
     2147st "D0_SROUT   : IN     std_logic  ;
     2148"
    21292149)
    21302150thePort (LogicalPort
    … …  
    21692189)
    21702190xt "44000,6800,61500,7600"
    2171 st "D1_SROUT   : IN     std_logic  ;"
     2191st "D1_SROUT   : IN     std_logic  ;
     2192"
    21722193)
    21732194thePort (LogicalPort
    … …  
    22122233)
    22132234xt "44000,7600,61500,8400"
    2214 st "D2_SROUT   : IN     std_logic  ;"
     2235st "D2_SROUT   : IN     std_logic  ;
     2236"
    22152237)
    22162238thePort (LogicalPort
    … …  
    22552277)
    22562278xt "44000,8400,61500,9200"
    2257 st "D3_SROUT   : IN     std_logic  ;"
     2279st "D3_SROUT   : IN     std_logic  ;
     2280"
    22582281)
    22592282thePort (LogicalPort
    … …  
    23092332)
    23102333xt "44000,20400,82000,21200"
    2311 st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
     2334st "D_A        : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
     2335"
    23122336)
    23132337thePort (LogicalPort
    … …  
    23662390)
    23672391xt "44000,19600,76000,20400"
    2368 st "DWRITE     : OUT    std_logic                       := '0' ;"
     2392st "DWRITE     : OUT    std_logic                       := '0' ;
     2393"
    23692394)
    23702395thePort (LogicalPort
    … …  
    24122437)
    24132438xt "44000,18000,61500,18800"
    2414 st "DAC_CS     : OUT    std_logic  ;"
     2439st "DAC_CS     : OUT    std_logic  ;
     2440"
    24152441)
    24162442thePort (LogicalPort
    … …  
    24572483)
    24582484xt "44000,31600,61500,32400"
    2459 st "T0_CS      : OUT    std_logic  ;"
     2485st "T0_CS      : OUT    std_logic  ;
     2486"
    24602487)
    24612488thePort (LogicalPort
    … …  
    25022529)
    25032530xt "44000,32400,61500,33200"
    2504 st "T1_CS      : OUT    std_logic  ;"
     2531st "T1_CS      : OUT    std_logic  ;
     2532"
    25052533)
    25062534thePort (LogicalPort
    … …  
    25472575)
    25482576xt "44000,33200,61500,34000"
    2549 st "T2_CS      : OUT    std_logic  ;"
     2577st "T2_CS      : OUT    std_logic  ;
     2578"
    25502579)
    25512580thePort (LogicalPort
    … …  
    25922621)
    25932622xt "44000,34000,61500,34800"
    2594 st "T3_CS      : OUT    std_logic  ;"
     2623st "T3_CS      : OUT    std_logic  ;
     2624"
    25952625)
    25962626thePort (LogicalPort
    … …  
    26372667)
    26382668xt "44000,30800,61500,31600"
    2639 st "S_CLK      : OUT    std_logic  ;"
     2669st "S_CLK      : OUT    std_logic  ;
     2670"
    26402671)
    26412672thePort (LogicalPort
    … …  
    26822713)
    26832714xt "44000,35600,71500,36400"
    2684 st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;"
     2715st "W_A        : OUT    std_logic_vector (9 DOWNTO 0) ;
     2716"
    26852717)
    26862718thePort (LogicalPort
    … …  
    27282760)
    27292761xt "44000,40400,71000,41200"
    2730 st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)"
     2762st "W_D        : INOUT  std_logic_vector (15 DOWNTO 0)
     2763"
    27312764)
    27322765thePort (LogicalPort
    … …  
    27842817)
    27852818xt "44000,38000,76000,38800"
    2786 st "W_RES      : OUT    std_logic                       := '1' ;"
     2819st "W_RES      : OUT    std_logic                       := '1' ;
     2820"
    27872821)
    27882822thePort (LogicalPort
    … …  
    28402874)
    28412875xt "44000,37200,76000,38000"
    2842 st "W_RD       : OUT    std_logic                       := '1' ;"
     2876st "W_RD       : OUT    std_logic                       := '1' ;
     2877"
    28432878)
    28442879thePort (LogicalPort
    … …  
    28962931)
    28972932xt "44000,38800,76000,39600"
    2898 st "W_WR       : OUT    std_logic                       := '1' ;"
     2933st "W_WR       : OUT    std_logic                       := '1' ;
     2934"
    28992935)
    29002936thePort (LogicalPort
    … …  
    29412977)
    29422978xt "44000,11600,61500,12400"
    2943 st "W_INT      : IN     std_logic  ;"
     2979st "W_INT      : IN     std_logic  ;
     2980"
    29442981)
    29452982thePort (LogicalPort
    … …  
    29953032)
    29963033xt "44000,36400,76000,37200"
    2997 st "W_CS       : OUT    std_logic                       := '1' ;"
     3034st "W_CS       : OUT    std_logic                       := '1' ;
     3035"
    29983036)
    29993037thePort (LogicalPort
    … …  
    30513089)
    30523090xt "44000,24400,76000,25200"
    3053 st "MOSI       : OUT    std_logic                       := '0' ;"
     3091st "MOSI       : OUT    std_logic                       := '0' ;
     3092"
    30543093)
    30553094thePort (LogicalPort
    … …  
    30973136)
    30983137xt "44000,39600,61500,40400"
    3099 st "MISO       : INOUT  std_logic  ;"
     3138st "MISO       : INOUT  std_logic  ;
     3139"
    31003140)
    31013141thePort (LogicalPort
    … …  
    31443184)
    31453185xt "44000,34800,61500,35600"
    3146 st "TRG_V      : OUT    std_logic  ;"
     3186st "TRG_V      : OUT    std_logic  ;
     3187"
    31473188)
    31483189thePort (LogicalPort
    … …  
    31893230)
    31903231xt "44000,26800,61500,27600"
    3191 st "RS485_C_RE : OUT    std_logic  ;"
     3232st "RS485_C_RE : OUT    std_logic  ;
     3233"
    31923234)
    31933235thePort (LogicalPort
    … …  
    32343276)
    32353277xt "44000,26000,61500,26800"
    3236 st "RS485_C_DE : OUT    std_logic  ;"
     3278st "RS485_C_DE : OUT    std_logic  ;
     3279"
    32373280)
    32383281thePort (LogicalPort
    … …  
    32793322)
    32803323xt "44000,28400,61500,29200"
    3281 st "RS485_E_RE : OUT    std_logic  ;"
     3324st "RS485_E_RE : OUT    std_logic  ;
     3325"
    32823326)
    32833327thePort (LogicalPort
    … …  
    33243368)
    33253369xt "44000,27600,61500,28400"
    3326 st "RS485_E_DE : OUT    std_logic  ;"
     3370st "RS485_E_DE : OUT    std_logic  ;
     3371"
    33273372)
    33283373thePort (LogicalPort
    … …  
    33793424)
    33803425xt "44000,18800,76000,19600"
    3381 st "DENABLE    : OUT    std_logic                       := '0' ;"
     3426st "DENABLE    : OUT    std_logic                       := '0' ;
     3427"
    33823428)
    33833429thePort (LogicalPort
    … …  
    34253471)
    34263472xt "44000,30000,61500,30800"
    3427 st "SRIN       : OUT    std_logic  ;"
     3473st "SRIN       : OUT    std_logic  ;
     3474"
    34283475)
    34293476thePort (LogicalPort
    … …  
    34703517)
    34713518xt "44000,22800,61500,23600"
    3472 st "EE_CS      : OUT    std_logic  ;"
     3519st "EE_CS      : OUT    std_logic  ;
     3520"
    34733521)
    34743522thePort (LogicalPort
    … …  
    35253573)
    35263574xt "44000,21200,82000,22000"
    3527 st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;"
     3575st "D_T        : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
     3576"
    35283577)
    35293578thePort (LogicalPort
    … …  
    35823631)
    35833632xt "44000,23600,82000,24400"
    3584 st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;"
     3633st "LED        : OUT    std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;
     3634"
    35853635)
    35863636thePort (LogicalPort
    … …  
    36283678)
    36293679xt "44000,10000,61500,10800"
    3630 st "TEST_TRG   : IN     std_logic  ;"
     3680st "TEST_TRG   : IN     std_logic  ;
     3681"
    36313682)
    36323683thePort (LogicalPort
    … …  
    36713722)
    36723723xt "44000,9200,71500,10000"
    3673 st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;"
     3724st "D_PLLLCK   : IN     std_logic_vector (3 DOWNTO 0) ;
     3725"
    36743726)
    36753727thePort (LogicalPort
    … …  
    37263778)
    37273779xt "44000,22000,82000,22800"
    3728 st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;"
     3780st "D_T2       : OUT    std_logic_vector (3 DOWNTO 0)   := (others => '0') ;
     3781"
    37293782)
    37303783thePort (LogicalPort
    … …  
    37613814)
    37623815xt "27200,97500,32000,98500"
    3763 st "A1_T : (3:0)"
     3816st "A1_T : (7:0)"
    37643817ju 2
    37653818blo "32000,98300"
    37663819tm "CptPortNameMgr"
    37673820)
     3821t (Text
     3822uid 3123,0
     3823va (VaSet
     3824)
     3825xt "25100,98500,32000,99500"
     3826st "(OTHERS => '0')"
     3827ju 2
     3828blo "32000,99300"
     3829tm "InitValueDelayMgr"
     3830)
    37683831)
    37693832dt (MLText
    … …  
    37723835font "Courier New,8,0"
    37733836)
    3774 xt "44000,13200,71500,14000"
    3775 st "A1_T       : OUT    std_logic_vector (3 DOWNTO 0) ;"
     3837xt "44000,13200,82000,14000"
     3838st "A1_T       : OUT    std_logic_vector (7 DOWNTO 0)   := (OTHERS => '0') ;
     3839"
    37763840)
    37773841thePort (LogicalPort
    … …  
    37803844n "A1_T"
    37813845t "std_logic_vector"
    3782 b "(3 DOWNTO 0)"
     3846b "(7 DOWNTO 0)"
    37833847o 15
    37843848suid 66,0
     3849i "(OTHERS => '0')"
    37853850)
    37863851)
    … …  
    37953860lineWidth 2
    37963861)
    3797 xt "15000,6000,33000,99000"
     3862xt "15000,6000,33000,101000"
    37983863)
    37993864oxt "15000,6000,33000,26000"
    … …  
    38693934bg "0,0,32768"
    38703935)
    3871 xt "36200,48000,45700,49000"
     3936xt "36200,48000,45500,49000"
    38723937st "
    38733938by %user on %dd %month %year
    … …  
    44524517)
    44534518)
    4454 lastUid 3076,0
     4519lastUid 3292,0
    44554520activeModelName "Symbol:CDM"
    44564521)

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd

    r249 r252  
    152152uid 8277,0
    153153)
     154(Instance
     155name "U_0"
     156duLibraryName "moduleware"
     157duName "mux"
     158elements [
     159]
     160mwi 1
     161uid 8562,0
     162)
    154163]
    155164libraryRefs [
    … …  
    359368(vvPair
    360369variable "time"
    361 value "11:42:03"
     370value "14:21:30"
    362371)
    363372(vvPair
    … …  
    450459font "Courier New,8,0"
    451460)
    452 xt "-85000,84200,-41500,85000"
    453 st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
     461xt "-85000,86600,-41500,87400"
     462st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\"
     463"
    454464)
    455465)
    … …  
    469479)
    470480xt "-85000,47400,-45000,48200"
    471 st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     481st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     482"
    472483)
    473484)
    … …  
    487498)
    488499xt "-85000,61800,-52500,62600"
    489 st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
     500st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)
     501"
    490502)
    491503)
    … …  
    504516font "Courier New,8,0"
    505517)
    506 xt "-85000,69000,-45000,69800"
    507 st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
     518xt "-85000,71400,-45000,72200"
     519st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)
     520"
    508521)
    509522)
    … …  
    522535font "Courier New,8,0"
    523536)
    524 xt "-85000,69800,-52500,70600"
    525 st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
     537xt "-85000,72200,-52500,73000"
     538st "SIGNAL ram_data               : std_logic_vector(15 downto 0)
     539"
    526540)
    527541)
    … …  
    541555)
    542556xt "-85000,39800,-45000,40600"
    543 st "wiz_reset              : std_logic                                    := '1'"
     557st "wiz_reset              : std_logic                                    := '1'
     558"
    544559)
    545560)
    … …  
    559574)
    560575xt "-85000,37400,-56500,38200"
    561 st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
     576st "wiz_addr               : std_logic_vector(9 DOWNTO 0)
     577"
    562578)
    563579)
    … …  
    577593)
    578594xt "-85000,42200,-56000,43000"
    579 st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
     595st "wiz_data               : std_logic_vector(15 DOWNTO 0)
     596"
    580597)
    581598)
    … …  
    595612)
    596613xt "-85000,38200,-45000,39000"
    597 st "wiz_cs                 : std_logic                                    := '1'"
     614st "wiz_cs                 : std_logic                                    := '1'
     615"
    598616)
    599617)
    … …  
    613631)
    614632xt "-85000,40600,-45000,41400"
    615 st "wiz_wr                 : std_logic                                    := '1'"
     633st "wiz_wr                 : std_logic                                    := '1'
     634"
    616635)
    617636)
    … …  
    631650)
    632651xt "-85000,39000,-45000,39800"
    633 st "wiz_rd                 : std_logic                                    := '1'"
     652st "wiz_rd                 : std_logic                                    := '1'
     653"
    634654)
    635655)
    … …  
    648668)
    649669xt "-85000,26200,-66500,27000"
    650 st "wiz_int                : std_logic"
     670st "wiz_int                : std_logic
     671"
    651672)
    652673)
    … …  
    24732494)
    24742495xt "-85000,23800,-56500,24600"
    2475 st "board_id               : std_logic_vector(3 downto 0)"
     2496st "board_id               : std_logic_vector(3 downto 0)
     2497"
    24762498)
    24772499)
    … …  
    24922514)
    24932515xt "-85000,25400,-66500,26200"
    2494 st "trigger                : std_logic"
     2516st "trigger                : std_logic
     2517"
    24952518)
    24962519)
    … …  
    37203743)
    37213744xt "-85000,24600,-56500,25400"
    3722 st "crate_id               : std_logic_vector(1 downto 0)"
     3745st "crate_id               : std_logic_vector(1 downto 0)
     3746"
    37233747)
    37243748)
    … …  
    39403964font "Courier New,8,0"
    39413965)
    3942 xt "-85000,77000,-52500,77800"
    3943 st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
     3966xt "-85000,79400,-52500,80200"
     3967st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)
     3968"
    39443969)
    39453970)
    … …  
    39603985font "Courier New,8,0"
    39613986)
    3962 xt "-85000,70600,-45000,71400"
    3963 st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
     3987xt "-85000,73000,-45000,73800"
     3988st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)
     3989"
    39643990)
    39653991)
    … …  
    47664792font "Courier New,8,0"
    47674793)
    4768 xt "-85000,78600,-62500,79400"
    4769 st "SIGNAL wiz_busy               : std_logic"
     4794xt "-85000,81000,-62500,81800"
     4795st "SIGNAL wiz_busy               : std_logic
     4796"
    47704797)
    47714798)
    … …  
    47854812font "Courier New,8,0"
    47864813)
    4787 xt "-85000,81000,-41500,81800"
    4788 st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
     4814xt "-85000,83400,-41500,84200"
     4815st "SIGNAL wiz_write_ea           : std_logic                                    := '0'
     4816"
    47894817)
    47904818)
    … …  
    48054833font "Courier New,8,0"
    48064834)
    4807 xt "-85000,83400,-35500,84200"
    4808 st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
     4835xt "-85000,85800,-35500,86600"
     4836st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')
     4837"
    48094838)
    48104839)
    … …  
    48264855font "Courier New,8,0"
    48274856)
    4828 xt "-85000,80200,-35500,81000"
    4829 st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
     4857xt "-85000,82600,-35500,83400"
     4858st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')
     4859"
    48304860)
    48314861)
    … …  
    48464876font "Courier New,8,0"
    48474877)
    4848 xt "-85000,79400,-35500,80200"
    4849 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
     4878xt "-85000,81800,-35500,82600"
     4879st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')
     4880"
    48504881)
    48514882)
    … …  
    48654896font "Courier New,8,0"
    48664897)
    4867 xt "-85000,81800,-41500,82600"
    4868 st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
     4898xt "-85000,84200,-41500,85000"
     4899st "SIGNAL wiz_write_end          : std_logic                                    := '0'
     4900"
    48694901)
    48704902)
    … …  
    48844916font "Courier New,8,0"
    48854917)
    4886 xt "-85000,82600,-41500,83400"
    4887 st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
     4918xt "-85000,85000,-41500,85800"
     4919st "SIGNAL wiz_write_header       : std_logic                                    := '0'
     4920"
    48884921)
    48894922)
    … …  
    49014934font "Courier New,8,0"
    49024935)
    4903 xt "-85000,71400,-62500,72200"
    4904 st "SIGNAL ram_write_ea           : std_logic"
     4936xt "-85000,73800,-62500,74600"
     4937st "SIGNAL ram_write_ea           : std_logic
     4938"
    49054939)
    49064940)
    … …  
    49194953font "Courier New,8,0"
    49204954)
    4921 xt "-85000,72200,-41500,73000"
    4922 st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
     4955xt "-85000,74600,-41500,75400"
     4956st "SIGNAL ram_write_ready        : std_logic                                    := '0'
     4957"
    49234958)
    49244959)
    … …  
    49384973)
    49394974xt "-85000,54600,-41500,55400"
    4940 st "SIGNAL config_start           : std_logic                                    := '0'"
     4975st "SIGNAL config_start           : std_logic                                    := '0'
     4976"
    49414977)
    49424978)
    … …  
    49554991)
    49564992xt "-85000,52200,-62500,53000"
    4957 st "SIGNAL config_ready           : std_logic"
     4993st "SIGNAL config_ready           : std_logic
     4994"
    49584995)
    49594996)
    … …  
    49715008font "Courier New,8,0"
    49725009)
    4973 xt "-85000,73800,-61000,74600"
    4974 st "SIGNAL roi_max                : roi_max_type"
     5010xt "-85000,76200,-61000,77000"
     5011st "SIGNAL roi_max                : roi_max_type
     5012"
    49755013)
    49765014)
    … …  
    49895027font "Courier New,8,0"
    49905028)
    4991 xt "-85000,68200,-52500,69000"
    4992 st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
     5029xt "-85000,70600,-52500,71400"
     5030st "SIGNAL package_length         : std_logic_vector(15 downto 0)
     5031"
    49935032)
    49945033)
    … …  
    50085047)
    50095048xt "-85000,30200,-45000,31000"
    5010 st "adc_oeb                : std_logic                                    := '1'"
     5049st "adc_oeb                : std_logic                                    := '1'
     5050"
    50115051)
    50125052)
    … …  
    51145154font "Courier New,8,0"
    51155155)
    5116 xt "-85000,73000,-60000,73800"
    5117 st "SIGNAL roi_array              : roi_array_type"
     5156xt "-85000,75400,-60000,76200"
     5157st "SIGNAL roi_array              : roi_array_type
     5158"
    51185159)
    51195160)
    … …  
    55485589)
    55495590xt "-85000,27000,-66500,27800"
    5550 st "CLK_25_PS              : std_logic"
     5591st "CLK_25_PS              : std_logic
     5592"
    55515593)
    55525594)
    … …  
    56105652)
    56115653xt "-85000,27800,-66500,28600"
    5612 st "CLK_50                 : std_logic"
     5654st "CLK_50                 : std_logic
     5655"
    56135656)
    56145657)
    … …  
    58605903)
    58615904xt "-85000,45000,-62500,45800"
    5862 st "SIGNAL CLK_25                 : std_logic"
     5905st "SIGNAL CLK_25                 : std_logic
     5906"
    58635907)
    58645908)
    … …  
    59225966)
    59235967xt "-85000,18200,-66500,19000"
    5924 st "CLK                    : std_logic"
     5968st "CLK                    : std_logic
     5969"
    59255970)
    59265971)
    … …  
    59405985)
    59415986xt "-85000,23000,-56500,23800"
    5942 st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
     5987st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)
     5988"
    59435989)
    59445990)
    … …  
    59576003)
    59586004xt "-85000,22200,-61000,23000"
    5959 st "adc_data_array         : adc_data_array_type"
     6005st "adc_data_array         : adc_data_array_type
     6006"
    59606007)
    59616008)
    … …  
    60196066font "Courier New,8,0"
    60206067)
    6021 xt "-85000,62600,-41500,63400"
    6022 st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
     6068xt "-85000,65000,-41500,65800"
     6069st "SIGNAL drs_clk_en             : std_logic                                    := '0'
     6070"
    60236071)
    60246072)
    … …  
    60366084font "Courier New,8,0"
    60376085)
    6038 xt "-85000,65000,-56500,65800"
    6039 st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
     6086xt "-85000,67400,-56500,68200"
     6087st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type
     6088"
    60406089)
    60416090)
    … …  
    60546103font "Courier New,8,0"
    60556104)
    6056 xt "-85000,63400,-41500,64200"
    6057 st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
     6105xt "-85000,65800,-41500,66600"
     6106st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'
     6107"
    60586108)
    60596109)
    … …  
    60746124)
    60756125xt "-85000,32600,-39000,33400"
    6076 st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
     6126st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')
     6127"
    60776128)
    60786129)
    … …  
    60926143)
    60936144xt "-85000,33400,-45000,34200"
    6094 st "drs_dwrite             : std_logic                                    := '1'"
     6145st "drs_dwrite             : std_logic                                    := '1'
     6146"
    60956147)
    60966148)
    … …  
    61086160sl 0
    61096161ro 90
    6110 xt "-28000,56625,-26500,57375"
     6162xt "-39000,99625,-37500,100375"
    61116163)
    61126164(Line
    … …  
    61146166sl 0
    61156167ro 90
    6116 xt "-26500,57000,-26000,57000"
     6168xt "-37500,100000,-37000,100000"
    61176169pts [
    6118 "-26000,57000"
    6119 "-26500,57000"
     6170"-37000,100000"
     6171"-37500,100000"
    61206172]
    61216173)
    … …  
    61326184va (VaSet
    61336185)
    6134 xt "-34900,56500,-29000,57500"
     6186xt "-45900,99500,-40000,100500"
    61356187st "drs_channel_id"
    61366188ju 2
    6137 blo "-29000,57300"
     6189blo "-40000,100300"
    61386190tm "WireNameMgr"
    61396191)
    … …  
    61996251)
    62006252xt "-85000,19000,-66500,19800"
    6201 st "SROUT_in_0             : std_logic"
     6253st "SROUT_in_0             : std_logic
     6254"
    62026255)
    62036256)
    … …  
    62166269)
    62176270xt "-85000,19800,-66500,20600"
    6218 st "SROUT_in_1             : std_logic"
     6271st "SROUT_in_1             : std_logic
     6272"
    62196273)
    62206274)
    … …  
    62336287)
    62346288xt "-85000,20600,-66500,21400"
    6235 st "SROUT_in_2             : std_logic"
     6289st "SROUT_in_2             : std_logic
     6290"
    62366291)
    62376292)
    … …  
    62506305)
    62516306xt "-85000,21400,-66500,22200"
    6252 st "SROUT_in_3             : std_logic"
     6307st "SROUT_in_3             : std_logic
     6308"
    62536309)
    62546310)
    … …  
    64466502font "Courier New,8,0"
    64476503)
    6448 xt "-85000,64200,-62500,65000"
    6449 st "SIGNAL drs_read_s_cell_ready  : std_logic"
     6504xt "-85000,66600,-62500,67400"
     6505st "SIGNAL drs_read_s_cell_ready  : std_logic
     6506"
    64506507)
    64516508)
    … …  
    69266983)
    69276984xt "-85000,28600,-45000,29400"
    6928 st "RSRLOAD                : std_logic                                    := '0'"
     6985st "RSRLOAD                : std_logic                                    := '0'
     6986"
    69296987)
    69306988)
    … …  
    69897047)
    69907048xt "-85000,29400,-45000,30200"
    6991 st "SRCLK                  : std_logic                                    := '0'"
     7049st "SRCLK                  : std_logic                                    := '0'
     7050"
    69927051)
    69937052)
    … …  
    72147273t "std_logic_vector"
    72157274b "(15 DOWNTO 0)"
    7216 o 12
     7275o 14
    72177276suid 5,0
    72187277)
    … …  
    72497308n "roi_array"
    72507309t "roi_array_type"
    7251 o 11
     7310o 13
    72527311suid 6,0
    72537312)
    … …  
    74647523)
    74657524)
     7525*227 (CptPort
     7526uid 8500,0
     7527ps "OnEdgeStrategy"
     7528shape (Triangle
     7529uid 8501,0
     7530ro 90
     7531va (VaSet
     7532vasetType 1
     7533fg "0,65535,0"
     7534)
     7535xt "92000,109625,92750,110375"
     7536)
     7537tg (CPTG
     7538uid 8502,0
     7539ps "CptPortTextPlaceStrategy"
     7540stg "RightVerticalLayoutStrategy"
     7541f (Text
     7542uid 8503,0
     7543va (VaSet
     7544)
     7545xt "83800,109500,91000,110500"
     7546st "drs_address : (3:0)"
     7547ju 2
     7548blo "91000,110300"
     7549)
     7550)
     7551thePort (LogicalPort
     7552m 1
     7553decl (Decl
     7554n "drs_address"
     7555t "std_logic_vector"
     7556b "(3 DOWNTO 0)"
     7557o 11
     7558suid 13,0
     7559)
     7560)
     7561)
     7562*228 (CptPort
     7563uid 8504,0
     7564ps "OnEdgeStrategy"
     7565shape (Triangle
     7566uid 8505,0
     7567ro 90
     7568va (VaSet
     7569vasetType 1
     7570fg "0,65535,0"
     7571)
     7572xt "92000,110625,92750,111375"
     7573)
     7574tg (CPTG
     7575uid 8506,0
     7576ps "CptPortTextPlaceStrategy"
     7577stg "RightVerticalLayoutStrategy"
     7578f (Text
     7579uid 8507,0
     7580va (VaSet
     7581)
     7582xt "83800,110500,91000,111500"
     7583st "drs_address_mode"
     7584ju 2
     7585blo "91000,111300"
     7586)
     7587)
     7588thePort (LogicalPort
     7589m 1
     7590decl (Decl
     7591n "drs_address_mode"
     7592t "std_logic"
     7593o 12
     7594suid 14,0
     7595)
     7596)
     7597)
    74667598]
    74677599shape (Rectangle
    … …  
    74817613stg "VerticalLayoutStrategy"
    74827614textVec [
    7483 *227 (Text
     7615*229 (Text
    74847616uid 5075,0
    74857617va (VaSet
    … …  
    74917623tm "BdLibraryNameMgr"
    74927624)
    7493 *228 (Text
     7625*230 (Text
    74947626uid 5076,0
    74957627va (VaSet
    … …  
    75017633tm "CptNameMgr"
    75027634)
    7503 *229 (Text
     7635*231 (Text
    75047636uid 5077,0
    75057637va (VaSet
    … …  
    75477679archFileType "UNKNOWN"
    75487680)
    7549 *230 (Net
     7681*232 (Net
    75507682uid 5088,0
    75517683decl (Decl
    … …  
    75627694)
    75637695xt "-85000,48200,-53000,49000"
    7564 st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
    7565 )
    7566 )
    7567 *231 (Net
     7696st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)
     7697"
     7698)
     7699)
     7700*233 (Net
    75687701uid 5096,0
    75697702decl (Decl
    … …  
    75797712)
    75807713xt "-85000,50600,-62500,51400"
    7581 st "SIGNAL config_data_valid      : std_logic"
    7582 )
    7583 )
    7584 *232 (Net
     7714st "SIGNAL config_data_valid      : std_logic
     7715"
     7716)
     7717)
     7718*234 (Net
    75857719uid 5104,0
    75867720decl (Decl
    … …  
    75967730)
    75977731xt "-85000,49000,-62500,49800"
    7598 st "SIGNAL config_busy            : std_logic"
    7599 )
    7600 )
    7601 *233 (Net
     7732st "SIGNAL config_busy            : std_logic
     7733"
     7734)
     7735)
     7736*235 (Net
    76027737uid 5112,0
    76037738decl (Decl
    … …  
    76147749)
    76157750xt "-85000,49800,-52500,50600"
    7616 st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
    7617 )
    7618 )
    7619 *234 (Net
     7751st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)
     7752"
     7753)
     7754)
     7755*236 (Net
    76207756uid 5120,0
    76217757decl (Decl
    … …  
    76317767)
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    1075011499shape (OrthoPolyLine
    … …  
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    … …  
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    … …  
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    1086211611shape (OrthoPolyLine
    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    1114711896es 0
    … …  
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    1117411923ps "OnConnectorStrategy"
    … …  
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    1118611935ps "OnConnectorStrategy"
    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    1135512104uid 4240,0
    1135612105shape (OrthoPolyLine
    … …  
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    … …  
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    … …  
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    … …  
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    1143312182shape (OrthoPolyLine
    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    1158112330shape (OrthoPolyLine
    … …  
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    1159412343sat 32
    … …  
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    … …  
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    … …  
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    1169412443shape (OrthoPolyLine
    … …  
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    … …  
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    … …  
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    1180912558ps "OnConnectorStrategy"
    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    1213312882shape (OrthoPolyLine
    … …  
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    1217012919optionalChildren [
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    … …  
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    … …  
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    … …  
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    … …  
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    1227213021sat 32
    … …  
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    1229513044shape (OrthoPolyLine
    … …  
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     13078)
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    … …  
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    1236913118shape (OrthoPolyLine
    … …  
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    … …  
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    12444 )
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    … …  
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    1246213211sat 32
    … …  
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     13229on &245
     13230)
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    1248413233shape (OrthoPolyLine
    … …  
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    1249613245)
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    1249913248sat 32
    … …  
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    1251613265)
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    12518 )
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     13267)
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    … …  
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    1253313282)
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    1253613285sat 32
    … …  
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    1255313302)
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     13303on &244
     13304)
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    … …  
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    1259313342optionalChildren [
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     13343&401
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    … …  
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    … …  
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    … …  
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    … …  
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    1268113430)
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    12683 )
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     13432)
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    … …  
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    1271913468)
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    12721 )
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     13470)
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    … …  
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    1273513484)
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     13485end &253
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    … …  
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     13507*427 (Wire
    1275913508uid 5745,0
    1276013509shape (OrthoPolyLine
    … …  
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    12774 end &260
     13523end &262
    1277513524sat 32
    1277613525eat 32
    … …  
    1279213541)
    1279313542)
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    12795 )
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     13543on &257
     13544)
     13545*428 (Wire
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    1279813547shape (OrthoPolyLine
    … …  
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    1280813557)
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     13558end &267
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    … …  
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     13579*429 (Wire
    1283113580uid 5813,0
    1283213581shape (OrthoPolyLine
    … …  
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    1284213591)
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    12844 end &276
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    … …  
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    1286513614)
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    12867 )
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     13616)
     13617*430 (Wire
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     13631end &279
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    … …  
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    1290313652)
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    12905 )
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     13653on &275
     13654)
     13655*431 (Wire
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    1290813657shape (OrthoPolyLine
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    1292213671eat 32
    … …  
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    1294113690)
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    12943 )
    12944 *406 (Wire
     13691on &276
     13692)
     13693*432 (Wire
    1294513694uid 5837,0
    1294613695shape (OrthoPolyLine
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    1295713706)
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    12959 end &279
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     13708end &281
    1296013709sat 32
    1296113710eat 32
    … …  
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    1298113730)
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    12983 )
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     13732)
     13733*433 (Wire
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    1298613735shape (OrthoPolyLine
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    13021 )
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     13770)
     13771*434 (Wire
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    1302413773shape (OrthoPolyLine
    … …  
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    13059 )
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     13807on &283
     13808)
     13809*435 (Wire
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    … …  
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    13097 )
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     13846)
     13847*436 (Wire
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    … …  
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    1311513864sat 32
    … …  
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     13883on &284
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     13885*437 (Wire
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    1313813887shape (OrthoPolyLine
    … …  
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    1317113920)
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     13922)
     13923*438 (Wire
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    1317613925shape (OrthoPolyLine
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     17019litem &529
    1600917020pos 51
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     17025litem &530
    1601517026pos 11
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    1601817029)
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     17031litem &531
    1602117032pos 12
    1602217033dimension 20
    1602317034uid 4071,0
    1602417035)
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     17036*621 (MRCItem
     17037litem &532
    1602717038pos 52
    1602817039dimension 20
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    1603017041)
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     17043litem &533
    1603317044pos 13
    1603417045dimension 20
    1603517046uid 4235,0
    1603617047)
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     17048*623 (MRCItem
     17049litem &534
    1603917050pos 14
    1604017051dimension 20
    1604117052uid 4263,0
    1604217053)
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    16044 litem &503
     17054*624 (MRCItem
     17055litem &535
    1604517056pos 15
    1604617057dimension 20
    1604717058uid 4277,0
    1604817059)
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    16050 litem &504
     17060*625 (MRCItem
     17061litem &536
    1605117062pos 53
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    1605317064uid 4564,0
    1605417065)
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     17066*626 (MRCItem
     17067litem &537
    1605717068pos 54
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    1605917070uid 4566,0
    1606017071)
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     17073litem &538
    1606317074pos 55
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    1606617077)
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     17079litem &539
    1606917080pos 16
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    1607217083)
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     17085litem &540
    1607517086pos 17
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    1607817089)
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    1608117092pos 18
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    1608417095)
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    1609017101)
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    1609617107)
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    1610217113)
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    1610817119)
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    1611417125)
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    1612017131)
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    1612617137)
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    1613217143)
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    1613817149)
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    1614117152pos 60
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    1614417155)
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    1614717158pos 61
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    1615017161)
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    1615317164pos 62
    1615417165dimension 20
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    1615617167)
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    1615917170pos 63
    1616017171dimension 20
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    1616217173)
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    1616517176pos 64
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    1617417185)
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     17186*646 (MRCItem
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    1617717188pos 24
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    1618017191)
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     17193litem &558
    1618317194pos 66
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    1618617197)
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     17199litem &559
    1618917200pos 67
    1619017201dimension 20
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    1619217203)
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    1619517206pos 68
    1619617207dimension 20
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    1619817209)
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     17210*650 (MRCItem
     17211litem &561
    1620117212pos 69
    1620217213dimension 20
    1620317214uid 5601,0
    1620417215)
    16205 *616 (MRCItem
    16206 litem &530
     17216*651 (MRCItem
     17217litem &562
    1620717218pos 70
    1620817219dimension 20
    1620917220uid 5643,0
    1621017221)
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     17222*652 (MRCItem
     17223litem &563
    1621317224pos 71
    1621417225dimension 20
    1621517226uid 5645,0
    1621617227)
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    16218 litem &532
     17228*653 (MRCItem
     17229litem &564
    1621917230pos 72
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    1622117232uid 5752,0
    1622217233)
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     17234*654 (MRCItem
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    1622517236pos 25
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    1622817239)
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    1623117242pos 26
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    1623417245)
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     17246*656 (MRCItem
     17247litem &567
    1623717248pos 27
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    1624017251)
    16241 *622 (MRCItem
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     17252*657 (MRCItem
     17253litem &568
    1624317254pos 28
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    1624617257)
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     17259litem &569
    1624917260pos 73
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    1625217263)
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     17264*659 (MRCItem
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    1625517266pos 74
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    1625817269)
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     17270*660 (MRCItem
     17271litem &571
    1626117272pos 75
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    1626317274uid 6023,0
    1626417275)
    16265 *626 (MRCItem
    16266 litem &540
     17276*661 (MRCItem
     17277litem &572
    1626717278pos 76
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    1627017281)
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    1627317284pos 77
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    1627617287)
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    16278 litem &542
     17288*663 (MRCItem
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    1627917290pos 29
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    1628217293)
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    1628817299)
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     17300*665 (MRCItem
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    1629117302pos 78
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    1629317304uid 6465,0
    1629417305)
    16295 *631 (MRCItem
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     17306*666 (MRCItem
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    1629717308pos 79
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    1630017311)
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    1630317314pos 80
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    1630517316uid 8421,0
     17317)
     17318*668 (MRCItem
     17319litem &579
     17320pos 81
     17321dimension 20
     17322uid 8610,0
     17323)
     17324*669 (MRCItem
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     17326pos 82
     17327dimension 20
     17328uid 8612,0
     17329)
     17330*670 (MRCItem
     17331litem &581
     17332pos 83
     17333dimension 20
     17334uid 8614,0
    1630617335)
    1630717336]
    … …  
    1631617345uid 73,0
    1631717346optionalChildren [
    16318 *633 (MRCItem
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    1633517364)
    16336 *636 (MRCItem
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     17365*674 (MRCItem
     17366litem &493
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    1634117370)
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     17371*675 (MRCItem
     17372litem &494
    1634417373pos 4
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    1634717376)
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     17378litem &495
    1635017379pos 5
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    1635317382)
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     17384litem &496
    1635617385pos 6
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    1635917388)
    16360 *640 (MRCItem
    16361 litem &465
     17389*678 (MRCItem
     17390litem &497
    1636217391pos 7
    1636317392dimension 80
    … …  
    1637917408genericsCommonDM (CommonDM
    1638017409ldm (LogicalDM
    16381 emptyRow *641 (LEmptyRow
     17410emptyRow *679 (LEmptyRow
    1638217411)
    1638317412uid 83,0
    1638417413optionalChildren [
    16385 *642 (RefLabelRowHdr
    16386 )
    16387 *643 (TitleRowHdr
    16388 )
    16389 *644 (FilterRowHdr
    16390 )
    16391 *645 (RefLabelColHdr
     17414*680 (RefLabelRowHdr
     17415)
     17416*681 (TitleRowHdr
     17417)
     17418*682 (FilterRowHdr
     17419)
     17420*683 (RefLabelColHdr
    1639217421tm "RefLabelColHdrMgr"
    1639317422)
    16394 *646 (RowExpandColHdr
     17423*684 (RowExpandColHdr
    1639517424tm "RowExpandColHdrMgr"
    1639617425)
    16397 *647 (GroupColHdr
     17426*685 (GroupColHdr
    1639817427tm "GroupColHdrMgr"
    1639917428)
    16400 *648 (NameColHdr
     17429*686 (NameColHdr
    1640117430tm "GenericNameColHdrMgr"
    1640217431)
    16403 *649 (TypeColHdr
     17432*687 (TypeColHdr
    1640417433tm "GenericTypeColHdrMgr"
    1640517434)
    16406 *650 (InitColHdr
     17435*688 (InitColHdr
    1640717436tm "GenericValueColHdrMgr"
    1640817437)
    16409 *651 (PragmaColHdr
     17438*689 (PragmaColHdr
    1641017439tm "GenericPragmaColHdrMgr"
    1641117440)
    16412 *652 (EolColHdr
     17441*690 (EolColHdr
    1641317442tm "GenericEolColHdrMgr"
    1641417443)
    16415 *653 (LogGeneric
     17444*691 (LogGeneric
    1641617445generic (GiElement
    1641717446name "RAMADDRWIDTH64b"
    … …  
    1642817457uid 95,0
    1642917458optionalChildren [
    16430 *654 (Sheet
     17459*692 (Sheet
    1643117460sheetRow (SheetRow
    1643217461headerVa (MVa
    … …  
    1644517474font "Tahoma,10,0"
    1644617475)
    16447 emptyMRCItem *655 (MRCItem
    16448 litem &641
     17476emptyMRCItem *693 (MRCItem
     17477litem &679
    1644917478pos 1
    1645017479dimension 20
    … …  
    1645217481uid 97,0
    1645317482optionalChildren [
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     17483*694 (MRCItem
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    16460 *657 (MRCItem
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    1646217491pos 1
    1646317492dimension 23
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    1646517494)
    16466 *658 (MRCItem
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    1646817497pos 2
    1646917498hidden 1
    … …  
    1647117500uid 100,0
    1647217501)
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    … …  
    1648817517uid 101,0
    1648917518optionalChildren [
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    1651917548)
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    1652517554)
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak

    r246 r252  
    167167(vvPair
    168168variable "HDLDir"
    169 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"
     169value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    170170)
    171171(vvPair
    172172variable "HDSDir"
    173 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
     173value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    174174)
    175175(vvPair
    176176variable "SideDataDesignDir"
    177 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
     177value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
    178178)
    179179(vvPair
    180180variable "SideDataUserDir"
    181 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
     181value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
    182182)
    183183(vvPair
    184184variable "SourceDir"
    185 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
     185value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    186186)
    187187(vvPair
    … …  
    199199(vvPair
    200200variable "d"
    201 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
     201value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
    202202)
    203203(vvPair
    204204variable "d_logical"
    205 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
     205value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
    206206)
    207207(vvPair
    208208variable "date"
    209 value "02.07.2010"
     209value "12.07.2010"
    210210)
    211211(vvPair
    212212variable "day"
    213 value "Fr"
     213value "Mo"
    214214)
    215215(vvPair
    216216variable "day_long"
    217 value "Freitag"
     217value "Montag"
    218218)
    219219(vvPair
    220220variable "dd"
    221 value "02"
     221value "12"
    222222)
    223223(vvPair
    … …  
    299299(vvPair
    300300variable "p"
    301 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
     301value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
    302302)
    303303(vvPair
    304304variable "p_logical"
    305 value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
     305value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
    306306)
    307307(vvPair
    … …  
    359359(vvPair
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_manager/symbol.sb

    r246 r252  
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    … …  
    710747(vvPair
    711748variable "HDLDir"
    712 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl"
     749value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    713750)
    714751(vvPair
    715752variable "HDSDir"
    716 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"
     753value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    717754)
    718755(vvPair
    719756variable "SideDataDesignDir"
    720 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"
     757value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"
    721758)
    722759(vvPair
    723760variable "SideDataUserDir"
    724 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"
     761value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"
    725762)
    726763(vvPair
    727764variable "SourceDir"
    728 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"
     765value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    729766)
    730767(vvPair
    … …  
    742779(vvPair
    743780variable "d"
    744 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
     781value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
    745782)
    746783(vvPair
    747784variable "d_logical"
    748 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
     785value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"
    749786)
    750787(vvPair
    751788variable "date"
    752 value "07.05.2010"
     789value "12.07.2010"
    753790)
    754791(vvPair
    755792variable "day"
    756 value "Fr"
     793value "Mo"
    757794)
    758795(vvPair
    759796variable "day_long"
    760 value "Freitag"
     797value "Montag"
    761798)
    762799(vvPair
    763800variable "dd"
    764 value "07"
     801value "12"
    765802)
    766803(vvPair
    … …  
    790827(vvPair
    791828variable "host"
    792 value "E5PCXX"
     829value "TU-CC4900F8C7D2"
    793830)
    794831(vvPair
    … …  
    818855(vvPair
    819856variable "mm"
    820 value "05"
     857value "07"
    821858)
    822859(vvPair
    … …  
    826863(vvPair
    827864variable "month"
    828 value "Mai"
     865value "Jul"
    829866)
    830867(vvPair
    831868variable "month_long"
    832 value "Mai"
     869value "Juli"
    833870)
    834871(vvPair
    835872variable "p"
    836 value "D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
     873value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
    837874)
    838875(vvPair
    839876variable "p_logical"
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     877value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"
    841878)
    842879(vvPair
    … …  
    858895(vvPair
    859896variable "task_LeonardoPath"
    860 value "$HDS_HOME/../Exemplar/bin/win32"
     897value "<TBD>"
    861898)
    862899(vvPair
    863900variable "task_ModelSimPath"
    864 value "D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32"
     901value "<TBD>"
    865902)
    866903(vvPair
    … …  
    870907(vvPair
    871908variable "task_PrecisionRTLPath"
    872 value "$HDS_HOME/../Precision/Mgc_home/bin"
     909value "<TBD>"
    873910)
    874911(vvPair
    … …  
    894931(vvPair
    895932variable "time"
    896 value "12:45:37"
     933value "14:11:44"
    897934)
    898935(vvPair
    … …  
    902939(vvPair
    903940variable "user"
    904 value "kai"
     941value "dneise"
    905942)
    906943(vvPair
    907944variable "version"
    908 value "2009.1 (Build 12)"
     945value "2009.2 (Build 10)"
    909946)
    910947(vvPair
    … …  
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     1681*109 (CptPort
    16451682uid 492,0
    16461683ps "OnEdgeStrategy"
    … …  
    16891726)
    16901727)
     1728*110 (CptPort
     1729uid 528,0
     1730ps "OnEdgeStrategy"
     1731shape (Triangle
     1732uid 529,0
     1733ro 90
     1734va (VaSet
     1735vasetType 1
     1736fg "0,65535,0"
     1737)
     1738xt "67000,32625,67750,33375"
     1739)
     1740tg (CPTG
     1741uid 530,0
     1742ps "CptPortTextPlaceStrategy"
     1743stg "RightVerticalLayoutStrategy"
     1744f (Text
     1745uid 531,0
     1746va (VaSet
     1747)
     1748xt "58800,32500,66000,33500"
     1749st "drs_address : (3:0)"
     1750ju 2
     1751blo "66000,33300"
     1752tm "CptPortNameMgr"
     1753)
     1754)
     1755dt (MLText
     1756uid 532,0
     1757va (VaSet
     1758font "Courier New,8,0"
     1759)
     1760xt "2000,23800,33000,24600"
     1761st "drs_address       : OUT    std_logic_vector (3 DOWNTO 0) ;
     1762"
     1763)
     1764thePort (LogicalPort
     1765m 1
     1766decl (Decl
     1767n "drs_address"
     1768t "std_logic_vector"
     1769b "(3 DOWNTO 0)"
     1770o 17
     1771suid 24,0
     1772)
     1773)
     1774)
     1775*111 (CptPort
     1776uid 533,0
     1777ps "OnEdgeStrategy"
     1778shape (Triangle
     1779uid 534,0
     1780ro 90
     1781va (VaSet
     1782vasetType 1
     1783fg "0,65535,0"
     1784)
     1785xt "67000,33625,67750,34375"
     1786)
     1787tg (CPTG
     1788uid 535,0
     1789ps "CptPortTextPlaceStrategy"
     1790stg "RightVerticalLayoutStrategy"
     1791f (Text
     1792uid 536,0
     1793va (VaSet
     1794)
     1795xt "58800,33500,66000,34500"
     1796st "drs_address_mode"
     1797ju 2
     1798blo "66000,34300"
     1799tm "CptPortNameMgr"
     1800)
     1801)
     1802dt (MLText
     1803uid 537,0
     1804va (VaSet
     1805font "Courier New,8,0"
     1806)
     1807xt "2000,24600,22000,25400"
     1808st "drs_address_mode  : OUT    std_logic
     1809"
     1810)
     1811thePort (LogicalPort
     1812m 1
     1813decl (Decl
     1814n "drs_address_mode"
     1815t "std_logic"
     1816o 18
     1817suid 25,0
     1818)
     1819)
     1820)
    16911821]
    16921822shape (Rectangle
    … …  
    16981828lineWidth 2
    16991829)
    1700 xt "42000,14000,67000,33000"
     1830xt "42000,14000,67000,35000"
    17011831)
    17021832oxt "42000,14000,66000,27000"
    … …  
    17241854)
    17251855)
    1726 gi *106 (GenericInterface
     1856gi *112 (GenericInterface
    17271857uid 13,0
    17281858ps "CenterOffsetStrategy"
    … …  
    17691899)
    17701900)
    1771 *107 (Grouping
     1901*113 (Grouping
    17721902uid 16,0
    17731903optionalChildren [
    1774 *108 (CommentText
     1904*114 (CommentText
    17751905uid 18,0
    17761906shape (Rectangle
    … …  
    18031933titleBlock 1
    18041934)
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     1935*115 (CommentText
    18061936uid 21,0
    18071937shape (Rectangle
    … …  
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    18351965)
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     1966*116 (CommentText
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    … …  
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    18661996)
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     1997*117 (CommentText
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    … …  
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    18972027)
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     2028*118 (CommentText
    18992029uid 30,0
    19002030shape (Rectangle
    … …  
    19262056titleBlock 1
    19272057)
    1928 *113 (CommentText
     2058*119 (CommentText
    19292059uid 33,0
    19302060shape (Rectangle
    … …  
    19572087titleBlock 1
    19582088)
    1959 *114 (CommentText
     2089*120 (CommentText
    19602090uid 36,0
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    … …  
    19892119titleBlock 1
    19902120)
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     2121*121 (CommentText
    19922122uid 39,0
    19932123shape (Rectangle
    … …  
    20202150titleBlock 1
    20212151)
    2022 *116 (CommentText
     2152*122 (CommentText
    20232153uid 42,0
    20242154shape (Rectangle
    … …  
    20512181titleBlock 1
    20522182)
    2053 *117 (CommentText
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    20542184uid 45,0
    20552185shape (Rectangle
    … …  
    20952225oxt "14000,66000,55000,71000"
    20962226)
    2097 *118 (CommentText
     2227*124 (CommentText
    20982228uid 134,0
    20992229shape (Rectangle
    … …  
    21382268color "26368,26368,26368"
    21392269)
    2140 packageList *119 (PackageList
     2270packageList *125 (PackageList
    21412271uid 169,0
    21422272stg "VerticalLayoutStrategy"
    21432273textVec [
    2144 *120 (Text
     2274*126 (Text
    21452275uid 170,0
    21462276va (VaSet
    … …  
    21512281blo "0,1800"
    21522282)
    2153 *121 (MLText
     2283*127 (MLText
    21542284uid 171,0
    21552285va (VaSet
    … …  
    22522382)
    22532383)
    2254 gi *122 (GenericInterface
     2384gi *128 (GenericInterface
    22552385ps "CenterOffsetStrategy"
    22562386matrix (Matrix
    … …  
    23492479)
    23502480)
    2351 DeclarativeBlock *123 (SymDeclBlock
     2481DeclarativeBlock *129 (SymDeclBlock
    23522482uid 1,0
    23532483stg "SymDeclLayoutStrategy"
    … …  
    23752505font "Arial,8,1"
    23762506)
    2377 xt "0,23800,2400,24800"
     2507xt "0,25400,2400,26400"
    23782508st "User:"
    2379 blo "0,24600"
     2509blo "0,26200"
    23802510)
    23812511internalLabel (Text
    … …  
    23942524font "Courier New,8,0"
    23952525)
    2396 xt "2000,24800,2000,24800"
     2526xt "2000,26400,2000,26400"
    23972527tm "SyDeclarativeTextMgr"
    23982528)
    … …  
    24072537)
    24082538)
    2409 lastUid 504,0
     2539lastUid 547,0
    24102540activeModelName "Symbol:CDM"
    24112541)

  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd

    r246 r252  
    6060)
    6161version "29.1"
    62 appVersion "2009.1 (Build 12)"
     62appVersion "2009.2 (Build 10)"
    6363noEmbeddedEditors 1
    6464model (BlockDiag
    … …  
    6767(vvPair
    6868variable "HDLDir"
    69 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"
     69value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    7070)
    7171(vvPair
    7272variable "HDSDir"
    73 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
     73value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    7474)
    7575(vvPair
    7676variable "SideDataDesignDir"
    77 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
     77value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
    7878)
    7979(vvPair
    8080variable "SideDataUserDir"
    81 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
     81value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
    8282)
    8383(vvPair
    8484variable "SourceDir"
    85 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
     85value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    8686)
    8787(vvPair
    … …  
    9999(vvPair
    100100variable "d"
    101 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
     101value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    102102)
    103103(vvPair
    104104variable "d_logical"
    105 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
     105value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    106106)
    107107(vvPair
    108108variable "date"
    109 value "27.05.2010"
     109value "12.07.2010"
    110110)
    111111(vvPair
    112112variable "day"
    113 value "Do"
     113value "Mo"
    114114)
    115115(vvPair
    116116variable "day_long"
    117 value "Donnerstag"
     117value "Montag"
    118118)
    119119(vvPair
    120120variable "dd"
    121 value "27"
     121value "12"
    122122)
    123123(vvPair
    … …  
    147147(vvPair
    148148variable "host"
    149 value "IHP110"
     149value "TU-CC4900F8C7D2"
    150150)
    151151(vvPair
    … …  
    175175(vvPair
    176176variable "mm"
    177 value "05"
     177value "07"
    178178)
    179179(vvPair
    … …  
    183183(vvPair
    184184variable "month"
    185 value "Mai"
     185value "Jul"
    186186)
    187187(vvPair
    188188variable "month_long"
    189 value "Mai"
     189value "Juli"
    190190)
    191191(vvPair
    192192variable "p"
    193 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
     193value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
    194194)
    195195(vvPair
    196196variable "p_logical"
    197 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
     197value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
    198198)
    199199(vvPair
    … …  
    219219(vvPair
    220220variable "task_ModelSimPath"
    221 value "D:\\modeltech_6.5e\\win32"
     221value "<TBD>"
    222222)
    223223(vvPair
    … …  
    251251(vvPair
    252252variable "time"
    253 value "10:24:05"
     253value "14:13:34"
    254254)
    255255(vvPair
    … …  
    259259(vvPair
    260260variable "user"
    261 value "daqct3"
     261value "dneise"
    262262)
    263263(vvPair
    264264variable "version"
    265 value "2009.1 (Build 12)"
     265value "2009.2 (Build 10)"
    266266)
    267267(vvPair
    … …  
    303303bg "0,0,32768"
    304304)
    305 xt "16200,76000,25900,77000"
     305xt "16200,76000,25500,77000"
    306306st "
    307307by %user on %dd %month %year
    … …  
    621621font "Courier New,8,0"
    622622)
    623 xt "22000,2000,38000,2800"
    624 st "clk               : STD_LOGIC"
     623xt "29000,2200,45000,3000"
     624st "clk               : STD_LOGIC
     625"
    625626)
    626627)
    … …  
    639640font "Courier New,8,0"
    640641)
    641 xt "22000,15000,51500,15800"
    642 st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)"
     642xt "29000,16800,58500,17600"
     643st "SIGNAL ram_wren          : std_logic_VECTOR(0 DOWNTO 0)
     644"
    643645)
    644646)
    … …  
    657659font "Courier New,8,0"
    658660)
    659 xt "22000,2800,48000,3600"
    660 st "config_addr       : std_logic_vector(7 DOWNTO 0)"
     661xt "29000,3000,55000,3800"
     662st "config_addr       : std_logic_vector(7 DOWNTO 0)
     663"
    661664)
    662665)
    … …  
    675678font "Courier New,8,0"
    676679)
    677 xt "22000,13400,52000,14200"
    678 st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)"
     680xt "29000,15200,59000,16000"
     681st "SIGNAL ram_data_in       : std_logic_VECTOR(15 DOWNTO 0)
     682"
    679683)
    680684)
    … …  
    692696font "Courier New,8,0"
    693697)
    694 xt "22000,6800,38000,7600"
    695 st "config_data_valid : std_logic"
     698xt "29000,7000,45000,7800"
     699st "config_data_valid : std_logic
     700"
    696701)
    697702)
    … …  
    709714font "Courier New,8,0"
    710715)
    711 xt "22000,6000,38000,6800"
    712 st "config_busy       : std_logic"
     716xt "29000,6200,45000,7000"
     717st "config_busy       : std_logic
     718"
    713719)
    714720)
    … …  
    727733font "Courier New,8,0"
    728734)
    729 xt "22000,10800,48500,11600"
    730 st "config_data       : std_logic_vector(15 DOWNTO 0)"
     735xt "29000,12600,55500,13400"
     736st "config_data       : std_logic_vector(15 DOWNTO 0)
     737"
    731738)
    732739)
    … …  
    744751font "Courier New,8,0"
    745752)
    746 xt "22000,10000,40500,10800"
    747 st "roi_array         : roi_array_type"
     753xt "29000,11800,47500,12600"
     754st "roi_array         : roi_array_type
     755"
    748756)
    749757)
    … …  
    762770font "Courier New,8,0"
    763771)
    764 xt "22000,12600,51500,13400"
    765 st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)"
     772xt "29000,14400,58500,15200"
     773st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)
     774"
    766775)
    767776)
    … …  
    779788font "Courier New,8,0"
    780789)
    781 xt "22000,5200,38000,6000"
    782 st "config_wr_en      : std_logic"
     790xt "29000,5400,45000,6200"
     791st "config_wr_en      : std_logic
     792"
    783793)
    784794)
    … …  
    797807font "Courier New,8,0"
    798808)
    799 xt "22000,14200,52000,15000"
    800 st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)"
     809xt "29000,16000,59000,16800"
     810st "SIGNAL ram_data_out      : std_logic_VECTOR(15 DOWNTO 0)
     811"
    801812)
    802813)
    … …  
    814825font "Courier New,8,0"
    815826)
    816 xt "22000,9200,40500,10000"
    817 st "dac_array         : dac_array_type"
     827xt "29000,9400,47500,10200"
     828st "dac_array         : dac_array_type
     829"
    818830)
    819831)
    … …  
    831843font "Courier New,8,0"
    832844)
    833 xt "22000,3600,38000,4400"
    834 st "config_rd_en      : std_logic"
     845xt "29000,3800,45000,4600"
     846st "config_rd_en      : std_logic
     847"
    835848)
    836849)
    … …  
    848861font "Courier New,8,0"
    849862)
    850 xt "22000,4400,38000,5200"
    851 st "config_start      : std_logic"
     863xt "29000,4600,45000,5400"
     864st "config_start      : std_logic
     865"
    852866)
    853867)
    … …  
    865879font "Courier New,8,0"
    866880)
    867 xt "22000,7600,38000,8400"
    868 st "config_ready      : std_logic"
     881xt "29000,7800,45000,8600"
     882st "config_ready      : std_logic
     883"
    869884)
    870885)
    … …  
    882897sl 0
    883898ro 270
    884 xt "3000,23625,4500,24375"
     899xt "2000,19625,3500,20375"
    885900)
    886901(Line
    … …  
    888903sl 0
    889904ro 270
    890 xt "4500,24000,5000,24000"
     905xt "3500,20000,4000,20000"
    891906pts [
    892 "4500,24000"
    893 "5000,24000"
     907"3500,20000"
     908"4000,20000"
    894909]
    895910)
    … …  
    906921va (VaSet
    907922)
    908 xt "700,23500,2000,24500"
     923xt "700,19500,2000,20500"
    909924st "clk"
    910925ju 2
    911 blo "2000,24300"
     926blo "2000,20300"
    912927tm "WireNameMgr"
    913928)
    … …  
    927942sl 0
    928943ro 270
    929 xt "42500,28625,44000,29375"
     944xt "36500,28625,38000,29375"
    930945)
    931946(Line
    … …  
    933948sl 0
    934949ro 270
    935 xt "42000,29000,42500,29000"
     950xt "36000,29000,36500,29000"
    936951pts [
    937 "42000,29000"
    938 "42500,29000"
     952"36000,29000"
     953"36500,29000"
    939954]
    940955)
    … …  
    951966va (VaSet
    952967)
    953 xt "45000,28500,50100,29500"
     968xt "39000,28500,44100,29500"
    954969st "config_ready"
    955 blo "45000,29300"
     970blo "39000,29300"
    956971tm "WireNameMgr"
    957972)
    … …  
    971986sl 0
    972987ro 90
    973 xt "42500,29625,44000,30375"
     988xt "36500,29625,38000,30375"
    974989)
    975990(Line
    … …  
    977992sl 0
    978993ro 90
    979 xt "42000,30000,42500,30000"
     994xt "36000,30000,36500,30000"
    980995pts [
    981 "42500,30000"
    982 "42000,30000"
     996"36500,30000"
     997"36000,30000"
    983998]
    984999)
    … …  
    9951010va (VaSet
    9961011)
    997 xt "45000,29500,49800,30500"
     1012xt "39000,29500,43800,30500"
    9981013st "config_start"
    999 blo "45000,30300"
     1014blo "39000,30300"
    10001015tm "WireNameMgr"
    10011016)
    … …  
    10141029uid 381,0
    10151030sl 0
    1016 xt "42500,24625,44000,25375"
     1031xt "36500,24625,38000,25375"
    10171032)
    10181033(Line
    10191034uid 382,0
    10201035sl 0
    1021 xt "42000,25000,42500,25000"
     1036xt "36000,25000,36500,25000"
    10221037pts [
    1023 "42000,25000"
    1024 "42500,25000"
     1038"36000,25000"
     1039"36500,25000"
    10251040]
    10261041)
    … …  
    10371052va (VaSet
    10381053)
    1039 xt "45000,24500,49700,25500"
     1054xt "39000,24500,43700,25500"
    10401055st "config_data"
    1041 blo "45000,25300"
     1056blo "39000,25300"
    10421057tm "WireNameMgr"
    10431058)
    … …  
    10571072sl 0
    10581073ro 90
    1059 xt "42500,23625,44000,24375"
     1074xt "36500,23625,38000,24375"
    10601075)
    10611076(Line
    … …  
    10631078sl 0
    10641079ro 90
    1065 xt "42000,24000,42500,24000"
     1080xt "36000,24000,36500,24000"
    10661081pts [
    1067 "42500,24000"
    1068 "42000,24000"
     1082"36500,24000"
     1083"36000,24000"
    10691084]
    10701085)
    … …  
    10811096va (VaSet
    10821097)
    1083 xt "45000,23500,49800,24500"
     1098xt "39000,23500,43800,24500"
    10841099st "config_addr"
    1085 blo "45000,24300"
     1100blo "39000,24300"
    10861101tm "WireNameMgr"
    10871102)
    … …  
    11011116sl 0
    11021117ro 90
    1103 xt "42500,26625,44000,27375"
     1118xt "36500,26625,38000,27375"
    11041119)
    11051120(Line
    … …  
    11071122sl 0
    11081123ro 90
    1109 xt "42000,27000,42500,27000"
     1124xt "36000,27000,36500,27000"
    11101125pts [
    1111 "42500,27000"
    1112 "42000,27000"
     1126"36500,27000"
     1127"36000,27000"
    11131128]
    11141129)
    … …  
    11251140va (VaSet
    11261141)
    1127 xt "45000,26500,50300,27500"
     1142xt "39000,26500,44300,27500"
    11281143st "config_wr_en"
    1129 blo "45000,27300"
     1144blo "39000,27300"
    11301145tm "WireNameMgr"
    11311146)
    … …  
    11451160sl 0
    11461161ro 90
    1147 xt "42500,27625,44000,28375"
     1162xt "36500,27625,38000,28375"
    11481163)
    11491164(Line
    … …  
    11511166sl 0
    11521167ro 90
    1153 xt "42000,28000,42500,28000"
     1168xt "36000,28000,36500,28000"
    11541169pts [
    1155 "42500,28000"
    1156 "42000,28000"
     1170"36500,28000"
     1171"36000,28000"
    11571172]
    11581173)
    … …  
    11691184va (VaSet
    11701185)
    1171 xt "45000,27500,50200,28500"
     1186xt "39000,27500,44200,28500"
    11721187st "config_rd_en"
    1173 blo "45000,28300"
     1188blo "39000,28300"
    11741189tm "WireNameMgr"
    11751190)
    … …  
    11891204sl 0
    11901205ro 270
    1191 xt "42500,33625,44000,34375"
     1206xt "36500,33625,38000,34375"
    11921207)
    11931208(Line
    … …  
    11951210sl 0
    11961211ro 270
    1197 xt "42000,34000,42500,34000"
     1212xt "36000,34000,36500,34000"
    11981213pts [
    1199 "42000,34000"
    1200 "42500,34000"
     1214"36000,34000"
     1215"36500,34000"
    12011216]
    12021217)
    … …  
    12131228va (VaSet
    12141229)
    1215 xt "45000,33500,48700,34500"
     1230xt "39000,33500,42700,34500"
    12161231st "dac_array"
    1217 blo "45000,34300"
     1232blo "39000,34300"
    12181233tm "WireNameMgr"
    12191234)
    … …  
    12331248sl 0
    12341249ro 270
    1235 xt "42500,34625,44000,35375"
     1250xt "36500,34625,38000,35375"
    12361251)
    12371252(Line
    … …  
    12391254sl 0
    12401255ro 270
    1241 xt "42000,35000,42500,35000"
     1256xt "36000,35000,36500,35000"
    12421257pts [
    1243 "42000,35000"
    1244 "42500,35000"
     1258"36000,35000"
     1259"36500,35000"
    12451260]
    12461261)
    … …  
    12571272va (VaSet
    12581273)
    1259 xt "45000,34500,48400,35500"
     1274xt "39000,34500,42400,35500"
    12601275st "roi_array"
    1261 blo "45000,35300"
     1276blo "39000,35300"
    12621277tm "WireNameMgr"
    12631278)
    … …  
    12771292sl 0
    12781293ro 270
    1279 xt "42500,31625,44000,32375"
     1294xt "36500,31625,38000,32375"
    12801295)
    12811296(Line
    … …  
    12831298sl 0
    12841299ro 270
    1285 xt "42000,32000,42500,32000"
     1300xt "36000,32000,36500,32000"
    12861301pts [
    1287 "42000,32000"
    1288 "42500,32000"
     1302"36000,32000"
     1303"36500,32000"
    12891304]
    12901305)
    … …  
    13011316va (VaSet
    13021317)
    1303 xt "45000,31500,51600,32500"
     1318xt "39000,31500,45600,32500"
    13041319st "config_data_valid"
    1305 blo "45000,32300"
     1320blo "39000,32300"
    13061321tm "WireNameMgr"
    13071322)
    … …  
    13211336sl 0
    13221337ro 270
    1323 xt "42500,32625,44000,33375"
     1338xt "36500,32625,38000,33375"
    13241339)
    13251340(Line
    … …  
    13271342sl 0
    13281343ro 270
    1329 xt "42000,33000,42500,33000"
     1344xt "36000,33000,36500,33000"
    13301345pts [
    1331 "42000,33000"
    1332 "42500,33000"
     1346"36000,33000"
     1347"36500,33000"
    13331348]
    13341349)
    … …  
    13451360va (VaSet
    13461361)
    1347 xt "45000,32500,49800,33500"
     1362xt "39000,32500,43800,33500"
    13481363st "config_busy"
    1349 blo "45000,33300"
     1364blo "39000,33300"
    13501365tm "WireNameMgr"
    13511366)
    … …  
    13651380fg "0,65535,0"
    13661381)
    1367 xt "12250,23625,13000,24375"
     1382xt "6250,23625,7000,24375"
    13681383)
    13691384tg (CPTG
    … …  
    13751390va (VaSet
    13761391)
    1377 xt "14000,23500,15300,24500"
     1392xt "8000,23500,9300,24500"
    13781393st "clk"
    1379 blo "14000,24300"
     1394blo "8000,24300"
    13801395)
    13811396)
    … …  
    14011416fg "0,65535,0"
    14021417)
    1403 xt "38000,28625,38750,29375"
     1418xt "32000,28625,32750,29375"
    14041419)
    14051420tg (CPTG
    … …  
    14111426va (VaSet
    14121427)
    1413 xt "31900,28500,37000,29500"
     1428xt "25900,28500,31000,29500"
    14141429st "config_ready"
    14151430ju 2
    1416 blo "37000,29300"
     1431blo "31000,29300"
    14171432)
    14181433)
    … …  
    14401455fg "0,65535,0"
    14411456)
    1442 xt "38000,29625,38750,30375"
     1457xt "32000,29625,32750,30375"
    14431458)
    14441459tg (CPTG
    … …  
    14501465va (VaSet
    14511466)
    1452 xt "32200,29500,37000,30500"
     1467xt "26200,29500,31000,30500"
    14531468st "config_start"
    14541469ju 2
    1455 blo "37000,30300"
     1470blo "31000,30300"
    14561471)
    14571472)
    … …  
    14771492fg "0,65535,0"
    14781493)
    1479 xt "38000,24625,38750,25375"
     1494xt "32000,24625,32750,25375"
    14801495)
    14811496tg (CPTG
    … …  
    14871502va (VaSet
    14881503)
    1489 xt "29300,24500,37000,25500"
     1504xt "23300,24500,31000,25500"
    14901505st "config_data : (15:0)"
    14911506ju 2
    1492 blo "37000,25300"
     1507blo "31000,25300"
    14931508)
    14941509)
    … …  
    15171532fg "0,65535,0"
    15181533)
    1519 xt "38000,23625,38750,24375"
     1534xt "32000,23625,32750,24375"
    15201535)
    15211536tg (CPTG
    … …  
    15271542va (VaSet
    15281543)
    1529 xt "23600,23500,37000,24500"
     1544xt "17600,23500,31000,24500"
    15301545st "config_addr : (ADDR_WIDTH - 1:0)"
    15311546ju 2
    1532 blo "37000,24300"
     1547blo "31000,24300"
    15331548)
    15341549)
    … …  
    15551570fg "0,65535,0"
    15561571)
    1557 xt "38000,26625,38750,27375"
     1572xt "32000,26625,32750,27375"
    15581573)
    15591574tg (CPTG
    … …  
    15651580va (VaSet
    15661581)
    1567 xt "31700,26500,37000,27500"
     1582xt "25700,26500,31000,27500"
    15681583st "config_wr_en"
    15691584ju 2
    1570 blo "37000,27300"
     1585blo "31000,27300"
    15711586)
    15721587)
    … …  
    15921607fg "0,65535,0"
    15931608)
    1594 xt "38000,27625,38750,28375"
     1609xt "32000,27625,32750,28375"
    15951610)
    15961611tg (CPTG
    … …  
    16021617va (VaSet
    16031618)
    1604 xt "31800,27500,37000,28500"
     1619xt "25800,27500,31000,28500"
    16051620st "config_rd_en"
    16061621ju 2
    1607 blo "37000,28300"
     1622blo "31000,28300"
    16081623)
    16091624)
    … …  
    16291644fg "0,65535,0"
    16301645)
    1631 xt "38000,31625,38750,32375"
     1646xt "32000,31625,32750,32375"
    16321647)
    16331648tg (CPTG
    … …  
    16391654va (VaSet
    16401655)
    1641 xt "30400,31500,37000,32500"
     1656xt "24400,31500,31000,32500"
    16421657st "config_data_valid"
    16431658ju 2
    1644 blo "37000,32300"
     1659blo "31000,32300"
    16451660)
    16461661)
    … …  
    16681683fg "0,65535,0"
    16691684)
    1670 xt "38000,32625,38750,33375"
     1685xt "32000,32625,32750,33375"
    16711686)
    16721687tg (CPTG
    … …  
    16781693va (VaSet
    16791694)
    1680 xt "32200,32500,37000,33500"
     1695xt "26200,32500,31000,33500"
    16811696st "config_busy"
    16821697ju 2
    1683 blo "37000,33300"
     1698blo "31000,33300"
    16841699)
    16851700)
    … …  
    17071722fg "0,65535,0"
    17081723)
    1709 xt "38000,33625,38750,34375"
     1724xt "32000,33625,32750,34375"
    17101725)
    17111726tg (CPTG
    … …  
    17171732va (VaSet
    17181733)
    1719 xt "33300,33500,37000,34500"
     1734xt "27300,33500,31000,34500"
    17201735st "dac_array"
    17211736ju 2
    1722 blo "37000,34300"
     1737blo "31000,34300"
    17231738)
    17241739)
    … …  
    17451760fg "0,65535,0"
    17461761)
    1747 xt "38000,34625,38750,35375"
     1762xt "32000,34625,32750,35375"
    17481763)
    17491764tg (CPTG
    … …  
    17551770va (VaSet
    17561771)
    1757 xt "33600,34500,37000,35500"
     1772xt "27600,34500,31000,35500"
    17581773st "roi_array"
    17591774ju 2
    1760 blo "37000,35300"
     1775blo "31000,35300"
    17611776)
    17621777)
    … …  
    17831798fg "0,65535,0"
    17841799)
    1785 xt "38000,37625,38750,38375"
     1800xt "32000,37625,32750,38375"
    17861801)
    17871802tg (CPTG
    … …  
    17931808va (VaSet
    17941809)
    1795 xt "29100,37500,37000,38500"
     1810xt "23100,37500,31000,38500"
    17961811st "ram_data_in : (15:0)"
    17971812ju 2
    1798 blo "37000,38300"
     1813blo "31000,38300"
    17991814)
    18001815)
    … …  
    18201835fg "0,65535,0"
    18211836)
    1822 xt "38000,38625,38750,39375"
     1837xt "32000,38625,32750,39375"
    18231838)
    18241839tg (CPTG
    … …  
    18301845va (VaSet
    18311846)
    1832 xt "29100,38500,37000,39500"
     1847xt "23100,38500,31000,39500"
    18331848st "ram_write_en : (0:0)"
    18341849ju 2
    1835 blo "37000,39300"
     1850blo "31000,39300"
    18361851)
    18371852)
    … …  
    18571872fg "0,65535,0"
    18581873)
    1859 xt "12250,24625,13000,25375"
     1874xt "6250,38625,7000,39375"
    18601875)
    18611876tg (CPTG
    … …  
    18671882va (VaSet
    18681883)
    1869 xt "14000,24500,22300,25500"
     1884xt "8000,38500,16300,39500"
    18701885st "ram_data_out : (15:0)"
    1871 blo "14000,25300"
     1886blo "8000,39300"
    18721887)
    18731888)
    … …  
    18921907fg "0,65535,0"
    18931908)
    1894 xt "38000,39625,38750,40375"
     1909xt "32000,39625,32750,40375"
    18951910)
    18961911tg (CPTG
    … …  
    19021917va (VaSet
    19031918)
    1904 xt "24400,39500,37000,40500"
     1919xt "18400,39500,31000,40500"
    19051920st "ram_addr : (ADDR_WIDTH - 1:0)"
    19061921ju 2
    1907 blo "37000,40300"
     1922blo "31000,40300"
    19081923)
    19091924)
    … …  
    19291944fg "0,65535,0"
    19301945)
    1931 xt "38000,30625,38750,31375"
     1946xt "32000,30625,32750,31375"
    19321947)
    19331948tg (CPTG
    … …  
    19391954va (VaSet
    19401955)
    1941 xt "31400,30500,37000,31500"
     1956xt "25400,30500,31000,31500"
    19421957st "config_started"
    19431958ju 2
    1944 blo "37000,31300"
     1959blo "31000,31300"
    19451960)
    19461961)
    … …  
    19561971)
    19571972)
     1973*55 (CptPort
     1974uid 1198,0
     1975ps "OnEdgeStrategy"
     1976shape (Triangle
     1977uid 1199,0
     1978ro 90
     1979va (VaSet
     1980vasetType 1
     1981fg "0,65535,0"
     1982)
     1983xt "32000,21625,32750,22375"
     1984)
     1985tg (CPTG
     1986uid 1200,0
     1987ps "CptPortTextPlaceStrategy"
     1988stg "RightVerticalLayoutStrategy"
     1989f (Text
     1990uid 1201,0
     1991va (VaSet
     1992)
     1993xt "23800,21500,31000,22500"
     1994st "drs_address : (3:0)"
     1995ju 2
     1996blo "31000,22300"
     1997)
     1998)
     1999thePort (LogicalPort
     2000m 1
     2001decl (Decl
     2002n "drs_address"
     2003t "std_logic_vector"
     2004b "(3 DOWNTO 0)"
     2005o 17
     2006suid 24,0
     2007)
     2008)
     2009)
     2010*56 (CptPort
     2011uid 1202,0
     2012ps "OnEdgeStrategy"
     2013shape (Triangle
     2014uid 1203,0
     2015ro 90
     2016va (VaSet
     2017vasetType 1
     2018fg "0,65535,0"
     2019)
     2020xt "32000,20625,32750,21375"
     2021)
     2022tg (CPTG
     2023uid 1204,0
     2024ps "CptPortTextPlaceStrategy"
     2025stg "RightVerticalLayoutStrategy"
     2026f (Text
     2027uid 1205,0
     2028va (VaSet
     2029)
     2030xt "23800,20500,31000,21500"
     2031st "drs_address_mode"
     2032ju 2
     2033blo "31000,21300"
     2034)
     2035)
     2036thePort (LogicalPort
     2037m 1
     2038decl (Decl
     2039n "drs_address_mode"
     2040t "std_logic"
     2041o 18
     2042suid 25,0
     2043)
     2044)
     2045)
    19582046]
    19592047shape (Rectangle
    … …  
    19652053lineWidth 2
    19662054)
    1967 xt "13000,23000,38000,42000"
     2055xt "7000,20000,32000,41000"
    19682056)
    19692057oxt "42000,14000,67000,32000"
    … …  
    19732061stg "VerticalLayoutStrategy"
    19742062textVec [
    1975 *55 (Text
     2063*57 (Text
    19762064uid 963,0
    19772065va (VaSet
    19782066font "Arial,8,1"
    19792067)
    1980 xt "12950,42000,19150,43000"
     2068xt "6950,42000,13150,43000"
    19812069st "FACT_FAD_lib"
    1982 blo "12950,42800"
     2070blo "6950,42800"
    19832071tm "BdLibraryNameMgr"
    19842072)
    1985 *56 (Text
     2073*58 (Text
    19862074uid 964,0
    19872075va (VaSet
    19882076font "Arial,8,1"
    19892077)
    1990 xt "12950,43000,20050,44000"
     2078xt "6950,43000,14050,44000"
    19912079st "control_manager"
    1992 blo "12950,43800"
     2080blo "6950,43800"
    19932081tm "CptNameMgr"
    19942082)
    1995 *57 (Text
     2083*59 (Text
    19962084uid 965,0
    19972085va (VaSet
    19982086font "Arial,8,1"
    19992087)
    2000 xt "12950,44000,20650,45000"
     2088xt "6950,44000,14650,45000"
    20012089st "I_control_manager"
    2002 blo "12950,44800"
     2090blo "6950,44800"
    20032091tm "InstanceNameMgr"
    20042092)
    … …  
    20152103font "Courier New,8,0"
    20162104)
    2017 xt "12500,10600,30000,13000"
     2105xt "10000,17600,27500,20000"
    20182106st "NO_OF_ROI  = 36    ( integer ) 
    20192107NO_OF_DAC  = 8     ( integer ) 
    … …  
    20472135fg "49152,49152,49152"
    20482136)
    2049 xt "13250,40250,14750,41750"
     2137xt "7250,39250,8750,40750"
    20502138iconName "VhdlFileViewIcon.png"
    20512139iconMaskName "VhdlFileViewIcon.msk"
    … …  
    20582146archFileType "UNKNOWN"
    20592147)
    2060 *58 (SaComponent
     2148*60 (SaComponent
    20612149uid 993,0
    20622150optionalChildren [
    2063 *59 (CptPort
     2151*61 (CptPort
    20642152uid 970,0
    20652153ps "OnEdgeStrategy"
    20662154shape (Triangle
    20672155uid 971,0
    2068 ro 90
     2156ro 180
    20692157va (VaSet
    20702158vasetType 1
    20712159fg "0,65535,0"
    20722160)
    2073 xt "19250,50625,20000,51375"
     2161xt "42625,41250,43375,42000"
    20742162)
    20752163tg (CPTG
    20762164uid 972,0
    20772165ps "CptPortTextPlaceStrategy"
    2078 stg "VerticalLayoutStrategy"
     2166stg "RightVerticalLayoutStrategy"
    20792167f (Text
    20802168uid 973,0
    2081 va (VaSet
    2082 )
    2083 xt "21000,50500,22700,51500"
     2169ro 270
     2170va (VaSet
     2171)
     2172xt "42500,43000,43500,44700"
    20842173st "clka"
    2085 blo "21000,51300"
     2174ju 2
     2175blo "43300,43000"
    20862176)
    20872177)
    … …  
    20972187)
    20982188)
    2099 *60 (CptPort
     2189*62 (CptPort
    21002190uid 974,0
    21012191ps "OnEdgeStrategy"
    … …  
    21072197fg "0,65535,0"
    21082198)
    2109 xt "19250,52625,20000,53375"
     2199xt "39250,45625,40000,46375"
    21102200)
    21112201tg (CPTG
    … …  
    21172207va (VaSet
    21182208)
    2119 xt "21000,52500,25800,53500"
     2209xt "41000,45500,45800,46500"
    21202210st "dina : (15:0)"
    2121 blo "21000,53300"
     2211blo "41000,46300"
    21222212)
    21232213)
    … …  
    21342224)
    21352225)
    2136 *61 (CptPort
     2226*63 (CptPort
    21372227uid 978,0
    21382228ps "OnEdgeStrategy"
    … …  
    21442234fg "0,65535,0"
    21452235)
    2146 xt "19250,54625,20000,55375"
     2236xt "39250,47625,40000,48375"
    21472237)
    21482238tg (CPTG
    … …  
    21542244va (VaSet
    21552245)
    2156 xt "21000,54500,25900,55500"
     2246xt "41000,47500,45900,48500"
    21572247st "addra : (7:0)"
    2158 blo "21000,55300"
     2248blo "41000,48300"
    21592249)
    21602250)
    … …  
    21712261)
    21722262)
    2173 *62 (CptPort
     2263*64 (CptPort
    21742264uid 982,0
    21752265ps "OnEdgeStrategy"
    … …  
    21812271fg "0,65535,0"
    21822272)
    2183 xt "19250,53625,20000,54375"
     2273xt "39250,46625,40000,47375"
    21842274)
    21852275tg (CPTG
    … …  
    21912281va (VaSet
    21922282)
    2193 xt "21000,53500,25300,54500"
     2283xt "41000,46500,45300,47500"
    21942284st "wea : (0:0)"
    2195 blo "21000,54300"
     2285blo "41000,47300"
    21962286)
    21972287)
    … …  
    22082298)
    22092299)
    2210 *63 (CptPort
     2300*65 (CptPort
    22112301uid 986,0
    22122302ps "OnEdgeStrategy"
    … …  
    22182308fg "0,65535,0"
    22192309)
    2220 xt "30000,50625,30750,51375"
     2310xt "50000,43625,50750,44375"
    22212311)
    22222312tg (CPTG
    … …  
    22282318va (VaSet
    22292319)
    2230 xt "23800,50500,29000,51500"
     2320xt "43800,43500,49000,44500"
    22312321st "douta : (15:0)"
    22322322ju 2
    2233 blo "29000,51300"
     2323blo "49000,44300"
    22342324)
    22352325)
    … …  
    22562346lineWidth 2
    22572347)
    2258 xt "20000,49000,30000,59000"
     2348xt "40000,42000,50000,52000"
    22592349)
    22602350oxt "30000,7000,40000,17000"
    … …  
    22642354stg "VerticalLayoutStrategy"
    22652355textVec [
    2266 *64 (Text
     2356*66 (Text
    22672357uid 996,0
    22682358va (VaSet
    22692359font "Arial,8,1"
    22702360)
    2271 xt "20200,59000,26400,60000"
     2361xt "40200,52000,46400,53000"
    22722362st "FACT_FAD_lib"
    2273 blo "20200,59800"
     2363blo "40200,52800"
    22742364tm "BdLibraryNameMgr"
    22752365)
    2276 *65 (Text
     2366*67 (Text
    22772367uid 997,0
    22782368va (VaSet
    22792369font "Arial,8,1"
    22802370)
    2281 xt "20200,60000,30100,61000"
     2371xt "40200,53000,50100,54000"
    22822372st "controlRAM_16bit_x256"
    2283 blo "20200,60800"
     2373blo "40200,53800"
    22842374tm "CptNameMgr"
    22852375)
    2286 *66 (Text
     2376*68 (Text
    22872377uid 998,0
    22882378va (VaSet
    22892379font "Arial,8,1"
    22902380)
    2291 xt "20200,61000,26100,62000"
     2381xt "40200,54000,46100,55000"
    22922382st "I_control_ram"
    2293 blo "20200,61800"
     2383blo "40200,54800"
    22942384tm "InstanceNameMgr"
    22952385)
    … …  
    23062396font "Courier New,8,0"
    23072397)
    2308 xt "19500,48000,19500,48000"
     2398xt "39500,41000,39500,41000"
    23092399)
    23102400header ""
    … …  
    23202410fg "49152,49152,49152"
    23212411)
    2322 xt "20250,57250,21750,58750"
     2412xt "40250,50250,41750,51750"
    23232413iconName "VhdlFileViewIcon.png"
    23242414iconMaskName "VhdlFileViewIcon.msk"
    … …  
    23322422archFileType "UNKNOWN"
    23332423)
    2334 *67 (Net
     2424*69 (Net
    23352425uid 1082,0
    23362426decl (Decl
    … …  
    23462436font "Courier New,8,0"
    23472437)
    2348 xt "22000,8400,41500,9200"
    2349 st "config_started    : std_logic := '0'"
    2350 )
    2351 )
    2352 *68 (PortIoOut
     2438xt "29000,8600,48500,9400"
     2439st "config_started    : std_logic := '0'
     2440"
     2441)
     2442)
     2443*70 (PortIoOut
    23532444uid 1090,0
    23542445shape (CompositeShape
    … …  
    23632454sl 0
    23642455ro 270
    2365 xt "42500,30625,44000,31375"
     2456xt "36500,30625,38000,31375"
    23662457)
    23672458(Line
    … …  
    23692460sl 0
    23702461ro 270
    2371 xt "42000,31000,42500,31000"
     2462xt "36000,31000,36500,31000"
    23722463pts [
    2373 "42000,31000"
    2374 "42500,31000"
     2464"36000,31000"
     2465"36500,31000"
    23752466]
    23762467)
    … …  
    23872478va (VaSet
    23882479)
    2389 xt "45000,30500,50600,31500"
     2480xt "39000,30500,44600,31500"
    23902481st "config_started"
    2391 blo "45000,31300"
     2482blo "39000,31300"
    23922483tm "WireNameMgr"
    23932484)
    23942485)
    23952486)
    2396 *69 (Wire
     2487*71 (Net
     2488uid 1206,0
     2489decl (Decl
     2490n "drs_address"
     2491t "std_logic_vector"
     2492b "(3 DOWNTO 0)"
     2493o 17
     2494suid 19,0
     2495)
     2496declText (MLText
     2497uid 1207,0
     2498va (VaSet
     2499font "Courier New,8,0"
     2500)
     2501xt "29000,10200,55000,11000"
     2502st "drs_address       : std_logic_vector(3 DOWNTO 0)
     2503"
     2504)
     2505)
     2506*72 (PortIoOut
     2507uid 1214,0
     2508shape (CompositeShape
     2509uid 1215,0
     2510va (VaSet
     2511vasetType 1
     2512fg "0,0,32768"
     2513)
     2514optionalChildren [
     2515(Pentagon
     2516uid 1216,0
     2517sl 0
     2518ro 270
     2519xt "36500,21625,38000,22375"
     2520)
     2521(Line
     2522uid 1217,0
     2523sl 0
     2524ro 270
     2525xt "36000,22000,36500,22000"
     2526pts [
     2527"36000,22000"
     2528"36500,22000"
     2529]
     2530)
     2531]
     2532)
     2533stc 0
     2534sf 1
     2535tg (WTG
     2536uid 1218,0
     2537ps "PortIoTextPlaceStrategy"
     2538stg "STSignalDisplayStrategy"
     2539f (Text
     2540uid 1219,0
     2541va (VaSet
     2542)
     2543xt "39000,21500,44000,22500"
     2544st "drs_address"
     2545blo "39000,22300"
     2546tm "WireNameMgr"
     2547)
     2548)
     2549)
     2550*73 (Net
     2551uid 1220,0
     2552decl (Decl
     2553n "drs_address_mode"
     2554t "std_logic"
     2555o 18
     2556suid 20,0
     2557)
     2558declText (MLText
     2559uid 1221,0
     2560va (VaSet
     2561font "Courier New,8,0"
     2562)
     2563xt "29000,11000,45000,11800"
     2564st "drs_address_mode  : std_logic
     2565"
     2566)
     2567)
     2568*74 (PortIoOut
     2569uid 1228,0
     2570shape (CompositeShape
     2571uid 1229,0
     2572va (VaSet
     2573vasetType 1
     2574fg "0,0,32768"
     2575)
     2576optionalChildren [
     2577(Pentagon
     2578uid 1230,0
     2579sl 0
     2580ro 270
     2581xt "36500,20625,38000,21375"
     2582)
     2583(Line
     2584uid 1231,0
     2585sl 0
     2586ro 270
     2587xt "36000,21000,36500,21000"
     2588pts [
     2589"36000,21000"
     2590"36500,21000"
     2591]
     2592)
     2593]
     2594)
     2595stc 0
     2596sf 1
     2597tg (WTG
     2598uid 1232,0
     2599ps "PortIoTextPlaceStrategy"
     2600stg "STSignalDisplayStrategy"
     2601f (Text
     2602uid 1233,0
     2603va (VaSet
     2604)
     2605xt "39000,20500,46200,21500"
     2606st "drs_address_mode"
     2607blo "39000,21300"
     2608tm "WireNameMgr"
     2609)
     2610)
     2611)
     2612*75 (Wire
    23972613uid 227,0
    23982614shape (OrthoPolyLine
    … …  
    24022618lineWidth 2
    24032619)
    2404 xt "38750,24000,42000,24000"
     2620xt "32750,24000,36000,24000"
    24052621pts [
    2406 "42000,24000"
    2407 "40000,24000"
    2408 "38750,24000"
     2622"36000,24000"
     2623"32750,24000"
    24092624]
    24102625)
    … …  
    24272642isHidden 1
    24282643)
    2429 xt "45000,23000,49800,24000"
     2644xt "39000,23000,43800,24000"
    24302645st "config_addr"
    2431 blo "45000,23800"
     2646blo "39000,23800"
    24322647tm "WireNameMgr"
    24332648)
    … …  
    24352650on &14
    24362651)
    2437 *70 (Wire
     2652*76 (Wire
    24382653uid 233,0
    24392654shape (OrthoPolyLine
    … …  
    24432658lineWidth 2
    24442659)
    2445 xt "13000,39000,43000,54000"
     2660xt "32750,39000,39250,47000"
    24462661pts [
    2447 "19250,54000"
    2448 "13000,54000"
    2449 "13000,47000"
    2450 "43000,47000"
    2451 "43000,39000"
    2452 "38750,39000"
    2453 ]
    2454 )
    2455 start &62
     2662"39250,47000"
     2663"34000,47000"
     2664"34000,39000"
     2665"32750,39000"
     2666]
     2667)
     2668start &64
    24562669end &51
    24572670sat 32
    … …  
    24692682va (VaSet
    24702683)
    2471 xt "23000,46000,29300,47000"
     2684xt "34000,46000,40300,47000"
    24722685st "ram_wren : (0:0)"
    2473 blo "23000,46800"
     2686blo "34000,46800"
    24742687tm "WireNameMgr"
    24752688)
    … …  
    24772690on &13
    24782691)
    2479 *71 (Wire
     2692*77 (Wire
    24802693uid 237,0
    24812694shape (OrthoPolyLine
    … …  
    24852698lineWidth 2
    24862699)
    2487 xt "14000,38000,44000,53000"
     2700xt "32750,38000,39250,46000"
    24882701pts [
    2489 "19250,53000"
    2490 "14000,53000"
    2491 "14000,48000"
    2492 "44000,48000"
    2493 "44000,38000"
    2494 "38750,38000"
    2495 ]
    2496 )
    2497 start &60
     2702"39250,46000"
     2703"35000,46000"
     2704"35000,38000"
     2705"32750,38000"
     2706]
     2707)
     2708start &62
    24982709end &50
    24992710sat 32
    … …  
    25112722va (VaSet
    25122723)
    2513 xt "23000,47000,30900,48000"
     2724xt "33000,37000,40900,38000"
    25142725st "ram_data_in : (15:0)"
    2515 blo "23000,47800"
     2726blo "33000,37800"
    25162727tm "WireNameMgr"
    25172728)
    … …  
    25192730on &15
    25202731)
    2521 *72 (Wire
     2732*78 (Wire
    25222733uid 241,0
    25232734shape (OrthoPolyLine
    … …  
    25262737vasetType 3
    25272738)
    2528 xt "5000,24000,12250,24000"
     2739xt "4000,20000,6250,24000"
    25292740pts [
     2741"4000,20000"
     2742"5000,20000"
    25302743"5000,24000"
    2531 "12250,24000"
     2744"6250,24000"
    25322745]
    25332746)
    … …  
    25492762isHidden 1
    25502763)
    2551 xt "7000,23000,8300,24000"
     2764xt "6000,19000,7300,20000"
    25522765st "clk"
    2553 blo "7000,23800"
     2766blo "6000,19800"
    25542767tm "WireNameMgr"
    25552768)
    … …  
    25572770on &12
    25582771)
    2559 *73 (Wire
     2772*79 (Wire
    25602773uid 255,0
    25612774shape (OrthoPolyLine
    … …  
    25642777vasetType 3
    25652778)
    2566 xt "38750,32000,42000,32000"
     2779xt "32750,32000,36000,32000"
    25672780pts [
    2568 "38750,32000"
    2569 "42000,32000"
     2781"32750,32000"
     2782"36000,32000"
    25702783]
    25712784)
    … …  
    25872800isHidden 1
    25882801)
    2589 xt "45000,30000,51600,31000"
     2802xt "39000,30000,45600,31000"
    25902803st "config_data_valid"
    2591 blo "45000,30800"
     2804blo "39000,30800"
    25922805tm "WireNameMgr"
    25932806)
    … …  
    25952808on &16
    25962809)
    2597 *74 (Wire
     2810*80 (Wire
    25982811uid 261,0
    25992812shape (OrthoPolyLine
    … …  
    26022815vasetType 3
    26032816)
    2604 xt "38750,33000,42000,33000"
     2817xt "32750,33000,36000,33000"
    26052818pts [
    2606 "38750,33000"
    2607 "42000,33000"
     2819"32750,33000"
     2820"36000,33000"
    26082821]
    26092822)
    … …  
    26252838isHidden 1
    26262839)
    2627 xt "45000,31000,49800,32000"
     2840xt "39000,31000,43800,32000"
    26282841st "config_busy"
    2629 blo "45000,31800"
     2842blo "39000,31800"
    26302843tm "WireNameMgr"
    26312844)
    … …  
    26332846on &17
    26342847)
    2635 *75 (Wire
     2848*81 (Wire
    26362849uid 267,0
    26372850shape (OrthoPolyLine
    … …  
    26412854lineWidth 2
    26422855)
    2643 xt "38750,25000,42000,25000"
     2856xt "32750,25000,36000,25000"
    26442857pts [
    2645 "42000,25000"
    2646 "40000,25000"
    2647 "38750,25000"
     2858"36000,25000"
     2859"32750,25000"
    26482860]
    26492861)
    … …  
    26662878isHidden 1
    26672879)
    2668 xt "45000,24000,49700,25000"
     2880xt "39000,24000,43700,25000"
    26692881st "config_data"
    2670 blo "45000,24800"
     2882blo "39000,24800"
    26712883tm "WireNameMgr"
    26722884)
    … …  
    26742886on &18
    26752887)
    2676 *76 (Wire
     2888*82 (Wire
    26772889uid 273,0
    26782890shape (OrthoPolyLine
    … …  
    26812893vasetType 3
    26822894)
    2683 xt "38750,35000,42000,35000"
     2895xt "32750,35000,36000,35000"
    26842896pts [
    2685 "38750,35000"
    2686 "40000,35000"
    2687 "42000,35000"
     2897"32750,35000"
     2898"36000,35000"
    26882899]
    26892900)
    … …  
    27052916isHidden 1
    27062917)
    2707 xt "45000,34000,48400,35000"
     2918xt "39000,34000,42400,35000"
    27082919st "roi_array"
    2709 blo "45000,34800"
     2920blo "39000,34800"
    27102921tm "WireNameMgr"
    27112922)
    … …  
    27132924on &19
    27142925)
    2715 *77 (Wire
     2926*83 (Wire
    27162927uid 279,0
    27172928shape (OrthoPolyLine
    … …  
    27202931vasetType 3
    27212932)
    2722 xt "17000,51000,19250,51000"
     2933xt "43000,38000,43000,41250"
    27232934pts [
    2724 "17000,51000"
    2725 "19250,51000"
    2726 ]
    2727 )
    2728 end &59
     2935"43000,38000"
     2936"43000,41250"
     2937]
     2938)
     2939end &61
    27292940sat 16
    27302941eat 32
    … …  
    27402951va (VaSet
    27412952)
    2742 xt "18000,50000,19300,51000"
     2953xt "44000,37000,45300,38000"
    27432954st "clk"
    2744 blo "18000,50800"
     2955blo "44000,37800"
    27452956tm "WireNameMgr"
    27462957)
    … …  
    27482959on &12
    27492960)
    2750 *78 (Wire
     2961*84 (Wire
    27512962uid 285,0
    27522963shape (OrthoPolyLine
    … …  
    27562967lineWidth 2
    27572968)
    2758 xt "12000,40000,42000,55000"
     2969xt "32750,40000,39250,48000"
    27592970pts [
    2760 "38750,40000"
    2761 "42000,40000"
    2762 "42000,46000"
    2763 "12000,46000"
    2764 "12000,55000"
    2765 "19250,55000"
     2971"32750,40000"
     2972"33000,40000"
     2973"33000,48000"
     2974"39250,48000"
    27662975]
    27672976)
    27682977start &53
    2769 end &61
     2978end &63
    27702979sat 32
    27712980eat 32
    … …  
    27822991va (VaSet
    27832992)
    2784 xt "23000,45000,29200,46000"
     2993xt "33000,47000,39200,48000"
    27852994st "ram_addr : (7:0)"
    2786 blo "23000,45800"
     2995blo "33000,47800"
    27872996tm "WireNameMgr"
    27882997)
    … …  
    27902999on &20
    27913000)
    2792 *79 (Wire
     3001*85 (Wire
    27933002uid 289,0
    27943003shape (OrthoPolyLine
    … …  
    27973006vasetType 3
    27983007)
    2799 xt "38750,30000,42000,30000"
     3008xt "32750,30000,36000,30000"
    28003009pts [
    2801 "42000,30000"
    2802 "40000,30000"
    2803 "38750,30000"
     3010"36000,30000"
     3011"32750,30000"
    28043012]
    28053013)
    … …  
    28213029isHidden 1
    28223030)
    2823 xt "45000,29000,49800,30000"
     3031xt "39000,29000,43800,30000"
    28243032st "config_start"
    2825 blo "45000,29800"
     3033blo "39000,29800"
    28263034tm "WireNameMgr"
    28273035)
    … …  
    28293037on &25
    28303038)
    2831 *80 (Wire
     3039*86 (Wire
    28323040uid 295,0
    28333041shape (OrthoPolyLine
    … …  
    28363044vasetType 3
    28373045)
    2838 xt "38750,27000,42000,27000"
     3046xt "32750,27000,36000,27000"
    28393047pts [
    2840 "42000,27000"
    2841 "40000,27000"
    2842 "38750,27000"
     3048"36000,27000"
     3049"32750,27000"
    28433050]
    28443051)
    … …  
    28603067isHidden 1
    28613068)
    2862 xt "45000,26000,50300,27000"
     3069xt "39000,26000,44300,27000"
    28633070st "config_wr_en"
    2864 blo "45000,26800"
     3071blo "39000,26800"
    28653072tm "WireNameMgr"
    28663073)
    … …  
    28683075on &21
    28693076)
    2870 *81 (Wire
     3077*87 (Wire
    28713078uid 301,0
    28723079shape (OrthoPolyLine
    … …  
    28763083lineWidth 2
    28773084)
    2878 xt "9000,25000,34000,64000"
     3085xt "3000,39000,52000,56000"
    28793086pts [
    2880 "12250,25000"
    2881 "9000,25000"
    2882 "9000,64000"
    2883 "34000,64000"
    2884 "34000,51000"
    2885 "30750,51000"
     3087"6250,39000"
     3088"3000,39000"
     3089"3000,56000"
     3090"52000,56000"
     3091"52000,44000"
     3092"50750,44000"
    28863093]
    28873094)
    28883095start &52
    2889 end &63
     3096end &65
    28903097sat 32
    28913098eat 32
    … …  
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     3111xt "33000,55000,41300,56000"
    29053112st "ram_data_out : (15:0)"
    2906 blo "20000,63800"
     3113blo "33000,55800"
    29073114tm "WireNameMgr"
    29083115)
    … …  
    29103117on &22
    29113118)
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     3119*88 (Wire
    29133120uid 305,0
    29143121shape (OrthoPolyLine
    … …  
    29173124vasetType 3
    29183125)
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     3126xt "32750,34000,36000,34000"
    29203127pts [
    2921 "38750,34000"
    2922 "40000,34000"
    2923 "42000,34000"
     3128"32750,34000"
     3129"36000,34000"
    29243130]
    29253131)
    … …  
    29413147isHidden 1
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    2943 xt "45000,33000,48700,34000"
     3149xt "39000,33000,42700,34000"
    29443150st "dac_array"
    2945 blo "45000,33800"
     3151blo "39000,33800"
    29463152tm "WireNameMgr"
    29473153)
    … …  
    29493155on &23
    29503156)
    2951 *83 (Wire
     3157*89 (Wire
    29523158uid 311,0
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    … …  
    29563162vasetType 3
    29573163)
    2958 xt "38750,28000,42000,28000"
     3164xt "32750,28000,36000,28000"
    29593165pts [
    2960 "42000,28000"
    2961 "40000,28000"
    2962 "38750,28000"
     3166"36000,28000"
     3167"32750,28000"
    29633168]
    29643169)
    … …  
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    2982 xt "45000,27000,50200,28000"
     3187xt "39000,27000,44200,28000"
    29833188st "config_rd_en"
    2984 blo "45000,27800"
     3189blo "39000,27800"
    29853190tm "WireNameMgr"
    29863191)
    … …  
    29883193on &24
    29893194)
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     3195*90 (Wire
    29913196uid 321,0
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    … …  
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     3202xt "32750,29000,36000,29000"
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    2999 "38750,29000"
    3000 "40000,29000"
    3001 "42000,29000"
     3204"32750,29000"
     3205"36000,29000"
    30023206]
    30033207)
    … …  
    30193223isHidden 1
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    3021 xt "45000,28000,50100,29000"
     3225xt "39000,28000,44100,29000"
    30223226st "config_ready"
    3023 blo "45000,28800"
     3227blo "39000,28800"
    30243228tm "WireNameMgr"
    30253229)
    … …  
    30273231on &26
    30283232)
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     3233*91 (Wire
    30303234uid 1084,0
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    … …  
    30343238vasetType 3
    30353239)
    3036 xt "38750,31000,42000,31000"
     3240xt "32750,31000,36000,31000"
    30373241pts [
    3038 "38750,31000"
    3039 "42000,31000"
     3242"32750,31000"
     3243"36000,31000"
    30403244]
    30413245)
    30423246start &54
    3043 end &68
     3247end &70
    30443248sat 32
    30453249eat 32
    … …  
    30573261isHidden 1
    30583262)
    3059 xt "40000,30000,45600,31000"
     3263xt "34000,30000,39600,31000"
    30603264st "config_started"
    3061 blo "40000,30800"
     3265blo "34000,30800"
    30623266tm "WireNameMgr"
    30633267)
    30643268)
    3065 on &67
     3269on &69
     3270)
     3271*92 (Wire
     3272uid 1208,0
     3273shape (OrthoPolyLine
     3274uid 1209,0
     3275va (VaSet
     3276vasetType 3
     3277lineWidth 2
     3278)
     3279xt "32750,22000,36000,22000"
     3280pts [
     3281"32750,22000"
     3282"36000,22000"
     3283]
     3284)
     3285start &55
     3286end &72
     3287sat 32
     3288eat 32
     3289sty 1
     3290stc 0
     3291st 0
     3292sf 1
     3293si 0
     3294tg (WTG
     3295uid 1212,0
     3296ps "ConnStartEndStrategy"
     3297stg "STSignalDisplayStrategy"
     3298f (Text
     3299uid 1213,0
     3300va (VaSet
     3301isHidden 1
     3302)
     3303xt "34000,21000,39000,22000"
     3304st "drs_address"
     3305blo "34000,21800"
     3306tm "WireNameMgr"
     3307)
     3308)
     3309on &71
     3310)
     3311*93 (Wire
     3312uid 1222,0
     3313shape (OrthoPolyLine
     3314uid 1223,0
     3315va (VaSet
     3316vasetType 3
     3317)
     3318xt "32750,21000,36000,21000"
     3319pts [
     3320"32750,21000"
     3321"36000,21000"
     3322]
     3323)
     3324start &56
     3325end &74
     3326sat 32
     3327eat 32
     3328stc 0
     3329st 0
     3330sf 1
     3331si 0
     3332tg (WTG
     3333uid 1226,0
     3334ps "ConnStartEndStrategy"
     3335stg "STSignalDisplayStrategy"
     3336f (Text
     3337uid 1227,0
     3338va (VaSet
     3339isHidden 1
     3340)
     3341xt "34000,20000,41200,21000"
     3342st "drs_address_mode"
     3343blo "34000,20800"
     3344tm "WireNameMgr"
     3345)
     3346)
     3347on &73
    30663348)
    30673349]
    … …  
    30773359color "26368,26368,26368"
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    30803362uid 41,0
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     3365*95 (Text
    30843366uid 42,0
    30853367va (VaSet
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    30873369)
    3088 xt "0,0,5400,1000"
     3370xt "1000,1000,6400,2000"
    30893371st "Package List"
    3090 blo "0,800"
    3091 )
    3092 *88 (MLText
     3372blo "1000,1800"
     3373)
     3374*96 (MLText
    30933375uid 43,0
    30943376va (VaSet
    30953377)
    3096 xt "0,1000,15300,6000"
     3378xt "1000,2000,16300,7000"
    30973379st "LIBRARY ieee;
    30983380USE ieee.std_logic_1164.ALL;
    … …  
    31083390stg "VerticalLayoutStrategy"
    31093391textVec [
    3110 *89 (Text
     3392*97 (Text
    31113393uid 45,0
    31123394va (VaSet
    … …  
    31183400blo "20000,800"
    31193401)
    3120 *90 (Text
     3402*98 (Text
    31213403uid 46,0
    31223404va (VaSet
    … …  
    31283410blo "20000,1800"
    31293411)
    3130 *91 (MLText
     3412*99 (MLText
    31313413uid 47,0
    31323414va (VaSet
    … …  
    31383420tm "BdCompilerDirectivesTextMgr"
    31393421)
    3140 *92 (Text
     3422*100 (Text
    31413423uid 48,0
    31423424va (VaSet
    … …  
    31483430blo "20000,4800"
    31493431)
    3150 *93 (MLText
     3432*101 (MLText
    31513433uid 49,0
    31523434va (VaSet
    … …  
    31563438tm "BdCompilerDirectivesTextMgr"
    31573439)
    3158 *94 (Text
     3440*102 (Text
    31593441uid 50,0
    31603442va (VaSet
    … …  
    31663448blo "20000,5800"
    31673449)
    3168 *95 (MLText
     3450*103 (MLText
    31693451uid 51,0
    31703452va (VaSet
    … …  
    31773459associable 1
    31783460)
    3179 windowSize "0,22,1286,1024"
    3180 viewArea "834,29654,54098,72685"
    3181 cachedDiagramExtent "0,0,53000,77000"
     3461windowSize "0,0,1281,1002"
     3462viewArea "-6400,12000,60443,65739"
     3463cachedDiagramExtent "700,0,59000,77000"
    31823464pageSetupInfo (PageSetupInfo
    31833465ptrCmd "Brother HL-5270DN series,winspool,"
    … …  
    32053487hasePageBreakOrigin 1
    32063488pageBreakOrigin "0,0"
    3207 lastUid 1122,0
     3489lastUid 1237,0
    32083490defaultCommentText (CommentText
    32093491shape (Rectangle
    … …  
    32673549stg "VerticalLayoutStrategy"
    32683550textVec [
    3269 *96 (Text
     3551*104 (Text
    32703552va (VaSet
    32713553font "Arial,8,1"
    … …  
    32763558tm "BdLibraryNameMgr"
    32773559)
    3278 *97 (Text
     3560*105 (Text
    32793561va (VaSet
    32803562font "Arial,8,1"
    … …  
    32853567tm "BlkNameMgr"
    32863568)
    3287 *98 (Text
     3569*106 (Text
    32883570va (VaSet
    32893571font "Arial,8,1"
    … …  
    33363618stg "VerticalLayoutStrategy"
    33373619textVec [
    3338 *99 (Text
     3620*107 (Text
    33393621va (VaSet
    33403622font "Arial,8,1"
    … …  
    33443626blo "550,4300"
    33453627)
    3346 *100 (Text
     3628*108 (Text
    33473629va (VaSet
    33483630font "Arial,8,1"
    … …  
    33523634blo "550,5300"
    33533635)
    3354 *101 (Text
     3636*109 (Text
    33553637va (VaSet
    33563638font "Arial,8,1"
    … …  
    34013683stg "VerticalLayoutStrategy"
    34023684textVec [
    3403 *102 (Text
     3685*110 (Text
    34043686va (VaSet
    34053687font "Arial,8,1"
    … …  
    34103692tm "BdLibraryNameMgr"
    34113693)
    3412 *103 (Text
     3694*111 (Text
    34133695va (VaSet
    34143696font "Arial,8,1"
    … …  
    34193701tm "CptNameMgr"
    34203702)
    3421 *104 (Text
     3703*112 (Text
    34223704va (VaSet
    34233705font "Arial,8,1"
    … …  
    34733755stg "VerticalLayoutStrategy"
    34743756textVec [
    3475 *105 (Text
     3757*113 (Text
    34763758va (VaSet
    34773759font "Arial,8,1"
    … …  
    34813763blo "500,4300"
    34823764)
    3483 *106 (Text
     3765*114 (Text
    34843766va (VaSet
    34853767font "Arial,8,1"
    … …  
    34893771blo "500,5300"
    34903772)
    3491 *107 (Text
     3773*115 (Text
    34923774va (VaSet
    34933775font "Arial,8,1"
    … …  
    35343816stg "VerticalLayoutStrategy"
    35353817textVec [
    3536 *108 (Text
     3818*116 (Text
    35373819va (VaSet
    35383820font "Arial,8,1"
    … …  
    35423824blo "50,4300"
    35433825)
    3544 *109 (Text
     3826*117 (Text
    35453827va (VaSet
    35463828font "Arial,8,1"
    … …  
    35503832blo "50,5300"
    35513833)
    3552 *110 (Text
     3834*118 (Text
    35533835va (VaSet
    35543836font "Arial,8,1"
    … …  
    35913873stg "VerticalLayoutStrategy"
    35923874textVec [
    3593 *111 (Text
     3875*119 (Text
    35943876va (VaSet
    35953877font "Arial,8,1"
    … …  
    36003882tm "HdlTextNameMgr"
    36013883)
    3602 *112 (Text
     3884*120 (Text
    36033885va (VaSet
    36043886font "Arial,8,1"
    … …  
    40034285stg "VerticalLayoutStrategy"
    40044286textVec [
    4005 *113 (Text
     4287*121 (Text
    40064288va (VaSet
    40074289font "Arial,8,1"
    … …  
    40114293blo "14100,20800"
    40124294)
    4013 *114 (MLText
     4295*122 (MLText
    40144296va (VaSet
    40154297)
    … …  
    40634345stg "VerticalLayoutStrategy"
    40644346textVec [
    4065 *115 (Text
     4347*123 (Text
    40664348va (VaSet
    40674349font "Arial,8,1"
    … …  
    40714353blo "14100,20800"
    40724354)
    4073 *116 (MLText
     4355*124 (MLText
    40744356va (VaSet
    40754357)
    … …  
    41524434font "Arial,8,1"
    41534435)
    4154 xt "20000,0,25400,1000"
     4436xt "27000,200,32400,1200"
    41554437st "Declarations"
    4156 blo "20000,800"
     4438blo "27000,1000"
    41574439)
    41584440portLabel (Text
    … …  
    41614443font "Arial,8,1"
    41624444)
    4163 xt "20000,1000,22700,2000"
     4445xt "27000,1200,29700,2200"
    41644446st "Ports:"
    4165 blo "20000,1800"
     4447blo "27000,2000"
    41664448)
    41674449preUserLabel (Text
    … …  
    41714453font "Arial,8,1"
    41724454)
    4173 xt "20000,0,23800,1000"
     4455xt "27000,200,30800,1200"
    41744456st "Pre User:"
    4175 blo "20000,800"
     4457blo "27000,1000"
    41764458)
    41774459preUserText (MLText
    … …  
    41814463font "Courier New,8,0"
    41824464)
    4183 xt "20000,0,20000,0"
     4465xt "27000,200,27000,200"
    41844466tm "BdDeclarativeTextMgr"
    41854467)
    … …  
    41894471font "Arial,8,1"
    41904472)
    4191 xt "20000,11600,27100,12600"
     4473xt "27000,13400,34100,14400"
    41924474st "Diagram Signals:"
    4193 blo "20000,12400"
     4475blo "27000,14200"
    41944476)
    41954477postUserLabel (Text
    … …  
    41994481font "Arial,8,1"
    42004482)
    4201 xt "20000,0,24700,1000"
     4483xt "27000,200,31700,1200"
    42024484st "Post User:"
    4203 blo "20000,800"
     4485blo "27000,1000"
    42044486)
    42054487postUserText (MLText
    … …  
    42094491font "Courier New,8,0"
    42104492)
    4211 xt "20000,0,20000,0"
     4493xt "27000,200,27000,200"
    42124494tm "BdDeclarativeTextMgr"
    42134495)
    … …  
    42154497commonDM (CommonDM
    42164498ldm (LogicalDM
    4217 suid 18,0
     4499suid 20,0
    42184500usingSuid 1
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     4501emptyRow *125 (LEmptyRow
    42204502)
    42214503uid 54,0
    42224504optionalChildren [
    4223 *118 (RefLabelRowHdr
    4224 )
    4225 *119 (TitleRowHdr
    4226 )
    4227 *120 (FilterRowHdr
    4228 )
    4229 *121 (RefLabelColHdr
     4505*126 (RefLabelRowHdr
     4506)
     4507*127 (TitleRowHdr
     4508)
     4509*128 (FilterRowHdr
     4510)
     4511*129 (RefLabelColHdr
    42304512tm "RefLabelColHdrMgr"
    42314513)
    4232 *122 (RowExpandColHdr
     4514*130 (RowExpandColHdr
    42334515tm "RowExpandColHdrMgr"
    42344516)
    4235 *123 (GroupColHdr
     4517*131 (GroupColHdr
    42364518tm "GroupColHdrMgr"
    42374519)
    4238 *124 (NameColHdr
     4520*132 (NameColHdr
    42394521tm "BlockDiagramNameColHdrMgr"
    42404522)
    4241 *125 (ModeColHdr
     4523*133 (ModeColHdr
    42424524tm "BlockDiagramModeColHdrMgr"
    42434525)
    4244 *126 (TypeColHdr
     4526*134 (TypeColHdr
    42454527tm "BlockDiagramTypeColHdrMgr"
    42464528)
    4247 *127 (BoundsColHdr
     4529*135 (BoundsColHdr
    42484530tm "BlockDiagramBoundsColHdrMgr"
    42494531)
    4250 *128 (InitColHdr
     4532*136 (InitColHdr
    42514533tm "BlockDiagramInitColHdrMgr"
    42524534)
    4253 *129 (EolColHdr
     4535*137 (EolColHdr
    42544536tm "BlockDiagramEolColHdrMgr"
    42554537)
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     4538*138 (LeafLogPort
    42574539port (LogicalPort
    42584540decl (Decl
    … …  
    42654547uid 427,0
    42664548)
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    42684550port (LogicalPort
    42694551m 4
    … …  
    42784560uid 429,0
    42794561)
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     4562*140 (LeafLogPort
    42814563port (LogicalPort
    42824564decl (Decl
    … …  
    42904572uid 431,0
    42914573)
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     4574*141 (LeafLogPort
    42934575port (LogicalPort
    42944576m 4
    … …  
    43034585uid 433,0
    43044586)
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     4587*142 (LeafLogPort
    43064588port (LogicalPort
    43074589m 1
    … …  
    43154597uid 435,0
    43164598)
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     4599*143 (LeafLogPort
    43184600port (LogicalPort
    43194601m 1
    … …  
    43274609uid 437,0
    43284610)
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     4611*144 (LeafLogPort
    43304612port (LogicalPort
    43314613m 2
    … …  
    43404622uid 439,0
    43414623)
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     4624*145 (LeafLogPort
    43434625port (LogicalPort
    43444626m 1
    … …  
    43524634uid 441,0
    43534635)
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     4636*146 (LeafLogPort
    43554637port (LogicalPort
    43564638m 4
    … …  
    43654647uid 443,0
    43664648)
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     4649*147 (LeafLogPort
    43684650port (LogicalPort
    43694651decl (Decl
    … …  
    43764658uid 445,0
    43774659)
    4378 *140 (LeafLogPort
     4660*148 (LeafLogPort
    43794661port (LogicalPort
    43804662m 4
    … …  
    43894671uid 447,0
    43904672)
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     4673*149 (LeafLogPort
    43924674port (LogicalPort
    43934675m 1
    … …  
    44014683uid 449,0
    44024684)
    4403 *142 (LeafLogPort
     4685*150 (LeafLogPort
    44044686port (LogicalPort
    44054687decl (Decl
    … …  
    44124694uid 451,0
    44134695)
    4414 *143 (LeafLogPort
     4696*151 (LeafLogPort
    44154697port (LogicalPort
    44164698decl (Decl
    … …  
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    44244706)
    4425 *144 (LeafLogPort
     4707*152 (LeafLogPort
    44264708port (LogicalPort
    44274709m 1
    … …  
    44354717uid 457,0
    44364718)
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     4719*153 (LeafLogPort
    44384720port (LogicalPort
    44394721m 1
    … …  
    44484730uid 1096,0
    44494731)
     4732*154 (LeafLogPort
     4733port (LogicalPort
     4734m 1
     4735decl (Decl
     4736n "drs_address"
     4737t "std_logic_vector"
     4738b "(3 DOWNTO 0)"
     4739o 17
     4740suid 19,0
     4741)
     4742)
     4743uid 1234,0
     4744)
     4745*155 (LeafLogPort
     4746port (LogicalPort
     4747m 1
     4748decl (Decl
     4749n "drs_address_mode"
     4750t "std_logic"
     4751o 18
     4752suid 20,0
     4753)
     4754)
     4755uid 1236,0
     4756)
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak

    r246 r252  
    6060)
    6161version "29.1"
    62 appVersion "2009.1 (Build 12)"
     62appVersion "2009.2 (Build 10)"
    6363noEmbeddedEditors 1
    6464model (BlockDiag
    … …  
    6767(vvPair
    6868variable "HDLDir"
    69 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"
     69value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
    7070)
    7171(vvPair
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     73value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    7474)
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    7676variable "SideDataDesignDir"
    77 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
     77value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"
    7878)
    7979(vvPair
    8080variable "SideDataUserDir"
    81 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
     81value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"
    8282)
    8383(vvPair
    8484variable "SourceDir"
    85 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
     85value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    8686)
    8787(vvPair
    … …  
    9999(vvPair
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    101 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
     101value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    102102)
    103103(vvPair
    104104variable "d_logical"
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     105value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    106106)
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    109 value "27.05.2010"
     109value "12.07.2010"
    110110)
    111111(vvPair
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    113 value "Do"
     113value "Mo"
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     121value "12"
    122122)
    123123(vvPair
    … …  
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     149value "TU-CC4900F8C7D2"
    150150)
    151151(vvPair
    … …  
    175175(vvPair
    176176variable "mm"
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     177value "07"
    178178)
    179179(vvPair
    … …  
    183183(vvPair
    184184variable "month"
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    187187(vvPair
    188188variable "month_long"
    189 value "Mai"
     189value "Juli"
    190190)
    191191(vvPair
    192192variable "p"
    193 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
     193value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
    194194)
    195195(vvPair
    196196variable "p_logical"
    197 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
     197value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"
    198198)
    199199(vvPair
    … …  
    219219(vvPair
    220220variable "task_ModelSimPath"
    221 value "D:\\modeltech_6.5e\\win32"
     221value "<TBD>"
    222222)
    223223(vvPair
    … …  
    251251(vvPair
    252252variable "time"
    253 value "10:24:01"
     253value "13:47:38"
    254254)
    255255(vvPair
    … …  
    259259(vvPair
    260260variable "user"
    261 value "daqct3"
     261value "dneise"
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    263263(vvPair
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     265value "2009.2 (Build 10)"
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    … …  
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    … …  
    733727font "Courier New,8,0"
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    774 "
     764xt "29000,12800,58500,13600"
     765st "SIGNAL ram_addr          : std_logic_VECTOR(7 DOWNTO 0)"
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    … …  
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    … …  
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    … …  
    843831font "Courier New,8,0"
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    846 st "config_rd_en      : std_logic
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     833xt "29000,3800,45000,4600"
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    … …  
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    … …  
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     867xt "29000,7800,45000,8600"
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    885870)
    … …  
    897882sl 0
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     884xt "2000,19625,3500,20375"
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    901886(Line
    … …  
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     890xt "3500,20000,4000,20000"
    906891pts [
    907 "4500,24000"
    908 "5000,24000"
     892"3500,20000"
     893"4000,20000"
    909894]
    910895)
    … …  
    921906va (VaSet
    922907)
    923 xt "700,23500,2000,24500"
     908xt "700,19500,2000,20500"
    924909st "clk"
    925910ju 2
    926 blo "2000,24300"
     911blo "2000,20300"
    927912tm "WireNameMgr"
    928913)
    … …  
    942927sl 0
    943928ro 270
    944 xt "42500,28625,44000,29375"
     929xt "36500,28625,38000,29375"
    945930)
    946931(Line
    … …  
    948933sl 0
    949934ro 270
    950 xt "42000,29000,42500,29000"
     935xt "36000,29000,36500,29000"
    951936pts [
    952 "42000,29000"
    953 "42500,29000"
     937"36000,29000"
     938"36500,29000"
    954939]
    955940)
    … …  
    966951va (VaSet
    967952)
    968 xt "45000,28500,50100,29500"
     953xt "39000,28500,44100,29500"
    969954st "config_ready"
    970 blo "45000,29300"
     955blo "39000,29300"
    971956tm "WireNameMgr"
    972957)
    … …  
    986971sl 0
    987972ro 90
    988 xt "42500,29625,44000,30375"
     973xt "36500,29625,38000,30375"
    989974)
    990975(Line
    … …  
    992977sl 0
    993978ro 90
    994 xt "42000,30000,42500,30000"
     979xt "36000,30000,36500,30000"
    995980pts [
    996 "42500,30000"
    997 "42000,30000"
     981"36500,30000"
     982"36000,30000"
    998983]
    999984)
    … …  
    1010995va (VaSet
    1011996)
    1012 xt "45000,29500,49800,30500"
     997xt "39000,29500,43800,30500"
    1013998st "config_start"
    1014 blo "45000,30300"
     999blo "39000,30300"
    10151000tm "WireNameMgr"
    10161001)
    … …  
    10291014uid 381,0
    10301015sl 0
    1031 xt "42500,24625,44000,25375"
     1016xt "36500,24625,38000,25375"
    10321017)
    10331018(Line
    10341019uid 382,0
    10351020sl 0
    1036 xt "42000,25000,42500,25000"
     1021xt "36000,25000,36500,25000"
    10371022pts [
    1038 "42000,25000"
    1039 "42500,25000"
     1023"36000,25000"
     1024"36500,25000"
    10401025]
    10411026)
    … …  
    10521037va (VaSet
    10531038)
    1054 xt "45000,24500,49700,25500"
     1039xt "39000,24500,43700,25500"
    10551040st "config_data"
    1056 blo "45000,25300"
     1041blo "39000,25300"
    10571042tm "WireNameMgr"
    10581043)
    … …  
    10721057sl 0
    10731058ro 90
    1074 xt "42500,23625,44000,24375"
     1059xt "36500,23625,38000,24375"
    10751060)
    10761061(Line
    … …  
    10781063sl 0
    10791064ro 90
    1080 xt "42000,24000,42500,24000"
     1065xt "36000,24000,36500,24000"
    10811066pts [
    1082 "42500,24000"
    1083 "42000,24000"
     1067"36500,24000"
     1068"36000,24000"
    10841069]
    10851070)
    … …  
    10961081va (VaSet
    10971082)
    1098 xt "45000,23500,49800,24500"
     1083xt "39000,23500,43800,24500"
    10991084st "config_addr"
    1100 blo "45000,24300"
     1085blo "39000,24300"
    11011086tm "WireNameMgr"
    11021087)
    … …  
    11161101sl 0
    11171102ro 90
    1118 xt "42500,26625,44000,27375"
     1103xt "36500,26625,38000,27375"
    11191104)
    11201105(Line
    … …  
    11221107sl 0
    11231108ro 90
    1124 xt "42000,27000,42500,27000"
     1109xt "36000,27000,36500,27000"
    11251110pts [
    1126 "42500,27000"
    1127 "42000,27000"
     1111"36500,27000"
     1112"36000,27000"
    11281113]
    11291114)
    … …  
    11401125va (VaSet
    11411126)
    1142 xt "45000,26500,50300,27500"
     1127xt "39000,26500,44300,27500"
    11431128st "config_wr_en"
    1144 blo "45000,27300"
     1129blo "39000,27300"
    11451130tm "WireNameMgr"
    11461131)
    … …  
    11601145sl 0
    11611146ro 90
    1162 xt "42500,27625,44000,28375"
     1147xt "36500,27625,38000,28375"
    11631148)
    11641149(Line
    … …  
    11661151sl 0
    11671152ro 90
    1168 xt "42000,28000,42500,28000"
     1153xt "36000,28000,36500,28000"
    11691154pts [
    1170 "42500,28000"
    1171 "42000,28000"
     1155"36500,28000"
     1156"36000,28000"
    11721157]
    11731158)
    … …  
    11841169va (VaSet
    11851170)
    1186 xt "45000,27500,50200,28500"
     1171xt "39000,27500,44200,28500"
    11871172st "config_rd_en"
    1188 blo "45000,28300"
     1173blo "39000,28300"
    11891174tm "WireNameMgr"
    11901175)
    … …  
    12041189sl 0
    12051190ro 270
    1206 xt "42500,33625,44000,34375"
     1191xt "36500,33625,38000,34375"
    12071192)
    12081193(Line
    … …  
    12101195sl 0
    12111196ro 270
    1212 xt "42000,34000,42500,34000"
     1197xt "36000,34000,36500,34000"
    12131198pts [
    1214 "42000,34000"
    1215 "42500,34000"
     1199"36000,34000"
     1200"36500,34000"
    12161201]
    12171202)
    … …  
    12281213va (VaSet
    12291214)
    1230 xt "45000,33500,48700,34500"
     1215xt "39000,33500,42700,34500"
    12311216st "dac_array"
    1232 blo "45000,34300"
     1217blo "39000,34300"
    12331218tm "WireNameMgr"
    12341219)
    … …  
    12481233sl 0
    12491234ro 270
    1250 xt "42500,34625,44000,35375"
     1235xt "36500,34625,38000,35375"
    12511236)
    12521237(Line
    … …  
    12541239sl 0
    12551240ro 270
    1256 xt "42000,35000,42500,35000"
     1241xt "36000,35000,36500,35000"
    12571242pts [
    1258 "42000,35000"
    1259 "42500,35000"
     1243"36000,35000"
     1244"36500,35000"
    12601245]
    12611246)
    … …  
    12721257va (VaSet
    12731258)
    1274 xt "45000,34500,48400,35500"
     1259xt "39000,34500,42400,35500"
    12751260st "roi_array"
    1276 blo "45000,35300"
     1261blo "39000,35300"
    12771262tm "WireNameMgr"
    12781263)
    … …  
    12921277sl 0
    12931278ro 270
    1294 xt "42500,31625,44000,32375"
     1279xt "36500,31625,38000,32375"
    12951280)
    12961281(Line
    … …  
    12981283sl 0
    12991284ro 270
    1300 xt "42000,32000,42500,32000"
     1285xt "36000,32000,36500,32000"
    13011286pts [
    1302 "42000,32000"
    1303 "42500,32000"
     1287"36000,32000"
     1288"36500,32000"
    13041289]
    13051290)
    … …  
    13161301va (VaSet
    13171302)
    1318 xt "45000,31500,51600,32500"
     1303xt "39000,31500,45600,32500"
    13191304st "config_data_valid"
    1320 blo "45000,32300"
     1305blo "39000,32300"
    13211306tm "WireNameMgr"
    13221307)
    … …  
    13361321sl 0
    13371322ro 270
    1338 xt "42500,32625,44000,33375"
     1323xt "36500,32625,38000,33375"
    13391324)
    13401325(Line
    … …  
    13421327sl 0
    13431328ro 270
    1344 xt "42000,33000,42500,33000"
     1329xt "36000,33000,36500,33000"
    13451330pts [
    1346 "42000,33000"
    1347 "42500,33000"
     1331"36000,33000"
     1332"36500,33000"
    13481333]
    13491334)
    … …  
    13601345va (VaSet
    13611346)
    1362 xt "45000,32500,49800,33500"
     1347xt "39000,32500,43800,33500"
    13631348st "config_busy"
    1364 blo "45000,33300"
     1349blo "39000,33300"
    13651350tm "WireNameMgr"
    13661351)
    … …  
    13801365fg "0,65535,0"
    13811366)
    1382 xt "12250,23625,13000,24375"
     1367xt "6250,23625,7000,24375"
    13831368)
    13841369tg (CPTG
    … …  
    13901375va (VaSet
    13911376)
    1392 xt "14000,23500,15300,24500"
     1377xt "8000,23500,9300,24500"
    13931378st "clk"
    1394 blo "14000,24300"
     1379blo "8000,24300"
    13951380)
    13961381)
    … …  
    14161401fg "0,65535,0"
    14171402)
    1418 xt "38000,28625,38750,29375"
     1403xt "32000,28625,32750,29375"
    14191404)
    14201405tg (CPTG
    … …  
    14261411va (VaSet
    14271412)
    1428 xt "31900,28500,37000,29500"
     1413xt "25900,28500,31000,29500"
    14291414st "config_ready"
    14301415ju 2
    1431 blo "37000,29300"
     1416blo "31000,29300"
    14321417)
    14331418)
    … …  
    14551440fg "0,65535,0"
    14561441)
    1457 xt "38000,29625,38750,30375"
     1442xt "32000,29625,32750,30375"
    14581443)
    14591444tg (CPTG
    … …  
    14651450va (VaSet
    14661451)
    1467 xt "32200,29500,37000,30500"
     1452xt "26200,29500,31000,30500"
    14681453st "config_start"
    14691454ju 2
    1470 blo "37000,30300"
     1455blo "31000,30300"
    14711456)
    14721457)
    … …  
    14921477fg "0,65535,0"
    14931478)
    1494 xt "38000,24625,38750,25375"
     1479xt "32000,24625,32750,25375"
    14951480)
    14961481tg (CPTG
    … …  
    15021487va (VaSet
    15031488)
    1504 xt "29300,24500,37000,25500"
     1489xt "23300,24500,31000,25500"
    15051490st "config_data : (15:0)"
    15061491ju 2
    1507 blo "37000,25300"
     1492blo "31000,25300"
    15081493)
    15091494)
    … …  
    15321517fg "0,65535,0"
    15331518)
    1534 xt "38000,23625,38750,24375"
     1519xt "32000,23625,32750,24375"
    15351520)
    15361521tg (CPTG
    … …  
    15421527va (VaSet
    15431528)
    1544 xt "23600,23500,37000,24500"
     1529xt "17600,23500,31000,24500"
    15451530st "config_addr : (ADDR_WIDTH - 1:0)"
    15461531ju 2
    1547 blo "37000,24300"
     1532blo "31000,24300"
    15481533)
    15491534)
    … …  
    15701555fg "0,65535,0"
    15711556)
    1572 xt "38000,26625,38750,27375"
     1557xt "32000,26625,32750,27375"
    15731558)
    15741559tg (CPTG
    … …  
    15801565va (VaSet
    15811566)
    1582 xt "31700,26500,37000,27500"
     1567xt "25700,26500,31000,27500"
    15831568st "config_wr_en"
    15841569ju 2
    1585 blo "37000,27300"
     1570blo "31000,27300"
    15861571)
    15871572)
    … …  
    16071592fg "0,65535,0"
    16081593)
    1609 xt "38000,27625,38750,28375"
     1594xt "32000,27625,32750,28375"
    16101595)
    16111596tg (CPTG
    … …  
    16171602va (VaSet
    16181603)
    1619 xt "31800,27500,37000,28500"
     1604xt "25800,27500,31000,28500"
    16201605st "config_rd_en"
    16211606ju 2
    1622 blo "37000,28300"
     1607blo "31000,28300"
    16231608)
    16241609)
    … …  
    16441629fg "0,65535,0"
    16451630)
    1646 xt "38000,31625,38750,32375"
     1631xt "32000,31625,32750,32375"
    16471632)
    16481633tg (CPTG
    … …  
    16541639va (VaSet
    16551640)
    1656 xt "30400,31500,37000,32500"
     1641xt "24400,31500,31000,32500"
    16571642st "config_data_valid"
    16581643ju 2
    1659 blo "37000,32300"
     1644blo "31000,32300"
    16601645)
    16611646)
    … …  
    16831668fg "0,65535,0"
    16841669)
    1685 xt "38000,32625,38750,33375"
     1670xt "32000,32625,32750,33375"
    16861671)
    16871672tg (CPTG
    … …  
    16931678va (VaSet
    16941679)
    1695 xt "32200,32500,37000,33500"
     1680xt "26200,32500,31000,33500"
    16961681st "config_busy"
    16971682ju 2
    1698 blo "37000,33300"
     1683blo "31000,33300"
    16991684)
    17001685)
    … …  
    17221707fg "0,65535,0"
    17231708)
    1724 xt "38000,33625,38750,34375"
     1709xt "32000,33625,32750,34375"
    17251710)
    17261711tg (CPTG
    … …  
    17321717va (VaSet
    17331718)
    1734 xt "33300,33500,37000,34500"
     1719xt "27300,33500,31000,34500"
    17351720st "dac_array"
    17361721ju 2
    1737 blo "37000,34300"
     1722blo "31000,34300"
    17381723)
    17391724)
    … …  
    17601745fg "0,65535,0"
    17611746)
    1762 xt "38000,34625,38750,35375"
     1747xt "32000,34625,32750,35375"
    17631748)
    17641749tg (CPTG
    … …  
    17701755va (VaSet
    17711756)
    1772 xt "33600,34500,37000,35500"
     1757xt "27600,34500,31000,35500"
    17731758st "roi_array"
    17741759ju 2
    1775 blo "37000,35300"
     1760blo "31000,35300"
    17761761)
    17771762)
    … …  
    17981783fg "0,65535,0"
    17991784)
    1800 xt "38000,37625,38750,38375"
     1785xt "32000,37625,32750,38375"
    18011786)
    18021787tg (CPTG
    … …  
    18081793va (VaSet
    18091794)
    1810 xt "29100,37500,37000,38500"
     1795xt "23100,37500,31000,38500"
    18111796st "ram_data_in : (15:0)"
    18121797ju 2
    1813 blo "37000,38300"
     1798blo "31000,38300"
    18141799)
    18151800)
    … …  
    18351820fg "0,65535,0"
    18361821)
    1837 xt "38000,38625,38750,39375"
     1822xt "32000,38625,32750,39375"
    18381823)
    18391824tg (CPTG
    … …  
    18451830va (VaSet
    18461831)
    1847 xt "29100,38500,37000,39500"
     1832xt "23100,38500,31000,39500"
    18481833st "ram_write_en : (0:0)"
    18491834ju 2
    1850 blo "37000,39300"
     1835blo "31000,39300"
    18511836)
    18521837)
    … …  
    18721857fg "0,65535,0"
    18731858)
    1874 xt "12250,24625,13000,25375"
     1859xt "6250,38625,7000,39375"
    18751860)
    18761861tg (CPTG
    … …  
    18821867va (VaSet
    18831868)
    1884 xt "14000,24500,22300,25500"
     1869xt "8000,38500,16300,39500"
    18851870st "ram_data_out : (15:0)"
    1886 blo "14000,25300"
     1871blo "8000,39300"
    18871872)
    18881873)
    … …  
    19071892fg "0,65535,0"
    19081893)
    1909 xt "38000,39625,38750,40375"
     1894xt "32000,39625,32750,40375"
    19101895)
    19111896tg (CPTG
    … …  
    19171902va (VaSet
    19181903)
    1919 xt "24400,39500,37000,40500"
     1904xt "18400,39500,31000,40500"
    19201905st "ram_addr : (ADDR_WIDTH - 1:0)"
    19211906ju 2
    1922 blo "37000,40300"
     1907blo "31000,40300"
    19231908)
    19241909)
    … …  
    19441929fg "0,65535,0"
    19451930)
    1946 xt "38000,30625,38750,31375"
     1931xt "32000,30625,32750,31375"
    19471932)
    19481933tg (CPTG
    … …  
    19541939va (VaSet
    19551940)
    1956 xt "31400,30500,37000,31500"
     1941xt "25400,30500,31000,31500"
    19571942st "config_started"
    19581943ju 2
    1959 blo "37000,31300"
     1944blo "31000,31300"
    19601945)
    19611946)
    … …  
    19801965lineWidth 2
    19811966)
    1982 xt "13000,23000,38000,42000"
     1967xt "7000,23000,32000,42000"
    19831968)
    19841969oxt "42000,14000,67000,32000"
    … …  
    19931978font "Arial,8,1"
    19941979)
    1995 xt "12950,42000,19150,43000"
     1980xt "6950,42000,13150,43000"
    19961981st "FACT_FAD_lib"
    1997 blo "12950,42800"
     1982blo "6950,42800"
    19981983tm "BdLibraryNameMgr"
    19991984)
    … …  
    20031988font "Arial,8,1"
    20041989)
    2005 xt "12950,43000,20050,44000"
     1990xt "6950,43000,14050,44000"
    20061991st "control_manager"
    2007 blo "12950,43800"
     1992blo "6950,43800"
    20081993tm "CptNameMgr"
    20091994)
    … …  
    20131998font "Arial,8,1"
    20141999)
    2015 xt "12950,44000,20650,45000"
     2000xt "6950,44000,14650,45000"
    20162001st "I_control_manager"
    2017 blo "12950,44800"
     2002blo "6950,44800"
    20182003tm "InstanceNameMgr"
    20192004)
    … …  
    20302015font "Courier New,8,0"
    20312016)
    2032 xt "12500,10600,30000,13000"
     2017xt "10000,20600,27500,23000"
    20332018st "NO_OF_ROI  = 36    ( integer ) 
    20342019NO_OF_DAC  = 8     ( integer ) 
    … …  
    20622047fg "49152,49152,49152"
    20632048)
    2064 xt "13250,40250,14750,41750"
     2049xt "7250,40250,8750,41750"
    20652050iconName "VhdlFileViewIcon.png"
    20662051iconMaskName "VhdlFileViewIcon.msk"
    … …  
    20812066shape (Triangle
    20822067uid 971,0
    2083 ro 90
     2068ro 180
    20842069va (VaSet
    20852070vasetType 1
    20862071fg "0,65535,0"
    20872072)
    2088 xt "19250,50625,20000,51375"
     2073xt "42625,41250,43375,42000"
    20892074)
    20902075tg (CPTG
    20912076uid 972,0
    20922077ps "CptPortTextPlaceStrategy"
    2093 stg "VerticalLayoutStrategy"
     2078stg "RightVerticalLayoutStrategy"
    20942079f (Text
    20952080uid 973,0
    2096 va (VaSet
    2097 )
    2098 xt "21000,50500,22700,51500"
     2081ro 270
     2082va (VaSet
     2083)
     2084xt "42500,43000,43500,44700"
    20992085st "clka"
    2100 blo "21000,51300"
     2086ju 2
     2087blo "43300,43000"
    21012088)
    21022089)
    … …  
    21222109fg "0,65535,0"
    21232110)
    2124 xt "19250,52625,20000,53375"
     2111xt "39250,45625,40000,46375"
    21252112)
    21262113tg (CPTG
    … …  
    21322119va (VaSet
    21332120)
    2134 xt "21000,52500,25800,53500"
     2121xt "41000,45500,45800,46500"
    21352122st "dina : (15:0)"
    2136 blo "21000,53300"
     2123blo "41000,46300"
    21372124)
    21382125)
    … …  
    21592146fg "0,65535,0"
    21602147)
    2161 xt "19250,54625,20000,55375"
     2148xt "39250,47625,40000,48375"
    21622149)
    21632150tg (CPTG
    … …  
    21692156va (VaSet
    21702157)
    2171 xt "21000,54500,25900,55500"
     2158xt "41000,47500,45900,48500"
    21722159st "addra : (7:0)"
    2173 blo "21000,55300"
     2160blo "41000,48300"
    21742161)
    21752162)
    … …  
    21962183fg "0,65535,0"
    21972184)
    2198 xt "19250,53625,20000,54375"
     2185xt "39250,46625,40000,47375"
    21992186)
    22002187tg (CPTG
    … …  
    22062193va (VaSet
    22072194)
    2208 xt "21000,53500,25300,54500"
     2195xt "41000,46500,45300,47500"
    22092196st "wea : (0:0)"
    2210 blo "21000,54300"
     2197blo "41000,47300"
    22112198)
    22122199)
    … …  
    22332220fg "0,65535,0"
    22342221)
    2235 xt "30000,50625,30750,51375"
     2222xt "50000,43625,50750,44375"
    22362223)
    22372224tg (CPTG
    … …  
    22432230va (VaSet
    22442231)
    2245 xt "23800,50500,29000,51500"
     2232xt "43800,43500,49000,44500"
    22462233st "douta : (15:0)"
    22472234ju 2
    2248 blo "29000,51300"
     2235blo "49000,44300"
    22492236)
    22502237)
    … …  
    22712258lineWidth 2
    22722259)
    2273 xt "20000,49000,30000,59000"
     2260xt "40000,42000,50000,52000"
    22742261)
    22752262oxt "30000,7000,40000,17000"
    … …  
    22842271font "Arial,8,1"
    22852272)
    2286 xt "20200,59000,26400,60000"
     2273xt "40200,52000,46400,53000"
    22872274st "FACT_FAD_lib"
    2288 blo "20200,59800"
     2275blo "40200,52800"
    22892276tm "BdLibraryNameMgr"
    22902277)
    … …  
    22942281font "Arial,8,1"
    22952282)
    2296 xt "20200,60000,30100,61000"
     2283xt "40200,53000,50100,54000"
    22972284st "controlRAM_16bit_x256"
    2298 blo "20200,60800"
     2285blo "40200,53800"
    22992286tm "CptNameMgr"
    23002287)
    … …  
    23042291font "Arial,8,1"
    23052292)
    2306 xt "20200,61000,26100,62000"
     2293xt "40200,54000,46100,55000"
    23072294st "I_control_ram"
    2308 blo "20200,61800"
     2295blo "40200,54800"
    23092296tm "InstanceNameMgr"
    23102297)
    … …  
    23212308font "Courier New,8,0"
    23222309)
    2323 xt "19500,48000,19500,48000"
     2310xt "39500,41000,39500,41000"
    23242311)
    23252312header ""
    … …  
    23352322fg "49152,49152,49152"
    23362323)
    2337 xt "20250,57250,21750,58750"
    2338 iconName "UnknownFile.png"
    2339 iconMaskName "UnknownFile.msk"
     2324xt "40250,50250,41750,51750"
     2325iconName "VhdlFileViewIcon.png"
     2326iconMaskName "VhdlFileViewIcon.msk"
     2327ftype 10
    23402328)
    23412329ordering 1
    … …  
    23602348font "Courier New,8,0"
    23612349)
    2362 xt "22000,8400,41500,9200"
    2363 st "config_started    : std_logic := '0'
    2364 "
     2350xt "29000,8600,48500,9400"
     2351st "config_started    : std_logic := '0'"
    23652352)
    23662353)
    … …  
    23782365sl 0
    23792366ro 270
    2380 xt "42500,30625,44000,31375"
     2367xt "36500,30625,38000,31375"
    23812368)
    23822369(Line
    … …  
    23842371sl 0
    23852372ro 270
    2386 xt "42000,31000,42500,31000"
     2373xt "36000,31000,36500,31000"
    23872374pts [
    2388 "42000,31000"
    2389 "42500,31000"
     2375"36000,31000"
     2376"36500,31000"
    23902377]
    23912378)
    … …  
    24022389va (VaSet
    24032390)
    2404 xt "45000,30500,50600,31500"
     2391xt "39000,30500,44600,31500"
    24052392st "config_started"
    2406 blo "45000,31300"
     2393blo "39000,31300"
    24072394tm "WireNameMgr"
    24082395)
    … …  
    24172404lineWidth 2
    24182405)
    2419 xt "38750,24000,42000,24000"
     2406xt "32750,24000,36000,24000"
    24202407pts [
    2421 "42000,24000"
    2422 "40000,24000"
    2423 "38750,24000"
     2408"36000,24000"
     2409"32750,24000"
    24242410]
    24252411)
    … …  
    24422428isHidden 1
    24432429)
    2444 xt "45000,23000,49800,24000"
     2430xt "39000,23000,43800,24000"
    24452431st "config_addr"
    2446 blo "45000,23800"
     2432blo "39000,23800"
    24472433tm "WireNameMgr"
    24482434)
    … …  
    24582444lineWidth 2
    24592445)
    2460 xt "13000,39000,43000,54000"
     2446xt "32750,39000,39250,47000"
    24612447pts [
    2462 "19250,54000"
    2463 "13000,54000"
    2464 "13000,47000"
    2465 "43000,47000"
    2466 "43000,39000"
    2467 "38750,39000"
     2448"39250,47000"
     2449"34000,47000"
     2450"34000,39000"
     2451"32750,39000"
    24682452]
    24692453)
    … …  
    24842468va (VaSet
    24852469)
    2486 xt "23000,46000,29300,47000"
     2470xt "34000,46000,40300,47000"
    24872471st "ram_wren : (0:0)"
    2488 blo "23000,46800"
     2472blo "34000,46800"
    24892473tm "WireNameMgr"
    24902474)
    … …  
    25002484lineWidth 2
    25012485)
    2502 xt "14000,38000,44000,53000"
     2486xt "32750,38000,39250,46000"
    25032487pts [
    2504 "19250,53000"
    2505 "14000,53000"
    2506 "14000,48000"
    2507 "44000,48000"
    2508 "44000,38000"
    2509 "38750,38000"
     2488"39250,46000"
     2489"35000,46000"
     2490"35000,38000"
     2491"32750,38000"
    25102492]
    25112493)
    … …  
    25262508va (VaSet
    25272509)
    2528 xt "23000,47000,30900,48000"
     2510xt "33000,37000,40900,38000"
    25292511st "ram_data_in : (15:0)"
    2530 blo "23000,47800"
     2512blo "33000,37800"
    25312513tm "WireNameMgr"
    25322514)
    … …  
    25412523vasetType 3
    25422524)
    2543 xt "5000,24000,12250,24000"
     2525xt "4000,20000,6250,24000"
    25442526pts [
     2527"4000,20000"
     2528"5000,20000"
    25452529"5000,24000"
    2546 "12250,24000"
     2530"6250,24000"
    25472531]
    25482532)
    … …  
    25642548isHidden 1
    25652549)
    2566 xt "7000,23000,8300,24000"
     2550xt "6000,19000,7300,20000"
    25672551st "clk"
    2568 blo "7000,23800"
     2552blo "6000,19800"
    25692553tm "WireNameMgr"
    25702554)
    … …  
    25792563vasetType 3
    25802564)
    2581 xt "38750,32000,42000,32000"
     2565xt "32750,32000,36000,32000"
    25822566pts [
    2583 "38750,32000"
    2584 "42000,32000"
     2567"32750,32000"
     2568"36000,32000"
    25852569]
    25862570)
    … …  
    26022586isHidden 1
    26032587)
    2604 xt "45000,30000,51600,31000"
     2588xt "39000,30000,45600,31000"
    26052589st "config_data_valid"
    2606 blo "45000,30800"
     2590blo "39000,30800"
    26072591tm "WireNameMgr"
    26082592)
    … …  
    26172601vasetType 3
    26182602)
    2619 xt "38750,33000,42000,33000"
     2603xt "32750,33000,36000,33000"
    26202604pts [
    2621 "38750,33000"
    2622 "42000,33000"
     2605"32750,33000"
     2606"36000,33000"
    26232607]
    26242608)
    … …  
    26402624isHidden 1
    26412625)
    2642 xt "45000,31000,49800,32000"
     2626xt "39000,31000,43800,32000"
    26432627st "config_busy"
    2644 blo "45000,31800"
     2628blo "39000,31800"
    26452629tm "WireNameMgr"
    26462630)
    … …  
    26562640lineWidth 2
    26572641)
    2658 xt "38750,25000,42000,25000"
     2642xt "32750,25000,36000,25000"
    26592643pts [
    2660 "42000,25000"
    2661 "40000,25000"
    2662 "38750,25000"
     2644"36000,25000"
     2645"32750,25000"
    26632646]
    26642647)
    … …  
    26812664isHidden 1
    26822665)
    2683 xt "45000,24000,49700,25000"
     2666xt "39000,24000,43700,25000"
    26842667st "config_data"
    2685 blo "45000,24800"
     2668blo "39000,24800"
    26862669tm "WireNameMgr"
    26872670)
    … …  
    26962679vasetType 3
    26972680)
    2698 xt "38750,35000,42000,35000"
     2681xt "32750,35000,36000,35000"
    26992682pts [
    2700 "38750,35000"
    2701 "40000,35000"
    2702 "42000,35000"
     2683"32750,35000"
     2684"36000,35000"
    27032685]
    27042686)
    … …  
    27202702isHidden 1
    27212703)
    2722 xt "45000,34000,48400,35000"
     2704xt "39000,34000,42400,35000"
    27232705st "roi_array"
    2724 blo "45000,34800"
     2706blo "39000,34800"
    27252707tm "WireNameMgr"
    27262708)
    … …  
    27352717vasetType 3
    27362718)
    2737 xt "17000,51000,19250,51000"
     2719xt "43000,38000,43000,41250"
    27382720pts [
    2739 "17000,51000"
    2740 "19250,51000"
     2721"43000,38000"
     2722"43000,41250"
    27412723]
    27422724)
    … …  
    27552737va (VaSet
    27562738)
    2757 xt "18000,50000,19300,51000"
     2739xt "44000,37000,45300,38000"
    27582740st "clk"
    2759 blo "18000,50800"
     2741blo "44000,37800"
    27602742tm "WireNameMgr"
    27612743)
    … …  
    27712753lineWidth 2
    27722754)
    2773 xt "12000,40000,42000,55000"
     2755xt "32750,40000,39250,48000"
    27742756pts [
    2775 "38750,40000"
    2776 "42000,40000"
    2777 "42000,46000"
    2778 "12000,46000"
    2779 "12000,55000"
    2780 "19250,55000"
     2757"32750,40000"
     2758"33000,40000"
     2759"33000,48000"
     2760"39250,48000"
    27812761]
    27822762)
    … …  
    27972777va (VaSet
    27982778)
    2799 xt "23000,45000,29200,46000"
     2779xt "33000,47000,39200,48000"
    28002780st "ram_addr : (7:0)"
    2801 blo "23000,45800"
     2781blo "33000,47800"
    28022782tm "WireNameMgr"
    28032783)
    … …  
    28122792vasetType 3
    28132793)
    2814 xt "38750,30000,42000,30000"
     2794xt "32750,30000,36000,30000"
    28152795pts [
    2816 "42000,30000"
    2817 "40000,30000"
    2818 "38750,30000"
     2796"36000,30000"
     2797"32750,30000"
    28192798]
    28202799)
    … …  
    28362815isHidden 1
    28372816)
    2838 xt "45000,29000,49800,30000"
     2817xt "39000,29000,43800,30000"
    28392818st "config_start"
    2840 blo "45000,29800"
     2819blo "39000,29800"
    28412820tm "WireNameMgr"
    28422821)
    … …  
    28512830vasetType 3
    28522831)
    2853 xt "38750,27000,42000,27000"
     2832xt "32750,27000,36000,27000"
    28542833pts [
    2855 "42000,27000"
    2856 "40000,27000"
    2857 "38750,27000"
     2834"36000,27000"
     2835"32750,27000"
    28582836]
    28592837)
    … …  
    28752853isHidden 1
    28762854)
    2877 xt "45000,26000,50300,27000"
     2855xt "39000,26000,44300,27000"
    28782856st "config_wr_en"
    2879 blo "45000,26800"
     2857blo "39000,26800"
    28802858tm "WireNameMgr"
    28812859)
    … …  
    28912869lineWidth 2
    28922870)
    2893 xt "9000,25000,34000,64000"
     2871xt "3000,39000,52000,56000"
    28942872pts [
    2895 "12250,25000"
    2896 "9000,25000"
    2897 "9000,64000"
    2898 "34000,64000"
    2899 "34000,51000"
    2900 "30750,51000"
     2873"6250,39000"
     2874"3000,39000"
     2875"3000,56000"
     2876"52000,56000"
     2877"52000,44000"
     2878"50750,44000"
    29012879]
    29022880)
    … …  
    29172895va (VaSet
    29182896)
    2919 xt "20000,63000,28300,64000"
     2897xt "33000,55000,41300,56000"
    29202898st "ram_data_out : (15:0)"
    2921 blo "20000,63800"
     2899blo "33000,55800"
    29222900tm "WireNameMgr"
    29232901)
    … …  
    29322910vasetType 3
    29332911)
    2934 xt "38750,34000,42000,34000"
     2912xt "32750,34000,36000,34000"
    29352913pts [
    2936 "38750,34000"
    2937 "40000,34000"
    2938 "42000,34000"
     2914"32750,34000"
     2915"36000,34000"
    29392916]
    29402917)
    … …  
    29562933isHidden 1
    29572934)
    2958 xt "45000,33000,48700,34000"
     2935xt "39000,33000,42700,34000"
    29592936st "dac_array"
    2960 blo "45000,33800"
     2937blo "39000,33800"
    29612938tm "WireNameMgr"
    29622939)
    … …  
    29712948vasetType 3
    29722949)
    2973 xt "38750,28000,42000,28000"
     2950xt "32750,28000,36000,28000"
    29742951pts [
    2975 "42000,28000"
    2976 "40000,28000"
    2977 "38750,28000"
     2952"36000,28000"
     2953"32750,28000"
    29782954]
    29792955)
    … …  
    29952971isHidden 1
    29962972)
    2997 xt "45000,27000,50200,28000"
     2973xt "39000,27000,44200,28000"
    29982974st "config_rd_en"
    2999 blo "45000,27800"
     2975blo "39000,27800"
    30002976tm "WireNameMgr"
    30012977)
    … …  
    30102986vasetType 3
    30112987)
    3012 xt "38750,29000,42000,29000"
     2988xt "32750,29000,36000,29000"
    30132989pts [
    3014 "38750,29000"
    3015 "40000,29000"
    3016 "42000,29000"
     2990"32750,29000"
     2991"36000,29000"
    30172992]
    30182993)
    … …  
    30343009isHidden 1
    30353010)
    3036 xt "45000,28000,50100,29000"
     3011xt "39000,28000,44100,29000"
    30373012st "config_ready"
    3038 blo "45000,28800"
     3013blo "39000,28800"
    30393014tm "WireNameMgr"
    30403015)
    … …  
    30493024vasetType 3
    30503025)
    3051 xt "38750,31000,42000,31000"
     3026xt "32750,31000,36000,31000"
    30523027pts [
    3053 "38750,31000"
    3054 "42000,31000"
     3028"32750,31000"
     3029"36000,31000"
    30553030]
    30563031)
    … …  
    30723047isHidden 1
    30733048)
    3074 xt "40000,30000,45600,31000"
     3049xt "34000,30000,39600,31000"
    30753050st "config_started"
    3076 blo "40000,30800"
     3051blo "34000,30800"
    30773052tm "WireNameMgr"
    30783053)
    … …  
    31013076font "arial,8,1"
    31023077)
    3103 xt "0,0,5400,1000"
     3078xt "1000,1000,6400,2000"
    31043079st "Package List"
    3105 blo "0,800"
     3080blo "1000,1800"
    31063081)
    31073082*88 (MLText
    … …  
    31093084va (VaSet
    31103085)
    3111 xt "0,1000,15300,6000"
     3086xt "1000,2000,16300,7000"
    31123087st "LIBRARY ieee;
    31133088USE ieee.std_logic_1164.ALL;
    … …  
    31923167associable 1
    31933168)
    3194 windowSize "0,22,1286,1024"
    3195 viewArea "834,16774,54098,59806"
    3196 cachedDiagramExtent "0,0,53000,77000"
     3169windowSize "0,0,1281,1002"
     3170viewArea "-6400,12035,60443,65774"
     3171cachedDiagramExtent "700,0,59000,77000"
    31973172pageSetupInfo (PageSetupInfo
    31983173ptrCmd "Brother HL-5270DN series,winspool,"
    … …  
    32203195hasePageBreakOrigin 1
    32213196pageBreakOrigin "0,0"
    3222 lastUid 1122,0
     3197lastUid 1172,0
    32233198defaultCommentText (CommentText
    32243199shape (Rectangle
    … …  
    41674142font "Arial,8,1"
    41684143)
    4169 xt "20000,0,25400,1000"
     4144xt "27000,200,32400,1200"
    41704145st "Declarations"
    4171 blo "20000,800"
     4146blo "27000,1000"
    41724147)
    41734148portLabel (Text
    … …  
    41764151font "Arial,8,1"
    41774152)
    4178 xt "20000,1000,22700,2000"
     4153xt "27000,1200,29700,2200"
    41794154st "Ports:"
    4180 blo "20000,1800"
     4155blo "27000,2000"
    41814156)
    41824157preUserLabel (Text
    … …  
    41864161font "Arial,8,1"
    41874162)
    4188 xt "20000,0,23800,1000"
     4163xt "27000,200,30800,1200"
    41894164st "Pre User:"
    4190 blo "20000,800"
     4165blo "27000,1000"
    41914166)
    41924167preUserText (MLText
    … …  
    41964171font "Courier New,8,0"
    41974172)
    4198 xt "20000,0,20000,0"
     4173xt "27000,200,27000,200"
    41994174tm "BdDeclarativeTextMgr"
    42004175)
    … …  
    42044179font "Arial,8,1"
    42054180)
    4206 xt "20000,11600,27100,12600"
     4181xt "27000,11800,34100,12800"
    42074182st "Diagram Signals:"
    4208 blo "20000,12400"
     4183blo "27000,12600"
    42094184)
    42104185postUserLabel (Text
    … …  
    42144189font "Arial,8,1"
    42154190)
    4216 xt "20000,0,24700,1000"
     4191xt "27000,200,31700,1200"
    42174192st "Post User:"
    4218 blo "20000,800"
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  • FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb

    r246 r252  
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    … …  
    561598(vvPair
    562599variable "HDLDir"
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     600value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl"
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     604value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    568605)
    569606(vvPair
    570607variable "SideDataDesignDir"
    571 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
     608value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"
    572609)
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    575 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
     612value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"
    576613)
    577614(vvPair
    578615variable "SourceDir"
    579 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"
     616value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds"
    580617)
    581618(vvPair
    … …  
    593630(vvPair
    594631variable "d"
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     632value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    596633)
    597634(vvPair
    598635variable "d_logical"
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     636value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"
    600637)
    601638(vvPair
    602639variable "date"
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     640value "12.07.2010"
    604641)
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     644value "Mo"
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    609646(vvPair
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    611 value "Donnerstag"
     648value "Montag"
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    613650(vvPair
    614651variable "dd"
    615 value "27"
     652value "12"
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    617654(vvPair
    … …  
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     680value "TU-CC4900F8C7D2"
    644681)
    645682(vvPair
    … …  
    669706(vvPair
    670707variable "mm"
    671 value "05"
     708value "07"
    672709)
    673710(vvPair
    … …  
    677714(vvPair
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    679 value "Mai"
     716value "Jul"
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    681718(vvPair
    682719variable "month_long"
    683 value "Mai"
     720value "Juli"
    684721)
    685722(vvPair
    686723variable "p"
    687 value "D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
     724value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
    688725)
    689726(vvPair
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     728value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"
    692729)
    693730(vvPair
    … …  
    713750(vvPair
    714751variable "task_ModelSimPath"
    715 value "D:\\modeltech_6.5e\\win32"
     752value "<TBD>"
    716753)
    717754(vvPair
    … …  
    745782(vvPair
    746783variable "time"
    747 value "10:24:05"
     784value "14:13:34"
    748785)
    749786(vvPair
    … …  
    753790(vvPair
    754791variable "user"
    755 value "daqct3"
     792value "dneise"
    756793)
    757794(vvPair
    758795variable "version"
    759 value "2009.1 (Build 12)"
     796value "2009.2 (Build 10)"
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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