Changeset 252 for FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib
- Timestamp:
- 07/16/10 16:25:44 (14 years ago)
- Location:
- FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib
- Files:
-
- 20 edited
-
hdl/control_manager_beha.vhd (modified) (6 diffs)
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hdl/control_unit_struct.vhd (modified) (5 diffs)
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hdl/fad_board.ucf (modified) (2 diffs)
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hdl/fad_board_struct.vhd (modified) (9 diffs)
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hdl/fad_definitions.vhd (modified) (1 diff)
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hdl/fad_definitions.vhd.bak (modified) (3 diffs)
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hdl/fad_main_struct.vhd (modified) (7 diffs)
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hds/.cache.dat (modified) ( previous)
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hds/.xrf/control_unit_struct.xrf (modified) (1 diff)
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hds/.xrf/fad_board_struct.xrf (modified) (4 diffs)
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hds/.xrf/fad_main_struct.xrf (modified) (2 diffs)
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hds/@f@a@d_@board/struct.bd (modified) (368 diffs)
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hds/@f@a@d_@board/struct.bd.bak (modified) (338 diffs)
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hds/@f@a@d_@board/symbol.sb (modified) (64 diffs)
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hds/@f@a@d_main/struct.bd (modified) (399 diffs)
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hds/@f@a@d_main/struct.bd.bak (modified) (9 diffs)
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hds/control_manager/symbol.sb (modified) (87 diffs)
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hds/control_unit/struct.bd (modified) (230 diffs)
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hds/control_unit/struct.bd.bak (modified) (159 diffs)
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hds/control_unit/symbol.sb (modified) (87 diffs)
Legend:
- Unmodified
- Added
- Removed
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FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_manager_beha.vhd
r246 r252 36 36 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 37 37 dac_array : OUT dac_array_type; 38 roi_array : OUT roi_array_type 38 roi_array : OUT roi_array_type; 39 drs_address : OUT std_logic_vector (3 DOWNTO 0); 40 drs_address_mode : OUT std_logic 39 41 ); 40 42 … … 53 55 signal int_dac_array : dac_array_type := DEFAULT_DAC; 54 56 signal int_roi_array : roi_array_type := DEFAULT_ROI; 57 signal int_drs_address: std_logic_vector (3 DOWNTO 0) := DEFAULT_DRSADDR; 58 signal int_drs_address_mode: std_logic := DEFAULT_DRSADDR_MODE; 55 59 56 60 BEGIN … … 66 70 67 71 when CTRL_INIT => 72 -- WRITES DEFAULT VALUES IN config ram 68 73 addr_cntr <= addr_cntr + 1; 69 74 ram_addr <= conv_std_logic_vector(addr_cntr, ADDR_WIDTH); … … 76 81 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then 77 82 ram_data_in <= conv_std_logic_vector(int_dac_array(addr_cntr - NO_OF_ROI), 16); 83 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then 84 ram_data_in <= "0000" & "0000" 85 & "000" & conv_std_logic_vector(int_drs_address_mode, 1) 86 & int_drs_address; 78 87 else 79 88 ram_write_en <= "0"; … … 82 91 83 92 when CTRL_IDLE => 93 -- 84 94 addr_cntr <= 0; 85 95 ram_write_en <= "0"; … … 119 129 dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); 120 130 ctrl_state <= CTRL_LOAD_ADDR; 121 else 131 elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC + 1) then 132 drs_address <= ram_data_out(3 downto 0); 133 drs_address_mode <= ram_data_out(4); 134 ctrl_state <= CTRL_LOAD_ADDR; 135 else 122 136 addr_cntr <= 0; 123 137 config_started <= '0'; -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/control_unit_struct.vhd
r246 r252 2 2 -- 3 3 -- Created: 4 -- by - Benjamin Krumm.UNKNOWN (EEPC8)5 -- at - 1 2:04:03 23.06.20104 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 5 -- at - 14:46:37 12.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 25 25 config_started : OUT std_logic := '0'; 26 26 dac_array : OUT dac_array_type; 27 drs_address : OUT std_logic_vector (3 DOWNTO 0); 28 drs_address_mode : OUT std_logic; 27 29 roi_array : OUT roi_array_type; 28 30 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 37 39 -- 38 40 -- Created: 39 -- by - Benjamin Krumm.UNKNOWN (EEPC8)40 -- at - 1 2:04:03 23.06.201041 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 42 -- at - 14:46:37 12.07.2010 41 43 -- 42 44 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 93 95 ram_write_en : OUT std_logic_vector (0 DOWNTO 0); 94 96 dac_array : OUT dac_array_type ; 95 roi_array : OUT roi_array_type 97 roi_array : OUT roi_array_type ; 98 drs_address : OUT std_logic_vector (3 DOWNTO 0); 99 drs_address_mode : OUT std_logic 96 100 ); 97 101 END COMPONENT; … … 137 141 ram_write_en => ram_wren, 138 142 dac_array => dac_array, 139 roi_array => roi_array 143 roi_array => roi_array, 144 drs_address => drs_address, 145 drs_address_mode => drs_address_mode 140 146 ); 141 147 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board.ucf
r246 r252 10 10 11 11 #Test Trigger input on 'Testpoint near W5300' 12 #NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok13 NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33 | PULLUP;12 #NET _TW<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok 13 NET TEST_TRG LOC = R19 | IOSTANDARD=LVCMOS33; 14 14 15 15 … … 229 229 NET A1_T<2> LOC = AC12 | IOSTANDARD=LVCMOS33; #ok 230 230 NET A1_T<3> LOC = AC14 | IOSTANDARD=LVCMOS33; #ok 231 #NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok231 NET A1_T<4> LOC = AC15 | IOSTANDARD=LVCMOS33; #ok 232 232 #NET A1_T<5> LOC = AB16 | IOSTANDARD=LVCMOS33; #ok 233 233 #NET A1_T<6> LOC = AC16 | IOSTANDARD=LVCMOS33; #ok -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd
r246 r252 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 2:42:19 02.07.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 15:25:14 14.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 27 27 W_INT : IN std_logic; 28 28 X_50M : IN STD_LOGIC; 29 A1_T : OUT std_logic_vector ( 3 DOWNTO 0);29 A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 30 30 A_CLK : OUT std_logic_vector (3 DOWNTO 0); 31 31 D0_SRCLK : OUT STD_LOGIC; … … 72 72 -- 73 73 -- Created: 74 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)75 -- at - 1 2:42:20 02.07.201074 -- by - dneise.UNKNOWN (E5B-LABOR6) 75 -- at - 15:25:14 14.07.2010 76 76 -- 77 77 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 95 95 SIGNAL CLK_25_PS : std_logic; 96 96 SIGNAL CLK_50 : std_logic; 97 SIGNAL SRCLK : std_logic := '0';97 SIGNAL SRCLK : std_logic := '0'; 98 98 SIGNAL TRG_OR : std_logic; 99 99 SIGNAL adc_data_array : adc_data_array_type; 100 100 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 101 101 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 102 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 102 103 SIGNAL dummy : std_logic; 103 SIGNAL not_TEST_TRG : STD_LOGIC;104 104 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 105 SIGNAL trigger_out : STD_LOGIC := '0';106 107 -- Implicit buffer signal declarations108 SIGNAL RSRLOAD_internal : std_logic;109 105 110 106 … … 148 144 ); 149 145 END COMPONENT; 150 COMPONENT debouncer151 GENERIC (152 WIDTH : INTEGER := 17153 );154 PORT (155 clk : IN STD_LOGIC ;156 -- rst : in STD_LOGIC;157 trigger_in : IN STD_LOGIC ;158 trigger_out : OUT STD_LOGIC := '0'159 );160 END COMPONENT;161 146 162 147 -- Optional embedded configurations 163 148 -- pragma synthesis_off 164 149 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main; 165 FOR ALL : debouncer USE ENTITY FACT_FAD_lib.debouncer;166 150 -- pragma synthesis_on 167 151 … … 228 212 -- HDL Embedded Text Block 8 eb2 229 213 -- eb2 8 230 A1_T(0) <= dummy; 231 A1_T(1) <= RSRLOAD_internal; 232 A1_T(2) <= D0_SROUT; 233 A1_T(3) <= D1_SROUT; 214 A1_T(3 downto 0) <= drs_channel_id; 215 D_A <= drs_channel_id; 216 A1_T(4) <= TRG_OR; 234 217 235 218 … … 237 220 DAC_CS <= dummy; 238 221 239 -- ModuleWare code(v1.9) for instance 'I1' of 'inv'240 not_TEST_TRG <= NOT(TEST_TRG);241 242 222 -- ModuleWare code(v1.9) for instance 'I2' of 'or' 243 TRG_OR <= TRG OR trigger_out;223 TRG_OR <= TRG OR TEST_TRG; 244 224 245 225 -- Instance port mappings. … … 262 242 CLK_25_PS => CLK_25_PS, 263 243 CLK_50 => CLK_50, 264 RSRLOAD => RSRLOAD _internal,244 RSRLOAD => RSRLOAD, 265 245 SRCLK => SRCLK, 266 246 adc_oeb => OE_ADC, 267 247 dac_cs => dummy, 268 248 denable => DENABLE, 269 drs_channel_id => D_A,249 drs_channel_id => drs_channel_id, 270 250 drs_dwrite => DWRITE, 271 251 led => D_T, … … 281 261 wiz_data => W_D 282 262 ); 283 I_debouncer : debouncer284 GENERIC MAP (285 WIDTH => 17286 )287 PORT MAP (288 clk => CLK_50,289 trigger_in => not_TEST_TRG,290 trigger_out => trigger_out291 );292 293 -- Implicit buffered output assignments294 RSRLOAD <= RSRLOAD_internal;295 263 296 264 END struct; -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd
r246 r252 104 104 constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); 105 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= "0000"; 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 110 106 111 107 112 -- Commands -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_definitions.vhd.bak
r246 r252 51 51 constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14"; 52 52 constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18"; 53 constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C"; 54 constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E"; 53 55 constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20"; 54 56 constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22"; … … 80 82 81 83 constant LOG2_OF_RAM_SIZE_64B : integer := 15; 82 constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; 84 --constant RAM_SIZE_64B : integer := 2**LOG2_OF_RAM_SIZE_64B; 85 constant RAM_SIZE_64B : integer := 24576; 83 86 constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4; 84 87 … … 101 104 constant DEFAULT_DAC : dac_array_type := (20972, 34079, 20526, 0, 28836, 28836, 28836, 28836); 102 105 --constant DEFAULT_DAC : dac_array_type := (others => 0); 106 107 constant DEFAULT_DRSADDR : std_logic_vector (3 downto 0):= X"0"; 108 constant DEFAULT_DRSADDR_MODE : std_logic := '0'; 109 110 103 111 104 112 -- Commands -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd
r246 r252 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 5 -- at - 1 2:42:19 02.07.20105 -- at - 14:46:38 12.07.2010 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 60 60 -- Created: 61 61 -- by - dneise.UNKNOWN (TU-CC4900F8C7D2) 62 -- at - 1 2:42:19 02.07.201062 -- at - 14:46:38 12.07.2010 63 63 -- 64 64 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 106 106 SIGNAL dac_array : dac_array_type; 107 107 SIGNAL data_out : std_logic_vector(63 DOWNTO 0); 108 SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0'); 109 SIGNAL drs_address_mode : std_logic; 110 SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0'); 108 111 SIGNAL drs_clk_en : std_logic := '0'; 109 112 SIGNAL drs_read_s_cell : std_logic := '0'; … … 170 173 config_started : OUT std_logic := '0'; 171 174 dac_array : OUT dac_array_type ; 175 drs_address : OUT std_logic_vector (3 DOWNTO 0); 176 drs_address_mode : OUT std_logic ; 172 177 roi_array : OUT roi_array_type ; 173 178 config_data : INOUT std_logic_vector (15 DOWNTO 0) … … 351 356 drs_dwrite <= dwrite AND dwrite_enable; 352 357 358 -- ModuleWare code(v1.9) for instance 'U_0' of 'mux' 359 u_0combo_proc: PROCESS(drs_channel_internal, drs_address, 360 drs_address_mode) 361 BEGIN 362 CASE drs_address_mode IS 363 WHEN '0' => drs_channel_id <= drs_channel_internal; 364 WHEN '1' => drs_channel_id <= drs_address; 365 WHEN OTHERS => drs_channel_id <= (OTHERS => 'X'); 366 END CASE; 367 END PROCESS u_0combo_proc; 368 353 369 -- Instance port mappings. 354 370 I_main_adc_buffer : adc_buffer … … 379 395 config_started => config_started_cu, 380 396 dac_array => dac_array, 397 drs_address => drs_address, 398 drs_address_mode => drs_address_mode, 381 399 roi_array => roi_array, 382 400 config_data => config_data … … 429 447 adc_oeb => adc_oeb, 430 448 adc_otr => adc_otr, 431 drs_channel_id => drs_channel_i d,449 drs_channel_id => drs_channel_internal, 432 450 drs_dwrite => dwrite, 433 451 drs_clk_en => drs_clk_en, -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/control_unit_struct.xrf
r246 r252 37 37 DESIGN control_unit 38 38 VIEW symbol.sb 39 GRAPHIC 155,0 26 0 40 DESIGN control_unit 41 VIEW symbol.sb 42 GRAPHIC 150,0 27 0 43 DESIGN control_unit 44 VIEW symbol.sb 45 GRAPHIC 1,0 30 0 46 DESIGN control_unit 47 VIEW symbol.sb 48 GRAPHIC 1,0 31 0 49 DESIGN control_unit 50 VIEW struct.bd 51 NO_GRAPHIC 34 52 DESIGN control_unit 53 VIEW struct.bd 54 GRAPHIC 41,0 43 0 55 DESIGN control_unit 56 VIEW struct.bd 57 NO_GRAPHIC 48 58 DESIGN control_unit 59 VIEW struct.bd 60 GRAPHIC 0,0 51 2 61 DESIGN control_unit 62 VIEW struct.bd 63 GRAPHIC 345,0 56 0 64 DESIGN control_unit 65 VIEW struct.bd 66 GRAPHIC 333,0 57 0 67 DESIGN control_unit 68 VIEW struct.bd 69 GRAPHIC 349,0 58 0 70 DESIGN control_unit 71 VIEW struct.bd 72 GRAPHIC 329,0 59 0 73 DESIGN control_unit 74 VIEW struct.bd 75 NO_GRAPHIC 60 76 DESIGN control_unit 77 VIEW struct.bd 78 NO_GRAPHIC 61 39 GRAPHIC 521,0 26 0 40 DESIGN control_unit 41 VIEW symbol.sb 42 GRAPHIC 526,0 27 0 43 DESIGN control_unit 44 VIEW symbol.sb 45 GRAPHIC 155,0 28 0 46 DESIGN control_unit 47 VIEW symbol.sb 48 GRAPHIC 150,0 29 0 49 DESIGN control_unit 50 VIEW symbol.sb 51 GRAPHIC 1,0 32 0 52 DESIGN control_unit 53 VIEW symbol.sb 54 GRAPHIC 1,0 33 0 55 DESIGN control_unit 56 VIEW struct.bd 57 NO_GRAPHIC 36 58 DESIGN control_unit 59 VIEW struct.bd 60 GRAPHIC 41,0 45 0 61 DESIGN control_unit 62 VIEW struct.bd 63 NO_GRAPHIC 50 64 DESIGN control_unit 65 VIEW struct.bd 66 GRAPHIC 0,0 53 2 67 DESIGN control_unit 68 VIEW struct.bd 69 GRAPHIC 345,0 58 0 70 DESIGN control_unit 71 VIEW struct.bd 72 GRAPHIC 333,0 59 0 73 DESIGN control_unit 74 VIEW struct.bd 75 GRAPHIC 349,0 60 0 76 DESIGN control_unit 77 VIEW struct.bd 78 GRAPHIC 329,0 61 0 79 DESIGN control_unit 80 VIEW struct.bd 81 NO_GRAPHIC 62 82 DESIGN control_unit 83 VIEW struct.bd 84 NO_GRAPHIC 63 79 85 LIBRARY FACT_FAD_lib 80 86 DESIGN control@r@a@m_16bit_x256 81 87 VIEW control@r@a@m_16bit_x256_a 82 GRAPHIC 993,0 63 0 83 DESIGN control@r@a@m_16bit_x256 84 VIEW control@r@a@m_16bit_x256_a 85 GRAPHIC 48,0 65 0 86 DESIGN control@r@a@m_16bit_x256 87 VIEW control@r@a@m_16bit_x256_a 88 GRAPHIC 53,0 66 0 89 DESIGN control@r@a@m_16bit_x256 90 VIEW control@r@a@m_16bit_x256_a 91 GRAPHIC 58,0 67 0 92 DESIGN control@r@a@m_16bit_x256 93 VIEW control@r@a@m_16bit_x256_a 94 GRAPHIC 63,0 68 0 95 DESIGN control@r@a@m_16bit_x256 96 VIEW control@r@a@m_16bit_x256_a 97 GRAPHIC 68,0 69 0 98 DESIGN control_unit 99 VIEW struct.bd 100 GRAPHIC 960,0 72 0 101 DESIGN control_manager 102 VIEW symbol.sb 103 GRAPHIC 14,0 73 1 104 DESIGN control_manager 105 VIEW beha 106 GRAPHIC 48,0 79 0 107 DESIGN control_manager 108 VIEW beha 109 GRAPHIC 310,0 80 0 110 DESIGN control_manager 111 VIEW beha 112 GRAPHIC 58,0 81 0 113 DESIGN control_manager 114 VIEW beha 115 GRAPHIC 492,0 82 0 116 DESIGN control_manager 117 VIEW beha 118 GRAPHIC 63,0 83 0 119 DESIGN control_manager 120 VIEW beha 121 GRAPHIC 68,0 84 0 122 DESIGN control_manager 123 VIEW beha 124 GRAPHIC 73,0 85 0 125 DESIGN control_manager 126 VIEW beha 127 GRAPHIC 78,0 86 0 128 DESIGN control_manager 129 VIEW beha 130 GRAPHIC 83,0 87 0 131 DESIGN control_manager 132 VIEW beha 133 GRAPHIC 88,0 88 0 134 DESIGN control_manager 135 VIEW beha 136 GRAPHIC 93,0 89 0 137 DESIGN control_manager 138 VIEW beha 139 GRAPHIC 346,0 90 0 140 DESIGN control_manager 141 VIEW beha 142 GRAPHIC 263,0 91 0 143 DESIGN control_manager 144 VIEW beha 145 GRAPHIC 268,0 92 0 146 DESIGN control_manager 147 VIEW beha 148 GRAPHIC 118,0 93 0 149 DESIGN control_manager 150 VIEW beha 151 GRAPHIC 123,0 94 0 88 GRAPHIC 993,0 65 0 89 DESIGN control@r@a@m_16bit_x256 90 VIEW control@r@a@m_16bit_x256_a 91 GRAPHIC 48,0 67 0 92 DESIGN control@r@a@m_16bit_x256 93 VIEW control@r@a@m_16bit_x256_a 94 GRAPHIC 53,0 68 0 95 DESIGN control@r@a@m_16bit_x256 96 VIEW control@r@a@m_16bit_x256_a 97 GRAPHIC 58,0 69 0 98 DESIGN control@r@a@m_16bit_x256 99 VIEW control@r@a@m_16bit_x256_a 100 GRAPHIC 63,0 70 0 101 DESIGN control@r@a@m_16bit_x256 102 VIEW control@r@a@m_16bit_x256_a 103 GRAPHIC 68,0 71 0 104 DESIGN control_unit 105 VIEW struct.bd 106 GRAPHIC 960,0 74 0 107 DESIGN control_manager 108 VIEW symbol.sb 109 GRAPHIC 14,0 75 1 110 DESIGN control_manager 111 VIEW beha 112 GRAPHIC 48,0 81 0 113 DESIGN control_manager 114 VIEW beha 115 GRAPHIC 310,0 82 0 116 DESIGN control_manager 117 VIEW beha 118 GRAPHIC 58,0 83 0 119 DESIGN control_manager 120 VIEW beha 121 GRAPHIC 492,0 84 0 122 DESIGN control_manager 123 VIEW beha 124 GRAPHIC 63,0 85 0 125 DESIGN control_manager 126 VIEW beha 127 GRAPHIC 68,0 86 0 128 DESIGN control_manager 129 VIEW beha 130 GRAPHIC 73,0 87 0 131 DESIGN control_manager 132 VIEW beha 133 GRAPHIC 78,0 88 0 134 DESIGN control_manager 135 VIEW beha 136 GRAPHIC 83,0 89 0 137 DESIGN control_manager 138 VIEW beha 139 GRAPHIC 88,0 90 0 140 DESIGN control_manager 141 VIEW beha 142 GRAPHIC 93,0 91 0 143 DESIGN control_manager 144 VIEW beha 145 GRAPHIC 346,0 92 0 146 DESIGN control_manager 147 VIEW beha 148 GRAPHIC 263,0 93 0 149 DESIGN control_manager 150 VIEW beha 151 GRAPHIC 268,0 94 0 152 DESIGN control_manager 153 VIEW beha 154 GRAPHIC 118,0 95 0 155 DESIGN control_manager 156 VIEW beha 157 GRAPHIC 123,0 96 0 158 DESIGN control_manager 159 VIEW beha 160 GRAPHIC 528,0 97 0 161 DESIGN control_manager 162 VIEW beha 163 GRAPHIC 533,0 98 0 152 164 LIBRARY FACT_FAD_lib 153 165 DESIGN control_unit 154 166 VIEW struct.bd 155 NO_GRAPHIC 97 156 DESIGN control_unit 157 VIEW struct.bd 158 GRAPHIC 993,0 100 0 159 DESIGN control_unit 160 VIEW struct.bd 161 GRAPHIC 960,0 101 0 162 DESIGN control_unit 163 VIEW struct.bd 164 NO_GRAPHIC 104 165 DESIGN control_unit 166 VIEW struct.bd 167 NO_GRAPHIC 106 168 DESIGN control_unit 169 VIEW struct.bd 170 GRAPHIC 993,0 108 0 171 DESIGN control_unit 172 VIEW struct.bd 173 GRAPHIC 279,0 110 0 174 DESIGN control_unit 175 VIEW struct.bd 176 GRAPHIC 237,0 111 0 177 DESIGN control_unit 178 VIEW struct.bd 179 GRAPHIC 285,0 112 0 180 DESIGN control_unit 181 VIEW struct.bd 182 GRAPHIC 233,0 113 0 183 DESIGN control_unit 184 VIEW struct.bd 185 GRAPHIC 301,0 114 0 186 DESIGN control_unit 187 VIEW struct.bd 188 GRAPHIC 960,0 116 0 189 DESIGN control_unit 190 VIEW struct.bd 191 GRAPHIC 967,0 117 1 192 DESIGN control_unit 193 VIEW struct.bd 194 GRAPHIC 241,0 123 0 195 DESIGN control_unit 196 VIEW struct.bd 197 GRAPHIC 301,0 124 0 198 DESIGN control_unit 199 VIEW struct.bd 200 GRAPHIC 321,0 125 0 201 DESIGN control_unit 202 VIEW struct.bd 203 GRAPHIC 1084,0 126 0 204 DESIGN control_unit 205 VIEW struct.bd 206 GRAPHIC 289,0 127 0 207 DESIGN control_unit 208 VIEW struct.bd 209 GRAPHIC 267,0 128 0 210 DESIGN control_unit 211 VIEW struct.bd 212 GRAPHIC 227,0 129 0 213 DESIGN control_unit 214 VIEW struct.bd 215 GRAPHIC 295,0 130 0 216 DESIGN control_unit 217 VIEW struct.bd 218 GRAPHIC 311,0 131 0 219 DESIGN control_unit 220 VIEW struct.bd 221 GRAPHIC 255,0 132 0 222 DESIGN control_unit 223 VIEW struct.bd 224 GRAPHIC 261,0 133 0 225 DESIGN control_unit 226 VIEW struct.bd 227 GRAPHIC 285,0 134 0 228 DESIGN control_unit 229 VIEW struct.bd 230 GRAPHIC 237,0 135 0 231 DESIGN control_unit 232 VIEW struct.bd 233 GRAPHIC 233,0 136 0 234 DESIGN control_unit 235 VIEW struct.bd 236 GRAPHIC 305,0 137 0 237 DESIGN control_unit 238 VIEW struct.bd 239 GRAPHIC 273,0 138 0 240 DESIGN control_unit 241 VIEW struct.bd 242 NO_GRAPHIC 141 167 NO_GRAPHIC 101 168 DESIGN control_unit 169 VIEW struct.bd 170 GRAPHIC 993,0 104 0 171 DESIGN control_unit 172 VIEW struct.bd 173 GRAPHIC 960,0 105 0 174 DESIGN control_unit 175 VIEW struct.bd 176 NO_GRAPHIC 108 177 DESIGN control_unit 178 VIEW struct.bd 179 NO_GRAPHIC 110 180 DESIGN control_unit 181 VIEW struct.bd 182 GRAPHIC 993,0 112 0 183 DESIGN control_unit 184 VIEW struct.bd 185 GRAPHIC 279,0 114 0 186 DESIGN control_unit 187 VIEW struct.bd 188 GRAPHIC 237,0 115 0 189 DESIGN control_unit 190 VIEW struct.bd 191 GRAPHIC 285,0 116 0 192 DESIGN control_unit 193 VIEW struct.bd 194 GRAPHIC 233,0 117 0 195 DESIGN control_unit 196 VIEW struct.bd 197 GRAPHIC 301,0 118 0 198 DESIGN control_unit 199 VIEW struct.bd 200 GRAPHIC 960,0 120 0 201 DESIGN control_unit 202 VIEW struct.bd 203 GRAPHIC 967,0 121 1 204 DESIGN control_unit 205 VIEW struct.bd 206 GRAPHIC 241,0 127 0 207 DESIGN control_unit 208 VIEW struct.bd 209 GRAPHIC 301,0 128 0 210 DESIGN control_unit 211 VIEW struct.bd 212 GRAPHIC 321,0 129 0 213 DESIGN control_unit 214 VIEW struct.bd 215 GRAPHIC 1084,0 130 0 216 DESIGN control_unit 217 VIEW struct.bd 218 GRAPHIC 289,0 131 0 219 DESIGN control_unit 220 VIEW struct.bd 221 GRAPHIC 267,0 132 0 222 DESIGN control_unit 223 VIEW struct.bd 224 GRAPHIC 227,0 133 0 225 DESIGN control_unit 226 VIEW struct.bd 227 GRAPHIC 295,0 134 0 228 DESIGN control_unit 229 VIEW struct.bd 230 GRAPHIC 311,0 135 0 231 DESIGN control_unit 232 VIEW struct.bd 233 GRAPHIC 255,0 136 0 234 DESIGN control_unit 235 VIEW struct.bd 236 GRAPHIC 261,0 137 0 237 DESIGN control_unit 238 VIEW struct.bd 239 GRAPHIC 285,0 138 0 240 DESIGN control_unit 241 VIEW struct.bd 242 GRAPHIC 237,0 139 0 243 DESIGN control_unit 244 VIEW struct.bd 245 GRAPHIC 233,0 140 0 246 DESIGN control_unit 247 VIEW struct.bd 248 GRAPHIC 305,0 141 0 249 DESIGN control_unit 250 VIEW struct.bd 251 GRAPHIC 273,0 142 0 252 DESIGN control_unit 253 VIEW struct.bd 254 GRAPHIC 1208,0 143 0 255 DESIGN control_unit 256 VIEW struct.bd 257 GRAPHIC 1222,0 144 0 258 DESIGN control_unit 259 VIEW struct.bd 260 NO_GRAPHIC 147 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf
r246 r252 175 175 DESIGN @f@a@d_@board 176 176 VIEW struct.bd 177 GRAPHIC 2267,0 95 0177 GRAPHIC 9500,0 95 0 178 178 DESIGN @f@a@d_@board 179 179 VIEW struct.bd … … 193 193 DESIGN @f@a@d_@board 194 194 VIEW struct.bd 195 GRAPHIC 7485,0 101 0196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 6326,0 102 0195 GRAPHIC 8851,0 101 0 196 DESIGN @f@a@d_@board 197 VIEW struct.bd 198 GRAPHIC 7485,0 102 0 199 199 DESIGN @f@a@d_@board 200 200 VIEW struct.bd … … 202 202 DESIGN @f@a@d_@board 203 203 VIEW struct.bd 204 GRAPHIC 6278,0 104 0 204 NO_GRAPHIC 104 205 205 DESIGN @f@a@d_@board 206 206 VIEW struct.bd 207 207 NO_GRAPHIC 105 208 DESIGN @f@a@d_@board209 VIEW struct.bd210 GRAPHIC 7118,0 107 0211 DESIGN @f@a@d_@board212 VIEW struct.bd213 NO_GRAPHIC 109214 208 LIBRARY FACT_FAD_lib 215 209 DESIGN @f@a@d_main 216 210 VIEW struct 217 GRAPHIC 169,0 111 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 14,0 112 1 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 1755,0 116 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 2710,0 117 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 2715,0 118 0 230 DESIGN @f@a@d_main 231 VIEW symbol.sb 232 GRAPHIC 2720,0 119 0 233 DESIGN @f@a@d_main 234 VIEW symbol.sb 235 GRAPHIC 2725,0 120 0 236 DESIGN @f@a@d_main 237 VIEW symbol.sb 238 GRAPHIC 2282,0 121 0 239 DESIGN @f@a@d_main 240 VIEW symbol.sb 241 GRAPHIC 1976,0 122 0 242 DESIGN @f@a@d_main 243 VIEW symbol.sb 244 GRAPHIC 923,0 123 0 245 DESIGN @f@a@d_main 246 VIEW symbol.sb 247 GRAPHIC 928,0 124 0 248 DESIGN @f@a@d_main 249 VIEW symbol.sb 250 GRAPHIC 464,0 125 0 251 DESIGN @f@a@d_main 252 VIEW symbol.sb 253 GRAPHIC 1062,0 126 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 1389,0 127 0 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 1725,0 128 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 2987,0 129 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 2992,0 130 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 833,0 131 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 3641,0 132 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 4144,0 133 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 2448,0 134 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 2453,0 135 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 163,0 136 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 4067,0 137 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 3631,0 138 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 3646,0 139 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 1037,0 140 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 1047,0 141 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 1057,0 142 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 135,0 143 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 1052,0 144 0 308 DESIGN @f@a@d_main 309 VIEW symbol.sb 310 GRAPHIC 3636,0 145 0 311 DESIGN @f@a@d_main 312 VIEW symbol.sb 313 GRAPHIC 1042,0 146 0 314 DESIGN @f@a@d_@board 315 VIEW struct.bd 316 GRAPHIC 6250,0 149 0 317 DESIGN debouncer 318 VIEW symbol.sb 319 GRAPHIC 14,0 150 1 320 DESIGN debouncer 321 VIEW @behavioral 322 GRAPHIC 48,0 154 0 323 DESIGN debouncer 324 VIEW @behavioral 325 GRAPHIC 53,0 155 0 326 DESIGN debouncer 327 VIEW @behavioral 328 GRAPHIC 58,0 157 0 211 GRAPHIC 169,0 107 0 212 DESIGN @f@a@d_main 213 VIEW symbol.sb 214 GRAPHIC 14,0 108 1 215 DESIGN @f@a@d_main 216 VIEW symbol.sb 217 GRAPHIC 1755,0 112 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 2710,0 113 0 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 2715,0 114 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 2720,0 115 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 2725,0 116 0 230 DESIGN @f@a@d_main 231 VIEW symbol.sb 232 GRAPHIC 2282,0 117 0 233 DESIGN @f@a@d_main 234 VIEW symbol.sb 235 GRAPHIC 1976,0 118 0 236 DESIGN @f@a@d_main 237 VIEW symbol.sb 238 GRAPHIC 923,0 119 0 239 DESIGN @f@a@d_main 240 VIEW symbol.sb 241 GRAPHIC 928,0 120 0 242 DESIGN @f@a@d_main 243 VIEW symbol.sb 244 GRAPHIC 464,0 121 0 245 DESIGN @f@a@d_main 246 VIEW symbol.sb 247 GRAPHIC 1062,0 122 0 248 DESIGN @f@a@d_main 249 VIEW symbol.sb 250 GRAPHIC 1389,0 123 0 251 DESIGN @f@a@d_main 252 VIEW symbol.sb 253 GRAPHIC 1725,0 124 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 2987,0 125 0 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 2992,0 126 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 833,0 127 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 3641,0 128 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 4144,0 129 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 2448,0 130 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 2453,0 131 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 163,0 132 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 4067,0 133 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 3631,0 134 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 3646,0 135 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 1037,0 136 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 1047,0 137 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 1057,0 138 0 296 DESIGN @f@a@d_main 297 VIEW symbol.sb 298 GRAPHIC 135,0 139 0 299 DESIGN @f@a@d_main 300 VIEW symbol.sb 301 GRAPHIC 1052,0 140 0 302 DESIGN @f@a@d_main 303 VIEW symbol.sb 304 GRAPHIC 3636,0 141 0 305 DESIGN @f@a@d_main 306 VIEW symbol.sb 307 GRAPHIC 1042,0 142 0 329 308 LIBRARY FACT_FAD_lib 330 309 DESIGN @f@a@d_@board 331 310 VIEW struct.bd 332 NO_GRAPHIC 160 333 DESIGN @f@a@d_@board 334 VIEW struct.bd 335 GRAPHIC 169,0 163 0 336 DESIGN @f@a@d_@board 337 VIEW struct.bd 338 GRAPHIC 6250,0 164 0 339 DESIGN @f@a@d_@board 340 VIEW struct.bd 341 NO_GRAPHIC 167 342 DESIGN @f@a@d_@board 343 VIEW struct.bd 344 GRAPHIC 265,0 170 0 345 DESIGN @f@a@d_@board 346 VIEW struct.bd 347 NO_GRAPHIC 174 348 DESIGN @f@a@d_@board 349 VIEW struct.bd 350 GRAPHIC 3248,0 175 0 351 DESIGN @f@a@d_@board 352 VIEW struct.bd 353 NO_GRAPHIC 181 354 DESIGN @f@a@d_@board 355 VIEW struct.bd 356 GRAPHIC 3300,0 182 0 357 DESIGN @f@a@d_@board 358 VIEW struct.bd 359 NO_GRAPHIC 188 360 DESIGN @f@a@d_@board 361 VIEW struct.bd 362 GRAPHIC 3394,0 189 0 363 DESIGN @f@a@d_@board 364 VIEW struct.bd 365 NO_GRAPHIC 195 366 DESIGN @f@a@d_@board 367 VIEW struct.bd 368 GRAPHIC 3542,0 196 0 369 DESIGN @f@a@d_@board 370 VIEW struct.bd 371 NO_GRAPHIC 202 372 DESIGN @f@a@d_@board 373 VIEW struct.bd 374 GRAPHIC 3700,0 203 0 311 NO_GRAPHIC 145 312 DESIGN @f@a@d_@board 313 VIEW struct.bd 314 GRAPHIC 169,0 148 0 315 DESIGN @f@a@d_@board 316 VIEW struct.bd 317 NO_GRAPHIC 151 318 DESIGN @f@a@d_@board 319 VIEW struct.bd 320 GRAPHIC 265,0 154 0 321 DESIGN @f@a@d_@board 322 VIEW struct.bd 323 NO_GRAPHIC 158 324 DESIGN @f@a@d_@board 325 VIEW struct.bd 326 GRAPHIC 3248,0 159 0 327 DESIGN @f@a@d_@board 328 VIEW struct.bd 329 NO_GRAPHIC 165 330 DESIGN @f@a@d_@board 331 VIEW struct.bd 332 GRAPHIC 3300,0 166 0 333 DESIGN @f@a@d_@board 334 VIEW struct.bd 335 NO_GRAPHIC 172 336 DESIGN @f@a@d_@board 337 VIEW struct.bd 338 GRAPHIC 3394,0 173 0 339 DESIGN @f@a@d_@board 340 VIEW struct.bd 341 NO_GRAPHIC 179 342 DESIGN @f@a@d_@board 343 VIEW struct.bd 344 GRAPHIC 3542,0 180 0 345 DESIGN @f@a@d_@board 346 VIEW struct.bd 347 NO_GRAPHIC 186 348 DESIGN @f@a@d_@board 349 VIEW struct.bd 350 GRAPHIC 3700,0 187 0 351 DESIGN @f@a@d_@board 352 VIEW struct.bd 353 NO_GRAPHIC 207 354 DESIGN @f@a@d_@board 355 VIEW struct.bd 356 GRAPHIC 6888,0 208 0 357 DESIGN @f@a@d_@board 358 VIEW struct.bd 359 NO_GRAPHIC 210 360 DESIGN @f@a@d_@board 361 VIEW struct.bd 362 GRAPHIC 7092,0 211 0 363 DESIGN @f@a@d_@board 364 VIEW struct.bd 365 NO_GRAPHIC 216 366 DESIGN @f@a@d_@board 367 VIEW struct.bd 368 GRAPHIC 7652,0 217 0 369 DESIGN @f@a@d_@board 370 VIEW struct.bd 371 GRAPHIC 6586,0 220 0 375 372 DESIGN @f@a@d_@board 376 373 VIEW struct.bd … … 378 375 DESIGN @f@a@d_@board 379 376 VIEW struct.bd 380 GRAPHIC 6888,0 224 0 381 DESIGN @f@a@d_@board 382 VIEW struct.bd 383 NO_GRAPHIC 226 384 DESIGN @f@a@d_@board 385 VIEW struct.bd 386 GRAPHIC 7092,0 227 0 387 DESIGN @f@a@d_@board 388 VIEW struct.bd 389 NO_GRAPHIC 233 390 DESIGN @f@a@d_@board 391 VIEW struct.bd 392 GRAPHIC 7652,0 234 0 393 DESIGN @f@a@d_@board 394 VIEW struct.bd 395 GRAPHIC 6539,0 237 0 396 DESIGN @f@a@d_@board 397 VIEW struct.bd 398 GRAPHIC 6586,0 240 0 399 DESIGN @f@a@d_@board 400 VIEW struct.bd 401 NO_GRAPHIC 243 402 DESIGN @f@a@d_@board 403 VIEW struct.bd 404 GRAPHIC 169,0 245 0 405 DESIGN @f@a@d_@board 406 VIEW struct.bd 407 GRAPHIC 176,0 246 1 408 DESIGN @f@a@d_@board 409 VIEW struct.bd 410 GRAPHIC 245,0 250 0 411 DESIGN @f@a@d_@board 412 VIEW struct.bd 413 GRAPHIC 1865,0 251 0 414 DESIGN @f@a@d_@board 415 VIEW struct.bd 416 GRAPHIC 1873,0 252 0 417 DESIGN @f@a@d_@board 418 VIEW struct.bd 419 GRAPHIC 1881,0 253 0 420 DESIGN @f@a@d_@board 421 VIEW struct.bd 422 GRAPHIC 1889,0 254 0 423 DESIGN @f@a@d_@board 424 VIEW struct.bd 425 GRAPHIC 1467,0 255 0 426 DESIGN @f@a@d_@board 427 VIEW struct.bd 428 GRAPHIC 1730,0 256 0 429 DESIGN @f@a@d_@board 430 VIEW struct.bd 431 GRAPHIC 277,0 257 0 432 DESIGN @f@a@d_@board 433 VIEW struct.bd 434 GRAPHIC 285,0 258 0 435 DESIGN @f@a@d_@board 436 VIEW struct.bd 437 GRAPHIC 6130,0 259 0 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 GRAPHIC 450,0 260 0 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 GRAPHIC 3270,0 261 0 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 GRAPHIC 2269,0 262 0 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 GRAPHIC 2409,0 263 0 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 GRAPHIC 2423,0 264 0 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 GRAPHIC 362,0 265 0 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 GRAPHIC 7477,0 266 0 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 GRAPHIC 6431,0 267 0 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 GRAPHIC 1833,0 268 0 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 GRAPHIC 1841,0 269 0 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 GRAPHIC 4942,0 270 0 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 GRAPHIC 3682,0 271 0 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 GRAPHIC 3009,0 272 0 477 DESIGN @f@a@d_@board 478 VIEW struct.bd 479 GRAPHIC 3021,0 273 0 480 DESIGN @f@a@d_@board 481 VIEW struct.bd 482 GRAPHIC 426,0 274 0 483 DESIGN @f@a@d_@board 484 VIEW struct.bd 485 GRAPHIC 434,0 275 0 486 DESIGN @f@a@d_@board 487 VIEW struct.bd 488 GRAPHIC 458,0 276 0 489 DESIGN @f@a@d_@board 490 VIEW struct.bd 491 GRAPHIC 418,0 277 0 492 DESIGN @f@a@d_@board 493 VIEW struct.bd 494 GRAPHIC 466,0 278 0 495 DESIGN @f@a@d_@board 496 VIEW struct.bd 497 GRAPHIC 3015,0 279 0 498 DESIGN @f@a@d_@board 499 VIEW struct.bd 500 GRAPHIC 442,0 280 0 501 DESIGN @f@a@d_@board 502 VIEW struct.bd 503 GRAPHIC 6250,0 282 0 504 DESIGN @f@a@d_@board 505 VIEW struct.bd 506 GRAPHIC 6257,0 283 1 507 DESIGN @f@a@d_@board 508 VIEW struct.bd 509 GRAPHIC 2269,0 287 0 510 DESIGN @f@a@d_@board 511 VIEW struct.bd 512 GRAPHIC 6328,0 288 0 513 DESIGN @f@a@d_@board 514 VIEW struct.bd 515 GRAPHIC 6288,0 289 0 516 DESIGN @f@a@d_@board 517 VIEW struct.bd 518 GRAPHIC 7118,0 293 0 519 DESIGN @f@a@d_@board 520 VIEW struct.bd 521 NO_GRAPHIC 295 377 GRAPHIC 169,0 225 0 378 DESIGN @f@a@d_@board 379 VIEW struct.bd 380 GRAPHIC 176,0 226 1 381 DESIGN @f@a@d_@board 382 VIEW struct.bd 383 GRAPHIC 245,0 230 0 384 DESIGN @f@a@d_@board 385 VIEW struct.bd 386 GRAPHIC 1865,0 231 0 387 DESIGN @f@a@d_@board 388 VIEW struct.bd 389 GRAPHIC 1873,0 232 0 390 DESIGN @f@a@d_@board 391 VIEW struct.bd 392 GRAPHIC 1881,0 233 0 393 DESIGN @f@a@d_@board 394 VIEW struct.bd 395 GRAPHIC 1889,0 234 0 396 DESIGN @f@a@d_@board 397 VIEW struct.bd 398 GRAPHIC 1467,0 235 0 399 DESIGN @f@a@d_@board 400 VIEW struct.bd 401 GRAPHIC 1730,0 236 0 402 DESIGN @f@a@d_@board 403 VIEW struct.bd 404 GRAPHIC 277,0 237 0 405 DESIGN @f@a@d_@board 406 VIEW struct.bd 407 GRAPHIC 285,0 238 0 408 DESIGN @f@a@d_@board 409 VIEW struct.bd 410 GRAPHIC 6130,0 239 0 411 DESIGN @f@a@d_@board 412 VIEW struct.bd 413 GRAPHIC 450,0 240 0 414 DESIGN @f@a@d_@board 415 VIEW struct.bd 416 GRAPHIC 3270,0 241 0 417 DESIGN @f@a@d_@board 418 VIEW struct.bd 419 GRAPHIC 9502,0 242 0 420 DESIGN @f@a@d_@board 421 VIEW struct.bd 422 GRAPHIC 2409,0 243 0 423 DESIGN @f@a@d_@board 424 VIEW struct.bd 425 GRAPHIC 2423,0 244 0 426 DESIGN @f@a@d_@board 427 VIEW struct.bd 428 GRAPHIC 362,0 245 0 429 DESIGN @f@a@d_@board 430 VIEW struct.bd 431 GRAPHIC 7477,0 246 0 432 DESIGN @f@a@d_@board 433 VIEW struct.bd 434 GRAPHIC 6431,0 247 0 435 DESIGN @f@a@d_@board 436 VIEW struct.bd 437 GRAPHIC 8853,0 248 0 438 DESIGN @f@a@d_@board 439 VIEW struct.bd 440 GRAPHIC 1841,0 249 0 441 DESIGN @f@a@d_@board 442 VIEW struct.bd 443 GRAPHIC 4942,0 250 0 444 DESIGN @f@a@d_@board 445 VIEW struct.bd 446 GRAPHIC 3682,0 251 0 447 DESIGN @f@a@d_@board 448 VIEW struct.bd 449 GRAPHIC 3009,0 252 0 450 DESIGN @f@a@d_@board 451 VIEW struct.bd 452 GRAPHIC 3021,0 253 0 453 DESIGN @f@a@d_@board 454 VIEW struct.bd 455 GRAPHIC 426,0 254 0 456 DESIGN @f@a@d_@board 457 VIEW struct.bd 458 GRAPHIC 434,0 255 0 459 DESIGN @f@a@d_@board 460 VIEW struct.bd 461 GRAPHIC 458,0 256 0 462 DESIGN @f@a@d_@board 463 VIEW struct.bd 464 GRAPHIC 418,0 257 0 465 DESIGN @f@a@d_@board 466 VIEW struct.bd 467 GRAPHIC 466,0 258 0 468 DESIGN @f@a@d_@board 469 VIEW struct.bd 470 GRAPHIC 3015,0 259 0 471 DESIGN @f@a@d_@board 472 VIEW struct.bd 473 GRAPHIC 442,0 260 0 474 DESIGN @f@a@d_@board 475 VIEW struct.bd 476 NO_GRAPHIC 263 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf
r246 r252 187 187 DESIGN @f@a@d_main 188 188 VIEW struct.bd 189 GRAPHIC 4399,0 107 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 4417,0 108 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 4741,0 109 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 4405,0 110 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 6544,0 111 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 6450,0 112 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 5948,0 113 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 2640,0 114 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 362,0 115 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 368,0 116 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 2297,0 117 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 2574,0 118 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 2580,0 119 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 2924,0 120 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 2598,0 121 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 5279,0 122 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 5478,0 123 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 5472,0 124 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 1981,0 125 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 8414,0 126 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 2468,0 127 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 2492,0 128 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 2486,0 129 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 2474,0 130 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 2498,0 131 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 2504,0 132 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 2480,0 133 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 320,0 134 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 NO_GRAPHIC 135 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 6276,0 137 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 3888,0 138 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 NO_GRAPHIC 140 189 GRAPHIC 8508,0 107 0 190 DESIGN @f@a@d_main 191 VIEW struct.bd 192 GRAPHIC 8516,0 108 0 193 DESIGN @f@a@d_main 194 VIEW struct.bd 195 GRAPHIC 8583,0 109 0 196 DESIGN @f@a@d_main 197 VIEW struct.bd 198 GRAPHIC 4399,0 110 0 199 DESIGN @f@a@d_main 200 VIEW struct.bd 201 GRAPHIC 4417,0 111 0 202 DESIGN @f@a@d_main 203 VIEW struct.bd 204 GRAPHIC 4741,0 112 0 205 DESIGN @f@a@d_main 206 VIEW struct.bd 207 GRAPHIC 4405,0 113 0 208 DESIGN @f@a@d_main 209 VIEW struct.bd 210 GRAPHIC 6544,0 114 0 211 DESIGN @f@a@d_main 212 VIEW struct.bd 213 GRAPHIC 6450,0 115 0 214 DESIGN @f@a@d_main 215 VIEW struct.bd 216 GRAPHIC 5948,0 116 0 217 DESIGN @f@a@d_main 218 VIEW struct.bd 219 GRAPHIC 2640,0 117 0 220 DESIGN @f@a@d_main 221 VIEW struct.bd 222 GRAPHIC 362,0 118 0 223 DESIGN @f@a@d_main 224 VIEW struct.bd 225 GRAPHIC 368,0 119 0 226 DESIGN @f@a@d_main 227 VIEW struct.bd 228 GRAPHIC 2297,0 120 0 229 DESIGN @f@a@d_main 230 VIEW struct.bd 231 GRAPHIC 2574,0 121 0 232 DESIGN @f@a@d_main 233 VIEW struct.bd 234 GRAPHIC 2580,0 122 0 235 DESIGN @f@a@d_main 236 VIEW struct.bd 237 GRAPHIC 2924,0 123 0 238 DESIGN @f@a@d_main 239 VIEW struct.bd 240 GRAPHIC 2598,0 124 0 241 DESIGN @f@a@d_main 242 VIEW struct.bd 243 GRAPHIC 5279,0 125 0 244 DESIGN @f@a@d_main 245 VIEW struct.bd 246 GRAPHIC 5478,0 126 0 247 DESIGN @f@a@d_main 248 VIEW struct.bd 249 GRAPHIC 5472,0 127 0 250 DESIGN @f@a@d_main 251 VIEW struct.bd 252 GRAPHIC 1981,0 128 0 253 DESIGN @f@a@d_main 254 VIEW struct.bd 255 GRAPHIC 8414,0 129 0 256 DESIGN @f@a@d_main 257 VIEW struct.bd 258 GRAPHIC 2468,0 130 0 259 DESIGN @f@a@d_main 260 VIEW struct.bd 261 GRAPHIC 2492,0 131 0 262 DESIGN @f@a@d_main 263 VIEW struct.bd 264 GRAPHIC 2486,0 132 0 265 DESIGN @f@a@d_main 266 VIEW struct.bd 267 GRAPHIC 2474,0 133 0 268 DESIGN @f@a@d_main 269 VIEW struct.bd 270 GRAPHIC 2498,0 134 0 271 DESIGN @f@a@d_main 272 VIEW struct.bd 273 GRAPHIC 2504,0 135 0 274 DESIGN @f@a@d_main 275 VIEW struct.bd 276 GRAPHIC 2480,0 136 0 277 DESIGN @f@a@d_main 278 VIEW struct.bd 279 GRAPHIC 320,0 137 0 280 DESIGN @f@a@d_main 281 VIEW struct.bd 282 NO_GRAPHIC 138 283 DESIGN @f@a@d_main 284 VIEW struct.bd 285 GRAPHIC 6276,0 140 0 286 DESIGN @f@a@d_main 287 VIEW struct.bd 288 GRAPHIC 3888,0 141 0 289 DESIGN @f@a@d_main 290 VIEW struct.bd 291 NO_GRAPHIC 143 283 292 LIBRARY FACT_FAD_lib 284 293 DESIGN adc_buffer 285 294 VIEW beha 286 GRAPHIC 5678,0 14 20287 DESIGN @f@a@d_main 288 VIEW struct.bd 289 NO_GRAPHIC 1 49290 DESIGN @f@a@d_main 291 VIEW struct.bd 292 GRAPHIC 4194,0 15 10295 GRAPHIC 5678,0 145 0 296 DESIGN @f@a@d_main 297 VIEW struct.bd 298 NO_GRAPHIC 152 299 DESIGN @f@a@d_main 300 VIEW struct.bd 301 GRAPHIC 4194,0 154 0 293 302 DESIGN clock_generator 294 303 VIEW symbol.sb 295 GRAPHIC 168,0 15 30304 GRAPHIC 168,0 156 0 296 305 DESIGN clock_generator 297 306 VIEW symbol.sb 298 GRAPHIC 126,0 15 40307 GRAPHIC 126,0 157 0 299 308 DESIGN clock_generator 300 309 VIEW symbol.sb 301 GRAPHIC 131,0 15 50310 GRAPHIC 131,0 158 0 302 311 DESIGN clock_generator 303 312 VIEW symbol.sb 304 GRAPHIC 121,0 156 0 305 DESIGN @f@a@d_main 306 VIEW struct.bd 307 GRAPHIC 5072,0 159 0 308 DESIGN control_unit 309 VIEW symbol.sb 310 GRAPHIC 130,0 161 0 311 DESIGN control_unit 312 VIEW symbol.sb 313 GRAPHIC 135,0 162 0 314 DESIGN control_unit 315 VIEW symbol.sb 316 GRAPHIC 170,0 163 0 317 DESIGN control_unit 318 VIEW symbol.sb 319 GRAPHIC 175,0 164 0 320 DESIGN control_unit 321 VIEW symbol.sb 322 GRAPHIC 160,0 165 0 323 DESIGN control_unit 324 VIEW symbol.sb 325 GRAPHIC 145,0 166 0 326 DESIGN control_unit 327 VIEW symbol.sb 328 GRAPHIC 140,0 167 0 329 DESIGN control_unit 330 VIEW symbol.sb 331 GRAPHIC 180,0 168 0 332 DESIGN control_unit 333 VIEW symbol.sb 334 GRAPHIC 350,0 169 0 335 DESIGN control_unit 336 VIEW symbol.sb 337 GRAPHIC 165,0 170 0 338 DESIGN control_unit 339 VIEW symbol.sb 340 GRAPHIC 155,0 171 0 341 DESIGN control_unit 342 VIEW symbol.sb 343 GRAPHIC 150,0 172 0 344 DESIGN @f@a@d_main 345 VIEW struct.bd 346 GRAPHIC 8277,0 175 0 313 GRAPHIC 121,0 159 0 314 DESIGN @f@a@d_main 315 VIEW struct.bd 316 GRAPHIC 5072,0 162 0 317 DESIGN control_unit 318 VIEW symbol.sb 319 GRAPHIC 130,0 164 0 320 DESIGN control_unit 321 VIEW symbol.sb 322 GRAPHIC 135,0 165 0 323 DESIGN control_unit 324 VIEW symbol.sb 325 GRAPHIC 170,0 166 0 326 DESIGN control_unit 327 VIEW symbol.sb 328 GRAPHIC 175,0 167 0 329 DESIGN control_unit 330 VIEW symbol.sb 331 GRAPHIC 160,0 168 0 332 DESIGN control_unit 333 VIEW symbol.sb 334 GRAPHIC 145,0 169 0 335 DESIGN control_unit 336 VIEW symbol.sb 337 GRAPHIC 140,0 170 0 338 DESIGN control_unit 339 VIEW symbol.sb 340 GRAPHIC 180,0 171 0 341 DESIGN control_unit 342 VIEW symbol.sb 343 GRAPHIC 350,0 172 0 344 DESIGN control_unit 345 VIEW symbol.sb 346 GRAPHIC 165,0 173 0 347 DESIGN control_unit 348 VIEW symbol.sb 349 GRAPHIC 521,0 174 0 350 DESIGN control_unit 351 VIEW symbol.sb 352 GRAPHIC 526,0 175 0 353 DESIGN control_unit 354 VIEW symbol.sb 355 GRAPHIC 155,0 176 0 356 DESIGN control_unit 357 VIEW symbol.sb 358 GRAPHIC 150,0 177 0 359 DESIGN @f@a@d_main 360 VIEW struct.bd 361 GRAPHIC 8277,0 180 0 347 362 DESIGN data@r@a@m_64b_16b_width14_5 348 363 VIEW data@r@a@m_64b_16b_width14_5_a 349 GRAPHIC 48,0 1 770364 GRAPHIC 48,0 182 0 350 365 DESIGN data@r@a@m_64b_16b_width14_5 351 366 VIEW data@r@a@m_64b_16b_width14_5_a 352 GRAPHIC 53,0 1 780367 GRAPHIC 53,0 183 0 353 368 DESIGN data@r@a@m_64b_16b_width14_5 354 369 VIEW data@r@a@m_64b_16b_width14_5_a 355 GRAPHIC 58,0 1 790370 GRAPHIC 58,0 184 0 356 371 DESIGN data@r@a@m_64b_16b_width14_5 357 372 VIEW data@r@a@m_64b_16b_width14_5_a 358 GRAPHIC 63,0 18 00373 GRAPHIC 63,0 185 0 359 374 DESIGN data@r@a@m_64b_16b_width14_5 360 375 VIEW data@r@a@m_64b_16b_width14_5_a 361 GRAPHIC 68,0 18 10376 GRAPHIC 68,0 186 0 362 377 DESIGN data@r@a@m_64b_16b_width14_5 363 378 VIEW data@r@a@m_64b_16b_width14_5_a 364 GRAPHIC 73,0 18 20379 GRAPHIC 73,0 187 0 365 380 DESIGN data@r@a@m_64b_16b_width14_5 366 381 VIEW data@r@a@m_64b_16b_width14_5_a 367 GRAPHIC 78,0 18 30368 DESIGN @f@a@d_main 369 VIEW struct.bd 370 GRAPHIC 1399,0 1 860371 DESIGN data_generator 372 VIEW symbol.sb 373 GRAPHIC 14,0 1 871374 DESIGN data_generator 375 VIEW @behavioral 376 GRAPHIC 48,0 19 10377 DESIGN data_generator 378 VIEW @behavioral 379 GRAPHIC 53,0 19 20380 DESIGN data_generator 381 VIEW @behavioral 382 GRAPHIC 58,0 19 30383 DESIGN data_generator 384 VIEW @behavioral 385 GRAPHIC 73,0 19 40386 DESIGN data_generator 387 VIEW @behavioral 388 GRAPHIC 78,0 1950389 DESIGN data_generator 390 VIEW @behavioral 391 GRAPHIC 402,0 1960392 DESIGN data_generator 393 VIEW @behavioral 394 GRAPHIC 407,0 1970395 DESIGN data_generator 396 VIEW @behavioral 397 GRAPHIC 1122,0 1980398 DESIGN data_generator 399 VIEW @behavioral 400 GRAPHIC 963,0 1990401 DESIGN data_generator 402 VIEW @behavioral 403 GRAPHIC 1127,0 20 00404 DESIGN data_generator 405 VIEW @behavioral 406 GRAPHIC 1048,0 20 10407 DESIGN data_generator 408 VIEW @behavioral 409 GRAPHIC 958,0 20 20410 DESIGN data_generator 411 VIEW @behavioral 412 GRAPHIC 1053,0 20 30413 DESIGN data_generator 414 VIEW @behavioral 415 GRAPHIC 1201,0 20 40416 DESIGN data_generator 417 VIEW @behavioral 418 GRAPHIC 1196,0 2 050419 DESIGN data_generator 420 VIEW @behavioral 421 GRAPHIC 1206,0 2 060422 DESIGN data_generator 423 VIEW @behavioral 424 GRAPHIC 473,0 2 070425 DESIGN data_generator 426 VIEW @behavioral 427 GRAPHIC 412,0 2 080428 DESIGN data_generator 429 VIEW @behavioral 430 GRAPHIC 1085,0 2 090431 DESIGN data_generator 432 VIEW @behavioral 433 GRAPHIC 1090,0 21 00434 DESIGN data_generator 435 VIEW @behavioral 436 GRAPHIC 1240,0 21 10437 DESIGN data_generator 438 VIEW @behavioral 439 GRAPHIC 526,0 21 20440 DESIGN data_generator 441 VIEW @behavioral 442 GRAPHIC 88,0 21 30443 DESIGN data_generator 444 VIEW @behavioral 445 GRAPHIC 285,0 21 40446 DESIGN data_generator 447 VIEW @behavioral 448 GRAPHIC 93,0 2 150449 DESIGN data_generator 450 VIEW @behavioral 451 GRAPHIC 98,0 2 160452 DESIGN data_generator 453 VIEW @behavioral 454 GRAPHIC 1018,0 2 170455 DESIGN data_generator 456 VIEW @behavioral 457 GRAPHIC 1164,0 2 180458 DESIGN data_generator 459 VIEW @behavioral 460 GRAPHIC 1159,0 2 190461 DESIGN data_generator 462 VIEW @behavioral 463 GRAPHIC 898,0 22 00464 DESIGN data_generator 465 VIEW @behavioral 466 GRAPHIC 637,0 22 10467 DESIGN data_generator 468 VIEW @behavioral 469 GRAPHIC 642,0 22 20470 DESIGN data_generator 471 VIEW @behavioral 472 GRAPHIC 676,0 22 30473 DESIGN data_generator 474 VIEW @behavioral 475 GRAPHIC 845,0 22 40476 DESIGN data_generator 477 VIEW @behavioral 478 GRAPHIC 681,0 2 250479 DESIGN data_generator 480 VIEW @behavioral 481 GRAPHIC 801,0 2 260482 DESIGN data_generator 483 VIEW @behavioral 484 GRAPHIC 806,0 2 270485 DESIGN data_generator 486 VIEW @behavioral 487 GRAPHIC 811,0 2 280488 DESIGN @f@a@d_main 489 VIEW struct.bd 490 GRAPHIC 4903,0 23 10491 DESIGN @f@a@d_main 492 VIEW struct.bd 493 NO_GRAPHIC 24 4494 DESIGN @f@a@d_main 495 VIEW struct.bd 496 GRAPHIC 2311,0 2 460497 DESIGN memory_manager 498 VIEW symbol.sb 499 GRAPHIC 14,0 2 471500 DESIGN memory_manager 501 VIEW beha 502 GRAPHIC 138,0 25 20503 DESIGN memory_manager 504 VIEW beha 505 GRAPHIC 194,0 25 30506 DESIGN memory_manager 507 VIEW beha 508 GRAPHIC 349,0 25 40509 DESIGN memory_manager 510 VIEW beha 511 GRAPHIC 569,0 2 550512 DESIGN memory_manager 513 VIEW beha 514 GRAPHIC 224,0 2 560515 DESIGN memory_manager 516 VIEW beha 517 GRAPHIC 254,0 2 570518 DESIGN memory_manager 519 VIEW beha 520 GRAPHIC 804,0 2 580521 DESIGN memory_manager 522 VIEW beha 523 GRAPHIC 433,0 2 590524 DESIGN memory_manager 525 VIEW beha 526 GRAPHIC 622,0 26 00527 DESIGN memory_manager 528 VIEW beha 529 GRAPHIC 289,0 26 10530 DESIGN memory_manager 531 VIEW beha 532 GRAPHIC 309,0 26 20533 DESIGN memory_manager 534 VIEW beha 535 GRAPHIC 284,0 26 30536 DESIGN memory_manager 537 VIEW beha 538 GRAPHIC 294,0 26 40539 DESIGN memory_manager 540 VIEW beha 541 GRAPHIC 304,0 2 650542 DESIGN memory_manager 543 VIEW beha 544 GRAPHIC 299,0 2 660545 DESIGN memory_manager 546 VIEW beha 547 GRAPHIC 379,0 2 670548 DESIGN memory_manager 549 VIEW beha 550 GRAPHIC 915,0 2 680551 DESIGN memory_manager 552 VIEW beha 553 GRAPHIC 51,0 2 690554 DESIGN @f@a@d_main 555 VIEW struct.bd 556 GRAPHIC 5793,0 27 20382 GRAPHIC 78,0 188 0 383 DESIGN @f@a@d_main 384 VIEW struct.bd 385 GRAPHIC 1399,0 191 0 386 DESIGN data_generator 387 VIEW symbol.sb 388 GRAPHIC 14,0 192 1 389 DESIGN data_generator 390 VIEW @behavioral 391 GRAPHIC 48,0 196 0 392 DESIGN data_generator 393 VIEW @behavioral 394 GRAPHIC 53,0 197 0 395 DESIGN data_generator 396 VIEW @behavioral 397 GRAPHIC 58,0 198 0 398 DESIGN data_generator 399 VIEW @behavioral 400 GRAPHIC 73,0 199 0 401 DESIGN data_generator 402 VIEW @behavioral 403 GRAPHIC 78,0 200 0 404 DESIGN data_generator 405 VIEW @behavioral 406 GRAPHIC 402,0 201 0 407 DESIGN data_generator 408 VIEW @behavioral 409 GRAPHIC 407,0 202 0 410 DESIGN data_generator 411 VIEW @behavioral 412 GRAPHIC 1122,0 203 0 413 DESIGN data_generator 414 VIEW @behavioral 415 GRAPHIC 963,0 204 0 416 DESIGN data_generator 417 VIEW @behavioral 418 GRAPHIC 1127,0 205 0 419 DESIGN data_generator 420 VIEW @behavioral 421 GRAPHIC 1048,0 206 0 422 DESIGN data_generator 423 VIEW @behavioral 424 GRAPHIC 958,0 207 0 425 DESIGN data_generator 426 VIEW @behavioral 427 GRAPHIC 1053,0 208 0 428 DESIGN data_generator 429 VIEW @behavioral 430 GRAPHIC 1201,0 209 0 431 DESIGN data_generator 432 VIEW @behavioral 433 GRAPHIC 1196,0 210 0 434 DESIGN data_generator 435 VIEW @behavioral 436 GRAPHIC 1206,0 211 0 437 DESIGN data_generator 438 VIEW @behavioral 439 GRAPHIC 473,0 212 0 440 DESIGN data_generator 441 VIEW @behavioral 442 GRAPHIC 412,0 213 0 443 DESIGN data_generator 444 VIEW @behavioral 445 GRAPHIC 1085,0 214 0 446 DESIGN data_generator 447 VIEW @behavioral 448 GRAPHIC 1090,0 215 0 449 DESIGN data_generator 450 VIEW @behavioral 451 GRAPHIC 1240,0 216 0 452 DESIGN data_generator 453 VIEW @behavioral 454 GRAPHIC 526,0 217 0 455 DESIGN data_generator 456 VIEW @behavioral 457 GRAPHIC 88,0 218 0 458 DESIGN data_generator 459 VIEW @behavioral 460 GRAPHIC 285,0 219 0 461 DESIGN data_generator 462 VIEW @behavioral 463 GRAPHIC 93,0 220 0 464 DESIGN data_generator 465 VIEW @behavioral 466 GRAPHIC 98,0 221 0 467 DESIGN data_generator 468 VIEW @behavioral 469 GRAPHIC 1018,0 222 0 470 DESIGN data_generator 471 VIEW @behavioral 472 GRAPHIC 1164,0 223 0 473 DESIGN data_generator 474 VIEW @behavioral 475 GRAPHIC 1159,0 224 0 476 DESIGN data_generator 477 VIEW @behavioral 478 GRAPHIC 898,0 225 0 479 DESIGN data_generator 480 VIEW @behavioral 481 GRAPHIC 637,0 226 0 482 DESIGN data_generator 483 VIEW @behavioral 484 GRAPHIC 642,0 227 0 485 DESIGN data_generator 486 VIEW @behavioral 487 GRAPHIC 676,0 228 0 488 DESIGN data_generator 489 VIEW @behavioral 490 GRAPHIC 845,0 229 0 491 DESIGN data_generator 492 VIEW @behavioral 493 GRAPHIC 681,0 230 0 494 DESIGN data_generator 495 VIEW @behavioral 496 GRAPHIC 801,0 231 0 497 DESIGN data_generator 498 VIEW @behavioral 499 GRAPHIC 806,0 232 0 500 DESIGN data_generator 501 VIEW @behavioral 502 GRAPHIC 811,0 233 0 503 DESIGN @f@a@d_main 504 VIEW struct.bd 505 GRAPHIC 4903,0 236 0 506 DESIGN @f@a@d_main 507 VIEW struct.bd 508 NO_GRAPHIC 249 509 DESIGN @f@a@d_main 510 VIEW struct.bd 511 GRAPHIC 2311,0 251 0 512 DESIGN memory_manager 513 VIEW symbol.sb 514 GRAPHIC 14,0 252 1 515 DESIGN memory_manager 516 VIEW beha 517 GRAPHIC 138,0 257 0 518 DESIGN memory_manager 519 VIEW beha 520 GRAPHIC 194,0 258 0 521 DESIGN memory_manager 522 VIEW beha 523 GRAPHIC 349,0 259 0 524 DESIGN memory_manager 525 VIEW beha 526 GRAPHIC 569,0 260 0 527 DESIGN memory_manager 528 VIEW beha 529 GRAPHIC 224,0 261 0 530 DESIGN memory_manager 531 VIEW beha 532 GRAPHIC 254,0 262 0 533 DESIGN memory_manager 534 VIEW beha 535 GRAPHIC 804,0 263 0 536 DESIGN memory_manager 537 VIEW beha 538 GRAPHIC 433,0 264 0 539 DESIGN memory_manager 540 VIEW beha 541 GRAPHIC 622,0 265 0 542 DESIGN memory_manager 543 VIEW beha 544 GRAPHIC 289,0 266 0 545 DESIGN memory_manager 546 VIEW beha 547 GRAPHIC 309,0 267 0 548 DESIGN memory_manager 549 VIEW beha 550 GRAPHIC 284,0 268 0 551 DESIGN memory_manager 552 VIEW beha 553 GRAPHIC 294,0 269 0 554 DESIGN memory_manager 555 VIEW beha 556 GRAPHIC 304,0 270 0 557 DESIGN memory_manager 558 VIEW beha 559 GRAPHIC 299,0 271 0 560 DESIGN memory_manager 561 VIEW beha 562 GRAPHIC 379,0 272 0 563 DESIGN memory_manager 564 VIEW beha 565 GRAPHIC 915,0 273 0 566 DESIGN memory_manager 567 VIEW beha 568 GRAPHIC 51,0 274 0 569 DESIGN @f@a@d_main 570 VIEW struct.bd 571 GRAPHIC 5793,0 277 0 557 572 DESIGN spi_interface 558 573 VIEW symbol.sb 559 GRAPHIC 1121,0 27 40574 GRAPHIC 1121,0 279 0 560 575 DESIGN spi_interface 561 576 VIEW symbol.sb 562 GRAPHIC 326,0 2 750577 GRAPHIC 326,0 280 0 563 578 DESIGN spi_interface 564 579 VIEW symbol.sb 565 GRAPHIC 197,0 2 760580 GRAPHIC 197,0 281 0 566 581 DESIGN spi_interface 567 582 VIEW symbol.sb 568 GRAPHIC 321,0 2 770583 GRAPHIC 321,0 282 0 569 584 DESIGN spi_interface 570 585 VIEW symbol.sb 571 GRAPHIC 1198,0 2 780586 GRAPHIC 1198,0 283 0 572 587 DESIGN spi_interface 573 588 VIEW symbol.sb 574 GRAPHIC 1017,0 2 790589 GRAPHIC 1017,0 284 0 575 590 DESIGN spi_interface 576 591 VIEW symbol.sb 577 GRAPHIC 1229,0 28 00592 GRAPHIC 1229,0 285 0 578 593 DESIGN spi_interface 579 594 VIEW symbol.sb 580 GRAPHIC 126,0 28 10595 GRAPHIC 126,0 286 0 581 596 DESIGN spi_interface 582 597 VIEW symbol.sb 583 GRAPHIC 819,0 28 20598 GRAPHIC 819,0 287 0 584 599 DESIGN spi_interface 585 600 VIEW symbol.sb 586 GRAPHIC 1022,0 28 30601 GRAPHIC 1022,0 288 0 587 602 DESIGN spi_interface 588 603 VIEW symbol.sb 589 GRAPHIC 824,0 28 40604 GRAPHIC 824,0 289 0 590 605 DESIGN spi_interface 591 606 VIEW symbol.sb 592 GRAPHIC 1283,0 2 850593 DESIGN @f@a@d_main 594 VIEW struct.bd 595 GRAPHIC 1768,0 2 880607 GRAPHIC 1283,0 290 0 608 DESIGN @f@a@d_main 609 VIEW struct.bd 610 GRAPHIC 1768,0 293 0 596 611 DESIGN trigger_counter 597 612 VIEW beha 598 GRAPHIC 48,0 29 00613 GRAPHIC 48,0 295 0 599 614 DESIGN trigger_counter 600 615 VIEW beha 601 GRAPHIC 53,0 29 10616 GRAPHIC 53,0 296 0 602 617 DESIGN trigger_counter 603 618 VIEW beha 604 GRAPHIC 148,0 29 20605 DESIGN @f@a@d_main 606 VIEW struct.bd 607 GRAPHIC 1606,0 2950608 DESIGN w5300_modul 609 VIEW symbol.sb 610 GRAPHIC 14,0 2961611 DESIGN w5300_modul 612 VIEW @behavioral 613 GRAPHIC 48,0 30 00614 DESIGN w5300_modul 615 VIEW @behavioral 616 GRAPHIC 53,0 30 10617 DESIGN w5300_modul 618 VIEW @behavioral 619 GRAPHIC 58,0 30 20620 DESIGN w5300_modul 621 VIEW @behavioral 622 GRAPHIC 63,0 30 30623 DESIGN w5300_modul 624 VIEW @behavioral 625 GRAPHIC 68,0 30 40626 DESIGN w5300_modul 627 VIEW @behavioral 628 GRAPHIC 73,0 3 050629 DESIGN w5300_modul 630 VIEW @behavioral 631 GRAPHIC 491,0 3 060632 DESIGN w5300_modul 633 VIEW @behavioral 634 GRAPHIC 83,0 3 070635 DESIGN w5300_modul 636 VIEW @behavioral 637 GRAPHIC 88,0 3 080638 DESIGN w5300_modul 639 VIEW @behavioral 640 GRAPHIC 93,0 3 090641 DESIGN w5300_modul 642 VIEW @behavioral 643 GRAPHIC 98,0 31 00644 DESIGN w5300_modul 645 VIEW @behavioral 646 GRAPHIC 103,0 31 10647 DESIGN w5300_modul 648 VIEW @behavioral 649 GRAPHIC 108,0 31 20650 DESIGN w5300_modul 651 VIEW @behavioral 652 GRAPHIC 113,0 31 30653 DESIGN w5300_modul 654 VIEW @behavioral 655 GRAPHIC 885,0 31 40656 DESIGN w5300_modul 657 VIEW @behavioral 658 GRAPHIC 118,0 3 150659 DESIGN w5300_modul 660 VIEW @behavioral 661 GRAPHIC 353,0 3 160662 DESIGN w5300_modul 663 VIEW @behavioral 664 GRAPHIC 348,0 3 170665 DESIGN w5300_modul 666 VIEW @behavioral 667 GRAPHIC 385,0 3 180668 DESIGN w5300_modul 669 VIEW @behavioral 670 GRAPHIC 521,0 3 190671 DESIGN w5300_modul 672 VIEW @behavioral 673 GRAPHIC 576,0 32 00674 DESIGN w5300_modul 675 VIEW @behavioral 676 GRAPHIC 566,0 32 10677 DESIGN w5300_modul 678 VIEW @behavioral 679 GRAPHIC 551,0 32 20680 DESIGN w5300_modul 681 VIEW @behavioral 682 GRAPHIC 561,0 32 30683 DESIGN w5300_modul 684 VIEW @behavioral 685 GRAPHIC 571,0 32 40686 DESIGN w5300_modul 687 VIEW @behavioral 688 GRAPHIC 640,0 3 250689 DESIGN w5300_modul 690 VIEW @behavioral 691 GRAPHIC 556,0 3 260692 DESIGN w5300_modul 693 VIEW @behavioral 694 GRAPHIC 670,0 3 270695 DESIGN w5300_modul 696 VIEW @behavioral 697 GRAPHIC 723,0 3 280619 GRAPHIC 148,0 297 0 620 DESIGN @f@a@d_main 621 VIEW struct.bd 622 GRAPHIC 1606,0 300 0 623 DESIGN w5300_modul 624 VIEW symbol.sb 625 GRAPHIC 14,0 301 1 626 DESIGN w5300_modul 627 VIEW @behavioral 628 GRAPHIC 48,0 305 0 629 DESIGN w5300_modul 630 VIEW @behavioral 631 GRAPHIC 53,0 306 0 632 DESIGN w5300_modul 633 VIEW @behavioral 634 GRAPHIC 58,0 307 0 635 DESIGN w5300_modul 636 VIEW @behavioral 637 GRAPHIC 63,0 308 0 638 DESIGN w5300_modul 639 VIEW @behavioral 640 GRAPHIC 68,0 309 0 641 DESIGN w5300_modul 642 VIEW @behavioral 643 GRAPHIC 73,0 310 0 644 DESIGN w5300_modul 645 VIEW @behavioral 646 GRAPHIC 491,0 311 0 647 DESIGN w5300_modul 648 VIEW @behavioral 649 GRAPHIC 83,0 312 0 650 DESIGN w5300_modul 651 VIEW @behavioral 652 GRAPHIC 88,0 313 0 653 DESIGN w5300_modul 654 VIEW @behavioral 655 GRAPHIC 93,0 314 0 656 DESIGN w5300_modul 657 VIEW @behavioral 658 GRAPHIC 98,0 315 0 659 DESIGN w5300_modul 660 VIEW @behavioral 661 GRAPHIC 103,0 316 0 662 DESIGN w5300_modul 663 VIEW @behavioral 664 GRAPHIC 108,0 317 0 665 DESIGN w5300_modul 666 VIEW @behavioral 667 GRAPHIC 113,0 318 0 668 DESIGN w5300_modul 669 VIEW @behavioral 670 GRAPHIC 885,0 319 0 671 DESIGN w5300_modul 672 VIEW @behavioral 673 GRAPHIC 118,0 320 0 674 DESIGN w5300_modul 675 VIEW @behavioral 676 GRAPHIC 353,0 321 0 677 DESIGN w5300_modul 678 VIEW @behavioral 679 GRAPHIC 348,0 322 0 680 DESIGN w5300_modul 681 VIEW @behavioral 682 GRAPHIC 385,0 323 0 683 DESIGN w5300_modul 684 VIEW @behavioral 685 GRAPHIC 521,0 324 0 686 DESIGN w5300_modul 687 VIEW @behavioral 688 GRAPHIC 576,0 325 0 689 DESIGN w5300_modul 690 VIEW @behavioral 691 GRAPHIC 566,0 326 0 692 DESIGN w5300_modul 693 VIEW @behavioral 694 GRAPHIC 551,0 327 0 695 DESIGN w5300_modul 696 VIEW @behavioral 697 GRAPHIC 561,0 328 0 698 DESIGN w5300_modul 699 VIEW @behavioral 700 GRAPHIC 571,0 329 0 701 DESIGN w5300_modul 702 VIEW @behavioral 703 GRAPHIC 640,0 330 0 704 DESIGN w5300_modul 705 VIEW @behavioral 706 GRAPHIC 556,0 331 0 707 DESIGN w5300_modul 708 VIEW @behavioral 709 GRAPHIC 670,0 332 0 710 DESIGN w5300_modul 711 VIEW @behavioral 712 GRAPHIC 723,0 333 0 698 713 LIBRARY FACT_FAD_lib 699 714 DESIGN @f@a@d_main 700 715 VIEW struct.bd 701 NO_GRAPHIC 331 702 DESIGN @f@a@d_main 703 VIEW struct.bd 704 GRAPHIC 5678,0 334 0 705 DESIGN @f@a@d_main 706 VIEW struct.bd 707 GRAPHIC 4194,0 335 0 708 DESIGN @f@a@d_main 709 VIEW struct.bd 710 GRAPHIC 5072,0 336 0 711 DESIGN @f@a@d_main 712 VIEW struct.bd 713 GRAPHIC 8277,0 337 0 714 DESIGN @f@a@d_main 715 VIEW struct.bd 716 GRAPHIC 1399,0 338 0 717 DESIGN @f@a@d_main 718 VIEW struct.bd 719 GRAPHIC 4903,0 339 0 720 DESIGN @f@a@d_main 721 VIEW struct.bd 722 GRAPHIC 2311,0 340 0 723 DESIGN @f@a@d_main 724 VIEW struct.bd 725 GRAPHIC 5793,0 341 0 726 DESIGN @f@a@d_main 727 VIEW struct.bd 728 GRAPHIC 1768,0 342 0 729 DESIGN @f@a@d_main 730 VIEW struct.bd 731 GRAPHIC 1606,0 343 0 732 DESIGN @f@a@d_main 733 VIEW struct.bd 734 NO_GRAPHIC 346 735 DESIGN @f@a@d_main 736 VIEW struct.bd 737 GRAPHIC 6529,0 348 0 716 NO_GRAPHIC 336 717 DESIGN @f@a@d_main 718 VIEW struct.bd 719 GRAPHIC 5678,0 339 0 720 DESIGN @f@a@d_main 721 VIEW struct.bd 722 GRAPHIC 4194,0 340 0 723 DESIGN @f@a@d_main 724 VIEW struct.bd 725 GRAPHIC 5072,0 341 0 726 DESIGN @f@a@d_main 727 VIEW struct.bd 728 GRAPHIC 8277,0 342 0 729 DESIGN @f@a@d_main 730 VIEW struct.bd 731 GRAPHIC 1399,0 343 0 732 DESIGN @f@a@d_main 733 VIEW struct.bd 734 GRAPHIC 4903,0 344 0 735 DESIGN @f@a@d_main 736 VIEW struct.bd 737 GRAPHIC 2311,0 345 0 738 DESIGN @f@a@d_main 739 VIEW struct.bd 740 GRAPHIC 5793,0 346 0 741 DESIGN @f@a@d_main 742 VIEW struct.bd 743 GRAPHIC 1768,0 347 0 744 DESIGN @f@a@d_main 745 VIEW struct.bd 746 GRAPHIC 1606,0 348 0 738 747 DESIGN @f@a@d_main 739 748 VIEW struct.bd … … 741 750 DESIGN @f@a@d_main 742 751 VIEW struct.bd 743 GRAPHIC 5678,0 353 0 744 DESIGN @f@a@d_main 745 VIEW struct.bd 746 GRAPHIC 5646,0 355 0 747 DESIGN @f@a@d_main 748 VIEW struct.bd 749 GRAPHIC 4272,0 356 0 750 DESIGN @f@a@d_main 751 VIEW struct.bd 752 GRAPHIC 2786,0 357 0 753 DESIGN @f@a@d_main 754 VIEW struct.bd 755 GRAPHIC 5626,0 358 0 756 DESIGN @f@a@d_main 757 VIEW struct.bd 758 GRAPHIC 5634,0 359 0 759 DESIGN @f@a@d_main 760 VIEW struct.bd 761 GRAPHIC 4194,0 361 0 762 DESIGN @f@a@d_main 763 VIEW struct.bd 764 GRAPHIC 4042,0 363 0 765 DESIGN @f@a@d_main 766 VIEW struct.bd 767 GRAPHIC 6072,0 364 0 768 DESIGN @f@a@d_main 769 VIEW struct.bd 770 GRAPHIC 3984,0 365 0 771 DESIGN @f@a@d_main 772 VIEW struct.bd 773 GRAPHIC 3888,0 366 0 774 DESIGN @f@a@d_main 775 VIEW struct.bd 776 GRAPHIC 5072,0 368 0 777 DESIGN @f@a@d_main 778 VIEW struct.bd 779 GRAPHIC 5582,0 370 0 780 DESIGN @f@a@d_main 781 VIEW struct.bd 782 GRAPHIC 5090,0 371 0 783 DESIGN @f@a@d_main 784 VIEW struct.bd 785 GRAPHIC 5130,0 372 0 786 DESIGN @f@a@d_main 787 VIEW struct.bd 788 GRAPHIC 5184,0 373 0 789 DESIGN @f@a@d_main 790 VIEW struct.bd 791 GRAPHIC 5122,0 374 0 792 DESIGN @f@a@d_main 793 VIEW struct.bd 794 GRAPHIC 5106,0 375 0 795 DESIGN @f@a@d_main 796 VIEW struct.bd 797 GRAPHIC 5098,0 376 0 798 DESIGN @f@a@d_main 799 VIEW struct.bd 800 GRAPHIC 5190,0 377 0 801 DESIGN @f@a@d_main 802 VIEW struct.bd 803 GRAPHIC 6002,0 378 0 804 DESIGN @f@a@d_main 805 VIEW struct.bd 806 GRAPHIC 5146,0 379 0 807 DESIGN @f@a@d_main 808 VIEW struct.bd 809 GRAPHIC 5138,0 380 0 810 DESIGN @f@a@d_main 811 VIEW struct.bd 812 GRAPHIC 5114,0 381 0 813 DESIGN @f@a@d_main 814 VIEW struct.bd 815 GRAPHIC 8277,0 383 0 816 DESIGN @f@a@d_main 817 VIEW struct.bd 818 GRAPHIC 5602,0 385 0 819 DESIGN @f@a@d_main 820 VIEW struct.bd 821 GRAPHIC 334,0 386 0 822 DESIGN @f@a@d_main 823 VIEW struct.bd 824 GRAPHIC 328,0 387 0 825 DESIGN @f@a@d_main 826 VIEW struct.bd 827 GRAPHIC 322,0 388 0 828 DESIGN @f@a@d_main 829 VIEW struct.bd 830 GRAPHIC 4240,0 389 0 831 DESIGN @f@a@d_main 832 VIEW struct.bd 833 GRAPHIC 364,0 390 0 834 DESIGN @f@a@d_main 835 VIEW struct.bd 836 GRAPHIC 370,0 391 0 837 DESIGN @f@a@d_main 838 VIEW struct.bd 839 GRAPHIC 1399,0 393 0 840 DESIGN @f@a@d_main 841 VIEW struct.bd 842 GRAPHIC 1406,0 394 1 843 DESIGN @f@a@d_main 844 VIEW struct.bd 845 GRAPHIC 5602,0 398 0 846 DESIGN @f@a@d_main 847 VIEW struct.bd 848 GRAPHIC 334,0 399 0 849 DESIGN @f@a@d_main 850 VIEW struct.bd 851 GRAPHIC 328,0 400 0 852 DESIGN @f@a@d_main 853 VIEW struct.bd 854 GRAPHIC 322,0 401 0 855 DESIGN @f@a@d_main 856 VIEW struct.bd 857 GRAPHIC 2299,0 402 0 858 DESIGN @f@a@d_main 859 VIEW struct.bd 860 GRAPHIC 2576,0 403 0 861 DESIGN @f@a@d_main 862 VIEW struct.bd 863 GRAPHIC 2582,0 404 0 864 DESIGN @f@a@d_main 865 VIEW struct.bd 866 GRAPHIC 2588,0 405 0 867 DESIGN @f@a@d_main 868 VIEW struct.bd 869 GRAPHIC 5184,0 406 0 870 DESIGN @f@a@d_main 871 VIEW struct.bd 872 GRAPHIC 5745,0 407 0 873 DESIGN @f@a@d_main 874 VIEW struct.bd 875 GRAPHIC 2594,0 408 0 876 DESIGN @f@a@d_main 877 VIEW struct.bd 878 GRAPHIC 5190,0 409 0 879 DESIGN @f@a@d_main 880 VIEW struct.bd 881 GRAPHIC 5404,0 410 0 882 DESIGN @f@a@d_main 883 VIEW struct.bd 884 GRAPHIC 6018,0 411 0 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 6002,0 412 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 6008,0 413 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 5138,0 414 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 2600,0 415 0 897 DESIGN @f@a@d_main 898 VIEW struct.bd 899 GRAPHIC 5480,0 416 0 900 DESIGN @f@a@d_main 901 VIEW struct.bd 902 GRAPHIC 5474,0 417 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 6064,0 418 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 2642,0 419 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 1411,0 420 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 1682,0 421 0 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 1983,0 422 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 1425,0 423 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 5281,0 424 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 5950,0 425 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 5962,0 426 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 5626,0 427 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 2778,0 428 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 5634,0 429 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 4537,0 430 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 6540,0 431 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 4401,0 432 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 GRAPHIC 4419,0 433 0 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 4743,0 434 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 4407,0 435 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 4903,0 437 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 4757,0 439 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 4401,0 440 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 4419,0 441 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 4671,0 442 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 4679,0 443 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 4687,0 444 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 4695,0 445 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 4407,0 446 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 4743,0 447 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 4948,0 448 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4962,0 449 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 2311,0 451 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 2318,0 452 1 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 6082,0 457 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 2588,0 458 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 2582,0 459 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 5168,0 460 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 2576,0 461 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 2594,0 462 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 6018,0 463 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 2600,0 464 0 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 2642,0 465 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 2488,0 466 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 2482,0 467 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 2494,0 468 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 2476,0 469 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 2506,0 470 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 2500,0 471 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 2470,0 472 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 8416,0 473 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 2299,0 474 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 5793,0 476 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 5805,0 478 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 5745,0 479 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 5146,0 480 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 5404,0 481 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 6008,0 482 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 5829,0 483 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 6160,0 484 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5813,0 485 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 5480,0 486 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 5837,0 487 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 5474,0 488 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5821,0 489 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 1768,0 491 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 1983,0 493 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 2876,0 494 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 6276,0 495 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 1606,0 497 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 1613,0 498 1 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 3888,0 502 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 376,0 503 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 384,0 504 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 392,0 505 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 400,0 506 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 408,0 507 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 5222,0 508 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 424,0 509 0 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 432,0 510 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 2482,0 511 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 2488,0 512 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 370,0 513 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 364,0 514 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 2476,0 515 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 8416,0 516 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 2470,0 517 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 2506,0 518 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2500,0 519 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 2494,0 520 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 5281,0 521 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 5950,0 522 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 5962,0 523 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 5090,0 524 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 5114,0 525 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 5122,0 526 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 5130,0 527 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 5106,0 528 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 6362,0 529 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 6452,0 530 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 6276,0 534 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 3888,0 535 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 NO_GRAPHIC 537 752 GRAPHIC 6529,0 353 0 753 DESIGN @f@a@d_main 754 VIEW struct.bd 755 GRAPHIC 8562,0 356 0 756 DESIGN @f@a@d_main 757 VIEW struct.bd 758 NO_GRAPHIC 367 759 DESIGN @f@a@d_main 760 VIEW struct.bd 761 GRAPHIC 5678,0 369 0 762 DESIGN @f@a@d_main 763 VIEW struct.bd 764 GRAPHIC 5646,0 371 0 765 DESIGN @f@a@d_main 766 VIEW struct.bd 767 GRAPHIC 4272,0 372 0 768 DESIGN @f@a@d_main 769 VIEW struct.bd 770 GRAPHIC 2786,0 373 0 771 DESIGN @f@a@d_main 772 VIEW struct.bd 773 GRAPHIC 5626,0 374 0 774 DESIGN @f@a@d_main 775 VIEW struct.bd 776 GRAPHIC 5634,0 375 0 777 DESIGN @f@a@d_main 778 VIEW struct.bd 779 GRAPHIC 4194,0 377 0 780 DESIGN @f@a@d_main 781 VIEW struct.bd 782 GRAPHIC 4042,0 379 0 783 DESIGN @f@a@d_main 784 VIEW struct.bd 785 GRAPHIC 6072,0 380 0 786 DESIGN @f@a@d_main 787 VIEW struct.bd 788 GRAPHIC 3984,0 381 0 789 DESIGN @f@a@d_main 790 VIEW struct.bd 791 GRAPHIC 3888,0 382 0 792 DESIGN @f@a@d_main 793 VIEW struct.bd 794 GRAPHIC 5072,0 384 0 795 DESIGN @f@a@d_main 796 VIEW struct.bd 797 GRAPHIC 5582,0 386 0 798 DESIGN @f@a@d_main 799 VIEW struct.bd 800 GRAPHIC 5090,0 387 0 801 DESIGN @f@a@d_main 802 VIEW struct.bd 803 GRAPHIC 5130,0 388 0 804 DESIGN @f@a@d_main 805 VIEW struct.bd 806 GRAPHIC 5184,0 389 0 807 DESIGN @f@a@d_main 808 VIEW struct.bd 809 GRAPHIC 5122,0 390 0 810 DESIGN @f@a@d_main 811 VIEW struct.bd 812 GRAPHIC 5106,0 391 0 813 DESIGN @f@a@d_main 814 VIEW struct.bd 815 GRAPHIC 5098,0 392 0 816 DESIGN @f@a@d_main 817 VIEW struct.bd 818 GRAPHIC 5190,0 393 0 819 DESIGN @f@a@d_main 820 VIEW struct.bd 821 GRAPHIC 6002,0 394 0 822 DESIGN @f@a@d_main 823 VIEW struct.bd 824 GRAPHIC 5146,0 395 0 825 DESIGN @f@a@d_main 826 VIEW struct.bd 827 GRAPHIC 8510,0 396 0 828 DESIGN @f@a@d_main 829 VIEW struct.bd 830 GRAPHIC 8518,0 397 0 831 DESIGN @f@a@d_main 832 VIEW struct.bd 833 GRAPHIC 5138,0 398 0 834 DESIGN @f@a@d_main 835 VIEW struct.bd 836 GRAPHIC 5114,0 399 0 837 DESIGN @f@a@d_main 838 VIEW struct.bd 839 GRAPHIC 8277,0 401 0 840 DESIGN @f@a@d_main 841 VIEW struct.bd 842 GRAPHIC 5602,0 403 0 843 DESIGN @f@a@d_main 844 VIEW struct.bd 845 GRAPHIC 334,0 404 0 846 DESIGN @f@a@d_main 847 VIEW struct.bd 848 GRAPHIC 328,0 405 0 849 DESIGN @f@a@d_main 850 VIEW struct.bd 851 GRAPHIC 322,0 406 0 852 DESIGN @f@a@d_main 853 VIEW struct.bd 854 GRAPHIC 4240,0 407 0 855 DESIGN @f@a@d_main 856 VIEW struct.bd 857 GRAPHIC 364,0 408 0 858 DESIGN @f@a@d_main 859 VIEW struct.bd 860 GRAPHIC 370,0 409 0 861 DESIGN @f@a@d_main 862 VIEW struct.bd 863 GRAPHIC 1399,0 411 0 864 DESIGN @f@a@d_main 865 VIEW struct.bd 866 GRAPHIC 1406,0 412 1 867 DESIGN @f@a@d_main 868 VIEW struct.bd 869 GRAPHIC 5602,0 416 0 870 DESIGN @f@a@d_main 871 VIEW struct.bd 872 GRAPHIC 334,0 417 0 873 DESIGN @f@a@d_main 874 VIEW struct.bd 875 GRAPHIC 328,0 418 0 876 DESIGN @f@a@d_main 877 VIEW struct.bd 878 GRAPHIC 322,0 419 0 879 DESIGN @f@a@d_main 880 VIEW struct.bd 881 GRAPHIC 2299,0 420 0 882 DESIGN @f@a@d_main 883 VIEW struct.bd 884 GRAPHIC 2576,0 421 0 885 DESIGN @f@a@d_main 886 VIEW struct.bd 887 GRAPHIC 2582,0 422 0 888 DESIGN @f@a@d_main 889 VIEW struct.bd 890 GRAPHIC 2588,0 423 0 891 DESIGN @f@a@d_main 892 VIEW struct.bd 893 GRAPHIC 5184,0 424 0 894 DESIGN @f@a@d_main 895 VIEW struct.bd 896 GRAPHIC 5745,0 425 0 897 DESIGN @f@a@d_main 898 VIEW struct.bd 899 GRAPHIC 2594,0 426 0 900 DESIGN @f@a@d_main 901 VIEW struct.bd 902 GRAPHIC 5190,0 427 0 903 DESIGN @f@a@d_main 904 VIEW struct.bd 905 GRAPHIC 5404,0 428 0 906 DESIGN @f@a@d_main 907 VIEW struct.bd 908 GRAPHIC 6018,0 429 0 909 DESIGN @f@a@d_main 910 VIEW struct.bd 911 GRAPHIC 6002,0 430 0 912 DESIGN @f@a@d_main 913 VIEW struct.bd 914 GRAPHIC 6008,0 431 0 915 DESIGN @f@a@d_main 916 VIEW struct.bd 917 GRAPHIC 5138,0 432 0 918 DESIGN @f@a@d_main 919 VIEW struct.bd 920 GRAPHIC 2600,0 433 0 921 DESIGN @f@a@d_main 922 VIEW struct.bd 923 GRAPHIC 5480,0 434 0 924 DESIGN @f@a@d_main 925 VIEW struct.bd 926 GRAPHIC 5474,0 435 0 927 DESIGN @f@a@d_main 928 VIEW struct.bd 929 GRAPHIC 6064,0 436 0 930 DESIGN @f@a@d_main 931 VIEW struct.bd 932 GRAPHIC 2642,0 437 0 933 DESIGN @f@a@d_main 934 VIEW struct.bd 935 GRAPHIC 1411,0 438 0 936 DESIGN @f@a@d_main 937 VIEW struct.bd 938 GRAPHIC 1682,0 439 0 939 DESIGN @f@a@d_main 940 VIEW struct.bd 941 GRAPHIC 1983,0 440 0 942 DESIGN @f@a@d_main 943 VIEW struct.bd 944 GRAPHIC 1425,0 441 0 945 DESIGN @f@a@d_main 946 VIEW struct.bd 947 GRAPHIC 5281,0 442 0 948 DESIGN @f@a@d_main 949 VIEW struct.bd 950 GRAPHIC 5950,0 443 0 951 DESIGN @f@a@d_main 952 VIEW struct.bd 953 GRAPHIC 5962,0 444 0 954 DESIGN @f@a@d_main 955 VIEW struct.bd 956 GRAPHIC 5626,0 445 0 957 DESIGN @f@a@d_main 958 VIEW struct.bd 959 GRAPHIC 2778,0 446 0 960 DESIGN @f@a@d_main 961 VIEW struct.bd 962 GRAPHIC 5634,0 447 0 963 DESIGN @f@a@d_main 964 VIEW struct.bd 965 GRAPHIC 8577,0 448 0 966 DESIGN @f@a@d_main 967 VIEW struct.bd 968 GRAPHIC 6540,0 449 0 969 DESIGN @f@a@d_main 970 VIEW struct.bd 971 GRAPHIC 4401,0 450 0 972 DESIGN @f@a@d_main 973 VIEW struct.bd 974 GRAPHIC 4419,0 451 0 975 DESIGN @f@a@d_main 976 VIEW struct.bd 977 GRAPHIC 4743,0 452 0 978 DESIGN @f@a@d_main 979 VIEW struct.bd 980 GRAPHIC 4407,0 453 0 981 DESIGN @f@a@d_main 982 VIEW struct.bd 983 GRAPHIC 4903,0 455 0 984 DESIGN @f@a@d_main 985 VIEW struct.bd 986 GRAPHIC 4757,0 457 0 987 DESIGN @f@a@d_main 988 VIEW struct.bd 989 GRAPHIC 4401,0 458 0 990 DESIGN @f@a@d_main 991 VIEW struct.bd 992 GRAPHIC 4419,0 459 0 993 DESIGN @f@a@d_main 994 VIEW struct.bd 995 GRAPHIC 4671,0 460 0 996 DESIGN @f@a@d_main 997 VIEW struct.bd 998 GRAPHIC 4679,0 461 0 999 DESIGN @f@a@d_main 1000 VIEW struct.bd 1001 GRAPHIC 4687,0 462 0 1002 DESIGN @f@a@d_main 1003 VIEW struct.bd 1004 GRAPHIC 4695,0 463 0 1005 DESIGN @f@a@d_main 1006 VIEW struct.bd 1007 GRAPHIC 4407,0 464 0 1008 DESIGN @f@a@d_main 1009 VIEW struct.bd 1010 GRAPHIC 4743,0 465 0 1011 DESIGN @f@a@d_main 1012 VIEW struct.bd 1013 GRAPHIC 4948,0 466 0 1014 DESIGN @f@a@d_main 1015 VIEW struct.bd 1016 GRAPHIC 4962,0 467 0 1017 DESIGN @f@a@d_main 1018 VIEW struct.bd 1019 GRAPHIC 2311,0 469 0 1020 DESIGN @f@a@d_main 1021 VIEW struct.bd 1022 GRAPHIC 2318,0 470 1 1023 DESIGN @f@a@d_main 1024 VIEW struct.bd 1025 GRAPHIC 6082,0 475 0 1026 DESIGN @f@a@d_main 1027 VIEW struct.bd 1028 GRAPHIC 2588,0 476 0 1029 DESIGN @f@a@d_main 1030 VIEW struct.bd 1031 GRAPHIC 2582,0 477 0 1032 DESIGN @f@a@d_main 1033 VIEW struct.bd 1034 GRAPHIC 5168,0 478 0 1035 DESIGN @f@a@d_main 1036 VIEW struct.bd 1037 GRAPHIC 2576,0 479 0 1038 DESIGN @f@a@d_main 1039 VIEW struct.bd 1040 GRAPHIC 2594,0 480 0 1041 DESIGN @f@a@d_main 1042 VIEW struct.bd 1043 GRAPHIC 6018,0 481 0 1044 DESIGN @f@a@d_main 1045 VIEW struct.bd 1046 GRAPHIC 2600,0 482 0 1047 DESIGN @f@a@d_main 1048 VIEW struct.bd 1049 GRAPHIC 2642,0 483 0 1050 DESIGN @f@a@d_main 1051 VIEW struct.bd 1052 GRAPHIC 2488,0 484 0 1053 DESIGN @f@a@d_main 1054 VIEW struct.bd 1055 GRAPHIC 2482,0 485 0 1056 DESIGN @f@a@d_main 1057 VIEW struct.bd 1058 GRAPHIC 2494,0 486 0 1059 DESIGN @f@a@d_main 1060 VIEW struct.bd 1061 GRAPHIC 2476,0 487 0 1062 DESIGN @f@a@d_main 1063 VIEW struct.bd 1064 GRAPHIC 2506,0 488 0 1065 DESIGN @f@a@d_main 1066 VIEW struct.bd 1067 GRAPHIC 2500,0 489 0 1068 DESIGN @f@a@d_main 1069 VIEW struct.bd 1070 GRAPHIC 2470,0 490 0 1071 DESIGN @f@a@d_main 1072 VIEW struct.bd 1073 GRAPHIC 8416,0 491 0 1074 DESIGN @f@a@d_main 1075 VIEW struct.bd 1076 GRAPHIC 2299,0 492 0 1077 DESIGN @f@a@d_main 1078 VIEW struct.bd 1079 GRAPHIC 5793,0 494 0 1080 DESIGN @f@a@d_main 1081 VIEW struct.bd 1082 GRAPHIC 5805,0 496 0 1083 DESIGN @f@a@d_main 1084 VIEW struct.bd 1085 GRAPHIC 5745,0 497 0 1086 DESIGN @f@a@d_main 1087 VIEW struct.bd 1088 GRAPHIC 5146,0 498 0 1089 DESIGN @f@a@d_main 1090 VIEW struct.bd 1091 GRAPHIC 5404,0 499 0 1092 DESIGN @f@a@d_main 1093 VIEW struct.bd 1094 GRAPHIC 6008,0 500 0 1095 DESIGN @f@a@d_main 1096 VIEW struct.bd 1097 GRAPHIC 5829,0 501 0 1098 DESIGN @f@a@d_main 1099 VIEW struct.bd 1100 GRAPHIC 6160,0 502 0 1101 DESIGN @f@a@d_main 1102 VIEW struct.bd 1103 GRAPHIC 5813,0 503 0 1104 DESIGN @f@a@d_main 1105 VIEW struct.bd 1106 GRAPHIC 5480,0 504 0 1107 DESIGN @f@a@d_main 1108 VIEW struct.bd 1109 GRAPHIC 5837,0 505 0 1110 DESIGN @f@a@d_main 1111 VIEW struct.bd 1112 GRAPHIC 5474,0 506 0 1113 DESIGN @f@a@d_main 1114 VIEW struct.bd 1115 GRAPHIC 5821,0 507 0 1116 DESIGN @f@a@d_main 1117 VIEW struct.bd 1118 GRAPHIC 1768,0 509 0 1119 DESIGN @f@a@d_main 1120 VIEW struct.bd 1121 GRAPHIC 1983,0 511 0 1122 DESIGN @f@a@d_main 1123 VIEW struct.bd 1124 GRAPHIC 2876,0 512 0 1125 DESIGN @f@a@d_main 1126 VIEW struct.bd 1127 GRAPHIC 6276,0 513 0 1128 DESIGN @f@a@d_main 1129 VIEW struct.bd 1130 GRAPHIC 1606,0 515 0 1131 DESIGN @f@a@d_main 1132 VIEW struct.bd 1133 GRAPHIC 1613,0 516 1 1134 DESIGN @f@a@d_main 1135 VIEW struct.bd 1136 GRAPHIC 3888,0 520 0 1137 DESIGN @f@a@d_main 1138 VIEW struct.bd 1139 GRAPHIC 376,0 521 0 1140 DESIGN @f@a@d_main 1141 VIEW struct.bd 1142 GRAPHIC 384,0 522 0 1143 DESIGN @f@a@d_main 1144 VIEW struct.bd 1145 GRAPHIC 392,0 523 0 1146 DESIGN @f@a@d_main 1147 VIEW struct.bd 1148 GRAPHIC 400,0 524 0 1149 DESIGN @f@a@d_main 1150 VIEW struct.bd 1151 GRAPHIC 408,0 525 0 1152 DESIGN @f@a@d_main 1153 VIEW struct.bd 1154 GRAPHIC 5222,0 526 0 1155 DESIGN @f@a@d_main 1156 VIEW struct.bd 1157 GRAPHIC 424,0 527 0 1158 DESIGN @f@a@d_main 1159 VIEW struct.bd 1160 GRAPHIC 432,0 528 0 1161 DESIGN @f@a@d_main 1162 VIEW struct.bd 1163 GRAPHIC 2482,0 529 0 1164 DESIGN @f@a@d_main 1165 VIEW struct.bd 1166 GRAPHIC 2488,0 530 0 1167 DESIGN @f@a@d_main 1168 VIEW struct.bd 1169 GRAPHIC 370,0 531 0 1170 DESIGN @f@a@d_main 1171 VIEW struct.bd 1172 GRAPHIC 364,0 532 0 1173 DESIGN @f@a@d_main 1174 VIEW struct.bd 1175 GRAPHIC 2476,0 533 0 1176 DESIGN @f@a@d_main 1177 VIEW struct.bd 1178 GRAPHIC 8416,0 534 0 1179 DESIGN @f@a@d_main 1180 VIEW struct.bd 1181 GRAPHIC 2470,0 535 0 1182 DESIGN @f@a@d_main 1183 VIEW struct.bd 1184 GRAPHIC 2506,0 536 0 1185 DESIGN @f@a@d_main 1186 VIEW struct.bd 1187 GRAPHIC 2500,0 537 0 1188 DESIGN @f@a@d_main 1189 VIEW struct.bd 1190 GRAPHIC 2494,0 538 0 1191 DESIGN @f@a@d_main 1192 VIEW struct.bd 1193 GRAPHIC 5281,0 539 0 1194 DESIGN @f@a@d_main 1195 VIEW struct.bd 1196 GRAPHIC 5950,0 540 0 1197 DESIGN @f@a@d_main 1198 VIEW struct.bd 1199 GRAPHIC 5962,0 541 0 1200 DESIGN @f@a@d_main 1201 VIEW struct.bd 1202 GRAPHIC 5090,0 542 0 1203 DESIGN @f@a@d_main 1204 VIEW struct.bd 1205 GRAPHIC 5114,0 543 0 1206 DESIGN @f@a@d_main 1207 VIEW struct.bd 1208 GRAPHIC 5122,0 544 0 1209 DESIGN @f@a@d_main 1210 VIEW struct.bd 1211 GRAPHIC 5130,0 545 0 1212 DESIGN @f@a@d_main 1213 VIEW struct.bd 1214 GRAPHIC 5106,0 546 0 1215 DESIGN @f@a@d_main 1216 VIEW struct.bd 1217 GRAPHIC 6362,0 547 0 1218 DESIGN @f@a@d_main 1219 VIEW struct.bd 1220 GRAPHIC 6452,0 548 0 1221 DESIGN @f@a@d_main 1222 VIEW struct.bd 1223 GRAPHIC 6276,0 552 0 1224 DESIGN @f@a@d_main 1225 VIEW struct.bd 1226 GRAPHIC 3888,0 553 0 1227 DESIGN @f@a@d_main 1228 VIEW struct.bd 1229 NO_GRAPHIC 555 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd
r246 r252 40 40 ) 41 41 (Instance 42 name "I_debouncer"43 duLibraryName "FACT_FAD_LIB"44 duName "debouncer"45 elements [46 (GiElement47 name "WIDTH"48 type "INTEGER"49 value "17"50 )51 ]52 mwi 053 uid 6250,054 )55 (Instance56 name "I1"57 duLibraryName "moduleware"58 duName "inv"59 elements [60 ]61 mwi 162 uid 6539,063 )64 (Instance65 42 name "I2" 66 43 duLibraryName "moduleware" … … 128 105 (vvPair 129 106 variable "HDLDir" 130 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hdl"107 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 131 108 ) 132 109 (vvPair 133 110 variable "HDSDir" 134 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"111 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 135 112 ) 136 113 (vvPair 137 114 variable "SideDataDesignDir" 138 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"115 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 139 116 ) 140 117 (vvPair 141 118 variable "SideDataUserDir" 142 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"119 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 143 120 ) 144 121 (vvPair 145 122 variable "SourceDir" 146 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds"123 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 147 124 ) 148 125 (vvPair … … 156 133 (vvPair 157 134 variable "config" 158 value "%(unit)_ config"135 value "%(unit)_%(view)_config" 159 136 ) 160 137 (vvPair 161 138 variable "d" 162 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board"139 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 163 140 ) 164 141 (vvPair 165 142 variable "d_logical" 166 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board"143 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 167 144 ) 168 145 (vvPair 169 146 variable "date" 170 value " 24.06.2010"147 value "14.07.2010" 171 148 ) 172 149 (vvPair 173 150 variable "day" 174 value " Do"151 value "Mi" 175 152 ) 176 153 (vvPair 177 154 variable "day_long" 178 value " Donnerstag"155 value "Mittwoch" 179 156 ) 180 157 (vvPair 181 158 variable "dd" 182 value " 24"159 value "14" 183 160 ) 184 161 (vvPair … … 208 185 (vvPair 209 186 variable "host" 210 value "E EPC8"187 value "E5B-LABOR6" 211 188 ) 212 189 (vvPair … … 219 196 ) 220 197 (vvPair 198 variable "library_downstream_HdsLintPlugin" 199 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 200 ) 201 (vvPair 221 202 variable "library_downstream_ISEPARInvoke" 222 203 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 236 217 (vvPair 237 218 variable "mm" 238 value "0 6"219 value "07" 239 220 ) 240 221 (vvPair … … 244 225 (vvPair 245 226 variable "month" 246 value "Ju n"227 value "Jul" 247 228 ) 248 229 (vvPair 249 230 variable "month_long" 250 value "Ju ni"231 value "Juli" 251 232 ) 252 233 (vvPair 253 234 variable "p" 254 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"235 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 255 236 ) 256 237 (vvPair 257 238 variable "p_logical" 258 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"239 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 259 240 ) 260 241 (vvPair … … 280 261 (vvPair 281 262 variable "task_ModelSimPath" 282 value " $HDS_HOME/../Modeltech/win32"263 value "<TBD>" 283 264 ) 284 265 (vvPair … … 288 269 (vvPair 289 270 variable "task_PrecisionRTLPath" 290 value " $HDS_HOME/../Precision/Mgc_home/bin"271 value "<TBD>" 291 272 ) 292 273 (vvPair … … 312 293 (vvPair 313 294 variable "time" 314 value "1 4:18:44"295 value "15:25:08" 315 296 ) 316 297 (vvPair … … 320 301 (vvPair 321 302 variable "user" 322 value " Benjamin Krumm"303 value "dneise" 323 304 ) 324 305 (vvPair … … 364 345 bg "0,0,32768" 365 346 ) 366 xt "99200,4000,108 700,5000"347 xt "99200,4000,108500,5000" 367 348 st " 368 349 by %user on %dd %month %year … … 2074 2055 ) 2075 2056 xt "39000,48000,67000,48800" 2076 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2057 st "SIGNAL board_id : std_logic_vector(3 downto 0) 2058 " 2077 2059 ) 2078 2060 ) … … 2092 2074 ) 2093 2075 xt "39000,48800,67000,49600" 2094 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2076 st "SIGNAL crate_id : std_logic_vector(1 downto 0) 2077 " 2095 2078 ) 2096 2079 ) … … 2415 2398 ) 2416 2399 xt "39000,47200,62500,48000" 2417 st "SIGNAL adc_data_array : adc_data_array_type" 2400 st "SIGNAL adc_data_array : adc_data_array_type 2401 " 2418 2402 ) 2419 2403 ) 2420 2404 *63 (Net 2421 uid 2267,02422 decl (Decl2423 n "CLK_50"2424 t "std_logic"2425 preAdd 02426 posAdd 02427 o 512428 suid 54,02429 )2430 declText (MLText2431 uid 2268,02432 va (VaSet2433 font "Courier New,8,0"2434 )2435 xt "39000,44800,57000,45600"2436 st "SIGNAL CLK_50 : std_logic"2437 )2438 )2439 *64 (Net2440 2405 uid 2407,0 2441 2406 decl (Decl … … 2452 2417 ) 2453 2418 xt "39000,31000,68000,31800" 2454 st "RSRLOAD : std_logic := '0'" 2455 ) 2456 ) 2457 *65 (PortIoOut 2419 st "RSRLOAD : std_logic := '0' 2420 " 2421 ) 2422 ) 2423 *64 (PortIoOut 2458 2424 uid 2415,0 2459 2425 shape (CompositeShape … … 2500 2466 ) 2501 2467 ) 2502 *6 6(Net2468 *65 (Net 2503 2469 uid 2421,0 2504 2470 decl (Decl … … 2515 2481 ) 2516 2482 xt "39000,45600,71500,46400" 2517 st "SIGNAL SRCLK : std_logic := '0'" 2518 ) 2519 ) 2520 *67 (Net 2483 st "SIGNAL SRCLK : std_logic := '0' 2484 " 2485 ) 2486 ) 2487 *66 (Net 2521 2488 uid 3019,0 2522 2489 decl (Decl … … 2533 2500 ) 2534 2501 xt "39000,51200,67000,52000" 2535 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2536 ) 2537 ) 2538 *68 (Net 2502 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0) 2503 " 2504 ) 2505 ) 2506 *67 (Net 2539 2507 uid 3025,0 2540 2508 decl (Decl … … 2550 2518 ) 2551 2519 xt "39000,19800,53500,20600" 2552 st "DAC_CS : std_logic" 2553 ) 2554 ) 2555 *69 (PortIoOut 2520 st "DAC_CS : std_logic 2521 " 2522 ) 2523 ) 2524 *68 (PortIoOut 2556 2525 uid 3153,0 2557 2526 shape (CompositeShape … … 2598 2567 ) 2599 2568 ) 2600 * 70(Net2569 *69 (Net 2601 2570 uid 3216,0 2602 2571 decl (Decl … … 2614 2583 ) 2615 2584 xt "39000,14200,53500,15000" 2616 st "X_50M : STD_LOGIC" 2617 ) 2618 ) 2619 *71 (Net 2585 st "X_50M : STD_LOGIC 2586 " 2587 ) 2588 ) 2589 *70 (Net 2620 2590 uid 3226,0 2621 2591 decl (Decl … … 2631 2601 ) 2632 2602 xt "39000,12600,53500,13400" 2633 st "TRG : STD_LOGIC" 2634 ) 2635 ) 2636 *72 (HdlText 2603 st "TRG : STD_LOGIC 2604 " 2605 ) 2606 ) 2607 *71 (HdlText 2637 2608 uid 3248,0 2638 2609 optionalChildren [ 2639 *7 3(EmbeddedText2610 *72 (EmbeddedText 2640 2611 uid 3254,0 2641 2612 commentText (CommentText … … 2689 2660 stg "VerticalLayoutStrategy" 2690 2661 textVec [ 2691 *7 4(Text2662 *73 (Text 2692 2663 uid 3251,0 2693 2664 va (VaSet … … 2699 2670 tm "HdlTextNameMgr" 2700 2671 ) 2701 *7 5(Text2672 *74 (Text 2702 2673 uid 3252,0 2703 2674 va (VaSet … … 2725 2696 viewiconposition 0 2726 2697 ) 2727 *7 6(Net2698 *75 (Net 2728 2699 uid 3266,0 2729 2700 decl (Decl … … 2740 2711 ) 2741 2712 xt "39000,15800,63500,16600" 2742 st "A_CLK : std_logic_vector(3 downto 0)" 2743 ) 2744 ) 2745 *77 (Net 2713 st "A_CLK : std_logic_vector(3 downto 0) 2714 " 2715 ) 2716 ) 2717 *76 (Net 2746 2718 uid 3268,0 2747 2719 decl (Decl … … 2757 2729 ) 2758 2730 xt "39000,44000,57000,44800" 2759 st "SIGNAL CLK_25_PS : std_logic" 2760 ) 2761 ) 2762 *78 (PortIoOut 2731 st "SIGNAL CLK_25_PS : std_logic 2732 " 2733 ) 2734 ) 2735 *77 (PortIoOut 2763 2736 uid 3284,0 2764 2737 shape (CompositeShape … … 2805 2778 ) 2806 2779 ) 2807 *7 9(Net2780 *78 (Net 2808 2781 uid 3290,0 2809 2782 decl (Decl … … 2821 2794 ) 2822 2795 xt "39000,27000,53500,27800" 2823 st "OE_ADC : STD_LOGIC" 2824 ) 2825 ) 2826 *80 (PortIoIn 2796 st "OE_ADC : STD_LOGIC 2797 " 2798 ) 2799 ) 2800 *79 (PortIoIn 2827 2801 uid 3292,0 2828 2802 shape (CompositeShape … … 2869 2843 ) 2870 2844 ) 2871 *8 1(Net2845 *80 (Net 2872 2846 uid 3298,0 2873 2847 decl (Decl … … 2884 2858 ) 2885 2859 xt "39000,7000,63500,7800" 2886 st "A_OTR : std_logic_vector(3 DOWNTO 0)" 2887 ) 2888 ) 2889 *82 (HdlText 2860 st "A_OTR : std_logic_vector(3 DOWNTO 0) 2861 " 2862 ) 2863 ) 2864 *81 (HdlText 2890 2865 uid 3300,0 2891 2866 optionalChildren [ 2892 *8 3(EmbeddedText2867 *82 (EmbeddedText 2893 2868 uid 3306,0 2894 2869 commentText (CommentText … … 2942 2917 stg "VerticalLayoutStrategy" 2943 2918 textVec [ 2944 *8 4(Text2919 *83 (Text 2945 2920 uid 3303,0 2946 2921 va (VaSet … … 2952 2927 tm "HdlTextNameMgr" 2953 2928 ) 2954 *8 5(Text2929 *84 (Text 2955 2930 uid 3304,0 2956 2931 va (VaSet … … 2978 2953 viewiconposition 0 2979 2954 ) 2980 *8 6(PortIoIn2955 *85 (PortIoIn 2981 2956 uid 3310,0 2982 2957 shape (CompositeShape … … 3023 2998 ) 3024 2999 ) 3025 *8 7(PortIoIn3000 *86 (PortIoIn 3026 3001 uid 3332,0 3027 3002 shape (CompositeShape … … 3068 3043 ) 3069 3044 ) 3070 *8 8(PortIoIn3045 *87 (PortIoIn 3071 3046 uid 3338,0 3072 3047 shape (CompositeShape … … 3113 3088 ) 3114 3089 ) 3115 *8 9(PortIoIn3090 *88 (PortIoIn 3116 3091 uid 3344,0 3117 3092 shape (CompositeShape … … 3158 3133 ) 3159 3134 ) 3160 * 90(Net3135 *89 (Net 3161 3136 uid 3374,0 3162 3137 decl (Decl … … 3173 3148 ) 3174 3149 xt "39000,3800,64000,4600" 3175 st "A0_D : std_logic_vector(11 DOWNTO 0)" 3176 ) 3177 ) 3178 *91 (Net 3150 st "A0_D : std_logic_vector(11 DOWNTO 0) 3151 " 3152 ) 3153 ) 3154 *90 (Net 3179 3155 uid 3376,0 3180 3156 decl (Decl … … 3191 3167 ) 3192 3168 xt "39000,4600,64000,5400" 3193 st "A1_D : std_logic_vector(11 DOWNTO 0)" 3194 ) 3195 ) 3196 *92 (Net 3169 st "A1_D : std_logic_vector(11 DOWNTO 0) 3170 " 3171 ) 3172 ) 3173 *91 (Net 3197 3174 uid 3378,0 3198 3175 decl (Decl … … 3209 3186 ) 3210 3187 xt "39000,5400,64000,6200" 3211 st "A2_D : std_logic_vector(11 DOWNTO 0)" 3212 ) 3213 ) 3214 *93 (Net 3188 st "A2_D : std_logic_vector(11 DOWNTO 0) 3189 " 3190 ) 3191 ) 3192 *92 (Net 3215 3193 uid 3380,0 3216 3194 decl (Decl … … 3227 3205 ) 3228 3206 xt "39000,6200,64000,7000" 3229 st "A3_D : std_logic_vector(11 DOWNTO 0)" 3230 ) 3231 ) 3232 *94 (HdlText 3207 st "A3_D : std_logic_vector(11 DOWNTO 0) 3208 " 3209 ) 3210 ) 3211 *93 (HdlText 3233 3212 uid 3394,0 3234 3213 optionalChildren [ 3235 *9 5(EmbeddedText3214 *94 (EmbeddedText 3236 3215 uid 3400,0 3237 3216 commentText (CommentText … … 3285 3264 stg "VerticalLayoutStrategy" 3286 3265 textVec [ 3287 *9 6(Text3266 *95 (Text 3288 3267 uid 3397,0 3289 3268 va (VaSet … … 3295 3274 tm "HdlTextNameMgr" 3296 3275 ) 3297 *9 7(Text3276 *96 (Text 3298 3277 uid 3398,0 3299 3278 va (VaSet … … 3321 3300 viewiconposition 0 3322 3301 ) 3323 *9 8(Net3302 *97 (Net 3324 3303 uid 3460,0 3325 3304 decl (Decl … … 3335 3314 ) 3336 3315 xt "39000,16600,53500,17400" 3337 st "D0_SRCLK : STD_LOGIC" 3338 ) 3339 ) 3340 *99 (Net 3316 st "D0_SRCLK : STD_LOGIC 3317 " 3318 ) 3319 ) 3320 *98 (Net 3341 3321 uid 3462,0 3342 3322 decl (Decl … … 3352 3332 ) 3353 3333 xt "39000,17400,53500,18200" 3354 st "D1_SRCLK : STD_LOGIC" 3355 ) 3356 ) 3357 *100 (Net 3334 st "D1_SRCLK : STD_LOGIC 3335 " 3336 ) 3337 ) 3338 *99 (Net 3358 3339 uid 3464,0 3359 3340 decl (Decl … … 3369 3350 ) 3370 3351 xt "39000,18200,53500,19000" 3371 st "D2_SRCLK : STD_LOGIC" 3372 ) 3373 ) 3374 *101 (Net 3352 st "D2_SRCLK : STD_LOGIC 3353 " 3354 ) 3355 ) 3356 *100 (Net 3375 3357 uid 3466,0 3376 3358 decl (Decl … … 3386 3368 ) 3387 3369 xt "39000,19000,53500,19800" 3388 st "D3_SRCLK : STD_LOGIC" 3389 ) 3390 ) 3391 *102 (PortIoIn 3370 st "D3_SRCLK : STD_LOGIC 3371 " 3372 ) 3373 ) 3374 *101 (PortIoIn 3392 3375 uid 3476,0 3393 3376 shape (CompositeShape … … 3434 3417 ) 3435 3418 ) 3436 *10 3(PortIoIn3419 *102 (PortIoIn 3437 3420 uid 3482,0 3438 3421 shape (CompositeShape … … 3479 3462 ) 3480 3463 ) 3481 *10 4(PortIoIn3464 *103 (PortIoIn 3482 3465 uid 3488,0 3483 3466 shape (CompositeShape … … 3524 3507 ) 3525 3508 ) 3526 *10 5(PortIoIn3509 *104 (PortIoIn 3527 3510 uid 3494,0 3528 3511 shape (CompositeShape … … 3569 3552 ) 3570 3553 ) 3571 *10 6(Net3554 *105 (Net 3572 3555 uid 3500,0 3573 3556 decl (Decl … … 3583 3566 ) 3584 3567 xt "39000,7800,53500,8600" 3585 st "D0_SROUT : std_logic" 3586 ) 3587 ) 3588 *107 (Net 3568 st "D0_SROUT : std_logic 3569 " 3570 ) 3571 ) 3572 *106 (Net 3589 3573 uid 3502,0 3590 3574 decl (Decl … … 3600 3584 ) 3601 3585 xt "39000,8600,53500,9400" 3602 st "D1_SROUT : std_logic" 3603 ) 3604 ) 3605 *108 (Net 3586 st "D1_SROUT : std_logic 3587 " 3588 ) 3589 ) 3590 *107 (Net 3606 3591 uid 3504,0 3607 3592 decl (Decl … … 3617 3602 ) 3618 3603 xt "39000,9400,53500,10200" 3619 st "D2_SROUT : std_logic" 3620 ) 3621 ) 3622 *109 (Net 3604 st "D2_SROUT : std_logic 3605 " 3606 ) 3607 ) 3608 *108 (Net 3623 3609 uid 3506,0 3624 3610 decl (Decl … … 3634 3620 ) 3635 3621 xt "39000,10200,53500,11000" 3636 st "D3_SROUT : std_logic" 3637 ) 3638 ) 3639 *110 (PortIoOut 3622 st "D3_SROUT : std_logic 3623 " 3624 ) 3625 ) 3626 *109 (PortIoOut 3640 3627 uid 3508,0 3641 3628 shape (CompositeShape … … 3650 3637 sl 0 3651 3638 ro 90 3652 xt " 19000,108625,20500,109375"3639 xt "4000,133625,5500,134375" 3653 3640 ) 3654 3641 (Line … … 3656 3643 sl 0 3657 3644 ro 90 3658 xt " 20500,109000,21000,109000"3659 pts [ 3660 " 21000,109000"3661 " 20500,109000"3645 xt "5500,134000,6000,134000" 3646 pts [ 3647 "6000,134000" 3648 "5500,134000" 3662 3649 ] 3663 3650 ) … … 3674 3661 va (VaSet 3675 3662 ) 3676 xt "1 6100,108500,18000,109500"3663 xt "1100,133500,3000,134500" 3677 3664 st "D_A" 3678 3665 ju 2 3679 blo " 18000,109300"3666 blo "3000,134300" 3680 3667 tm "WireNameMgr" 3681 3668 ) 3682 3669 ) 3683 3670 ) 3684 *11 1(Net3671 *110 (Net 3685 3672 uid 3514,0 3686 3673 decl (Decl … … 3698 3685 ) 3699 3686 xt "39000,22200,74000,23000" 3700 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 3701 ) 3702 ) 3703 *112 (PortIoOut 3687 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0') 3688 " 3689 ) 3690 ) 3691 *111 (PortIoOut 3704 3692 uid 3516,0 3705 3693 shape (CompositeShape … … 3746 3734 ) 3747 3735 ) 3748 *11 3(Net3736 *112 (Net 3749 3737 uid 3522,0 3750 3738 decl (Decl … … 3761 3749 ) 3762 3750 xt "39000,21400,68000,22200" 3763 st "DWRITE : std_logic := '0'" 3764 ) 3765 ) 3766 *114 (PortIoOut 3751 st "DWRITE : std_logic := '0' 3752 " 3753 ) 3754 ) 3755 *113 (PortIoOut 3767 3756 uid 3536,0 3768 3757 shape (CompositeShape … … 3808 3797 ) 3809 3798 ) 3810 *11 5(HdlText3799 *114 (HdlText 3811 3800 uid 3542,0 3812 3801 optionalChildren [ 3813 *11 6(EmbeddedText3802 *115 (EmbeddedText 3814 3803 uid 3612,0 3815 3804 commentText (CommentText … … 3863 3852 stg "VerticalLayoutStrategy" 3864 3853 textVec [ 3865 *11 7(Text3854 *116 (Text 3866 3855 uid 3545,0 3867 3856 va (VaSet … … 3873 3862 tm "HdlTextNameMgr" 3874 3863 ) 3875 *11 8(Text3864 *117 (Text 3876 3865 uid 3546,0 3877 3866 va (VaSet … … 3899 3888 viewiconposition 0 3900 3889 ) 3901 *11 9(PortIoOut3890 *118 (PortIoOut 3902 3891 uid 3548,0 3903 3892 shape (CompositeShape … … 3943 3932 ) 3944 3933 ) 3945 *1 20(PortIoOut3934 *119 (PortIoOut 3946 3935 uid 3554,0 3947 3936 shape (CompositeShape … … 3987 3976 ) 3988 3977 ) 3989 *12 1(PortIoOut3978 *120 (PortIoOut 3990 3979 uid 3560,0 3991 3980 shape (CompositeShape … … 4031 4020 ) 4032 4021 ) 4033 *12 2(PortIoOut4022 *121 (PortIoOut 4034 4023 uid 3566,0 4035 4024 shape (CompositeShape … … 4075 4064 ) 4076 4065 ) 4077 *12 3(Net4066 *122 (Net 4078 4067 uid 3604,0 4079 4068 decl (Decl … … 4089 4078 ) 4090 4079 xt "39000,33400,53500,34200" 4091 st "T0_CS : std_logic" 4092 ) 4093 ) 4094 *124 (Net 4080 st "T0_CS : std_logic 4081 " 4082 ) 4083 ) 4084 *123 (Net 4095 4085 uid 3606,0 4096 4086 decl (Decl … … 4106 4096 ) 4107 4097 xt "39000,34200,53500,35000" 4108 st "T1_CS : std_logic" 4109 ) 4110 ) 4111 *125 (Net 4098 st "T1_CS : std_logic 4099 " 4100 ) 4101 ) 4102 *124 (Net 4112 4103 uid 3608,0 4113 4104 decl (Decl … … 4123 4114 ) 4124 4115 xt "39000,35000,53500,35800" 4125 st "T2_CS : std_logic" 4126 ) 4127 ) 4128 *126 (Net 4116 st "T2_CS : std_logic 4117 " 4118 ) 4119 ) 4120 *125 (Net 4129 4121 uid 3610,0 4130 4122 decl (Decl … … 4140 4132 ) 4141 4133 xt "39000,35800,53500,36600" 4142 st "T3_CS : std_logic" 4143 ) 4144 ) 4145 *127 (PortIoOut 4134 st "T3_CS : std_logic 4135 " 4136 ) 4137 ) 4138 *126 (PortIoOut 4146 4139 uid 3624,0 4147 4140 shape (CompositeShape … … 4187 4180 ) 4188 4181 ) 4189 *12 8(Net4182 *127 (Net 4190 4183 uid 3630,0 4191 4184 decl (Decl … … 4201 4194 ) 4202 4195 xt "39000,32600,53500,33400" 4203 st "S_CLK : std_logic" 4204 ) 4205 ) 4206 *129 (Net 4196 st "S_CLK : std_logic 4197 " 4198 ) 4199 ) 4200 *128 (Net 4207 4201 uid 3632,0 4208 4202 decl (Decl … … 4219 4213 ) 4220 4214 xt "39000,37400,63500,38200" 4221 st "W_A : std_logic_vector(9 DOWNTO 0)" 4222 ) 4223 ) 4224 *130 (Net 4215 st "W_A : std_logic_vector(9 DOWNTO 0) 4216 " 4217 ) 4218 ) 4219 *129 (Net 4225 4220 uid 3634,0 4226 4221 decl (Decl … … 4237 4232 ) 4238 4233 xt "39000,42200,64000,43000" 4239 st "W_D : std_logic_vector(15 DOWNTO 0)" 4240 ) 4241 ) 4242 *131 (Net 4234 st "W_D : std_logic_vector(15 DOWNTO 0) 4235 " 4236 ) 4237 ) 4238 *130 (Net 4243 4239 uid 3636,0 4244 4240 decl (Decl … … 4255 4251 ) 4256 4252 xt "39000,39800,68000,40600" 4257 st "W_RES : std_logic := '1'" 4258 ) 4259 ) 4260 *132 (Net 4253 st "W_RES : std_logic := '1' 4254 " 4255 ) 4256 ) 4257 *131 (Net 4261 4258 uid 3638,0 4262 4259 decl (Decl … … 4273 4270 ) 4274 4271 xt "39000,39000,68000,39800" 4275 st "W_RD : std_logic := '1'" 4276 ) 4277 ) 4278 *133 (Net 4272 st "W_RD : std_logic := '1' 4273 " 4274 ) 4275 ) 4276 *132 (Net 4279 4277 uid 3640,0 4280 4278 decl (Decl … … 4291 4289 ) 4292 4290 xt "39000,40600,68000,41400" 4293 st "W_WR : std_logic := '1'" 4294 ) 4295 ) 4296 *134 (Net 4291 st "W_WR : std_logic := '1' 4292 " 4293 ) 4294 ) 4295 *133 (Net 4297 4296 uid 3642,0 4298 4297 decl (Decl … … 4308 4307 ) 4309 4308 xt "39000,13400,53500,14200" 4310 st "W_INT : std_logic" 4311 ) 4312 ) 4313 *135 (Net 4309 st "W_INT : std_logic 4310 " 4311 ) 4312 ) 4313 *134 (Net 4314 4314 uid 3644,0 4315 4315 decl (Decl … … 4326 4326 ) 4327 4327 xt "39000,38200,68000,39000" 4328 st "W_CS : std_logic := '1'" 4329 ) 4330 ) 4331 *136 (PortIoInOut 4328 st "W_CS : std_logic := '1' 4329 " 4330 ) 4331 ) 4332 *135 (PortIoInOut 4332 4333 uid 3674,0 4333 4334 shape (CompositeShape … … 4371 4372 ) 4372 4373 ) 4373 *13 7(Net4374 *136 (Net 4374 4375 uid 3680,0 4375 4376 decl (Decl … … 4386 4387 ) 4387 4388 xt "39000,26200,68000,27000" 4388 st "MOSI : std_logic := '0'" 4389 ) 4390 ) 4391 *138 (PortIoOut 4389 st "MOSI : std_logic := '0' 4390 " 4391 ) 4392 ) 4393 *137 (PortIoOut 4392 4394 uid 3688,0 4393 4395 shape (CompositeShape … … 4433 4435 ) 4434 4436 ) 4435 *13 9(Net4437 *138 (Net 4436 4438 uid 3694,0 4437 4439 decl (Decl … … 4449 4451 ) 4450 4452 xt "39000,41400,53500,42200" 4451 st "MISO : std_logic" 4452 ) 4453 ) 4454 *140 (HdlText 4453 st "MISO : std_logic 4454 " 4455 ) 4456 ) 4457 *139 (HdlText 4455 4458 uid 3700,0 4456 4459 optionalChildren [ 4457 *14 1(EmbeddedText4460 *140 (EmbeddedText 4458 4461 uid 3706,0 4459 4462 commentText (CommentText … … 4522 4525 stg "VerticalLayoutStrategy" 4523 4526 textVec [ 4524 *14 2(Text4527 *141 (Text 4525 4528 uid 3703,0 4526 4529 va (VaSet … … 4532 4535 tm "HdlTextNameMgr" 4533 4536 ) 4534 *14 3(Text4537 *142 (Text 4535 4538 uid 3704,0 4536 4539 va (VaSet … … 4558 4561 viewiconposition 0 4559 4562 ) 4560 *14 4(PortIoOut4563 *143 (PortIoOut 4561 4564 uid 3710,0 4562 4565 shape (CompositeShape … … 4602 4605 ) 4603 4606 ) 4604 *14 5(PortIoOut4607 *144 (PortIoOut 4605 4608 uid 3716,0 4606 4609 shape (CompositeShape … … 4646 4649 ) 4647 4650 ) 4648 *14 6(PortIoOut4651 *145 (PortIoOut 4649 4652 uid 3722,0 4650 4653 shape (CompositeShape … … 4690 4693 ) 4691 4694 ) 4692 *14 7(PortIoOut4695 *146 (PortIoOut 4693 4696 uid 3728,0 4694 4697 shape (CompositeShape … … 4734 4737 ) 4735 4738 ) 4736 *14 8(PortIoOut4739 *147 (PortIoOut 4737 4740 uid 3734,0 4738 4741 shape (CompositeShape … … 4778 4781 ) 4779 4782 ) 4780 *14 9(PortIoOut4783 *148 (PortIoOut 4781 4784 uid 3740,0 4782 4785 shape (CompositeShape … … 4822 4825 ) 4823 4826 ) 4824 *1 50(PortIoOut4827 *149 (PortIoOut 4825 4828 uid 3746,0 4826 4829 shape (CompositeShape … … 4866 4869 ) 4867 4870 ) 4868 *15 1(PortIoOut4871 *150 (PortIoOut 4869 4872 uid 3752,0 4870 4873 shape (CompositeShape … … 4910 4913 ) 4911 4914 ) 4912 *15 2(PortIoOut4915 *151 (PortIoOut 4913 4916 uid 3758,0 4914 4917 shape (CompositeShape … … 4954 4957 ) 4955 4958 ) 4956 *15 3(Net4959 *152 (Net 4957 4960 uid 3864,0 4958 4961 decl (Decl … … 4968 4971 ) 4969 4972 xt "39000,36600,53500,37400" 4970 st "TRG_V : std_logic" 4971 ) 4972 ) 4973 *154 (Net 4973 st "TRG_V : std_logic 4974 " 4975 ) 4976 ) 4977 *153 (Net 4974 4978 uid 3866,0 4975 4979 decl (Decl … … 4985 4989 ) 4986 4990 xt "39000,28600,53500,29400" 4987 st "RS485_C_RE : std_logic" 4988 ) 4989 ) 4990 *155 (Net 4991 st "RS485_C_RE : std_logic 4992 " 4993 ) 4994 ) 4995 *154 (Net 4991 4996 uid 3868,0 4992 4997 decl (Decl … … 5002 5007 ) 5003 5008 xt "39000,27800,53500,28600" 5004 st "RS485_C_DE : std_logic" 5005 ) 5006 ) 5007 *156 (Net 5009 st "RS485_C_DE : std_logic 5010 " 5011 ) 5012 ) 5013 *155 (Net 5008 5014 uid 3870,0 5009 5015 decl (Decl … … 5019 5025 ) 5020 5026 xt "39000,30200,53500,31000" 5021 st "RS485_E_RE : std_logic" 5022 ) 5023 ) 5024 *157 (Net 5027 st "RS485_E_RE : std_logic 5028 " 5029 ) 5030 ) 5031 *156 (Net 5025 5032 uid 3872,0 5026 5033 decl (Decl … … 5036 5043 ) 5037 5044 xt "39000,29400,53500,30200" 5038 st "RS485_E_DE : std_logic" 5039 ) 5040 ) 5041 *158 (Net 5045 st "RS485_E_DE : std_logic 5046 " 5047 ) 5048 ) 5049 *157 (Net 5042 5050 uid 3874,0 5043 5051 decl (Decl … … 5054 5062 ) 5055 5063 xt "39000,20600,68000,21400" 5056 st "DENABLE : std_logic := '0'" 5057 ) 5058 ) 5059 *159 (Net 5064 st "DENABLE : std_logic := '0' 5065 " 5066 ) 5067 ) 5068 *158 (Net 5060 5069 uid 3876,0 5061 5070 decl (Decl … … 5071 5080 ) 5072 5081 xt "39000,31800,53500,32600" 5073 st "SRIN : std_logic" 5074 ) 5075 ) 5076 *160 (Net 5082 st "SRIN : std_logic 5083 " 5084 ) 5085 ) 5086 *159 (Net 5077 5087 uid 3878,0 5078 5088 decl (Decl … … 5088 5098 ) 5089 5099 xt "39000,24600,53500,25400" 5090 st "EE_CS : std_logic" 5091 ) 5092 ) 5093 *161 (Net 5100 st "EE_CS : std_logic 5101 " 5102 ) 5103 ) 5104 *160 (Net 5094 5105 uid 3880,0 5095 5106 decl (Decl … … 5107 5118 ) 5108 5119 xt "39000,25400,74000,26200" 5109 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" 5110 ) 5111 ) 5112 *162 (PortIoOut 5120 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1') 5121 " 5122 ) 5123 ) 5124 *161 (PortIoOut 5113 5125 uid 3995,0 5114 5126 shape (CompositeShape … … 5155 5167 ) 5156 5168 ) 5157 *16 3(PortIoOut5169 *162 (PortIoOut 5158 5170 uid 4001,0 5159 5171 shape (CompositeShape … … 5200 5212 ) 5201 5213 ) 5202 *16 4(PortIoOut5214 *163 (PortIoOut 5203 5215 uid 4007,0 5204 5216 shape (CompositeShape … … 5245 5257 ) 5246 5258 ) 5247 *16 5(PortIoOut5259 *164 (PortIoOut 5248 5260 uid 4013,0 5249 5261 shape (CompositeShape … … 5290 5302 ) 5291 5303 ) 5292 *16 6(PortIoOut5304 *165 (PortIoOut 5293 5305 uid 4916,0 5294 5306 shape (CompositeShape … … 5334 5346 ) 5335 5347 ) 5336 *16 7(Net5348 *166 (Net 5337 5349 uid 5320,0 5338 5350 decl (Decl … … 5350 5362 ) 5351 5363 xt "39000,23000,74000,23800" 5352 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5353 ) 5354 ) 5355 *168 (PortIoIn 5364 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 5365 " 5366 ) 5367 ) 5368 *167 (PortIoIn 5356 5369 uid 5650,0 5357 5370 shape (CompositeShape … … 5366 5379 sl 0 5367 5380 ro 270 5368 xt " -30000,88625,-28500,89375"5381 xt "9000,78625,10500,79375" 5369 5382 ) 5370 5383 (Line … … 5372 5385 sl 0 5373 5386 ro 270 5374 xt " -28500,89000,-28000,89000"5375 pts [ 5376 " -28500,89000"5377 " -28000,89000"5387 xt "10500,79000,11000,79000" 5388 pts [ 5389 "10500,79000" 5390 "11000,79000" 5378 5391 ] 5379 5392 ) … … 5390 5403 va (VaSet 5391 5404 ) 5392 xt " -35500,88500,-31000,89500"5405 xt "3500,78500,8000,79500" 5393 5406 st "TEST_TRG" 5394 5407 ju 2 5395 blo " -31000,89300"5408 blo "8000,79300" 5396 5409 tm "WireNameMgr" 5397 5410 ) 5398 5411 ) 5399 5412 ) 5400 *16 9(Net5413 *168 (Net 5401 5414 uid 5662,0 5402 5415 decl (Decl … … 5412 5425 ) 5413 5426 xt "39000,11800,53500,12600" 5414 st "TEST_TRG : std_logic" 5415 ) 5416 ) 5417 *170 (Net 5427 st "TEST_TRG : std_logic 5428 " 5429 ) 5430 ) 5431 *169 (Net 5418 5432 uid 6138,0 5419 5433 decl (Decl … … 5429 5443 ) 5430 5444 xt "39000,46400,57000,47200" 5431 st "SIGNAL TRG_OR : std_logic" 5432 ) 5433 ) 5434 *171 (SaComponent 5435 uid 6250,0 5436 optionalChildren [ 5437 *172 (CptPort 5438 uid 6235,0 5439 ps "OnEdgeStrategy" 5440 shape (Triangle 5441 uid 6236,0 5442 ro 90 5443 va (VaSet 5444 vasetType 1 5445 fg "0,65535,0" 5446 ) 5447 xt "-11750,87625,-11000,88375" 5448 ) 5449 tg (CPTG 5450 uid 6237,0 5451 ps "CptPortTextPlaceStrategy" 5452 stg "VerticalLayoutStrategy" 5453 f (Text 5454 uid 6238,0 5455 va (VaSet 5456 ) 5457 xt "-10000,87500,-8700,88500" 5458 st "clk" 5459 blo "-10000,88300" 5460 ) 5461 ) 5462 thePort (LogicalPort 5463 decl (Decl 5464 n "clk" 5465 t "STD_LOGIC" 5466 preAdd 0 5467 posAdd 0 5468 o 1 5469 suid 1,0 5470 ) 5471 ) 5472 ) 5473 *173 (CptPort 5474 uid 6239,0 5475 ps "OnEdgeStrategy" 5476 shape (Triangle 5477 uid 6240,0 5478 ro 90 5479 va (VaSet 5480 vasetType 1 5481 fg "0,65535,0" 5482 ) 5483 xt "-11750,88625,-11000,89375" 5484 ) 5485 tg (CPTG 5486 uid 6241,0 5487 ps "CptPortTextPlaceStrategy" 5488 stg "VerticalLayoutStrategy" 5489 f (Text 5490 uid 6242,0 5491 va (VaSet 5492 ) 5493 xt "-10000,88500,-5800,89500" 5494 st "trigger_in" 5495 blo "-10000,89300" 5496 ) 5497 ) 5498 thePort (LogicalPort 5499 decl (Decl 5500 n "trigger_in" 5501 t "STD_LOGIC" 5502 prec "-- rst : in STD_LOGIC;" 5503 preAdd 0 5504 posAdd 0 5505 o 2 5506 suid 2,0 5507 ) 5508 ) 5509 ) 5510 *174 (CptPort 5511 uid 6243,0 5512 ps "OnEdgeStrategy" 5513 shape (Triangle 5514 uid 6244,0 5515 ro 90 5516 va (VaSet 5517 vasetType 1 5518 fg "0,65535,0" 5519 ) 5520 xt "1000,88625,1750,89375" 5521 ) 5522 tg (CPTG 5523 uid 6245,0 5524 ps "CptPortTextPlaceStrategy" 5525 stg "RightVerticalLayoutStrategy" 5526 f (Text 5527 uid 6246,0 5528 va (VaSet 5529 ) 5530 xt "-4600,88500,0,89500" 5531 st "trigger_out" 5532 ju 2 5533 blo "0,89300" 5534 ) 5535 ) 5536 thePort (LogicalPort 5537 m 1 5538 decl (Decl 5539 n "trigger_out" 5540 t "STD_LOGIC" 5541 preAdd 0 5542 posAdd 0 5543 o 3 5544 suid 3,0 5545 i "'0'" 5546 ) 5547 ) 5548 ) 5549 ] 5550 shape (Rectangle 5551 uid 6251,0 5552 va (VaSet 5553 vasetType 1 5554 fg "0,65535,0" 5555 lineColor "0,32896,0" 5556 lineWidth 2 5557 ) 5558 xt "-11000,87000,1000,92000" 5559 ) 5560 oxt "25000,13000,37000,18000" 5561 ttg (MlTextGroup 5562 uid 6252,0 5563 ps "CenterOffsetStrategy" 5564 stg "VerticalLayoutStrategy" 5565 textVec [ 5566 *175 (Text 5567 uid 6253,0 5568 va (VaSet 5569 font "Arial,8,1" 5570 ) 5571 xt "-10800,92000,-4200,93000" 5572 st "FACT_FAD_LIB" 5573 blo "-10800,92800" 5574 tm "BdLibraryNameMgr" 5575 ) 5576 *176 (Text 5577 uid 6254,0 5578 va (VaSet 5579 font "Arial,8,1" 5580 ) 5581 xt "-10800,93000,-6400,94000" 5582 st "debouncer" 5583 blo "-10800,93800" 5584 tm "CptNameMgr" 5585 ) 5586 *177 (Text 5587 uid 6255,0 5588 va (VaSet 5589 font "Arial,8,1" 5590 ) 5591 xt "-10800,94000,-5400,95000" 5592 st "I_debouncer" 5593 blo "-10800,94800" 5594 tm "InstanceNameMgr" 5595 ) 5596 ] 5597 ) 5598 ga (GenericAssociation 5599 uid 6256,0 5600 ps "EdgeToEdgeStrategy" 5601 matrix (Matrix 5602 uid 6257,0 5603 text (MLText 5604 uid 6258,0 5605 va (VaSet 5606 font "Courier New,8,0" 5607 ) 5608 xt "-11000,86200,4000,87000" 5609 st "WIDTH = 17 ( INTEGER ) " 5610 ) 5611 header "" 5612 ) 5613 elements [ 5614 (GiElement 5615 name "WIDTH" 5616 type "INTEGER" 5617 value "17" 5618 ) 5619 ] 5620 ) 5621 viewicon (ZoomableIcon 5622 uid 6259,0 5623 sl 0 5624 va (VaSet 5625 vasetType 1 5626 fg "49152,49152,49152" 5627 ) 5628 xt "-10750,90250,-9250,91750" 5629 iconName "VhdlFileViewIcon.png" 5630 iconMaskName "VhdlFileViewIcon.msk" 5631 ftype 10 5632 ) 5633 ordering 1 5634 viewiconposition 0 5635 portVis (PortSigDisplay 5636 ) 5637 archFileType "UNKNOWN" 5638 ) 5639 *178 (Net 5640 uid 6278,0 5641 decl (Decl 5642 n "trigger_out" 5643 t "STD_LOGIC" 5644 preAdd 0 5645 posAdd 0 5646 o 60 5647 suid 147,0 5648 i "'0'" 5649 ) 5650 declText (MLText 5651 uid 6279,0 5652 va (VaSet 5653 font "Courier New,8,0" 5654 ) 5655 xt "39000,52000,71500,52800" 5656 st "SIGNAL trigger_out : STD_LOGIC := '0'" 5657 ) 5658 ) 5659 *179 (Net 5660 uid 6326,0 5661 decl (Decl 5662 n "not_TEST_TRG" 5663 t "STD_LOGIC" 5664 o 58 5665 suid 148,0 5666 ) 5667 declText (MLText 5668 uid 6327,0 5669 va (VaSet 5670 font "Courier New,8,0" 5671 ) 5672 xt "39000,50400,57000,51200" 5673 st "SIGNAL not_TEST_TRG : STD_LOGIC" 5674 ) 5675 ) 5676 *180 (MWC 5677 uid 6539,0 5678 optionalChildren [ 5679 *181 (CptPort 5680 uid 6526,0 5681 optionalChildren [ 5682 *182 (Line 5683 uid 6530,0 5684 layer 5 5685 sl 0 5686 va (VaSet 5687 vasetType 3 5688 ) 5689 xt "-22000,89000,-20999,89000" 5690 pts [ 5691 "-22000,89000" 5692 "-20999,89000" 5693 ] 5694 ) 5695 ] 5696 ps "OnEdgeStrategy" 5697 shape (Triangle 5698 uid 6527,0 5699 ro 90 5700 va (VaSet 5701 vasetType 1 5702 isHidden 1 5703 fg "0,65535,65535" 5704 ) 5705 xt "-22750,88625,-22000,89375" 5706 ) 5707 tg (CPTG 5708 uid 6528,0 5709 ps "CptPortTextPlaceStrategy" 5710 stg "VerticalLayoutStrategy" 5711 f (Text 5712 uid 6529,0 5713 sl 0 5714 va (VaSet 5715 isHidden 1 5716 font "arial,8,0" 5717 ) 5718 xt "-25000,88500,-23600,89500" 5719 st "din" 5720 blo "-25000,89300" 5721 ) 5722 s (Text 5723 uid 6548,0 5724 sl 0 5725 va (VaSet 5726 font "arial,8,0" 5727 ) 5728 xt "-25000,89500,-25000,89500" 5729 blo "-25000,89500" 5730 ) 5731 ) 5732 thePort (LogicalPort 5733 decl (Decl 5734 n "din" 5735 t "std_logic" 5736 o 11 5737 suid 1,0 5738 ) 5739 ) 5740 ) 5741 *183 (CptPort 5742 uid 6531,0 5743 optionalChildren [ 5744 *184 (Line 5745 uid 6535,0 5746 layer 5 5747 sl 0 5748 va (VaSet 5749 vasetType 3 5750 ) 5751 xt "-17249,89000,-17000,89000" 5752 pts [ 5753 "-17000,89000" 5754 "-17249,89000" 5755 ] 5756 ) 5757 *185 (Circle 5758 uid 6536,0 5759 va (VaSet 5760 vasetType 1 5761 fg "65535,65535,65535" 5762 lineColor "26368,26368,26368" 5763 ) 5764 xt "-17999,88625,-17249,89375" 5765 radius 375 5766 ) 5767 ] 5768 ps "OnEdgeStrategy" 5769 shape (Triangle 5770 uid 6532,0 5771 ro 90 5772 va (VaSet 5773 vasetType 1 5774 isHidden 1 5775 fg "0,65535,65535" 5776 ) 5777 xt "-17000,88625,-16250,89375" 5778 ) 5779 tg (CPTG 5780 uid 6533,0 5781 ps "CptPortTextPlaceStrategy" 5782 stg "RightVerticalLayoutStrategy" 5783 f (Text 5784 uid 6534,0 5785 sl 0 5786 va (VaSet 5787 isHidden 1 5788 font "arial,8,0" 5789 ) 5790 xt "-15050,88500,-13250,89500" 5791 st "dout" 5792 ju 2 5793 blo "-13250,89300" 5794 ) 5795 s (Text 5796 uid 6549,0 5797 sl 0 5798 va (VaSet 5799 font "arial,8,0" 5800 ) 5801 xt "-13250,89500,-13250,89500" 5802 ju 2 5803 blo "-13250,89500" 5804 ) 5805 ) 5806 thePort (LogicalPort 5807 m 1 5808 decl (Decl 5809 n "dout" 5810 t "STD_LOGIC" 5811 o 58 5812 suid 2,0 5813 ) 5814 ) 5815 ) 5816 *186 (CommentGraphic 5817 uid 6537,0 5818 shape (CustomPolygon 5819 pts [ 5820 "-21000,87000" 5821 "-18000,89000" 5822 "-21000,91000" 5823 "-21000,87000" 5824 ] 5825 uid 6538,0 5826 layer 0 5827 sl 0 5828 va (VaSet 5829 vasetType 1 5830 fg "0,65535,65535" 5831 bg "0,65535,65535" 5832 lineColor "26368,26368,26368" 5833 ) 5834 xt "-21000,87000,-18000,91000" 5835 ) 5836 oxt "7000,6000,10000,10000" 5837 ) 5838 ] 5839 shape (Rectangle 5840 uid 6540,0 5841 va (VaSet 5842 vasetType 1 5843 transparent 1 5844 fg "0,65535,0" 5845 lineColor "65535,65535,65535" 5846 lineWidth -1 5847 ) 5848 xt "-22000,87000,-17000,91000" 5849 fos 1 5850 ) 5851 showPorts 0 5852 oxt "6000,6000,11000,10000" 5853 ttg (MlTextGroup 5854 uid 6541,0 5855 ps "CenterOffsetStrategy" 5856 stg "VerticalLayoutStrategy" 5857 textVec [ 5858 *187 (Text 5859 uid 6542,0 5860 va (VaSet 5861 isHidden 1 5862 font "arial,8,0" 5863 ) 5864 xt "-19650,89100,-14850,90100" 5865 st "moduleware" 5866 blo "-19650,89900" 5867 ) 5868 *188 (Text 5869 uid 6543,0 5870 va (VaSet 5871 font "arial,8,0" 5872 ) 5873 xt "-19650,90100,-18350,91100" 5874 st "inv" 5875 blo "-19650,90900" 5876 ) 5877 *189 (Text 5878 uid 6544,0 5879 va (VaSet 5880 font "arial,8,0" 5881 ) 5882 xt "-19650,91100,-18650,92100" 5883 st "I1" 5884 blo "-19650,91900" 5885 tm "InstanceNameMgr" 5886 ) 5887 ] 5888 ) 5889 ga (GenericAssociation 5890 uid 6545,0 5891 ps "EdgeToEdgeStrategy" 5892 matrix (Matrix 5893 uid 6546,0 5894 text (MLText 5895 uid 6547,0 5896 va (VaSet 5897 font "arial,8,0" 5898 ) 5899 xt "-25000,68400,-25000,68400" 5900 ) 5901 header "" 5902 ) 5903 elements [ 5904 ] 5905 ) 5906 sed 1 5907 awe 1 5908 portVis (PortSigDisplay 5909 disp 1 5910 sN 0 5911 sTC 0 5912 selT 0 5913 ) 5914 prms (Property 5915 pclass "params" 5916 pname "params" 5917 ptn "String" 5918 ) 5919 visOptions (mwParamsVisibilityOptions 5920 ) 5921 ) 5922 *190 (MWC 5445 st "SIGNAL TRG_OR : std_logic 5446 " 5447 ) 5448 ) 5449 *170 (MWC 5923 5450 uid 6586,0 5924 5451 optionalChildren [ 5925 *1 91 (CptPort5452 *171 (CptPort 5926 5453 uid 6550,0 5927 5454 optionalChildren [ 5928 *1 92 (Line5455 *172 (Line 5929 5456 uid 6554,0 5930 5457 layer 5 … … 5970 5497 decl (Decl 5971 5498 n "din1" 5972 t "STD_LOGIC" 5973 preAdd 0 5974 posAdd 0 5975 o 60 5499 t "std_logic" 5500 o 11 5976 5501 suid 1,0 5977 i "'0'" 5978 ) 5979 ) 5980 ) 5981 *193 (CptPort 5502 ) 5503 ) 5504 ) 5505 *173 (CptPort 5982 5506 uid 6555,0 5983 5507 optionalChildren [ 5984 *1 94 (Property5508 *174 (Property 5985 5509 uid 6559,0 5986 5510 pclass "_MW_GEOM_" … … 5988 5512 ptn "String" 5989 5513 ) 5990 *1 95 (Line5514 *175 (Line 5991 5515 uid 6560,0 5992 5516 layer 5 … … 6040 5564 ) 6041 5565 ) 6042 *1 96 (CptPort5566 *176 (CptPort 6043 5567 uid 6561,0 6044 5568 optionalChildren [ 6045 *1 97 (Line5569 *177 (Line 6046 5570 uid 6565,0 6047 5571 layer 5 … … 6093 5617 ) 6094 5618 ) 6095 *1 98 (CommentGraphic5619 *178 (CommentGraphic 6096 5620 uid 6566,0 6097 5621 shape (Arc2D … … 6114 5638 oxt "7000,6003,11000,8000" 6115 5639 ) 6116 *1 99 (CommentGraphic5640 *179 (CommentGraphic 6117 5641 uid 6568,0 6118 5642 shape (Arc2D … … 6135 5659 oxt "6996,8005,11000,10000" 6136 5660 ) 6137 * 200 (Grouping5661 *180 (Grouping 6138 5662 uid 6570,0 6139 5663 optionalChildren [ 6140 * 201 (CommentGraphic5664 *181 (CommentGraphic 6141 5665 uid 6572,0 6142 5666 optionalChildren [ 6143 * 202 (Property5667 *182 (Property 6144 5668 uid 6574,0 6145 5669 pclass "_MW_GEOM_" … … 6172 5696 oxt "7000,6000,11000,9998" 6173 5697 ) 6174 * 203 (CommentGraphic5698 *183 (CommentGraphic 6175 5699 uid 6575,0 6176 5700 optionalChildren [ 6177 * 204 (Property5701 *184 (Property 6178 5702 uid 6577,0 6179 5703 pclass "_MW_GEOM_" … … 6217 5741 oxt "7000,6000,11000,10000" 6218 5742 ) 6219 * 205 (CommentGraphic5743 *185 (CommentGraphic 6220 5744 uid 6578,0 6221 5745 shape (PolyLine2D … … 6236 5760 oxt "11000,8000,11000,8000" 6237 5761 ) 6238 * 206 (CommentGraphic5762 *186 (CommentGraphic 6239 5763 uid 6580,0 6240 5764 optionalChildren [ 6241 * 207 (Property5765 *187 (Property 6242 5766 uid 6582,0 6243 5767 pclass "_MW_GEOM_" … … 6263 5787 oxt "7000,6000,7000,6000" 6264 5788 ) 6265 * 208 (CommentGraphic5789 *188 (CommentGraphic 6266 5790 uid 6583,0 6267 5791 optionalChildren [ 6268 * 209 (Property5792 *189 (Property 6269 5793 uid 6585,0 6270 5794 pclass "_MW_GEOM_" … … 6309 5833 stg "VerticalLayoutStrategy" 6310 5834 textVec [ 6311 * 210 (Text5835 *190 (Text 6312 5836 uid 6589,0 6313 5837 va (VaSet … … 6319 5843 blo "15500,77300" 6320 5844 ) 6321 * 211 (Text5845 *191 (Text 6322 5846 uid 6590,0 6323 5847 va (VaSet … … 6328 5852 blo "15500,78300" 6329 5853 ) 6330 * 212 (Text5854 *192 (Text 6331 5855 uid 6591,0 6332 5856 va (VaSet … … 6373 5897 ) 6374 5898 ) 6375 * 213 (PortIoIn5899 *193 (PortIoIn 6376 5900 uid 6781,0 6377 5901 shape (CompositeShape … … 6418 5942 ) 6419 5943 ) 6420 * 214 (Net5944 *194 (Net 6421 5945 uid 6793,0 6422 5946 decl (Decl … … 6433 5957 ) 6434 5958 xt "39000,11000,63500,11800" 6435 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0)" 6436 ) 6437 ) 6438 *215 (PortIoOut 5959 st "D_PLLLCK : std_logic_vector(3 DOWNTO 0) 5960 " 5961 ) 5962 ) 5963 *195 (PortIoOut 6439 5964 uid 6874,0 6440 5965 shape (CompositeShape … … 6480 6005 ) 6481 6006 ) 6482 * 216 (Net6007 *196 (Net 6483 6008 uid 6886,0 6484 6009 decl (Decl … … 6496 6021 ) 6497 6022 xt "39000,23800,74000,24600" 6498 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6499 ) 6500 ) 6501 *217 (HdlText 6023 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0') 6024 " 6025 ) 6026 ) 6027 *197 (HdlText 6502 6028 uid 6888,0 6503 6029 optionalChildren [ 6504 * 218 (EmbeddedText6030 *198 (EmbeddedText 6505 6031 uid 6894,0 6506 6032 commentText (CommentText … … 6550 6076 stg "VerticalLayoutStrategy" 6551 6077 textVec [ 6552 * 219 (Text6078 *199 (Text 6553 6079 uid 6891,0 6554 6080 va (VaSet … … 6560 6086 tm "HdlTextNameMgr" 6561 6087 ) 6562 *2 20 (Text6088 *200 (Text 6563 6089 uid 6892,0 6564 6090 va (VaSet … … 6586 6112 viewiconposition 0 6587 6113 ) 6588 *2 21 (HdlText6114 *201 (HdlText 6589 6115 uid 7092,0 6590 6116 optionalChildren [ 6591 *2 22 (EmbeddedText6117 *202 (EmbeddedText 6592 6118 uid 7098,0 6593 6119 commentText (CommentText … … 6602 6128 lineWidth 2 6603 6129 ) 6604 xt "2 7000,137000,45000,145000"6130 xt "26000,137000,46000,143000" 6605 6131 ) 6606 6132 oxt "0,0,18000,5000" … … 6609 6135 va (VaSet 6610 6136 ) 6611 xt "2 7200,137200,39400,142200"6137 xt "26200,137200,40000,141200" 6612 6138 st " 6613 6139 -- eb2 8 6614 A1_T(0) <= dummy; 6615 A1_T(1) <= RSRLOAD; 6616 A1_T(2) <= D0_SROUT; 6617 A1_T(3) <= D1_SROUT; 6140 A1_T(3 downto 0) <= drs_channel_id; 6141 D_A <= drs_channel_id; 6142 A1_T(4) <= TRG_OR; 6618 6143 " 6619 6144 tm "HdlTextMgr" 6620 6145 wrapOption 3 6621 visibleHeight 80006622 visibleWidth 180006146 visibleHeight 6000 6147 visibleWidth 20000 6623 6148 ) 6624 6149 ) … … 6641 6166 stg "VerticalLayoutStrategy" 6642 6167 textVec [ 6643 *2 23 (Text6168 *203 (Text 6644 6169 uid 7095,0 6645 6170 va (VaSet … … 6651 6176 tm "HdlTextNameMgr" 6652 6177 ) 6653 *2 24 (Text6178 *204 (Text 6654 6179 uid 7096,0 6655 6180 va (VaSet … … 6677 6202 viewiconposition 0 6678 6203 ) 6679 *2 25 (PortIoOut6204 *205 (PortIoOut 6680 6205 uid 7138,0 6681 6206 shape (CompositeShape … … 6721 6246 ) 6722 6247 ) 6723 *2 26 (Net6248 *206 (Net 6724 6249 uid 7150,0 6725 6250 decl (Decl 6726 6251 n "A1_T" 6727 6252 t "std_logic_vector" 6728 b "( 3DOWNTO 0)"6253 b "(7 DOWNTO 0)" 6729 6254 o 15 6730 6255 suid 155,0 6256 i "(OTHERS => '0')" 6731 6257 ) 6732 6258 declText (MLText … … 6735 6261 font "Courier New,8,0" 6736 6262 ) 6737 xt "39000,15000,63500,15800" 6738 st "A1_T : std_logic_vector(3 DOWNTO 0)" 6739 ) 6740 ) 6741 *227 (Net 6263 xt "39000,15000,74000,15800" 6264 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 6265 " 6266 ) 6267 ) 6268 *207 (Net 6742 6269 uid 7485,0 6743 6270 decl (Decl 6744 6271 n "dummy" 6745 6272 t "std_logic" 6746 o 606273 o 58 6747 6274 suid 157,0 6748 6275 ) … … 6752 6279 font "Courier New,8,0" 6753 6280 ) 6754 xt "39000,49600,57000,50400" 6755 st "SIGNAL dummy : std_logic" 6756 ) 6757 ) 6758 *228 (MWC 6281 xt "39000,50400,57000,51200" 6282 st "SIGNAL dummy : std_logic 6283 " 6284 ) 6285 ) 6286 *208 (MWC 6759 6287 uid 7652,0 6760 6288 optionalChildren [ 6761 *2 29 (CptPort6289 *209 (CptPort 6762 6290 uid 7632,0 6763 6291 optionalChildren [ 6764 *2 30 (Line6292 *210 (Line 6765 6293 uid 7636,0 6766 6294 layer 5 … … 6816 6344 n "s" 6817 6345 t "std_logic" 6818 o 606346 o 58 6819 6347 suid 1,0 6820 6348 ) 6821 6349 ) 6822 6350 ) 6823 *2 31 (CptPort6351 *211 (CptPort 6824 6352 uid 7637,0 6825 6353 optionalChildren [ 6826 *2 32 (Line6354 *212 (Line 6827 6355 uid 7641,0 6828 6356 layer 5 … … 6886 6414 ) 6887 6415 ) 6888 *2 33 (CommentGraphic6416 *213 (CommentGraphic 6889 6417 uid 7642,0 6890 6418 shape (PolyLine2D … … 6907 6435 oxt "6000,6000,7000,7000" 6908 6436 ) 6909 *2 34 (CommentGraphic6437 *214 (CommentGraphic 6910 6438 uid 7644,0 6911 6439 shape (PolyLine2D … … 6928 6456 oxt "6000,7000,7000,8000" 6929 6457 ) 6930 *2 35 (CommentGraphic6458 *215 (CommentGraphic 6931 6459 uid 7646,0 6932 6460 shape (PolyLine2D … … 6949 6477 oxt "6988,7329,7988,7329" 6950 6478 ) 6951 *2 36 (CommentGraphic6479 *216 (CommentGraphic 6952 6480 uid 7648,0 6953 6481 shape (PolyLine2D … … 6968 6496 oxt "8000,7000,9000,7000" 6969 6497 ) 6970 *2 37 (CommentGraphic6498 *217 (CommentGraphic 6971 6499 uid 7650,0 6972 6500 shape (PolyLine2D … … 7009 6537 stg "VerticalLayoutStrategy" 7010 6538 textVec [ 7011 *2 38 (Text6539 *218 (Text 7012 6540 uid 7655,0 7013 6541 va (VaSet … … 7019 6547 blo "90350,83900" 7020 6548 ) 7021 *2 39 (Text6549 *219 (Text 7022 6550 uid 7656,0 7023 6551 va (VaSet … … 7028 6556 blo "90350,84900" 7029 6557 ) 7030 *2 40 (Text6558 *220 (Text 7031 6559 uid 7657,0 7032 6560 va (VaSet … … 7073 6601 ) 7074 6602 ) 7075 *241 (Wire 6603 *221 (Net 6604 uid 8851,0 6605 decl (Decl 6606 n "drs_channel_id" 6607 t "std_logic_vector" 6608 b "(3 downto 0)" 6609 o 57 6610 suid 159,0 6611 i "(others => '0')" 6612 ) 6613 declText (MLText 6614 uid 8852,0 6615 va (VaSet 6616 font "Courier New,8,0" 6617 ) 6618 xt "39000,49600,77500,50400" 6619 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6620 " 6621 ) 6622 ) 6623 *222 (Net 6624 uid 9500,0 6625 decl (Decl 6626 n "CLK_50" 6627 t "std_logic" 6628 o 51 6629 suid 163,0 6630 ) 6631 declText (MLText 6632 uid 9501,0 6633 va (VaSet 6634 font "Courier New,8,0" 6635 ) 6636 xt "39000,44800,57000,45600" 6637 st "SIGNAL CLK_50 : std_logic 6638 " 6639 ) 6640 ) 6641 *223 (Wire 7076 6642 uid 245,0 7077 6643 shape (OrthoPolyLine … … 7110 6676 ) 7111 6677 ) 7112 on & 707113 ) 7114 *2 42(Wire6678 on &69 6679 ) 6680 *224 (Wire 7115 6681 uid 277,0 7116 6682 shape (OrthoPolyLine … … 7150 6716 on &53 7151 6717 ) 7152 *2 43(Wire6718 *225 (Wire 7153 6719 uid 285,0 7154 6720 shape (OrthoPolyLine … … 7188 6754 on &54 7189 6755 ) 7190 *2 44(Wire6756 *226 (Wire 7191 6757 uid 362,0 7192 6758 shape (OrthoPolyLine … … 7201 6767 ] 7202 6768 ) 7203 start &7 86769 start &77 7204 6770 end &16 7205 6771 sat 32 … … 7224 6790 ) 7225 6791 ) 7226 on &7 97227 ) 7228 *2 45(Wire6792 on &78 6793 ) 6794 *227 (Wire 7229 6795 uid 418,0 7230 6796 shape (OrthoPolyLine … … 7262 6828 ) 7263 6829 ) 7264 on &13 17265 ) 7266 *2 46(Wire6830 on &130 6831 ) 6832 *228 (Wire 7267 6833 uid 426,0 7268 6834 shape (OrthoPolyLine … … 7302 6868 ) 7303 6869 ) 7304 on &12 97305 ) 7306 *2 47(Wire6870 on &128 6871 ) 6872 *229 (Wire 7307 6873 uid 434,0 7308 6874 shape (OrthoPolyLine … … 7340 6906 ) 7341 6907 ) 7342 on &13 57343 ) 7344 *2 48(Wire6908 on &134 6909 ) 6910 *230 (Wire 7345 6911 uid 442,0 7346 6912 shape (OrthoPolyLine … … 7380 6946 ) 7381 6947 ) 7382 on &1 307383 ) 7384 *2 49(Wire6948 on &129 6949 ) 6950 *231 (Wire 7385 6951 uid 450,0 7386 6952 shape (OrthoPolyLine … … 7418 6984 ) 7419 6985 ) 7420 on &13 47421 ) 7422 *2 50(Wire6986 on &133 6987 ) 6988 *232 (Wire 7423 6989 uid 458,0 7424 6990 shape (OrthoPolyLine … … 7456 7022 ) 7457 7023 ) 7458 on &13 27459 ) 7460 *2 51(Wire7024 on &131 7025 ) 7026 *233 (Wire 7461 7027 uid 466,0 7462 7028 shape (OrthoPolyLine … … 7494 7060 ) 7495 7061 ) 7496 on &13 37497 ) 7498 *2 52(Wire7062 on &132 7063 ) 7064 *234 (Wire 7499 7065 uid 1467,0 7500 7066 shape (OrthoPolyLine … … 7509 7075 ] 7510 7076 ) 7511 start &8 27077 start &81 7512 7078 end &28 7513 7079 sat 2 … … 7532 7098 on &62 7533 7099 ) 7534 *2 53(Wire7100 *235 (Wire 7535 7101 uid 1730,0 7536 7102 shape (OrthoPolyLine … … 7546 7112 ] 7547 7113 ) 7548 start & 807114 start &79 7549 7115 end &29 7550 7116 sat 32 … … 7570 7136 ) 7571 7137 ) 7572 on &8 17573 ) 7574 *2 54(Wire7138 on &80 7139 ) 7140 *236 (Wire 7575 7141 uid 1833,0 7576 7142 shape (OrthoPolyLine … … 7580 7146 lineWidth 2 7581 7147 ) 7582 xt " 21000,109000,51250,109000"7583 pts [ 7584 " 51250,109000"7585 " 21000,109000"7586 ] 7587 ) 7588 start & 307589 end &1 107590 sat 327148 xt "6000,134000,31000,134000" 7149 pts [ 7150 "31000,134000" 7151 "6000,134000" 7152 ] 7153 ) 7154 start &201 7155 end &109 7156 sat 2 7591 7157 eat 32 7592 7158 sty 1 … … 7604 7170 isHidden 1 7605 7171 ) 7606 xt " 22000,108000,23900,109000"7172 xt "7000,133000,8900,134000" 7607 7173 st "D_A" 7608 blo " 22000,108800"7174 blo "7000,133800" 7609 7175 tm "WireNameMgr" 7610 7176 ) 7611 7177 ) 7612 on &11 17613 ) 7614 *2 55(Wire7178 on &110 7179 ) 7180 *237 (Wire 7615 7181 uid 1841,0 7616 7182 shape (OrthoPolyLine … … 7626 7192 ) 7627 7193 start &31 7628 end &11 27194 end &111 7629 7195 sat 32 7630 7196 eat 32 … … 7648 7214 ) 7649 7215 ) 7650 on &11 37651 ) 7652 *2 56(Wire7216 on &112 7217 ) 7218 *238 (Wire 7653 7219 uid 1865,0 7654 7220 shape (OrthoPolyLine … … 7663 7229 ] 7664 7230 ) 7665 start &10 27231 start &101 7666 7232 end &32 7667 7233 sat 32 … … 7686 7252 ) 7687 7253 ) 7688 on &10 67689 ) 7690 *2 57(Wire7254 on &105 7255 ) 7256 *239 (Wire 7691 7257 uid 1873,0 7692 7258 shape (OrthoPolyLine … … 7701 7267 ] 7702 7268 ) 7703 start &10 37269 start &102 7704 7270 end &33 7705 7271 sat 32 … … 7724 7290 ) 7725 7291 ) 7726 on &10 77727 ) 7728 *2 58(Wire7292 on &106 7293 ) 7294 *240 (Wire 7729 7295 uid 1881,0 7730 7296 shape (OrthoPolyLine … … 7739 7305 ] 7740 7306 ) 7741 start &10 47307 start &103 7742 7308 end &34 7743 7309 sat 32 … … 7762 7328 ) 7763 7329 ) 7764 on &10 87765 ) 7766 *2 59(Wire7330 on &107 7331 ) 7332 *241 (Wire 7767 7333 uid 1889,0 7768 7334 shape (OrthoPolyLine … … 7777 7343 ] 7778 7344 ) 7779 start &10 57345 start &104 7780 7346 end &35 7781 7347 sat 32 … … 7800 7366 ) 7801 7367 ) 7802 on &109 7803 ) 7804 *260 (Wire 7805 uid 2269,0 7806 shape (OrthoPolyLine 7807 uid 2270,0 7808 va (VaSet 7809 vasetType 3 7810 ) 7811 xt "-15000,69000,51250,88000" 7812 pts [ 7813 "51250,69000" 7814 "-15000,69000" 7815 "-15000,88000" 7816 "-11750,88000" 7817 ] 7818 ) 7819 start &26 7820 end &172 7821 sat 32 7822 eat 32 7823 stc 0 7824 st 0 7825 sf 1 7826 si 0 7827 tg (WTG 7828 uid 2273,0 7829 ps "ConnStartEndStrategy" 7830 stg "STSignalDisplayStrategy" 7831 f (Text 7832 uid 2274,0 7833 va (VaSet 7834 isHidden 1 7835 ) 7836 xt "50250,68000,53350,69000" 7837 st "CLK_50" 7838 blo "50250,68800" 7839 tm "WireNameMgr" 7840 ) 7841 ) 7842 on &63 7843 ) 7844 *261 (Wire 7368 on &108 7369 ) 7370 *242 (Wire 7845 7371 uid 2409,0 7846 7372 shape (OrthoPolyLine … … 7856 7382 ) 7857 7383 start &36 7858 end &6 57384 end &64 7859 7385 sat 32 7860 7386 eat 32 … … 7878 7404 ) 7879 7405 ) 7880 on &6 47881 ) 7882 *2 62(Wire7406 on &63 7407 ) 7408 *243 (Wire 7883 7409 uid 2423,0 7884 7410 shape (OrthoPolyLine … … 7894 7420 ) 7895 7421 start &37 7896 end &9 47422 end &93 7897 7423 sat 32 7898 7424 eat 1 … … 7916 7442 ) 7917 7443 ) 7918 on &6 67919 ) 7920 *2 63(Wire7444 on &65 7445 ) 7446 *244 (Wire 7921 7447 uid 3009,0 7922 7448 shape (OrthoPolyLine … … 7932 7458 ) 7933 7459 start &39 7934 end &12 77460 end &126 7935 7461 sat 32 7936 7462 eat 32 … … 7954 7480 ) 7955 7481 ) 7956 on &12 87957 ) 7958 *2 64(Wire7482 on &127 7483 ) 7484 *245 (Wire 7959 7485 uid 3015,0 7960 7486 shape (OrthoPolyLine … … 7970 7496 ) 7971 7497 start &41 7972 end &13 67498 end &135 7973 7499 sat 32 7974 7500 eat 32 … … 7992 7518 ) 7993 7519 ) 7994 on &13 97995 ) 7996 *2 65(Wire7520 on &138 7521 ) 7522 *246 (Wire 7997 7523 uid 3021,0 7998 7524 shape (OrthoPolyLine … … 8009 7535 ) 8010 7536 start &40 8011 end &11 57537 end &114 8012 7538 sat 32 8013 7539 eat 1 … … 8030 7556 ) 8031 7557 ) 8032 on &6 78033 ) 8034 *2 66(Wire7558 on &66 7559 ) 7560 *247 (Wire 8035 7561 uid 3027,0 8036 7562 shape (OrthoPolyLine … … 8045 7571 ] 8046 7572 ) 8047 start &2 318048 end &11 47573 start &211 7574 end &113 8049 7575 ss 0 8050 7576 sat 32 … … 8069 7595 ) 8070 7596 ) 8071 on &6 88072 ) 8073 *2 67(Wire7597 on &67 7598 ) 7599 *248 (Wire 8074 7600 uid 3218,0 8075 7601 shape (OrthoPolyLine … … 8085 7611 ) 8086 7612 start &47 8087 end &1 967613 end &176 8088 7614 sat 32 8089 7615 eat 32 … … 8107 7633 ) 8108 7634 ) 8109 on &7 18110 ) 8111 *2 68(Wire7635 on &70 7636 ) 7637 *249 (Wire 8112 7638 uid 3260,0 8113 7639 shape (OrthoPolyLine … … 8123 7649 ] 8124 7650 ) 8125 start &6 98126 end &7 27651 start &68 7652 end &71 8127 7653 sat 32 8128 7654 eat 2 … … 8147 7673 ) 8148 7674 ) 8149 on &7 68150 ) 8151 *2 69(Wire7675 on &75 7676 ) 7677 *250 (Wire 8152 7678 uid 3270,0 8153 7679 shape (OrthoPolyLine … … 8163 7689 ) 8164 7690 start &25 8165 end &7 27691 end &71 8166 7692 sat 32 8167 7693 eat 1 … … 8183 7709 ) 8184 7710 ) 8185 on &7 78186 ) 8187 *2 70(Wire7711 on &76 7712 ) 7713 *251 (Wire 8188 7714 uid 3318,0 8189 7715 shape (OrthoPolyLine … … 8199 7725 ] 8200 7726 ) 8201 start &8 68202 end &8 27727 start &85 7728 end &81 8203 7729 sat 32 8204 7730 eat 1 … … 8223 7749 ) 8224 7750 ) 8225 on & 908226 ) 8227 *2 71(Wire7751 on &89 7752 ) 7753 *252 (Wire 8228 7754 uid 3352,0 8229 7755 shape (OrthoPolyLine … … 8239 7765 ] 8240 7766 ) 8241 start &8 78242 end &8 27767 start &86 7768 end &81 8243 7769 sat 32 8244 7770 eat 1 … … 8263 7789 ) 8264 7790 ) 8265 on &9 18266 ) 8267 *2 72(Wire7791 on &90 7792 ) 7793 *253 (Wire 8268 7794 uid 3360,0 8269 7795 shape (OrthoPolyLine … … 8279 7805 ] 8280 7806 ) 8281 start &8 88282 end &8 27807 start &87 7808 end &81 8283 7809 sat 32 8284 7810 eat 1 … … 8303 7829 ) 8304 7830 ) 8305 on &9 28306 ) 8307 *2 73(Wire7831 on &91 7832 ) 7833 *254 (Wire 8308 7834 uid 3368,0 8309 7835 shape (OrthoPolyLine … … 8319 7845 ] 8320 7846 ) 8321 start &8 98322 end &8 27847 start &88 7848 end &81 8323 7849 sat 32 8324 7850 eat 1 … … 8343 7869 ) 8344 7870 ) 8345 on &9 38346 ) 8347 *2 74(Wire7871 on &92 7872 ) 7873 *255 (Wire 8348 7874 uid 3430,0 8349 7875 shape (OrthoPolyLine … … 8358 7884 ] 8359 7885 ) 8360 start &16 28361 end &9 47886 start &161 7887 end &93 8362 7888 sat 32 8363 7889 eat 2 … … 8381 7907 ) 8382 7908 ) 8383 on &9 88384 ) 8385 *2 75(Wire7909 on &97 7910 ) 7911 *256 (Wire 8386 7912 uid 3438,0 8387 7913 shape (OrthoPolyLine … … 8396 7922 ] 8397 7923 ) 8398 start &16 38399 end &9 47924 start &162 7925 end &93 8400 7926 sat 32 8401 7927 eat 2 … … 8419 7945 ) 8420 7946 ) 8421 on &9 98422 ) 8423 *2 76(Wire7947 on &98 7948 ) 7949 *257 (Wire 8424 7950 uid 3446,0 8425 7951 shape (OrthoPolyLine … … 8434 7960 ] 8435 7961 ) 8436 start &16 48437 end &9 47962 start &163 7963 end &93 8438 7964 sat 32 8439 7965 eat 2 … … 8457 7983 ) 8458 7984 ) 8459 on & 1008460 ) 8461 *2 77(Wire7985 on &99 7986 ) 7987 *258 (Wire 8462 7988 uid 3454,0 8463 7989 shape (OrthoPolyLine … … 8472 7998 ] 8473 7999 ) 8474 start &16 58475 end &9 48000 start &164 8001 end &93 8476 8002 sat 32 8477 8003 eat 2 … … 8495 8021 ) 8496 8022 ) 8497 on &10 18498 ) 8499 *2 78(Wire8023 on &100 8024 ) 8025 *259 (Wire 8500 8026 uid 3574,0 8501 8027 shape (OrthoPolyLine … … 8510 8036 ] 8511 8037 ) 8512 start &11 98513 end &11 58038 start &118 8039 end &114 8514 8040 sat 32 8515 8041 eat 2 … … 8533 8059 ) 8534 8060 ) 8535 on &12 38536 ) 8537 *2 79(Wire8061 on &122 8062 ) 8063 *260 (Wire 8538 8064 uid 3582,0 8539 8065 shape (OrthoPolyLine … … 8548 8074 ] 8549 8075 ) 8550 start &1 208551 end &11 58076 start &119 8077 end &114 8552 8078 sat 32 8553 8079 eat 2 … … 8571 8097 ) 8572 8098 ) 8573 on &12 48574 ) 8575 *2 80(Wire8099 on &123 8100 ) 8101 *261 (Wire 8576 8102 uid 3590,0 8577 8103 shape (OrthoPolyLine … … 8586 8112 ] 8587 8113 ) 8588 start &12 18589 end &11 58114 start &120 8115 end &114 8590 8116 sat 32 8591 8117 eat 2 … … 8609 8135 ) 8610 8136 ) 8611 on &12 58612 ) 8613 *2 81(Wire8137 on &124 8138 ) 8139 *262 (Wire 8614 8140 uid 3598,0 8615 8141 shape (OrthoPolyLine … … 8624 8150 ] 8625 8151 ) 8626 start &12 28627 end &11 58152 start &121 8153 end &114 8628 8154 sat 32 8629 8155 eat 2 … … 8647 8173 ) 8648 8174 ) 8649 on &12 68650 ) 8651 *2 82(Wire8175 on &125 8176 ) 8177 *263 (Wire 8652 8178 uid 3682,0 8653 8179 shape (OrthoPolyLine … … 8663 8189 ) 8664 8190 start &42 8665 end &13 88191 end &137 8666 8192 sat 32 8667 8193 eat 32 … … 8685 8211 ) 8686 8212 ) 8687 on &13 78688 ) 8689 *2 83(Wire8213 on &136 8214 ) 8215 *264 (Wire 8690 8216 uid 3778,0 8691 8217 shape (OrthoPolyLine … … 8700 8226 ] 8701 8227 ) 8702 start &14 48703 end &1 408228 start &143 8229 end &139 8704 8230 sat 32 8705 8231 eat 2 … … 8723 8249 ) 8724 8250 ) 8725 on &15 38726 ) 8727 *2 84(Wire8251 on &152 8252 ) 8253 *265 (Wire 8728 8254 uid 3786,0 8729 8255 shape (OrthoPolyLine … … 8738 8264 ] 8739 8265 ) 8740 start &14 58741 end &1 408266 start &144 8267 end &139 8742 8268 sat 32 8743 8269 eat 2 … … 8761 8287 ) 8762 8288 ) 8763 on &15 48764 ) 8765 *2 85(Wire8289 on &153 8290 ) 8291 *266 (Wire 8766 8292 uid 3794,0 8767 8293 shape (OrthoPolyLine … … 8776 8302 ] 8777 8303 ) 8778 start &14 68779 end &1 408304 start &145 8305 end &139 8780 8306 sat 32 8781 8307 eat 2 … … 8799 8325 ) 8800 8326 ) 8801 on &15 58802 ) 8803 *2 86(Wire8327 on &154 8328 ) 8329 *267 (Wire 8804 8330 uid 3802,0 8805 8331 shape (OrthoPolyLine … … 8814 8340 ] 8815 8341 ) 8816 start &14 78817 end &1 408342 start &146 8343 end &139 8818 8344 sat 32 8819 8345 eat 2 … … 8837 8363 ) 8838 8364 ) 8839 on &15 68840 ) 8841 *2 87(Wire8365 on &155 8366 ) 8367 *268 (Wire 8842 8368 uid 3810,0 8843 8369 shape (OrthoPolyLine … … 8852 8378 ] 8853 8379 ) 8854 start &14 88855 end &1 408380 start &147 8381 end &139 8856 8382 sat 32 8857 8383 eat 2 … … 8875 8401 ) 8876 8402 ) 8877 on &15 78878 ) 8879 *2 88(Wire8403 on &156 8404 ) 8405 *269 (Wire 8880 8406 uid 3826,0 8881 8407 shape (OrthoPolyLine … … 8890 8416 ] 8891 8417 ) 8892 start &1 508893 end &1 408418 start &149 8419 end &139 8894 8420 sat 32 8895 8421 eat 2 … … 8913 8439 ) 8914 8440 ) 8915 on &15 98916 ) 8917 *2 89(Wire8441 on &158 8442 ) 8443 *270 (Wire 8918 8444 uid 3834,0 8919 8445 shape (OrthoPolyLine … … 8928 8454 ] 8929 8455 ) 8930 start &15 18931 end &1 408456 start &150 8457 end &139 8932 8458 sat 32 8933 8459 eat 2 … … 8951 8477 ) 8952 8478 ) 8953 on &1 608954 ) 8955 *2 90(Wire8479 on &159 8480 ) 8481 *271 (Wire 8956 8482 uid 3842,0 8957 8483 shape (OrthoPolyLine … … 8967 8493 ] 8968 8494 ) 8969 start &15 28970 end &1 408495 start &151 8496 end &139 8971 8497 sat 32 8972 8498 eat 2 … … 8991 8517 ) 8992 8518 ) 8993 on &16 18994 ) 8995 *2 91(Wire8519 on &160 8520 ) 8521 *272 (Wire 8996 8522 uid 4942,0 8997 8523 shape (OrthoPolyLine … … 9008 8534 ) 9009 8535 start &14 9010 end &16 68536 end &165 9011 8537 sat 32 9012 8538 eat 32 … … 9031 8557 ) 9032 8558 ) 9033 on &16 79034 ) 9035 *2 92(Wire8559 on &166 8560 ) 8561 *273 (Wire 9036 8562 uid 6130,0 9037 8563 shape (OrthoPolyLine … … 9046 8572 ] 9047 8573 ) 9048 start &1 938574 start &173 9049 8575 end &15 9050 8576 sat 32 … … 9067 8593 ) 9068 8594 ) 9069 on &170 9070 ) 9071 *293 (Wire 9072 uid 6288,0 9073 shape (OrthoPolyLine 9074 uid 6289,0 9075 va (VaSet 9076 vasetType 3 9077 ) 9078 xt "1750,79000,13000,89000" 9079 pts [ 9080 "1750,89000" 9081 "9000,89000" 9082 "9000,86000" 9083 "9000,79000" 9084 "13000,79000" 9085 ] 9086 ) 9087 start &174 9088 end &191 9089 sat 32 9090 eat 32 9091 st 0 9092 sf 1 9093 si 0 9094 tg (WTG 9095 uid 6294,0 9096 ps "ConnStartEndStrategy" 9097 stg "STSignalDisplayStrategy" 9098 f (Text 9099 uid 6295,0 9100 va (VaSet 9101 ) 9102 xt "4000,88000,8600,89000" 9103 st "trigger_out" 9104 blo "4000,88800" 9105 tm "WireNameMgr" 9106 ) 9107 ) 9108 on &178 9109 ) 9110 *294 (Wire 8595 on &169 8596 ) 8597 *274 (Wire 9111 8598 uid 6306,0 9112 8599 shape (OrthoPolyLine … … 9115 8602 vasetType 3 9116 8603 ) 9117 xt "-28000,89000,-22000,89000" 9118 pts [ 9119 "-28000,89000" 9120 "-22000,89000" 9121 ] 9122 ) 9123 start &168 9124 end &181 9125 es 0 8604 xt "11000,79000,13000,79000" 8605 pts [ 8606 "11000,79000" 8607 "13000,79000" 8608 ] 8609 ) 8610 start &167 8611 end &171 9126 8612 sat 32 9127 8613 eat 32 8614 stc 0 9128 8615 st 0 9129 8616 sf 1 … … 9136 8623 uid 6313,0 9137 8624 va (VaSet 9138 ) 9139 xt "-26000,88000,-21500,89000" 8625 isHidden 1 8626 ) 8627 xt "13000,78000,17500,79000" 9140 8628 st "TEST_TRG" 9141 blo " -26000,88800"8629 blo "13000,78800" 9142 8630 tm "WireNameMgr" 9143 8631 ) 9144 8632 ) 9145 on &169 9146 ) 9147 *295 (Wire 9148 uid 6328,0 9149 shape (OrthoPolyLine 9150 uid 6329,0 9151 va (VaSet 9152 vasetType 3 9153 ) 9154 xt "-17000,89000,-11750,89000" 9155 pts [ 9156 "-17000,89000" 9157 "-11750,89000" 9158 ] 9159 ) 9160 start &183 9161 end &173 9162 sat 32 9163 eat 32 9164 st 0 9165 sf 1 9166 si 0 9167 tg (WTG 9168 uid 6334,0 9169 ps "ConnStartEndStrategy" 9170 stg "STSignalDisplayStrategy" 9171 f (Text 9172 uid 6335,0 9173 va (VaSet 9174 ) 9175 xt "-18000,92000,-11700,93000" 9176 st "not_TEST_TRG" 9177 blo "-18000,92800" 9178 tm "WireNameMgr" 9179 ) 9180 ) 9181 on &179 9182 ) 9183 *296 (Wire 8633 on &168 8634 ) 8635 *275 (Wire 9184 8636 uid 6431,0 9185 8637 shape (OrthoPolyLine … … 9195 8647 ) 9196 8648 start &43 9197 end &14 98649 end &148 9198 8650 sat 32 9199 8651 eat 32 … … 9217 8669 ) 9218 8670 ) 9219 on &15 89220 ) 9221 *2 97(Wire8671 on &157 8672 ) 8673 *276 (Wire 9222 8674 uid 6787,0 9223 8675 shape (OrthoPolyLine … … 9233 8685 ] 9234 8686 ) 9235 start & 2139236 end & 2178687 start &193 8688 end &197 9237 8689 sat 32 9238 8690 eat 1 … … 9256 8708 ) 9257 8709 ) 9258 on & 2149259 ) 9260 *2 98(Wire8710 on &194 8711 ) 8712 *277 (Wire 9261 8713 uid 6880,0 9262 8714 shape (OrthoPolyLine … … 9272 8724 ] 9273 8725 ) 9274 start & 2179275 end & 2158726 start &197 8727 end &195 9276 8728 sat 2 9277 8729 eat 32 … … 9295 8747 ) 9296 8748 ) 9297 on &216 9298 ) 9299 *299 (Wire 9300 uid 7102,0 9301 shape (OrthoPolyLine 9302 uid 7103,0 9303 va (VaSet 9304 vasetType 3 9305 ) 9306 xt "21000,132000,31000,132000" 9307 pts [ 9308 "21000,132000" 9309 "31000,132000" 9310 ] 9311 ) 9312 end &221 9313 sat 16 9314 eat 1 9315 st 0 9316 sf 1 9317 si 0 9318 tg (WTG 9319 uid 7108,0 9320 ps "ConnStartEndStrategy" 9321 stg "STSignalDisplayStrategy" 9322 f (Text 9323 uid 7109,0 9324 va (VaSet 9325 ) 9326 xt "23000,131000,27600,132000" 9327 st "D0_SROUT" 9328 blo "23000,131800" 9329 tm "WireNameMgr" 9330 ) 9331 ) 9332 on &106 9333 ) 9334 *300 (Wire 9335 uid 7110,0 9336 shape (OrthoPolyLine 9337 uid 7111,0 9338 va (VaSet 9339 vasetType 3 9340 ) 9341 xt "21000,133000,31000,133000" 9342 pts [ 9343 "21000,133000" 9344 "31000,133000" 9345 ] 9346 ) 9347 end &221 9348 sat 16 9349 eat 1 9350 st 0 9351 sf 1 9352 si 0 9353 tg (WTG 9354 uid 7116,0 9355 ps "ConnStartEndStrategy" 9356 stg "STSignalDisplayStrategy" 9357 f (Text 9358 uid 7117,0 9359 va (VaSet 9360 ) 9361 xt "23000,132000,27600,133000" 9362 st "D1_SROUT" 9363 blo "23000,132800" 9364 tm "WireNameMgr" 9365 ) 9366 ) 9367 on &107 9368 ) 9369 *301 (Wire 9370 uid 7118,0 9371 shape (OrthoPolyLine 9372 uid 7119,0 9373 va (VaSet 9374 vasetType 3 9375 ) 9376 xt "21000,134000,31000,134000" 9377 pts [ 9378 "21000,134000" 9379 "31000,134000" 9380 ] 9381 ) 9382 end &221 9383 sat 16 9384 eat 1 9385 st 0 9386 sf 1 9387 si 0 9388 tg (WTG 9389 uid 7124,0 9390 ps "ConnStartEndStrategy" 9391 stg "STSignalDisplayStrategy" 9392 f (Text 9393 uid 7125,0 9394 va (VaSet 9395 ) 9396 xt "23000,133000,27200,134000" 9397 st "RSRLOAD" 9398 blo "23000,133800" 9399 tm "WireNameMgr" 9400 ) 9401 ) 9402 on &64 9403 ) 9404 *302 (Wire 8749 on &196 8750 ) 8751 *278 (Wire 9405 8752 uid 7144,0 9406 8753 shape (OrthoPolyLine … … 9416 8763 ] 9417 8764 ) 9418 start &2 219419 end &2 258765 start &201 8766 end &205 9420 8767 sat 2 9421 8768 eat 32 … … 9434 8781 ) 9435 8782 xt "41000,131000,45800,132000" 9436 st "A1_T : ( 3:0)"8783 st "A1_T : (7:0)" 9437 8784 blo "41000,131800" 9438 8785 tm "WireNameMgr" 9439 8786 ) 9440 8787 ) 9441 on &2 269442 ) 9443 * 303(Wire8788 on &206 8789 ) 8790 *279 (Wire 9444 8791 uid 7477,0 9445 8792 shape (OrthoPolyLine … … 9455 8802 ) 9456 8803 start &38 9457 end &2 298804 end &209 9458 8805 es 0 9459 8806 sat 32 … … 9476 8823 ) 9477 8824 ) 9478 on &2 279479 ) 9480 * 304(Wire9481 uid 7487,08825 on &207 8826 ) 8827 *280 (Wire 8828 uid 8853,0 9482 8829 shape (OrthoPolyLine 9483 uid 7488,0 8830 uid 8854,0 8831 va (VaSet 8832 vasetType 3 8833 lineWidth 2 8834 ) 8835 xt "10000,109000,51250,132000" 8836 pts [ 8837 "51250,109000" 8838 "10000,109000" 8839 "10000,132000" 8840 "31000,132000" 8841 ] 8842 ) 8843 start &30 8844 end &201 8845 sat 32 8846 eat 1 8847 sty 1 8848 st 0 8849 sf 1 8850 si 0 8851 tg (WTG 8852 uid 8857,0 8853 ps "ConnStartEndStrategy" 8854 stg "STSignalDisplayStrategy" 8855 f (Text 8856 uid 8858,0 8857 va (VaSet 8858 ) 8859 xt "42000,108000,50500,109000" 8860 st "drs_channel_id : (3:0)" 8861 blo "42000,108800" 8862 tm "WireNameMgr" 8863 ) 8864 ) 8865 on &221 8866 ) 8867 *281 (Wire 8868 uid 9492,0 8869 shape (OrthoPolyLine 8870 uid 9493,0 9484 8871 va (VaSet 9485 8872 vasetType 3 … … 9491 8878 ] 9492 8879 ) 9493 end &2 218880 end &201 9494 8881 sat 16 9495 8882 eat 1 … … 9498 8885 si 0 9499 8886 tg (WTG 9500 uid 7493,08887 uid 9498,0 9501 8888 ps "ConnStartEndStrategy" 9502 8889 stg "STSignalDisplayStrategy" 9503 8890 f (Text 9504 uid 7494,09505 va (VaSet 9506 ) 9507 xt "23000,134000,2 5700,135000"9508 st " dummy"8891 uid 9499,0 8892 va (VaSet 8893 ) 8894 xt "23000,134000,26700,135000" 8895 st "TRG_OR" 9509 8896 blo "23000,134800" 9510 8897 tm "WireNameMgr" 9511 8898 ) 9512 8899 ) 9513 on &227 8900 on &169 8901 ) 8902 *282 (Wire 8903 uid 9502,0 8904 shape (OrthoPolyLine 8905 uid 9503,0 8906 va (VaSet 8907 vasetType 3 8908 ) 8909 xt "46000,69000,51250,69000" 8910 pts [ 8911 "51250,69000" 8912 "46000,69000" 8913 ] 8914 ) 8915 start &26 8916 sat 32 8917 eat 16 8918 st 0 8919 sf 1 8920 si 0 8921 tg (WTG 8922 uid 9506,0 8923 ps "ConnStartEndStrategy" 8924 stg "STSignalDisplayStrategy" 8925 f (Text 8926 uid 9507,0 8927 va (VaSet 8928 ) 8929 xt "47000,68000,50100,69000" 8930 st "CLK_50" 8931 blo "47000,68800" 8932 tm "WireNameMgr" 8933 ) 8934 ) 8935 on &222 9514 8936 ) 9515 8937 ] … … 9525 8947 color "26368,26368,26368" 9526 8948 ) 9527 packageList * 305(PackageList8949 packageList *283 (PackageList 9528 8950 uid 41,0 9529 8951 stg "VerticalLayoutStrategy" 9530 8952 textVec [ 9531 * 306(Text8953 *284 (Text 9532 8954 uid 42,0 9533 8955 va (VaSet … … 9538 8960 blo "0,800" 9539 8961 ) 9540 * 307(MLText8962 *285 (MLText 9541 8963 uid 43,0 9542 8964 va (VaSet … … 9559 8981 stg "VerticalLayoutStrategy" 9560 8982 textVec [ 9561 * 308(Text8983 *286 (Text 9562 8984 uid 45,0 9563 8985 va (VaSet … … 9569 8991 blo "20000,800" 9570 8992 ) 9571 * 309(Text8993 *287 (Text 9572 8994 uid 46,0 9573 8995 va (VaSet … … 9579 9001 blo "20000,1800" 9580 9002 ) 9581 * 310(MLText9003 *288 (MLText 9582 9004 uid 47,0 9583 9005 va (VaSet … … 9589 9011 tm "BdCompilerDirectivesTextMgr" 9590 9012 ) 9591 * 311(Text9013 *289 (Text 9592 9014 uid 48,0 9593 9015 va (VaSet … … 9599 9021 blo "20000,4800" 9600 9022 ) 9601 * 312(MLText9023 *290 (MLText 9602 9024 uid 49,0 9603 9025 va (VaSet … … 9607 9029 tm "BdCompilerDirectivesTextMgr" 9608 9030 ) 9609 * 313(Text9031 *291 (Text 9610 9032 uid 50,0 9611 9033 va (VaSet … … 9617 9039 blo "20000,5800" 9618 9040 ) 9619 * 314(MLText9041 *292 (MLText 9620 9042 uid 51,0 9621 9043 va (VaSet … … 9628 9050 associable 1 9629 9051 ) 9630 windowSize "0, 0,1281,1002"9631 viewArea " 2340,64220,87220,128140"9632 cachedDiagramExtent " -35500,0,699000,450107"9052 windowSize "0,22,1281,1024" 9053 viewArea "-13800,92200,71080,160280" 9054 cachedDiagramExtent "0,0,699000,450107" 9633 9055 pageSetupInfo (PageSetupInfo 9634 9056 ptrCmd "" … … 9641 9063 ) 9642 9064 hasePageBreakOrigin 1 9643 pageBreakOrigin " -73000,0"9644 lastUid 8751,09065 pageBreakOrigin "0,0" 9066 lastUid 9715,0 9645 9067 defaultCommentText (CommentText 9646 9068 shape (Rectangle … … 9704 9126 stg "VerticalLayoutStrategy" 9705 9127 textVec [ 9706 * 315(Text9128 *293 (Text 9707 9129 va (VaSet 9708 9130 font "Arial,8,1" … … 9713 9135 tm "BdLibraryNameMgr" 9714 9136 ) 9715 * 316(Text9137 *294 (Text 9716 9138 va (VaSet 9717 9139 font "Arial,8,1" … … 9722 9144 tm "BlkNameMgr" 9723 9145 ) 9724 * 317(Text9146 *295 (Text 9725 9147 va (VaSet 9726 9148 font "Arial,8,1" … … 9773 9195 stg "VerticalLayoutStrategy" 9774 9196 textVec [ 9775 * 318(Text9197 *296 (Text 9776 9198 va (VaSet 9777 9199 font "Arial,8,1" … … 9781 9203 blo "550,4300" 9782 9204 ) 9783 * 319(Text9205 *297 (Text 9784 9206 va (VaSet 9785 9207 font "Arial,8,1" … … 9789 9211 blo "550,5300" 9790 9212 ) 9791 * 320(Text9213 *298 (Text 9792 9214 va (VaSet 9793 9215 font "Arial,8,1" … … 9838 9260 stg "VerticalLayoutStrategy" 9839 9261 textVec [ 9840 * 321(Text9262 *299 (Text 9841 9263 va (VaSet 9842 9264 font "Arial,8,1" … … 9847 9269 tm "BdLibraryNameMgr" 9848 9270 ) 9849 *3 22(Text9271 *300 (Text 9850 9272 va (VaSet 9851 9273 font "Arial,8,1" … … 9856 9278 tm "CptNameMgr" 9857 9279 ) 9858 *3 23(Text9280 *301 (Text 9859 9281 va (VaSet 9860 9282 font "Arial,8,1" … … 9910 9332 stg "VerticalLayoutStrategy" 9911 9333 textVec [ 9912 *3 24(Text9334 *302 (Text 9913 9335 va (VaSet 9914 9336 font "Arial,8,1" … … 9918 9340 blo "500,4300" 9919 9341 ) 9920 *3 25(Text9342 *303 (Text 9921 9343 va (VaSet 9922 9344 font "Arial,8,1" … … 9926 9348 blo "500,5300" 9927 9349 ) 9928 *3 26(Text9350 *304 (Text 9929 9351 va (VaSet 9930 9352 font "Arial,8,1" … … 9971 9393 stg "VerticalLayoutStrategy" 9972 9394 textVec [ 9973 *3 27(Text9395 *305 (Text 9974 9396 va (VaSet 9975 9397 font "Arial,8,1" … … 9979 9401 blo "50,4300" 9980 9402 ) 9981 *3 28(Text9403 *306 (Text 9982 9404 va (VaSet 9983 9405 font "Arial,8,1" … … 9987 9409 blo "50,5300" 9988 9410 ) 9989 *3 29(Text9411 *307 (Text 9990 9412 va (VaSet 9991 9413 font "Arial,8,1" … … 10028 9450 stg "VerticalLayoutStrategy" 10029 9451 textVec [ 10030 *3 30(Text9452 *308 (Text 10031 9453 va (VaSet 10032 9454 font "Arial,8,1" … … 10037 9459 tm "HdlTextNameMgr" 10038 9460 ) 10039 *3 31(Text9461 *309 (Text 10040 9462 va (VaSet 10041 9463 font "Arial,8,1" … … 10440 9862 stg "VerticalLayoutStrategy" 10441 9863 textVec [ 10442 *3 32(Text9864 *310 (Text 10443 9865 va (VaSet 10444 9866 font "Arial,8,1" … … 10448 9870 blo "14100,20800" 10449 9871 ) 10450 *3 33(MLText9872 *311 (MLText 10451 9873 va (VaSet 10452 9874 ) … … 10500 9922 stg "VerticalLayoutStrategy" 10501 9923 textVec [ 10502 *3 34(Text9924 *312 (Text 10503 9925 va (VaSet 10504 9926 font "Arial,8,1" … … 10508 9930 blo "14100,20800" 10509 9931 ) 10510 *3 35(MLText9932 *313 (MLText 10511 9933 va (VaSet 10512 9934 ) … … 10652 10074 commonDM (CommonDM 10653 10075 ldm (LogicalDM 10654 suid 1 58,010076 suid 163,0 10655 10077 usingSuid 1 10656 emptyRow *3 36(LEmptyRow10078 emptyRow *314 (LEmptyRow 10657 10079 ) 10658 10080 uid 54,0 10659 10081 optionalChildren [ 10660 *3 37(RefLabelRowHdr10661 ) 10662 *3 38(TitleRowHdr10663 ) 10664 *3 39(FilterRowHdr10665 ) 10666 *3 40(RefLabelColHdr10082 *315 (RefLabelRowHdr 10083 ) 10084 *316 (TitleRowHdr 10085 ) 10086 *317 (FilterRowHdr 10087 ) 10088 *318 (RefLabelColHdr 10667 10089 tm "RefLabelColHdrMgr" 10668 10090 ) 10669 *3 41(RowExpandColHdr10091 *319 (RowExpandColHdr 10670 10092 tm "RowExpandColHdrMgr" 10671 10093 ) 10672 *3 42(GroupColHdr10094 *320 (GroupColHdr 10673 10095 tm "GroupColHdrMgr" 10674 10096 ) 10675 *3 43(NameColHdr10097 *321 (NameColHdr 10676 10098 tm "BlockDiagramNameColHdrMgr" 10677 10099 ) 10678 *3 44(ModeColHdr10100 *322 (ModeColHdr 10679 10101 tm "BlockDiagramModeColHdrMgr" 10680 10102 ) 10681 *3 45(TypeColHdr10103 *323 (TypeColHdr 10682 10104 tm "BlockDiagramTypeColHdrMgr" 10683 10105 ) 10684 *3 46(BoundsColHdr10106 *324 (BoundsColHdr 10685 10107 tm "BlockDiagramBoundsColHdrMgr" 10686 10108 ) 10687 *3 47(InitColHdr10109 *325 (InitColHdr 10688 10110 tm "BlockDiagramInitColHdrMgr" 10689 10111 ) 10690 *3 48(EolColHdr10112 *326 (EolColHdr 10691 10113 tm "BlockDiagramEolColHdrMgr" 10692 10114 ) 10693 *3 49(LeafLogPort10115 *327 (LeafLogPort 10694 10116 port (LogicalPort 10695 10117 m 4 … … 10706 10128 uid 327,0 10707 10129 ) 10708 *3 50(LeafLogPort10130 *328 (LeafLogPort 10709 10131 port (LogicalPort 10710 10132 m 4 … … 10719 10141 uid 329,0 10720 10142 ) 10721 *3 51(LeafLogPort10143 *329 (LeafLogPort 10722 10144 port (LogicalPort 10723 10145 m 4 … … 10731 10153 uid 1491,0 10732 10154 ) 10733 *352 (LeafLogPort 10734 port (LogicalPort 10735 m 4 10736 decl (Decl 10737 n "CLK_50" 10738 t "std_logic" 10739 preAdd 0 10740 posAdd 0 10741 o 51 10742 suid 54,0 10743 ) 10744 ) 10745 uid 2275,0 10746 ) 10747 *353 (LeafLogPort 10155 *330 (LeafLogPort 10748 10156 port (LogicalPort 10749 10157 m 1 … … 10758 10166 uid 2435,0 10759 10167 ) 10760 *3 54(LeafLogPort10168 *331 (LeafLogPort 10761 10169 port (LogicalPort 10762 10170 m 4 … … 10771 10179 uid 2437,0 10772 10180 ) 10773 *3 55(LeafLogPort10181 *332 (LeafLogPort 10774 10182 port (LogicalPort 10775 10183 m 4 … … 10784 10192 uid 3037,0 10785 10193 ) 10786 *3 56(LeafLogPort10194 *333 (LeafLogPort 10787 10195 port (LogicalPort 10788 10196 m 1 … … 10796 10204 uid 3039,0 10797 10205 ) 10798 *3 57(LeafLogPort10206 *334 (LeafLogPort 10799 10207 port (LogicalPort 10800 10208 decl (Decl … … 10809 10217 uid 3276,0 10810 10218 ) 10811 *3 58(LeafLogPort10219 *335 (LeafLogPort 10812 10220 port (LogicalPort 10813 10221 decl (Decl … … 10820 10228 uid 3278,0 10821 10229 ) 10822 *3 59(LeafLogPort10230 *336 (LeafLogPort 10823 10231 port (LogicalPort 10824 10232 m 1 … … 10833 10241 uid 3280,0 10834 10242 ) 10835 *3 60(LeafLogPort10243 *337 (LeafLogPort 10836 10244 port (LogicalPort 10837 10245 m 4 … … 10845 10253 uid 3282,0 10846 10254 ) 10847 *3 61(LeafLogPort10255 *338 (LeafLogPort 10848 10256 port (LogicalPort 10849 10257 m 1 … … 10859 10267 uid 3382,0 10860 10268 ) 10861 *3 62(LeafLogPort10269 *339 (LeafLogPort 10862 10270 port (LogicalPort 10863 10271 decl (Decl … … 10871 10279 uid 3384,0 10872 10280 ) 10873 *3 63(LeafLogPort10281 *340 (LeafLogPort 10874 10282 port (LogicalPort 10875 10283 decl (Decl … … 10883 10291 uid 3386,0 10884 10292 ) 10885 *3 64(LeafLogPort10293 *341 (LeafLogPort 10886 10294 port (LogicalPort 10887 10295 decl (Decl … … 10895 10303 uid 3388,0 10896 10304 ) 10897 *3 65(LeafLogPort10305 *342 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(LogicalPort 10982 10390 decl (Decl … … 10989 10397 uid 3526,0 10990 10398 ) 10991 *3 73(LeafLogPort10399 *350 (LeafLogPort 10992 10400 port (LogicalPort 10993 10401 decl (Decl … … 11000 10408 uid 3528,0 11001 10409 ) 11002 *3 74(LeafLogPort10410 *351 (LeafLogPort 11003 10411 port (LogicalPort 11004 10412 decl (Decl … … 11011 10419 uid 3530,0 11012 10420 ) 11013 *3 75(LeafLogPort10421 *352 (LeafLogPort 11014 10422 port (LogicalPort 11015 10423 m 1 … … 11025 10433 uid 3532,0 11026 10434 ) 11027 *3 76(LeafLogPort10435 *353 (LeafLogPort 11028 10436 port (LogicalPort 11029 10437 m 1 … … 11038 10446 uid 3534,0 11039 10447 ) 11040 *3 77(LeafLogPort10448 *354 (LeafLogPort 11041 10449 port (LogicalPort 11042 10450 m 1 … … 11050 10458 uid 3646,0 11051 10459 ) 11052 *3 78(LeafLogPort10460 *355 (LeafLogPort 11053 10461 port (LogicalPort 11054 10462 m 1 … … 11062 10470 uid 3648,0 11063 10471 ) 11064 *3 79(LeafLogPort10472 *356 (LeafLogPort 11065 10473 port (LogicalPort 11066 10474 m 1 … … 11074 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10662 m 1 … … 11262 10670 uid 3892,0 11263 10671 ) 11264 *3 95(LeafLogPort10672 *372 (LeafLogPort 11265 10673 port (LogicalPort 11266 10674 m 1 … … 11274 10682 uid 3894,0 11275 10683 ) 11276 *3 96(LeafLogPort10684 *373 (LeafLogPort 11277 10685 port (LogicalPort 11278 10686 m 1 … … 11287 10695 uid 3896,0 11288 10696 ) 11289 *3 97(LeafLogPort10697 *374 (LeafLogPort 11290 10698 port (LogicalPort 11291 10699 m 1 … … 11299 10707 uid 3898,0 11300 10708 ) 11301 *3 98(LeafLogPort10709 *375 (LeafLogPort 11302 10710 port (LogicalPort 11303 10711 m 1 … … 11311 10719 uid 3900,0 11312 10720 ) 11313 *3 99(LeafLogPort10721 *376 (LeafLogPort 11314 10722 port (LogicalPort 11315 10723 m 1 … … 11325 10733 uid 3902,0 11326 10734 ) 11327 * 400(LeafLogPort10735 *377 (LeafLogPort 11328 10736 port (LogicalPort 11329 10737 m 1 … … 11339 10747 uid 5322,0 11340 10748 ) 11341 * 401(LeafLogPort10749 *378 (LeafLogPort 11342 10750 port (LogicalPort 11343 10751 decl (Decl … … 11351 10759 scheme 0 11352 10760 ) 11353 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3697,0 11744 11145 ) 11745 *4 55(MRCItem11746 litem &3 9011146 *431 (MRCItem 11147 litem &367 11747 11148 pos 34 11748 11149 dimension 20 11749 11150 uid 3699,0 11750 11151 ) 11751 *4 56(MRCItem11752 litem &3 9111152 *432 (MRCItem 11153 litem &368 11753 11154 pos 35 11754 11155 dimension 20 11755 11156 uid 3887,0 11756 11157 ) 11757 *4 57(MRCItem11758 litem &3 9211158 *433 (MRCItem 11159 litem &369 11759 11160 pos 36 11760 11161 dimension 20 11761 11162 uid 3889,0 11762 11163 ) 11763 *4 58(MRCItem11764 litem &3 9311164 *434 (MRCItem 11165 litem &370 11765 11166 pos 37 11766 11167 dimension 20 11767 11168 uid 3891,0 11768 11169 ) 11769 *4 59(MRCItem11770 litem &3 9411170 *435 (MRCItem 11171 litem &371 11771 11172 pos 38 11772 11173 dimension 20 11773 11174 uid 3893,0 11774 11175 ) 11775 *4 60(MRCItem11776 litem &3 9511176 *436 (MRCItem 11177 litem &372 11777 11178 pos 39 11778 11179 dimension 20 11779 11180 uid 3895,0 11780 11181 ) 11781 *4 61(MRCItem11782 litem &3 9611182 *437 (MRCItem 11183 litem &373 11783 11184 pos 40 11784 11185 dimension 20 11785 11186 uid 3897,0 11786 11187 ) 11787 *4 62(MRCItem11788 litem &3 9711188 *438 (MRCItem 11189 litem &374 11789 11190 pos 41 11790 11191 dimension 20 11791 11192 uid 3899,0 11792 11193 ) 11793 *4 63(MRCItem11794 litem &3 9811194 *439 (MRCItem 11195 litem &375 11795 11196 pos 42 11796 11197 dimension 20 11797 11198 uid 3901,0 11798 11199 ) 11799 *4 64(MRCItem11800 litem &3 9911200 *440 (MRCItem 11201 litem &376 11801 11202 pos 43 11802 11203 dimension 20 11803 11204 uid 3903,0 11804 11205 ) 11805 *4 65(MRCItem11806 litem & 40011807 pos 5111206 *441 (MRCItem 11207 litem &377 11208 pos 44 11808 11209 dimension 20 11809 11210 uid 5323,0 11810 11211 ) 11811 *4 66(MRCItem11812 litem & 40111813 pos 5211212 *442 (MRCItem 11213 litem &378 11214 pos 45 11814 11215 dimension 20 11815 11216 uid 5649,0 11816 11217 ) 11817 *4 67(MRCItem11818 litem & 40211819 pos 5 311218 *443 (MRCItem 11219 litem &379 11220 pos 55 11820 11221 dimension 20 11821 11222 uid 6129,0 11822 11223 ) 11823 *4 68(MRCItem11824 litem & 40311825 pos 5411224 *444 (MRCItem 11225 litem &380 11226 pos 46 11826 11227 dimension 20 11827 uid 6 287,011828 ) 11829 *4 69(MRCItem11830 litem & 40411831 pos 5511228 uid 6778,0 11229 ) 11230 *445 (MRCItem 11231 litem &381 11232 pos 47 11832 11233 dimension 20 11833 uid 6315,0 11834 ) 11835 *470 (MRCItem 11836 litem &405 11234 uid 6873,0 11235 ) 11236 *446 (MRCItem 11237 litem &382 11238 pos 48 11239 dimension 20 11240 uid 7135,0 11241 ) 11242 *447 (MRCItem 11243 litem &383 11837 11244 pos 56 11838 11245 dimension 20 11839 uid 6778,011840 ) 11841 *4 71(MRCItem11842 litem & 40611246 uid 7474,0 11247 ) 11248 *448 (MRCItem 11249 litem &384 11843 11250 pos 57 11844 11251 dimension 20 11845 uid 6873,011846 ) 11847 *4 72(MRCItem11848 litem & 40711252 uid 8876,0 11253 ) 11254 *449 (MRCItem 11255 litem &385 11849 11256 pos 58 11850 11257 dimension 20 11851 uid 7135,0 11852 ) 11853 *473 (MRCItem 11854 litem &408 11855 pos 59 11856 dimension 20 11857 uid 7474,0 11258 uid 9517,0 11858 11259 ) 11859 11260 ] … … 11868 11269 uid 73,0 11869 11270 optionalChildren [ 11870 *4 74(MRCItem11871 litem &3 4011271 *450 (MRCItem 11272 litem &318 11872 11273 pos 0 11873 11274 dimension 20 11874 11275 uid 74,0 11875 11276 ) 11876 *4 75(MRCItem11877 litem &3 4211277 *451 (MRCItem 11278 litem &320 11878 11279 pos 1 11879 11280 dimension 50 11880 11281 uid 75,0 11881 11282 ) 11882 *4 76(MRCItem11883 litem &3 4311283 *452 (MRCItem 11284 litem &321 11884 11285 pos 2 11885 11286 dimension 100 11886 11287 uid 76,0 11887 11288 ) 11888 *4 77(MRCItem11889 litem &3 4411289 *453 (MRCItem 11290 litem &322 11890 11291 pos 3 11891 11292 dimension 50 11892 11293 uid 77,0 11893 11294 ) 11894 *4 78(MRCItem11895 litem &3 4511295 *454 (MRCItem 11296 litem &323 11896 11297 pos 4 11897 11298 dimension 100 11898 11299 uid 78,0 11899 11300 ) 11900 *4 79(MRCItem11901 litem &3 4611301 *455 (MRCItem 11302 litem &324 11902 11303 pos 5 11903 11304 dimension 100 11904 11305 uid 79,0 11905 11306 ) 11906 *4 80(MRCItem11907 litem &3 4711307 *456 (MRCItem 11308 litem &325 11908 11309 pos 6 11909 11310 dimension 92 11910 11311 uid 80,0 11911 11312 ) 11912 *4 81(MRCItem11913 litem &3 4811313 *457 (MRCItem 11314 litem &326 11914 11315 pos 7 11915 11316 dimension 80 … … 11931 11332 genericsCommonDM (CommonDM 11932 11333 ldm (LogicalDM 11933 emptyRow *4 82(LEmptyRow11334 emptyRow *458 (LEmptyRow 11934 11335 ) 11935 11336 uid 83,0 11936 11337 optionalChildren [ 11937 *4 83(RefLabelRowHdr11938 ) 11939 *4 84(TitleRowHdr11940 ) 11941 *4 85(FilterRowHdr11942 ) 11943 *4 86(RefLabelColHdr11338 *459 (RefLabelRowHdr 11339 ) 11340 *460 (TitleRowHdr 11341 ) 11342 *461 (FilterRowHdr 11343 ) 11344 *462 (RefLabelColHdr 11944 11345 tm "RefLabelColHdrMgr" 11945 11346 ) 11946 *4 87(RowExpandColHdr11347 *463 (RowExpandColHdr 11947 11348 tm "RowExpandColHdrMgr" 11948 11349 ) 11949 *4 88(GroupColHdr11350 *464 (GroupColHdr 11950 11351 tm "GroupColHdrMgr" 11951 11352 ) 11952 *4 89(NameColHdr11353 *465 (NameColHdr 11953 11354 tm "GenericNameColHdrMgr" 11954 11355 ) 11955 *4 90(TypeColHdr11356 *466 (TypeColHdr 11956 11357 tm "GenericTypeColHdrMgr" 11957 11358 ) 11958 *4 91(InitColHdr11359 *467 (InitColHdr 11959 11360 tm "GenericValueColHdrMgr" 11960 11361 ) 11961 *4 92(PragmaColHdr11362 *468 (PragmaColHdr 11962 11363 tm "GenericPragmaColHdrMgr" 11963 11364 ) 11964 *4 93(EolColHdr11365 *469 (EolColHdr 11965 11366 tm "GenericEolColHdrMgr" 11966 11367 ) … … 11972 11373 uid 95,0 11973 11374 optionalChildren [ 11974 *4 94(Sheet11375 *470 (Sheet 11975 11376 sheetRow (SheetRow 11976 11377 headerVa (MVa … … 11989 11390 font "Tahoma,10,0" 11990 11391 ) 11991 emptyMRCItem *4 95(MRCItem11992 litem &4 8211392 emptyMRCItem *471 (MRCItem 11393 litem &458 11993 11394 pos 0 11994 11395 dimension 20 … … 11996 11397 uid 97,0 11997 11398 optionalChildren [ 11998 *4 96(MRCItem11999 litem &4 8311399 *472 (MRCItem 11400 litem &459 12000 11401 pos 0 12001 11402 dimension 20 12002 11403 uid 98,0 12003 11404 ) 12004 *4 97(MRCItem12005 litem &4 8411405 *473 (MRCItem 11406 litem &460 12006 11407 pos 1 12007 11408 dimension 23 12008 11409 uid 99,0 12009 11410 ) 12010 *4 98(MRCItem12011 litem &4 8511411 *474 (MRCItem 11412 litem &461 12012 11413 pos 2 12013 11414 hidden 1 … … 12026 11427 uid 101,0 12027 11428 optionalChildren [ 12028 *4 99(MRCItem12029 litem &4 8611429 *475 (MRCItem 11430 litem &462 12030 11431 pos 0 12031 11432 dimension 20 12032 11433 uid 102,0 12033 11434 ) 12034 * 500(MRCItem12035 litem &4 8811435 *476 (MRCItem 11436 litem &464 12036 11437 pos 1 12037 11438 dimension 50 12038 11439 uid 103,0 12039 11440 ) 12040 * 501(MRCItem12041 litem &4 8911441 *477 (MRCItem 11442 litem &465 12042 11443 pos 2 12043 11444 dimension 100 12044 11445 uid 104,0 12045 11446 ) 12046 * 502(MRCItem12047 litem &4 9011447 *478 (MRCItem 11448 litem &466 12048 11449 pos 3 12049 11450 dimension 100 12050 11451 uid 105,0 12051 11452 ) 12052 * 503(MRCItem12053 litem &4 9111453 *479 (MRCItem 11454 litem &467 12054 11455 pos 4 12055 11456 dimension 50 12056 11457 uid 106,0 12057 11458 ) 12058 * 504(MRCItem12059 litem &4 9211459 *480 (MRCItem 11460 litem &468 12060 11461 pos 5 12061 11462 dimension 50 12062 11463 uid 107,0 12063 11464 ) 12064 * 505(MRCItem12065 litem &4 9311465 *481 (MRCItem 11466 litem &469 12066 11467 pos 6 12067 11468 dimension 80 … … 12082 11483 type 1 12083 11484 ) 12084 activeModelName "BlockDiag "12085 ) 11485 activeModelName "BlockDiag:CDM" 11486 ) -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd.bak
r246 r252 26 26 instances [ 27 27 (Instance 28 name "I_ testboard_main"28 name "I_board_main" 29 29 duLibraryName "FACT_FAD_lib" 30 30 duName "FAD_main" … … 38 38 mwi 0 39 39 uid 169,0 40 )41 (Instance42 name "I0"43 duLibraryName "FACT_FAD_LIB"44 duName "debouncer"45 elements [46 (GiElement47 name "WIDTH"48 type "INTEGER"49 value "17"50 )51 ]52 mwi 053 uid 6250,054 )55 (Instance56 name "I1"57 duLibraryName "moduleware"58 duName "inv"59 elements [60 ]61 mwi 162 uid 6539,063 40 ) 64 41 (Instance … … 128 105 (vvPair 129 106 variable "HDLDir" 130 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hdl"107 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 131 108 ) 132 109 (vvPair 133 110 variable "HDSDir" 134 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds"111 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 135 112 ) 136 113 (vvPair 137 114 variable "SideDataDesignDir" 138 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info"115 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.info" 139 116 ) 140 117 (vvPair 141 118 variable "SideDataUserDir" 142 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user"119 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd.user" 143 120 ) 144 121 (vvPair 145 122 variable "SourceDir" 146 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds"123 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 147 124 ) 148 125 (vvPair … … 160 137 (vvPair 161 138 variable "d" 162 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board"139 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 163 140 ) 164 141 (vvPair 165 142 variable "d_logical" 166 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board"143 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 167 144 ) 168 145 (vvPair 169 146 variable "date" 170 value " 22.06.2010"147 value "14.07.2010" 171 148 ) 172 149 (vvPair 173 150 variable "day" 174 value " Di"151 value "Mi" 175 152 ) 176 153 (vvPair 177 154 variable "day_long" 178 value " Dienstag"155 value "Mittwoch" 179 156 ) 180 157 (vvPair 181 158 variable "dd" 182 value " 22"159 value "14" 183 160 ) 184 161 (vvPair … … 208 185 (vvPair 209 186 variable "host" 210 value " TU-CC4900F8C7D2"187 value "E5B-LABOR6" 211 188 ) 212 189 (vvPair … … 219 196 ) 220 197 (vvPair 198 variable "library_downstream_HdsLintPlugin" 199 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 200 ) 201 (vvPair 221 202 variable "library_downstream_ISEPARInvoke" 222 203 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 236 217 (vvPair 237 218 variable "mm" 238 value "0 6"219 value "07" 239 220 ) 240 221 (vvPair … … 244 225 (vvPair 245 226 variable "month" 246 value "Ju n"227 value "Jul" 247 228 ) 248 229 (vvPair 249 230 variable "month_long" 250 value "Ju ni"231 value "Juli" 251 232 ) 252 233 (vvPair 253 234 variable "p" 254 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd"235 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\struct.bd" 255 236 ) 256 237 (vvPair 257 238 variable "p_logical" 258 value "C:\\FPGA_projects\\ FACT_FAD_22062010\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd"239 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\struct.bd" 259 240 ) 260 241 (vvPair … … 312 293 (vvPair 313 294 variable "time" 314 value "1 1:16:21"295 value "15:24:46" 315 296 ) 316 297 (vvPair … … 364 345 bg "0,0,32768" 365 346 ) 366 xt "99200,4000,108 700,5000"347 xt "99200,4000,108500,5000" 367 348 st " 368 349 by %user on %dd %month %year … … 1831 1812 font "Arial,8,1" 1832 1813 ) 1833 xt "52200,125000,5 9400,126000"1834 st "I_ testboard_main"1814 xt "52200,125000,58000,126000" 1815 st "I_board_main" 1835 1816 blo "52200,125800" 1836 1817 tm "InstanceNameMgr" … … 2065 2046 preAdd 0 2066 2047 posAdd 0 2067 o 5 52048 o 56 2068 2049 suid 5,0 2069 2050 ) … … 2073 2054 font "Courier New,8,0" 2074 2055 ) 2075 xt "39000,48 000,67000,48800"2056 xt "39000,48800,67000,49600" 2076 2057 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 2077 2058 ) … … 2083 2064 t "std_logic_vector" 2084 2065 b "(1 downto 0)" 2085 o 5 62066 o 57 2086 2067 suid 6,0 2087 2068 ) … … 2091 2072 font "Courier New,8,0" 2092 2073 ) 2093 xt "39000,4 8800,67000,49600"2074 xt "39000,49600,67000,50400" 2094 2075 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 2095 2076 ) … … 2406 2387 n "adc_data_array" 2407 2388 t "adc_data_array_type" 2408 o 5 42389 o 55 2409 2390 suid 29,0 2410 2391 ) … … 2414 2395 font "Courier New,8,0" 2415 2396 ) 2416 xt "39000,4 7200,62500,48000"2397 xt "39000,48000,62500,48800" 2417 2398 st "SIGNAL adc_data_array : adc_data_array_type" 2418 2399 ) 2419 2400 ) 2420 2401 *63 (Net 2421 uid 2267,02422 decl (Decl2423 n "CLK_50"2424 t "std_logic"2425 preAdd 02426 posAdd 02427 o 512428 suid 54,02429 )2430 declText (MLText2431 uid 2268,02432 va (VaSet2433 font "Courier New,8,0"2434 )2435 xt "39000,44800,57000,45600"2436 st "SIGNAL CLK_50 : std_logic"2437 )2438 )2439 *64 (Net2440 2402 uid 2407,0 2441 2403 decl (Decl 2442 2404 n "RSRLOAD" 2443 2405 t "std_logic" 2444 o 3 52406 o 36 2445 2407 suid 57,0 2446 2408 i "'0'" … … 2451 2413 font "Courier New,8,0" 2452 2414 ) 2453 xt "39000,31 000,68000,31800"2415 xt "39000,31800,68000,32600" 2454 2416 st "RSRLOAD : std_logic := '0'" 2455 2417 ) 2456 2418 ) 2457 *6 5(PortIoOut2419 *64 (PortIoOut 2458 2420 uid 2415,0 2459 2421 shape (CompositeShape … … 2500 2462 ) 2501 2463 ) 2502 *6 6(Net2464 *65 (Net 2503 2465 uid 2421,0 2504 2466 decl (Decl 2505 2467 n "SRCLK" 2506 2468 t "std_logic" 2507 o 5 22469 o 53 2508 2470 suid 58,0 2509 2471 i "'0'" … … 2514 2476 font "Courier New,8,0" 2515 2477 ) 2516 xt "39000,4 5600,71500,46400"2478 xt "39000,46400,71500,47200" 2517 2479 st "SIGNAL SRCLK : std_logic := '0'" 2518 2480 ) 2519 2481 ) 2520 *6 7(Net2482 *66 (Net 2521 2483 uid 3019,0 2522 2484 decl (Decl … … 2524 2486 t "std_logic_vector" 2525 2487 b "(3 DOWNTO 0)" 2526 o 592488 o 60 2527 2489 suid 65,0 2528 2490 ) … … 2532 2494 font "Courier New,8,0" 2533 2495 ) 2534 xt "39000,5 1200,67000,52000"2496 xt "39000,52000,67000,52800" 2535 2497 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 2536 2498 ) 2537 2499 ) 2538 *6 8(Net2500 *67 (Net 2539 2501 uid 3025,0 2540 2502 decl (Decl 2541 2503 n "DAC_CS" 2542 2504 t "std_logic" 2543 o 2 12505 o 22 2544 2506 suid 66,0 2545 2507 ) … … 2549 2511 font "Courier New,8,0" 2550 2512 ) 2551 xt "39000, 19800,53500,20600"2513 xt "39000,20600,53500,21400" 2552 2514 st "DAC_CS : std_logic" 2553 2515 ) 2554 2516 ) 2555 *6 9(PortIoOut2517 *68 (PortIoOut 2556 2518 uid 3153,0 2557 2519 shape (CompositeShape … … 2598 2560 ) 2599 2561 ) 2600 * 70(Net2562 *69 (Net 2601 2563 uid 3216,0 2602 2564 decl (Decl … … 2617 2579 ) 2618 2580 ) 2619 *7 1(Net2581 *70 (Net 2620 2582 uid 3226,0 2621 2583 decl (Decl … … 2634 2596 ) 2635 2597 ) 2636 *7 2(HdlText2598 *71 (HdlText 2637 2599 uid 3248,0 2638 2600 optionalChildren [ 2639 *7 3(EmbeddedText2601 *72 (EmbeddedText 2640 2602 uid 3254,0 2641 2603 commentText (CommentText … … 2689 2651 stg "VerticalLayoutStrategy" 2690 2652 textVec [ 2691 *7 4(Text2653 *73 (Text 2692 2654 uid 3251,0 2693 2655 va (VaSet … … 2699 2661 tm "HdlTextNameMgr" 2700 2662 ) 2701 *7 5(Text2663 *74 (Text 2702 2664 uid 3252,0 2703 2665 va (VaSet … … 2725 2687 viewiconposition 0 2726 2688 ) 2727 *7 6(Net2689 *75 (Net 2728 2690 uid 3266,0 2729 2691 decl (Decl … … 2731 2693 t "std_logic_vector" 2732 2694 b "(3 downto 0)" 2733 o 1 62695 o 17 2734 2696 suid 71,0 2735 2697 ) … … 2739 2701 font "Courier New,8,0" 2740 2702 ) 2741 xt "39000,1 5800,63500,16600"2703 xt "39000,16600,63500,17400" 2742 2704 st "A_CLK : std_logic_vector(3 downto 0)" 2743 2705 ) 2744 2706 ) 2745 *7 7(Net2707 *76 (Net 2746 2708 uid 3268,0 2747 2709 decl (Decl 2748 2710 n "CLK_25_PS" 2749 2711 t "std_logic" 2750 o 5 02712 o 51 2751 2713 suid 72,0 2752 2714 ) … … 2756 2718 font "Courier New,8,0" 2757 2719 ) 2758 xt "39000,44 000,57000,44800"2720 xt "39000,44800,57000,45600" 2759 2721 st "SIGNAL CLK_25_PS : std_logic" 2760 2722 ) 2761 2723 ) 2762 *7 8(PortIoOut2724 *77 (PortIoOut 2763 2725 uid 3284,0 2764 2726 shape (CompositeShape … … 2805 2767 ) 2806 2768 ) 2807 *7 9(Net2769 *78 (Net 2808 2770 uid 3290,0 2809 2771 decl (Decl … … 2812 2774 preAdd 0 2813 2775 posAdd 0 2814 o 3 02776 o 31 2815 2777 suid 73,0 2816 2778 ) … … 2820 2782 font "Courier New,8,0" 2821 2783 ) 2822 xt "39000,27 000,53500,27800"2784 xt "39000,27800,53500,28600" 2823 2785 st "OE_ADC : STD_LOGIC" 2824 2786 ) 2825 2787 ) 2826 * 80(PortIoIn2788 *79 (PortIoIn 2827 2789 uid 3292,0 2828 2790 shape (CompositeShape … … 2869 2831 ) 2870 2832 ) 2871 *8 1(Net2833 *80 (Net 2872 2834 uid 3298,0 2873 2835 decl (Decl … … 2887 2849 ) 2888 2850 ) 2889 *8 2(HdlText2851 *81 (HdlText 2890 2852 uid 3300,0 2891 2853 optionalChildren [ 2892 *8 3(EmbeddedText2854 *82 (EmbeddedText 2893 2855 uid 3306,0 2894 2856 commentText (CommentText … … 2942 2904 stg "VerticalLayoutStrategy" 2943 2905 textVec [ 2944 *8 4(Text2906 *83 (Text 2945 2907 uid 3303,0 2946 2908 va (VaSet … … 2952 2914 tm "HdlTextNameMgr" 2953 2915 ) 2954 *8 5(Text2916 *84 (Text 2955 2917 uid 3304,0 2956 2918 va (VaSet … … 2978 2940 viewiconposition 0 2979 2941 ) 2980 *8 6(PortIoIn2942 *85 (PortIoIn 2981 2943 uid 3310,0 2982 2944 shape (CompositeShape … … 3023 2985 ) 3024 2986 ) 3025 *8 7(PortIoIn2987 *86 (PortIoIn 3026 2988 uid 3332,0 3027 2989 shape (CompositeShape … … 3068 3030 ) 3069 3031 ) 3070 *8 8(PortIoIn3032 *87 (PortIoIn 3071 3033 uid 3338,0 3072 3034 shape (CompositeShape … … 3113 3075 ) 3114 3076 ) 3115 *8 9(PortIoIn3077 *88 (PortIoIn 3116 3078 uid 3344,0 3117 3079 shape (CompositeShape … … 3158 3120 ) 3159 3121 ) 3160 * 90(Net3122 *89 (Net 3161 3123 uid 3374,0 3162 3124 decl (Decl … … 3176 3138 ) 3177 3139 ) 3178 *9 1(Net3140 *90 (Net 3179 3141 uid 3376,0 3180 3142 decl (Decl … … 3194 3156 ) 3195 3157 ) 3196 *9 2(Net3158 *91 (Net 3197 3159 uid 3378,0 3198 3160 decl (Decl … … 3212 3174 ) 3213 3175 ) 3214 *9 3(Net3176 *92 (Net 3215 3177 uid 3380,0 3216 3178 decl (Decl … … 3230 3192 ) 3231 3193 ) 3232 *9 4(HdlText3194 *93 (HdlText 3233 3195 uid 3394,0 3234 3196 optionalChildren [ 3235 *9 5(EmbeddedText3197 *94 (EmbeddedText 3236 3198 uid 3400,0 3237 3199 commentText (CommentText … … 3285 3247 stg "VerticalLayoutStrategy" 3286 3248 textVec [ 3287 *9 6(Text3249 *95 (Text 3288 3250 uid 3397,0 3289 3251 va (VaSet … … 3295 3257 tm "HdlTextNameMgr" 3296 3258 ) 3297 *9 7(Text3259 *96 (Text 3298 3260 uid 3398,0 3299 3261 va (VaSet … … 3321 3283 viewiconposition 0 3322 3284 ) 3323 *9 8(Net3285 *97 (Net 3324 3286 uid 3460,0 3325 3287 decl (Decl 3326 3288 n "D0_SRCLK" 3327 3289 t "STD_LOGIC" 3328 o 1 73290 o 18 3329 3291 suid 87,0 3330 3292 ) … … 3334 3296 font "Courier New,8,0" 3335 3297 ) 3336 xt "39000,1 6600,53500,17400"3298 xt "39000,17400,53500,18200" 3337 3299 st "D0_SRCLK : STD_LOGIC" 3338 3300 ) 3339 3301 ) 3340 *9 9(Net3302 *98 (Net 3341 3303 uid 3462,0 3342 3304 decl (Decl 3343 3305 n "D1_SRCLK" 3344 3306 t "STD_LOGIC" 3345 o 1 83307 o 19 3346 3308 suid 88,0 3347 3309 ) … … 3351 3313 font "Courier New,8,0" 3352 3314 ) 3353 xt "39000,1 7400,53500,18200"3315 xt "39000,18200,53500,19000" 3354 3316 st "D1_SRCLK : STD_LOGIC" 3355 3317 ) 3356 3318 ) 3357 * 100(Net3319 *99 (Net 3358 3320 uid 3464,0 3359 3321 decl (Decl 3360 3322 n "D2_SRCLK" 3361 3323 t "STD_LOGIC" 3362 o 193324 o 20 3363 3325 suid 89,0 3364 3326 ) … … 3368 3330 font "Courier New,8,0" 3369 3331 ) 3370 xt "39000,1 8200,53500,19000"3332 xt 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"3000,134300" 3642 tm "WireNameMgr" 3643 ) 3644 ) 3645 ) 3646 *110 (Net 3685 3647 uid 3514,0 3686 3648 decl (Decl … … 3688 3650 t "std_logic_vector" 3689 3651 b "(3 DOWNTO 0)" 3690 o 2 43652 o 25 3691 3653 suid 95,0 3692 3654 i "(others => '0')" … … 3697 3659 font "Courier New,8,0" 3698 3660 ) 3699 xt "39000,2 2200,74000,23000"3661 xt "39000,23000,74000,23800" 3700 3662 st "D_A : std_logic_vector(3 DOWNTO 0) := (others => '0')" 3701 3663 ) 3702 3664 ) 3703 *11 2(PortIoOut3665 *111 (PortIoOut 3704 3666 uid 3516,0 3705 3667 shape (CompositeShape … … 3746 3708 ) 3747 3709 ) 3748 *11 3(Net3710 *112 (Net 3749 3711 uid 3522,0 3750 3712 decl (Decl 3751 3713 n "DWRITE" 3752 3714 t "std_logic" 3753 o 2 33715 o 24 3754 3716 suid 96,0 3755 3717 i "'0'" … … 3760 3722 font "Courier New,8,0" 3761 3723 ) 3762 xt "39000,2 1400,68000,22200"3724 xt "39000,22200,68000,23000" 3763 3725 st "DWRITE : std_logic := '0'" 3764 3726 ) 3765 3727 ) 3766 *11 4(PortIoOut3728 *113 (PortIoOut 3767 3729 uid 3536,0 3768 3730 shape (CompositeShape … … 3808 3770 ) 3809 3771 ) 3810 *11 5(HdlText3772 *114 (HdlText 3811 3773 uid 3542,0 3812 3774 optionalChildren [ 3813 *11 6(EmbeddedText3775 *115 (EmbeddedText 3814 3776 uid 3612,0 3815 3777 commentText (CommentText … … 3863 3825 stg "VerticalLayoutStrategy" 3864 3826 textVec [ 3865 *11 7(Text3827 *116 (Text 3866 3828 uid 3545,0 3867 3829 va (VaSet … … 3873 3835 tm "HdlTextNameMgr" 3874 3836 ) 3875 *11 8(Text3837 *117 (Text 3876 3838 uid 3546,0 3877 3839 va (VaSet … … 3899 3861 viewiconposition 0 3900 3862 ) 3901 *11 9(PortIoOut3863 *118 (PortIoOut 3902 3864 uid 3548,0 3903 3865 shape (CompositeShape … … 3943 3905 ) 3944 3906 ) 3945 *1 20(PortIoOut3907 *119 (PortIoOut 3946 3908 uid 3554,0 3947 3909 shape (CompositeShape … … 3987 3949 ) 3988 3950 ) 3989 *12 1(PortIoOut3951 *120 (PortIoOut 3990 3952 uid 3560,0 3991 3953 shape (CompositeShape … … 4031 3993 ) 4032 3994 ) 4033 *12 2(PortIoOut3995 *121 (PortIoOut 4034 3996 uid 3566,0 4035 3997 shape (CompositeShape … … 4075 4037 ) 4076 4038 ) 4077 *12 3(Net4039 *122 (Net 4078 4040 uid 3604,0 4079 4041 decl (Decl 4080 4042 n "T0_CS" 4081 4043 t "std_logic" 4082 o 3 84044 o 39 4083 4045 suid 101,0 4084 4046 ) … … 4088 4050 font "Courier New,8,0" 4089 4051 ) 4090 xt "39000,3 3400,53500,34200"4052 xt "39000,34200,53500,35000" 4091 4053 st "T0_CS : std_logic" 4092 4054 ) 4093 4055 ) 4094 *12 4(Net4056 *123 (Net 4095 4057 uid 3606,0 4096 4058 decl (Decl 4097 4059 n "T1_CS" 4098 4060 t "std_logic" 4099 o 394061 o 40 4100 4062 suid 102,0 4101 4063 ) … … 4105 4067 font "Courier New,8,0" 4106 4068 ) 4107 xt "39000,3 4200,53500,35000"4069 xt "39000,35000,53500,35800" 4108 4070 st "T1_CS : std_logic" 4109 4071 ) 4110 4072 ) 4111 *12 5(Net4073 *124 (Net 4112 4074 uid 3608,0 4113 4075 decl (Decl 4114 4076 n "T2_CS" 4115 4077 t "std_logic" 4116 o 4 04078 o 41 4117 4079 suid 103,0 4118 4080 ) … … 4122 4084 font "Courier New,8,0" 4123 4085 ) 4124 xt "39000,35 000,53500,35800"4086 xt "39000,35800,53500,36600" 4125 4087 st "T2_CS : std_logic" 4126 4088 ) 4127 4089 ) 4128 *12 6(Net4090 *125 (Net 4129 4091 uid 3610,0 4130 4092 decl (Decl 4131 4093 n "T3_CS" 4132 4094 t "std_logic" 4133 o 4 14095 o 42 4134 4096 suid 104,0 4135 4097 ) … … 4139 4101 font "Courier New,8,0" 4140 4102 ) 4141 xt "39000,3 5800,53500,36600"4103 xt "39000,36600,53500,37400" 4142 4104 st "T3_CS : std_logic" 4143 4105 ) 4144 4106 ) 4145 *12 7(PortIoOut4107 *126 (PortIoOut 4146 4108 uid 3624,0 4147 4109 shape (CompositeShape … … 4187 4149 ) 4188 4150 ) 4189 *12 8(Net4151 *127 (Net 4190 4152 uid 3630,0 4191 4153 decl (Decl 4192 4154 n "S_CLK" 4193 4155 t "std_logic" 4194 o 3 74156 o 38 4195 4157 suid 105,0 4196 4158 ) … … 4200 4162 font "Courier New,8,0" 4201 4163 ) 4202 xt "39000,3 2600,53500,33400"4164 xt "39000,33400,53500,34200" 4203 4165 st "S_CLK : std_logic" 4204 4166 ) 4205 4167 ) 4206 *12 9(Net4168 *128 (Net 4207 4169 uid 3632,0 4208 4170 decl (Decl … … 4210 4172 t "std_logic_vector" 4211 4173 b "(9 DOWNTO 0)" 4212 o 4 34174 o 44 4213 4175 suid 106,0 4214 4176 ) … … 4218 4180 font "Courier New,8,0" 4219 4181 ) 4220 xt "39000,3 7400,63500,38200"4182 xt "39000,38200,63500,39000" 4221 4183 st "W_A : std_logic_vector(9 DOWNTO 0)" 4222 4184 ) 4223 4185 ) 4224 *1 30(Net4186 *129 (Net 4225 4187 uid 3634,0 4226 4188 decl (Decl … … 4228 4190 t "std_logic_vector" 4229 4191 b "(15 DOWNTO 0)" 4230 o 494192 o 50 4231 4193 suid 107,0 4232 4194 ) … … 4236 4198 font "Courier New,8,0" 4237 4199 ) 4238 xt "39000,4 2200,64000,43000"4200 xt "39000,43000,64000,43800" 4239 4201 st "W_D : std_logic_vector(15 DOWNTO 0)" 4240 4202 ) 4241 4203 ) 4242 *13 1(Net4204 *130 (Net 4243 4205 uid 3636,0 4244 4206 decl (Decl 4245 4207 n "W_RES" 4246 4208 t "std_logic" 4247 o 4 64209 o 47 4248 4210 suid 108,0 4249 4211 i "'1'" … … 4254 4216 font "Courier New,8,0" 4255 4217 ) 4256 xt "39000, 39800,68000,40600"4218 xt "39000,40600,68000,41400" 4257 4219 st "W_RES : std_logic := '1'" 4258 4220 ) 4259 4221 ) 4260 *13 2(Net4222 *131 (Net 4261 4223 uid 3638,0 4262 4224 decl (Decl 4263 4225 n "W_RD" 4264 4226 t "std_logic" 4265 o 4 54227 o 46 4266 4228 suid 109,0 4267 4229 i "'1'" … … 4272 4234 font "Courier New,8,0" 4273 4235 ) 4274 xt "39000,39 000,68000,39800"4236 xt "39000,39800,68000,40600" 4275 4237 st "W_RD : std_logic := '1'" 4276 4238 ) 4277 4239 ) 4278 *13 3(Net4240 *132 (Net 4279 4241 uid 3640,0 4280 4242 decl (Decl 4281 4243 n "W_WR" 4282 4244 t "std_logic" 4283 o 4 74245 o 48 4284 4246 suid 110,0 4285 4247 i "'1'" … … 4290 4252 font "Courier New,8,0" 4291 4253 ) 4292 xt "39000,4 0600,68000,41400"4254 xt "39000,41400,68000,42200" 4293 4255 st "W_WR : std_logic := '1'" 4294 4256 ) 4295 4257 ) 4296 *13 4(Net4258 *133 (Net 4297 4259 uid 3642,0 4298 4260 decl (Decl … … 4311 4273 ) 4312 4274 ) 4313 *13 5(Net4275 *134 (Net 4314 4276 uid 3644,0 4315 4277 decl (Decl 4316 4278 n "W_CS" 4317 4279 t "std_logic" 4318 o 4 44280 o 45 4319 4281 suid 112,0 4320 4282 i "'1'" … … 4325 4287 font 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1400,53500,42200"4412 xt "39000,42200,53500,43000" 4451 4413 st "MISO : std_logic" 4452 4414 ) 4453 4415 ) 4454 *1 40(HdlText4416 *139 (HdlText 4455 4417 uid 3700,0 4456 4418 optionalChildren [ 4457 *14 1(EmbeddedText4419 *140 (EmbeddedText 4458 4420 uid 3706,0 4459 4421 commentText (CommentText … … 4522 4484 stg "VerticalLayoutStrategy" 4523 4485 textVec [ 4524 *14 2(Text4486 *141 (Text 4525 4487 uid 3703,0 4526 4488 va (VaSet … … 4532 4494 tm "HdlTextNameMgr" 4533 4495 ) 4534 *14 3(Text4496 *142 (Text 4535 4497 uid 3704,0 4536 4498 va (VaSet … … 4558 4520 viewiconposition 0 4559 4521 ) 4560 *14 4(PortIoOut4522 *143 (PortIoOut 4561 4523 uid 3710,0 4562 4524 shape (CompositeShape … … 4602 4564 ) 4603 4565 ) 4604 *14 5(PortIoOut4566 *144 (PortIoOut 4605 4567 uid 3716,0 4606 4568 shape (CompositeShape … … 4646 4608 ) 4647 4609 ) 4648 *14 6(PortIoOut4610 *145 (PortIoOut 4649 4611 uid 3722,0 4650 4612 shape (CompositeShape … … 4690 4652 ) 4691 4653 ) 4692 *14 7(PortIoOut4654 *146 (PortIoOut 4693 4655 uid 3728,0 4694 4656 shape (CompositeShape … … 4734 4696 ) 4735 4697 ) 4736 *14 8(PortIoOut4698 *147 (PortIoOut 4737 4699 uid 3734,0 4738 4700 shape (CompositeShape … … 4778 4740 ) 4779 4741 ) 4780 *14 9(PortIoOut4742 *148 (PortIoOut 4781 4743 uid 3740,0 4782 4744 shape (CompositeShape … … 4822 4784 ) 4823 4785 ) 4824 *1 50(PortIoOut4786 *149 (PortIoOut 4825 4787 uid 3746,0 4826 4788 shape (CompositeShape … … 4866 4828 ) 4867 4829 ) 4868 *15 1(PortIoOut4830 *150 (PortIoOut 4869 4831 uid 3752,0 4870 4832 shape (CompositeShape … … 4910 4872 ) 4911 4873 ) 4912 *15 2(PortIoOut4874 *151 (PortIoOut 4913 4875 uid 3758,0 4914 4876 shape (CompositeShape … … 4954 4916 ) 4955 4917 ) 4956 *15 3(Net4918 *152 (Net 4957 4919 uid 3864,0 4958 4920 decl (Decl 4959 4921 n "TRG_V" 4960 4922 t "std_logic" 4961 o 4 24923 o 43 4962 4924 suid 126,0 4963 4925 ) … … 4967 4929 font "Courier New,8,0" 4968 4930 ) 4969 xt "39000,3 6600,53500,37400"4931 xt "39000,37400,53500,38200" 4970 4932 st "TRG_V : std_logic" 4971 4933 ) 4972 4934 ) 4973 *15 4(Net4935 *153 (Net 4974 4936 uid 3866,0 4975 4937 decl (Decl 4976 4938 n "RS485_C_RE" 4977 4939 t "std_logic" 4978 o 3 24940 o 33 4979 4941 suid 127,0 4980 4942 ) … … 4984 4946 font "Courier New,8,0" 4985 4947 ) 4986 xt "39000,2 8600,53500,29400"4948 xt "39000,29400,53500,30200" 4987 4949 st "RS485_C_RE : std_logic" 4988 4950 ) 4989 4951 ) 4990 *15 5(Net4952 *154 (Net 4991 4953 uid 3868,0 4992 4954 decl (Decl 4993 4955 n "RS485_C_DE" 4994 4956 t "std_logic" 4995 o 3 14957 o 32 4996 4958 suid 128,0 4997 4959 ) … … 5001 4963 font "Courier New,8,0" 5002 4964 ) 5003 xt "39000,2 7800,53500,28600"4965 xt "39000,28600,53500,29400" 5004 4966 st "RS485_C_DE : std_logic" 5005 4967 ) 5006 4968 ) 5007 *15 6(Net4969 *155 (Net 5008 4970 uid 3870,0 5009 4971 decl (Decl 5010 4972 n "RS485_E_RE" 5011 4973 t "std_logic" 5012 o 3 44974 o 35 5013 4975 suid 129,0 5014 4976 ) … … 5018 4980 font "Courier New,8,0" 5019 4981 ) 5020 xt "39000,3 0200,53500,31000"4982 xt "39000,31000,53500,31800" 5021 4983 st "RS485_E_RE : std_logic" 5022 4984 ) 5023 4985 ) 5024 *15 7(Net4986 *156 (Net 5025 4987 uid 3872,0 5026 4988 decl (Decl 5027 4989 n "RS485_E_DE" 5028 4990 t "std_logic" 5029 o 3 34991 o 34 5030 4992 suid 130,0 5031 4993 ) … … 5035 4997 font "Courier New,8,0" 5036 4998 ) 5037 xt "39000, 29400,53500,30200"4999 xt "39000,30200,53500,31000" 5038 5000 st "RS485_E_DE : std_logic" 5039 5001 ) 5040 5002 ) 5041 *15 8(Net5003 *157 (Net 5042 5004 uid 3874,0 5043 5005 decl (Decl 5044 5006 n "DENABLE" 5045 5007 t "std_logic" 5046 o 2 25008 o 23 5047 5009 suid 131,0 5048 5010 i "'0'" … … 5053 5015 font "Courier New,8,0" 5054 5016 ) 5055 xt "39000,2 0600,68000,21400"5017 xt "39000,21400,68000,22200" 5056 5018 st "DENABLE : std_logic := '0'" 5057 5019 ) 5058 5020 ) 5059 *15 9(Net5021 *158 (Net 5060 5022 uid 3876,0 5061 5023 decl (Decl 5062 5024 n "SRIN" 5063 5025 t "std_logic" 5064 o 3 65026 o 37 5065 5027 suid 132,0 5066 5028 ) … … 5070 5032 font "Courier New,8,0" 5071 5033 ) 5072 xt "39000,3 1800,53500,32600"5034 xt "39000,32600,53500,33400" 5073 5035 st "SRIN : std_logic" 5074 5036 ) 5075 5037 ) 5076 *1 60(Net5038 *159 (Net 5077 5039 uid 3878,0 5078 5040 decl (Decl 5079 5041 n "EE_CS" 5080 5042 t "std_logic" 5081 o 2 75043 o 28 5082 5044 suid 133,0 5083 5045 ) … … 5087 5049 font "Courier New,8,0" 5088 5050 ) 5089 xt "39000,2 4600,53500,25400"5051 xt "39000,25400,53500,26200" 5090 5052 st "EE_CS : std_logic" 5091 5053 ) 5092 5054 ) 5093 *16 1(Net5055 *160 (Net 5094 5056 uid 3880,0 5095 5057 decl (Decl … … 5097 5059 t "std_logic_vector" 5098 5060 b "( 2 DOWNTO 0 )" 5099 o 2 85061 o 29 5100 5062 suid 134,0 5101 5063 i "(others => '1')" … … 5106 5068 font "Courier New,8,0" 5107 5069 ) 5108 xt "39000,2 5400,74000,26200"5070 xt "39000,26200,74000,27000" 5109 5071 st "LED : std_logic_vector( 2 DOWNTO 0 ) := (others => '1')" 5110 5072 ) 5111 5073 ) 5112 *16 2(PortIoOut5074 *161 (PortIoOut 5113 5075 uid 3995,0 5114 5076 shape (CompositeShape … … 5155 5117 ) 5156 5118 ) 5157 *16 3(PortIoOut5119 *162 (PortIoOut 5158 5120 uid 4001,0 5159 5121 shape (CompositeShape … … 5200 5162 ) 5201 5163 ) 5202 *16 4(PortIoOut5164 *163 (PortIoOut 5203 5165 uid 4007,0 5204 5166 shape (CompositeShape … … 5245 5207 ) 5246 5208 ) 5247 *16 5(PortIoOut5209 *164 (PortIoOut 5248 5210 uid 4013,0 5249 5211 shape (CompositeShape … … 5290 5252 ) 5291 5253 ) 5292 *16 6(PortIoOut5254 *165 (PortIoOut 5293 5255 uid 4916,0 5294 5256 shape (CompositeShape … … 5334 5296 ) 5335 5297 ) 5336 *16 7(Net5298 *166 (Net 5337 5299 uid 5320,0 5338 5300 decl (Decl … … 5340 5302 t "std_logic_vector" 5341 5303 b "(7 DOWNTO 0)" 5342 o 2 55304 o 26 5343 5305 suid 141,0 5344 5306 i "(OTHERS => '0')" … … 5349 5311 font "Courier New,8,0" 5350 5312 ) 5351 xt "39000,23 000,74000,23800"5313 xt "39000,23800,74000,24600" 5352 5314 st "D_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 5353 5315 ) 5354 5316 ) 5355 *16 8(PortIoIn5317 *167 (PortIoIn 5356 5318 uid 5650,0 5357 5319 shape (CompositeShape … … 5366 5328 sl 0 5367 5329 ro 270 5368 xt " -30000,88625,-28500,89375"5330 xt "9000,78625,10500,79375" 5369 5331 ) 5370 5332 (Line … … 5372 5334 sl 0 5373 5335 ro 270 5374 xt " -28500,89000,-28000,89000"5375 pts [ 5376 " -28500,89000"5377 " -28000,89000"5336 xt "10500,79000,11000,79000" 5337 pts [ 5338 "10500,79000" 5339 "11000,79000" 5378 5340 ] 5379 5341 ) … … 5390 5352 va (VaSet 5391 5353 ) 5392 xt " -35500,88500,-31000,89500"5354 xt "3500,78500,8000,79500" 5393 5355 st "TEST_TRG" 5394 5356 ju 2 5395 blo " -31000,89300"5396 tm "WireNameMgr" 5397 ) 5398 ) 5399 ) 5400 *16 9(Net5357 blo "8000,79300" 5358 tm "WireNameMgr" 5359 ) 5360 ) 5361 ) 5362 *168 (Net 5401 5363 uid 5662,0 5402 5364 decl (Decl … … 5415 5377 ) 5416 5378 ) 5417 *1 70(Net5379 *169 (Net 5418 5380 uid 6138,0 5419 5381 decl (Decl 5420 5382 n "TRG_OR" 5421 5383 t "std_logic" 5422 o 5 35384 o 54 5423 5385 suid 146,0 5424 5386 ) … … 5428 5390 font "Courier New,8,0" 5429 5391 ) 5430 xt "39000,4 6400,57000,47200"5392 xt "39000,47200,57000,48000" 5431 5393 st "SIGNAL TRG_OR : std_logic" 5432 5394 ) 5433 5395 ) 5434 *171 (SaComponent 5435 uid 6250,0 5436 optionalChildren [ 5437 *172 (CptPort 5438 uid 6235,0 5439 ps "OnEdgeStrategy" 5440 shape (Triangle 5441 uid 6236,0 5442 ro 90 5443 va (VaSet 5444 vasetType 1 5445 fg "0,65535,0" 5446 ) 5447 xt "-11750,87625,-11000,88375" 5448 ) 5449 tg (CPTG 5450 uid 6237,0 5451 ps "CptPortTextPlaceStrategy" 5452 stg "VerticalLayoutStrategy" 5453 f (Text 5454 uid 6238,0 5455 va (VaSet 5456 ) 5457 xt "-10000,87500,-8700,88500" 5458 st "clk" 5459 blo "-10000,88300" 5460 ) 5461 ) 5462 thePort (LogicalPort 5463 decl (Decl 5464 n "clk" 5465 t "STD_LOGIC" 5466 preAdd 0 5467 posAdd 0 5468 o 1 5469 suid 1,0 5470 ) 5471 ) 5472 ) 5473 *173 (CptPort 5474 uid 6239,0 5475 ps "OnEdgeStrategy" 5476 shape (Triangle 5477 uid 6240,0 5478 ro 90 5479 va (VaSet 5480 vasetType 1 5481 fg "0,65535,0" 5482 ) 5483 xt "-11750,88625,-11000,89375" 5484 ) 5485 tg (CPTG 5486 uid 6241,0 5487 ps "CptPortTextPlaceStrategy" 5488 stg "VerticalLayoutStrategy" 5489 f (Text 5490 uid 6242,0 5491 va (VaSet 5492 ) 5493 xt "-10000,88500,-5800,89500" 5494 st "trigger_in" 5495 blo "-10000,89300" 5496 ) 5497 ) 5498 thePort (LogicalPort 5499 decl (Decl 5500 n "trigger_in" 5501 t "STD_LOGIC" 5502 prec "-- rst : in STD_LOGIC;" 5503 preAdd 0 5504 posAdd 0 5505 o 2 5506 suid 2,0 5507 ) 5508 ) 5509 ) 5510 *174 (CptPort 5511 uid 6243,0 5512 ps "OnEdgeStrategy" 5513 shape (Triangle 5514 uid 6244,0 5515 ro 90 5516 va (VaSet 5517 vasetType 1 5518 fg "0,65535,0" 5519 ) 5520 xt "1000,88625,1750,89375" 5521 ) 5522 tg (CPTG 5523 uid 6245,0 5524 ps "CptPortTextPlaceStrategy" 5525 stg "RightVerticalLayoutStrategy" 5526 f (Text 5527 uid 6246,0 5528 va (VaSet 5529 ) 5530 xt "-4600,88500,0,89500" 5531 st "trigger_out" 5532 ju 2 5533 blo "0,89300" 5534 ) 5535 ) 5536 thePort (LogicalPort 5537 m 1 5538 decl (Decl 5539 n "trigger_out" 5540 t "STD_LOGIC" 5541 preAdd 0 5542 posAdd 0 5543 o 3 5544 suid 3,0 5545 i "'0'" 5546 ) 5547 ) 5548 ) 5549 ] 5550 shape (Rectangle 5551 uid 6251,0 5552 va (VaSet 5553 vasetType 1 5554 fg "0,65535,0" 5555 lineColor "0,32896,0" 5556 lineWidth 2 5557 ) 5558 xt "-11000,87000,1000,92000" 5559 ) 5560 oxt "25000,13000,37000,18000" 5561 ttg (MlTextGroup 5562 uid 6252,0 5563 ps "CenterOffsetStrategy" 5564 stg "VerticalLayoutStrategy" 5565 textVec [ 5566 *175 (Text 5567 uid 6253,0 5568 va (VaSet 5569 font "Arial,8,1" 5570 ) 5571 xt "-10800,92000,-4200,93000" 5572 st "FACT_FAD_LIB" 5573 blo "-10800,92800" 5574 tm "BdLibraryNameMgr" 5575 ) 5576 *176 (Text 5577 uid 6254,0 5578 va (VaSet 5579 font "Arial,8,1" 5580 ) 5581 xt "-10800,93000,-6400,94000" 5582 st "debouncer" 5583 blo "-10800,93800" 5584 tm "CptNameMgr" 5585 ) 5586 *177 (Text 5587 uid 6255,0 5588 va (VaSet 5589 font "Arial,8,1" 5590 ) 5591 xt "-10800,94000,-9800,95000" 5592 st "I0" 5593 blo "-10800,94800" 5594 tm "InstanceNameMgr" 5595 ) 5596 ] 5597 ) 5598 ga (GenericAssociation 5599 uid 6256,0 5600 ps "EdgeToEdgeStrategy" 5601 matrix (Matrix 5602 uid 6257,0 5603 text (MLText 5604 uid 6258,0 5605 va (VaSet 5606 font "Courier New,8,0" 5607 ) 5608 xt "-11000,86200,4000,87000" 5609 st "WIDTH = 17 ( INTEGER ) " 5610 ) 5611 header "" 5612 ) 5613 elements [ 5614 (GiElement 5615 name "WIDTH" 5616 type "INTEGER" 5617 value "17" 5618 ) 5619 ] 5620 ) 5621 viewicon (ZoomableIcon 5622 uid 6259,0 5623 sl 0 5624 va (VaSet 5625 vasetType 1 5626 fg "49152,49152,49152" 5627 ) 5628 xt "-10750,90250,-9250,91750" 5629 iconName "VhdlFileViewIcon.png" 5630 iconMaskName "VhdlFileViewIcon.msk" 5631 ftype 10 5632 ) 5633 ordering 1 5634 viewiconposition 0 5635 portVis (PortSigDisplay 5636 ) 5637 archFileType "UNKNOWN" 5638 ) 5639 *178 (Net 5640 uid 6278,0 5641 decl (Decl 5642 n "trigger_out" 5643 t "STD_LOGIC" 5644 preAdd 0 5645 posAdd 0 5646 o 60 5647 suid 147,0 5648 i "'0'" 5649 ) 5650 declText (MLText 5651 uid 6279,0 5652 va (VaSet 5653 font "Courier New,8,0" 5654 ) 5655 xt "39000,52000,71500,52800" 5656 st "SIGNAL trigger_out : STD_LOGIC := '0'" 5657 ) 5658 ) 5659 *179 (Net 5660 uid 6326,0 5661 decl (Decl 5662 n "not_TEST_TRG" 5663 t "STD_LOGIC" 5664 o 58 5665 suid 148,0 5666 ) 5667 declText (MLText 5668 uid 6327,0 5669 va (VaSet 5670 font "Courier New,8,0" 5671 ) 5672 xt "39000,50400,57000,51200" 5673 st "SIGNAL not_TEST_TRG : STD_LOGIC" 5674 ) 5675 ) 5676 *180 (MWC 5677 uid 6539,0 5678 optionalChildren [ 5679 *181 (CptPort 5680 uid 6526,0 5681 optionalChildren [ 5682 *182 (Line 5683 uid 6530,0 5684 layer 5 5685 sl 0 5686 va (VaSet 5687 vasetType 3 5688 ) 5689 xt "-22000,89000,-20999,89000" 5690 pts [ 5691 "-22000,89000" 5692 "-20999,89000" 5693 ] 5694 ) 5695 ] 5696 ps "OnEdgeStrategy" 5697 shape (Triangle 5698 uid 6527,0 5699 ro 90 5700 va (VaSet 5701 vasetType 1 5702 isHidden 1 5703 fg "0,65535,65535" 5704 ) 5705 xt "-22750,88625,-22000,89375" 5706 ) 5707 tg (CPTG 5708 uid 6528,0 5709 ps "CptPortTextPlaceStrategy" 5710 stg "VerticalLayoutStrategy" 5711 f (Text 5712 uid 6529,0 5713 sl 0 5714 va (VaSet 5715 isHidden 1 5716 font "arial,8,0" 5717 ) 5718 xt "-25000,88500,-23600,89500" 5719 st "din" 5720 blo "-25000,89300" 5721 ) 5722 s (Text 5723 uid 6548,0 5724 sl 0 5725 va (VaSet 5726 font "arial,8,0" 5727 ) 5728 xt "-25000,89500,-25000,89500" 5729 blo "-25000,89500" 5730 ) 5731 ) 5732 thePort (LogicalPort 5733 decl (Decl 5734 n "din" 5735 t "std_logic" 5736 o 11 5737 suid 1,0 5738 ) 5739 ) 5740 ) 5741 *183 (CptPort 5742 uid 6531,0 5743 optionalChildren [ 5744 *184 (Line 5745 uid 6535,0 5746 layer 5 5747 sl 0 5748 va (VaSet 5749 vasetType 3 5750 ) 5751 xt "-17249,89000,-17000,89000" 5752 pts [ 5753 "-17000,89000" 5754 "-17249,89000" 5755 ] 5756 ) 5757 *185 (Circle 5758 uid 6536,0 5759 va (VaSet 5760 vasetType 1 5761 fg "65535,65535,65535" 5762 lineColor "26368,26368,26368" 5763 ) 5764 xt "-17999,88625,-17249,89375" 5765 radius 375 5766 ) 5767 ] 5768 ps "OnEdgeStrategy" 5769 shape (Triangle 5770 uid 6532,0 5771 ro 90 5772 va (VaSet 5773 vasetType 1 5774 isHidden 1 5775 fg "0,65535,65535" 5776 ) 5777 xt "-17000,88625,-16250,89375" 5778 ) 5779 tg (CPTG 5780 uid 6533,0 5781 ps "CptPortTextPlaceStrategy" 5782 stg "RightVerticalLayoutStrategy" 5783 f (Text 5784 uid 6534,0 5785 sl 0 5786 va (VaSet 5787 isHidden 1 5788 font "arial,8,0" 5789 ) 5790 xt "-15050,88500,-13250,89500" 5791 st "dout" 5792 ju 2 5793 blo "-13250,89300" 5794 ) 5795 s (Text 5796 uid 6549,0 5797 sl 0 5798 va (VaSet 5799 font "arial,8,0" 5800 ) 5801 xt "-13250,89500,-13250,89500" 5802 ju 2 5803 blo "-13250,89500" 5804 ) 5805 ) 5806 thePort (LogicalPort 5807 m 1 5808 decl (Decl 5809 n "dout" 5810 t "STD_LOGIC" 5811 o 58 5812 suid 2,0 5813 ) 5814 ) 5815 ) 5816 *186 (CommentGraphic 5817 uid 6537,0 5818 shape (CustomPolygon 5819 pts [ 5820 "-21000,87000" 5821 "-18000,89000" 5822 "-21000,91000" 5823 "-21000,87000" 5824 ] 5825 uid 6538,0 5826 layer 0 5827 sl 0 5828 va (VaSet 5829 vasetType 1 5830 fg "0,65535,65535" 5831 bg "0,65535,65535" 5832 lineColor "26368,26368,26368" 5833 ) 5834 xt "-21000,87000,-18000,91000" 5835 ) 5836 oxt "7000,6000,10000,10000" 5837 ) 5838 ] 5839 shape (Rectangle 5840 uid 6540,0 5841 va (VaSet 5842 vasetType 1 5843 transparent 1 5844 fg "0,65535,0" 5845 lineColor "65535,65535,65535" 5846 lineWidth -1 5847 ) 5848 xt "-22000,87000,-17000,91000" 5849 fos 1 5850 ) 5851 showPorts 0 5852 oxt "6000,6000,11000,10000" 5853 ttg (MlTextGroup 5854 uid 6541,0 5855 ps "CenterOffsetStrategy" 5856 stg "VerticalLayoutStrategy" 5857 textVec [ 5858 *187 (Text 5859 uid 6542,0 5860 va (VaSet 5861 isHidden 1 5862 font "arial,8,0" 5863 ) 5864 xt "-19650,89100,-14850,90100" 5865 st "moduleware" 5866 blo "-19650,89900" 5867 ) 5868 *188 (Text 5869 uid 6543,0 5870 va (VaSet 5871 font "arial,8,0" 5872 ) 5873 xt "-19650,90100,-18350,91100" 5874 st "inv" 5875 blo "-19650,90900" 5876 ) 5877 *189 (Text 5878 uid 6544,0 5879 va (VaSet 5880 font "arial,8,0" 5881 ) 5882 xt "-19650,91100,-18650,92100" 5883 st "I1" 5884 blo "-19650,91900" 5885 tm "InstanceNameMgr" 5886 ) 5887 ] 5888 ) 5889 ga (GenericAssociation 5890 uid 6545,0 5891 ps "EdgeToEdgeStrategy" 5892 matrix (Matrix 5893 uid 6546,0 5894 text (MLText 5895 uid 6547,0 5896 va (VaSet 5897 font "arial,8,0" 5898 ) 5899 xt "-25000,68400,-25000,68400" 5900 ) 5901 header "" 5902 ) 5903 elements [ 5904 ] 5905 ) 5906 sed 1 5907 awe 1 5908 portVis (PortSigDisplay 5909 disp 1 5910 sN 0 5911 sTC 0 5912 selT 0 5913 ) 5914 prms (Property 5915 pclass "params" 5916 pname "params" 5917 ptn "String" 5918 ) 5919 visOptions (mwParamsVisibilityOptions 5920 ) 5921 ) 5922 *190 (MWC 5396 *170 (MWC 5923 5397 uid 6586,0 5924 5398 optionalChildren [ 5925 *1 91 (CptPort5399 *171 (CptPort 5926 5400 uid 6550,0 5927 5401 optionalChildren [ 5928 *1 92 (Line5402 *172 (Line 5929 5403 uid 6554,0 5930 5404 layer 5 … … 5970 5444 decl (Decl 5971 5445 n "din1" 5972 t "STD_LOGIC" 5973 preAdd 0 5974 posAdd 0 5975 o 60 5446 t "std_logic" 5447 o 11 5976 5448 suid 1,0 5977 i "'0'" 5978 ) 5979 ) 5980 ) 5981 *193 (CptPort 5449 ) 5450 ) 5451 ) 5452 *173 (CptPort 5982 5453 uid 6555,0 5983 5454 optionalChildren [ 5984 *1 94 (Property5455 *174 (Property 5985 5456 uid 6559,0 5986 5457 pclass "_MW_GEOM_" … … 5988 5459 ptn "String" 5989 5460 ) 5990 *1 95 (Line5461 *175 (Line 5991 5462 uid 6560,0 5992 5463 layer 5 … … 6035 5506 n "dout" 6036 5507 t "std_logic" 6037 o 5 35508 o 54 6038 5509 suid 2,0 6039 5510 ) 6040 5511 ) 6041 5512 ) 6042 *1 96 (CptPort5513 *176 (CptPort 6043 5514 uid 6561,0 6044 5515 optionalChildren [ 6045 *1 97 (Line5516 *177 (Line 6046 5517 uid 6565,0 6047 5518 layer 5 … … 6093 5564 ) 6094 5565 ) 6095 *1 98 (CommentGraphic5566 *178 (CommentGraphic 6096 5567 uid 6566,0 6097 5568 shape (Arc2D … … 6114 5585 oxt "7000,6003,11000,8000" 6115 5586 ) 6116 *1 99 (CommentGraphic5587 *179 (CommentGraphic 6117 5588 uid 6568,0 6118 5589 shape (Arc2D … … 6135 5606 oxt "6996,8005,11000,10000" 6136 5607 ) 6137 * 200 (Grouping5608 *180 (Grouping 6138 5609 uid 6570,0 6139 5610 optionalChildren [ 6140 * 201 (CommentGraphic5611 *181 (CommentGraphic 6141 5612 uid 6572,0 6142 5613 optionalChildren [ 6143 * 202 (Property5614 *182 (Property 6144 5615 uid 6574,0 6145 5616 pclass "_MW_GEOM_" … … 6172 5643 oxt "7000,6000,11000,9998" 6173 5644 ) 6174 * 203 (CommentGraphic5645 *183 (CommentGraphic 6175 5646 uid 6575,0 6176 5647 optionalChildren [ 6177 * 204 (Property5648 *184 (Property 6178 5649 uid 6577,0 6179 5650 pclass "_MW_GEOM_" … … 6217 5688 oxt "7000,6000,11000,10000" 6218 5689 ) 6219 * 205 (CommentGraphic5690 *185 (CommentGraphic 6220 5691 uid 6578,0 6221 5692 shape (PolyLine2D … … 6236 5707 oxt "11000,8000,11000,8000" 6237 5708 ) 6238 * 206 (CommentGraphic5709 *186 (CommentGraphic 6239 5710 uid 6580,0 6240 5711 optionalChildren [ 6241 * 207 (Property5712 *187 (Property 6242 5713 uid 6582,0 6243 5714 pclass "_MW_GEOM_" … … 6263 5734 oxt "7000,6000,7000,6000" 6264 5735 ) 6265 * 208 (CommentGraphic5736 *188 (CommentGraphic 6266 5737 uid 6583,0 6267 5738 optionalChildren [ 6268 * 209 (Property5739 *189 (Property 6269 5740 uid 6585,0 6270 5741 pclass "_MW_GEOM_" … … 6309 5780 stg "VerticalLayoutStrategy" 6310 5781 textVec [ 6311 * 210 (Text5782 *190 (Text 6312 5783 uid 6589,0 6313 5784 va (VaSet … … 6319 5790 blo "15500,77300" 6320 5791 ) 6321 * 211 (Text5792 *191 (Text 6322 5793 uid 6590,0 6323 5794 va (VaSet … … 6328 5799 blo "15500,78300" 6329 5800 ) 6330 * 212 (Text5801 *192 (Text 6331 5802 uid 6591,0 6332 5803 va (VaSet … … 6373 5844 ) 6374 5845 ) 6375 * 213 (PortIoIn5846 *193 (PortIoIn 6376 5847 uid 6781,0 6377 5848 shape (CompositeShape … … 6418 5889 ) 6419 5890 ) 6420 * 214 (Net5891 *194 (Net 6421 5892 uid 6793,0 6422 5893 decl (Decl … … 6436 5907 ) 6437 5908 ) 6438 * 215 (PortIoOut5909 *195 (PortIoOut 6439 5910 uid 6874,0 6440 5911 shape (CompositeShape … … 6480 5951 ) 6481 5952 ) 6482 * 216 (Net5953 *196 (Net 6483 5954 uid 6886,0 6484 5955 decl (Decl … … 6486 5957 t "std_logic_vector" 6487 5958 b "(3 DOWNTO 0)" 6488 o 2 65959 o 27 6489 5960 suid 154,0 6490 5961 i "(others => '0')" … … 6495 5966 font "Courier New,8,0" 6496 5967 ) 6497 xt "39000,2 3800,74000,24600"5968 xt "39000,24600,74000,25400" 6498 5969 st "D_T2 : std_logic_vector(3 DOWNTO 0) := (others => '0')" 6499 5970 ) 6500 5971 ) 6501 * 217 (HdlText5972 *197 (HdlText 6502 5973 uid 6888,0 6503 5974 optionalChildren [ 6504 * 218 (EmbeddedText5975 *198 (EmbeddedText 6505 5976 uid 6894,0 6506 5977 commentText (CommentText … … 6550 6021 stg "VerticalLayoutStrategy" 6551 6022 textVec [ 6552 * 219 (Text6023 *199 (Text 6553 6024 uid 6891,0 6554 6025 va (VaSet … … 6560 6031 tm "HdlTextNameMgr" 6561 6032 ) 6562 *2 20 (Text6033 *200 (Text 6563 6034 uid 6892,0 6564 6035 va (VaSet … … 6586 6057 viewiconposition 0 6587 6058 ) 6588 *2 21 (HdlText6059 *201 (HdlText 6589 6060 uid 7092,0 6590 6061 optionalChildren [ 6591 *2 22 (EmbeddedText6062 *202 (EmbeddedText 6592 6063 uid 7098,0 6593 6064 commentText (CommentText … … 6602 6073 lineWidth 2 6603 6074 ) 6604 xt "2 7000,137000,45000,145000"6075 xt "26000,137000,46000,143000" 6605 6076 ) 6606 6077 oxt "0,0,18000,5000" … … 6609 6080 va (VaSet 6610 6081 ) 6611 xt "2 7200,137200,39400,142200"6082 xt "26200,137200,40000,141200" 6612 6083 st " 6613 6084 -- eb2 8 6614 A1_T(0) <= dummy; 6615 A1_T(1) <= RSRLOAD; 6616 A1_T(2) <= D0_SROUT; 6617 A1_T(3) <= D1_SROUT; 6085 A1_T(3 downto 0) <= drs_channel_id; 6086 D_A <= drs_channel_id; 6087 A1_T(4) <= TRG_OR; 6618 6088 " 6619 6089 tm "HdlTextMgr" 6620 6090 wrapOption 3 6621 visibleHeight 80006622 visibleWidth 180006091 visibleHeight 6000 6092 visibleWidth 20000 6623 6093 ) 6624 6094 ) … … 6641 6111 stg "VerticalLayoutStrategy" 6642 6112 textVec [ 6643 *2 23 (Text6113 *203 (Text 6644 6114 uid 7095,0 6645 6115 va (VaSet … … 6651 6121 tm "HdlTextNameMgr" 6652 6122 ) 6653 *2 24 (Text6123 *204 (Text 6654 6124 uid 7096,0 6655 6125 va (VaSet … … 6677 6147 viewiconposition 0 6678 6148 ) 6679 *2 25 (PortIoOut6149 *205 (PortIoOut 6680 6150 uid 7138,0 6681 6151 shape (CompositeShape … … 6721 6191 ) 6722 6192 ) 6723 *2 26 (Net6193 *206 (Net 6724 6194 uid 7150,0 6725 6195 decl (Decl 6726 6196 n "A1_T" 6727 6197 t "std_logic_vector" 6728 b "( 3DOWNTO 0)"6729 o 1 56198 b "(7 DOWNTO 0)" 6199 o 16 6730 6200 suid 155,0 6201 i "(OTHERS => '0')" 6731 6202 ) 6732 6203 declText (MLText … … 6735 6206 font "Courier New,8,0" 6736 6207 ) 6737 xt "39000,15 000,63500,15800"6738 st "A1_T : std_logic_vector( 3 DOWNTO 0)"6739 ) 6740 ) 6741 *2 27 (Net6208 xt "39000,15800,74000,16600" 6209 st "A1_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6210 ) 6211 ) 6212 *207 (Net 6742 6213 uid 7485,0 6743 6214 decl (Decl 6744 6215 n "dummy" 6745 6216 t "std_logic" 6746 o 606217 o 59 6747 6218 suid 157,0 6748 6219 ) … … 6752 6223 font "Courier New,8,0" 6753 6224 ) 6754 xt "39000, 49600,57000,50400"6225 xt "39000,51200,57000,52000" 6755 6226 st "SIGNAL dummy : std_logic" 6756 6227 ) 6757 6228 ) 6758 *2 28 (MWC6229 *208 (MWC 6759 6230 uid 7652,0 6760 6231 optionalChildren [ 6761 *2 29 (CptPort6232 *209 (CptPort 6762 6233 uid 7632,0 6763 6234 optionalChildren [ 6764 *2 30 (Line6235 *210 (Line 6765 6236 uid 7636,0 6766 6237 layer 5 … … 6816 6287 n "s" 6817 6288 t "std_logic" 6818 o 606289 o 59 6819 6290 suid 1,0 6820 6291 ) 6821 6292 ) 6822 6293 ) 6823 *2 31 (CptPort6294 *211 (CptPort 6824 6295 uid 7637,0 6825 6296 optionalChildren [ 6826 *2 32 (Line6297 *212 (Line 6827 6298 uid 7641,0 6828 6299 layer 5 … … 6881 6352 n "t" 6882 6353 t "std_logic" 6883 o 2 16354 o 22 6884 6355 suid 2,0 6885 6356 ) 6886 6357 ) 6887 6358 ) 6888 *2 33 (CommentGraphic6359 *213 (CommentGraphic 6889 6360 uid 7642,0 6890 6361 shape (PolyLine2D … … 6907 6378 oxt "6000,6000,7000,7000" 6908 6379 ) 6909 *2 34 (CommentGraphic6380 *214 (CommentGraphic 6910 6381 uid 7644,0 6911 6382 shape (PolyLine2D … … 6928 6399 oxt "6000,7000,7000,8000" 6929 6400 ) 6930 *2 35 (CommentGraphic6401 *215 (CommentGraphic 6931 6402 uid 7646,0 6932 6403 shape (PolyLine2D … … 6949 6420 oxt "6988,7329,7988,7329" 6950 6421 ) 6951 *2 36 (CommentGraphic6422 *216 (CommentGraphic 6952 6423 uid 7648,0 6953 6424 shape (PolyLine2D … … 6968 6439 oxt "8000,7000,9000,7000" 6969 6440 ) 6970 *2 37 (CommentGraphic6441 *217 (CommentGraphic 6971 6442 uid 7650,0 6972 6443 shape (PolyLine2D … … 7009 6480 stg "VerticalLayoutStrategy" 7010 6481 textVec [ 7011 *2 38 (Text6482 *218 (Text 7012 6483 uid 7655,0 7013 6484 va (VaSet … … 7019 6490 blo "90350,83900" 7020 6491 ) 7021 *2 39 (Text6492 *219 (Text 7022 6493 uid 7656,0 7023 6494 va (VaSet … … 7028 6499 blo "90350,84900" 7029 6500 ) 7030 *2 40 (Text6501 *220 (Text 7031 6502 uid 7657,0 7032 6503 va (VaSet … … 7073 6544 ) 7074 6545 ) 7075 *241 (Wire 6546 *221 (Net 6547 uid 8851,0 6548 decl (Decl 6549 n "drs_channel_id" 6550 t "std_logic_vector" 6551 b "(3 downto 0)" 6552 o 58 6553 suid 159,0 6554 i "(others => '0')" 6555 ) 6556 declText (MLText 6557 uid 8852,0 6558 va (VaSet 6559 font "Courier New,8,0" 6560 ) 6561 xt "39000,50400,77500,51200" 6562 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6563 ) 6564 ) 6565 *222 (Net 6566 uid 9201,0 6567 decl (Decl 6568 n "A0_T" 6569 t "std_logic_vector" 6570 b "(7 DOWNTO 0)" 6571 o 15 6572 suid 162,0 6573 i "(OTHERS => '0')" 6574 ) 6575 declText (MLText 6576 uid 9202,0 6577 va (VaSet 6578 font "Courier New,8,0" 6579 ) 6580 xt "39000,15000,74000,15800" 6581 st "A0_T : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 6582 ) 6583 ) 6584 *223 (PortIoOut 6585 uid 9294,0 6586 shape (CompositeShape 6587 uid 9295,0 6588 va (VaSet 6589 vasetType 1 6590 fg "0,0,32768" 6591 ) 6592 optionalChildren [ 6593 (Pentagon 6594 uid 9296,0 6595 sl 0 6596 ro 270 6597 xt "64500,139625,66000,140375" 6598 ) 6599 (Line 6600 uid 9297,0 6601 sl 0 6602 ro 270 6603 xt "64000,140000,64500,140000" 6604 pts [ 6605 "64000,140000" 6606 "64500,140000" 6607 ] 6608 ) 6609 ] 6610 ) 6611 stc 0 6612 sf 1 6613 tg (WTG 6614 uid 9298,0 6615 ps "PortIoTextPlaceStrategy" 6616 stg "STSignalDisplayStrategy" 6617 f (Text 6618 uid 9299,0 6619 va (VaSet 6620 ) 6621 xt "67000,139500,69200,140500" 6622 st "A0_T" 6623 blo "67000,140300" 6624 tm "WireNameMgr" 6625 ) 6626 ) 6627 ) 6628 *224 (Net 6629 uid 9500,0 6630 decl (Decl 6631 n "CLK_50" 6632 t "std_logic" 6633 o 52 6634 suid 163,0 6635 ) 6636 declText (MLText 6637 uid 9501,0 6638 va (VaSet 6639 font "Courier New,8,0" 6640 ) 6641 xt "39000,45600,57000,46400" 6642 st "SIGNAL CLK_50 : std_logic" 6643 ) 6644 ) 6645 *225 (Wire 7076 6646 uid 245,0 7077 6647 shape (OrthoPolyLine … … 7110 6680 ) 7111 6681 ) 7112 on & 707113 ) 7114 *2 42(Wire6682 on &69 6683 ) 6684 *226 (Wire 7115 6685 uid 277,0 7116 6686 shape (OrthoPolyLine … … 7150 6720 on &53 7151 6721 ) 7152 *2 43(Wire6722 *227 (Wire 7153 6723 uid 285,0 7154 6724 shape (OrthoPolyLine … … 7188 6758 on &54 7189 6759 ) 7190 *2 44(Wire6760 *228 (Wire 7191 6761 uid 362,0 7192 6762 shape (OrthoPolyLine … … 7201 6771 ] 7202 6772 ) 7203 start &7 86773 start &77 7204 6774 end &16 7205 6775 sat 32 … … 7224 6794 ) 7225 6795 ) 7226 on &7 97227 ) 7228 *2 45(Wire6796 on &78 6797 ) 6798 *229 (Wire 7229 6799 uid 418,0 7230 6800 shape (OrthoPolyLine … … 7262 6832 ) 7263 6833 ) 7264 on &13 17265 ) 7266 *2 46(Wire6834 on &130 6835 ) 6836 *230 (Wire 7267 6837 uid 426,0 7268 6838 shape (OrthoPolyLine … … 7302 6872 ) 7303 6873 ) 7304 on &12 97305 ) 7306 *2 47(Wire6874 on &128 6875 ) 6876 *231 (Wire 7307 6877 uid 434,0 7308 6878 shape (OrthoPolyLine … … 7340 6910 ) 7341 6911 ) 7342 on &13 57343 ) 7344 *2 48(Wire6912 on &134 6913 ) 6914 *232 (Wire 7345 6915 uid 442,0 7346 6916 shape (OrthoPolyLine … … 7380 6950 ) 7381 6951 ) 7382 on &1 307383 ) 7384 *2 49(Wire6952 on &129 6953 ) 6954 *233 (Wire 7385 6955 uid 450,0 7386 6956 shape (OrthoPolyLine … … 7418 6988 ) 7419 6989 ) 7420 on &13 47421 ) 7422 *2 50(Wire6990 on &133 6991 ) 6992 *234 (Wire 7423 6993 uid 458,0 7424 6994 shape (OrthoPolyLine … … 7456 7026 ) 7457 7027 ) 7458 on &13 27459 ) 7460 *2 51(Wire7028 on &131 7029 ) 7030 *235 (Wire 7461 7031 uid 466,0 7462 7032 shape (OrthoPolyLine … … 7494 7064 ) 7495 7065 ) 7496 on &13 37497 ) 7498 *2 52(Wire7066 on &132 7067 ) 7068 *236 (Wire 7499 7069 uid 1467,0 7500 7070 shape (OrthoPolyLine … … 7509 7079 ] 7510 7080 ) 7511 start &8 27081 start &81 7512 7082 end &28 7513 7083 sat 2 … … 7532 7102 on &62 7533 7103 ) 7534 *2 53(Wire7104 *237 (Wire 7535 7105 uid 1730,0 7536 7106 shape (OrthoPolyLine … … 7546 7116 ] 7547 7117 ) 7548 start & 807118 start &79 7549 7119 end &29 7550 7120 sat 32 … … 7570 7140 ) 7571 7141 ) 7572 on &8 17573 ) 7574 *2 54(Wire7142 on &80 7143 ) 7144 *238 (Wire 7575 7145 uid 1833,0 7576 7146 shape (OrthoPolyLine … … 7580 7150 lineWidth 2 7581 7151 ) 7582 xt "21000,109000,51250,109000" 7583 pts [ 7584 "51250,109000" 7585 "21000,109000" 7586 ] 7587 ) 7588 start &30 7589 end &110 7152 xt "6000,134000,31000,134000" 7153 pts [ 7154 "31000,134000" 7155 "6000,134000" 7156 ] 7157 ) 7158 start &201 7159 end &109 7160 sat 2 7161 eat 32 7162 sty 1 7163 stc 0 7164 st 0 7165 sf 1 7166 si 0 7167 tg (WTG 7168 uid 1837,0 7169 ps "ConnStartEndStrategy" 7170 stg "STSignalDisplayStrategy" 7171 f (Text 7172 uid 1838,0 7173 va (VaSet 7174 isHidden 1 7175 ) 7176 xt "7000,133000,8900,134000" 7177 st "D_A" 7178 blo "7000,133800" 7179 tm "WireNameMgr" 7180 ) 7181 ) 7182 on &110 7183 ) 7184 *239 (Wire 7185 uid 1841,0 7186 shape (OrthoPolyLine 7187 uid 1842,0 7188 va (VaSet 7189 vasetType 3 7190 ) 7191 xt "21000,110000,51250,110000" 7192 pts [ 7193 "51250,110000" 7194 "21000,110000" 7195 ] 7196 ) 7197 start &31 7198 end &111 7199 sat 32 7200 eat 32 7201 stc 0 7202 st 0 7203 sf 1 7204 si 0 7205 tg (WTG 7206 uid 1845,0 7207 ps "ConnStartEndStrategy" 7208 stg "STSignalDisplayStrategy" 7209 f (Text 7210 uid 1846,0 7211 va (VaSet 7212 isHidden 1 7213 ) 7214 xt "22000,109000,25500,110000" 7215 st "DWRITE" 7216 blo "22000,109800" 7217 tm "WireNameMgr" 7218 ) 7219 ) 7220 on &112 7221 ) 7222 *240 (Wire 7223 uid 1865,0 7224 shape (OrthoPolyLine 7225 uid 1866,0 7226 va (VaSet 7227 vasetType 3 7228 ) 7229 xt "21000,105000,51250,105000" 7230 pts [ 7231 "21000,105000" 7232 "51250,105000" 7233 ] 7234 ) 7235 start &101 7236 end &32 7237 sat 32 7238 eat 32 7239 stc 0 7240 st 0 7241 sf 1 7242 si 0 7243 tg (WTG 7244 uid 1869,0 7245 ps "ConnStartEndStrategy" 7246 stg "STSignalDisplayStrategy" 7247 f (Text 7248 uid 1870,0 7249 va (VaSet 7250 isHidden 1 7251 ) 7252 xt "22000,104000,26600,105000" 7253 st "D0_SROUT" 7254 blo "22000,104800" 7255 tm "WireNameMgr" 7256 ) 7257 ) 7258 on &105 7259 ) 7260 *241 (Wire 7261 uid 1873,0 7262 shape (OrthoPolyLine 7263 uid 1874,0 7264 va (VaSet 7265 vasetType 3 7266 ) 7267 xt "21000,106000,51250,106000" 7268 pts [ 7269 "21000,106000" 7270 "51250,106000" 7271 ] 7272 ) 7273 start &102 7274 end &33 7275 sat 32 7276 eat 32 7277 stc 0 7278 st 0 7279 sf 1 7280 si 0 7281 tg (WTG 7282 uid 1877,0 7283 ps "ConnStartEndStrategy" 7284 stg "STSignalDisplayStrategy" 7285 f (Text 7286 uid 1878,0 7287 va (VaSet 7288 isHidden 1 7289 ) 7290 xt "22000,105000,26600,106000" 7291 st "D1_SROUT" 7292 blo "22000,105800" 7293 tm "WireNameMgr" 7294 ) 7295 ) 7296 on &106 7297 ) 7298 *242 (Wire 7299 uid 1881,0 7300 shape (OrthoPolyLine 7301 uid 1882,0 7302 va (VaSet 7303 vasetType 3 7304 ) 7305 xt "21000,107000,51250,107000" 7306 pts [ 7307 "21000,107000" 7308 "51250,107000" 7309 ] 7310 ) 7311 start &103 7312 end &34 7313 sat 32 7314 eat 32 7315 stc 0 7316 st 0 7317 sf 1 7318 si 0 7319 tg (WTG 7320 uid 1885,0 7321 ps "ConnStartEndStrategy" 7322 stg "STSignalDisplayStrategy" 7323 f (Text 7324 uid 1886,0 7325 va (VaSet 7326 isHidden 1 7327 ) 7328 xt "22000,106000,26600,107000" 7329 st "D2_SROUT" 7330 blo "22000,106800" 7331 tm "WireNameMgr" 7332 ) 7333 ) 7334 on &107 7335 ) 7336 *243 (Wire 7337 uid 1889,0 7338 shape (OrthoPolyLine 7339 uid 1890,0 7340 va (VaSet 7341 vasetType 3 7342 ) 7343 xt "21000,108000,51250,108000" 7344 pts [ 7345 "21000,108000" 7346 "51250,108000" 7347 ] 7348 ) 7349 start &104 7350 end &35 7351 sat 32 7352 eat 32 7353 stc 0 7354 st 0 7355 sf 1 7356 si 0 7357 tg (WTG 7358 uid 1893,0 7359 ps "ConnStartEndStrategy" 7360 stg "STSignalDisplayStrategy" 7361 f (Text 7362 uid 1894,0 7363 va (VaSet 7364 isHidden 1 7365 ) 7366 xt "22000,107000,26600,108000" 7367 st "D3_SROUT" 7368 blo "22000,107800" 7369 tm "WireNameMgr" 7370 ) 7371 ) 7372 on &108 7373 ) 7374 *244 (Wire 7375 uid 2409,0 7376 shape (OrthoPolyLine 7377 uid 2410,0 7378 va (VaSet 7379 vasetType 3 7380 ) 7381 xt "21000,111000,51250,111000" 7382 pts [ 7383 "51250,111000" 7384 "21000,111000" 7385 ] 7386 ) 7387 start &36 7388 end &64 7389 sat 32 7390 eat 32 7391 stc 0 7392 st 0 7393 sf 1 7394 si 0 7395 tg (WTG 7396 uid 2413,0 7397 ps "ConnStartEndStrategy" 7398 stg "STSignalDisplayStrategy" 7399 f (Text 7400 uid 2414,0 7401 va (VaSet 7402 isHidden 1 7403 ) 7404 xt "22000,110000,26200,111000" 7405 st "RSRLOAD" 7406 blo "22000,110800" 7407 tm "WireNameMgr" 7408 ) 7409 ) 7410 on &63 7411 ) 7412 *245 (Wire 7413 uid 2423,0 7414 shape (OrthoPolyLine 7415 uid 2424,0 7416 va (VaSet 7417 vasetType 3 7418 ) 7419 xt "32000,113000,51250,113000" 7420 pts [ 7421 "51250,113000" 7422 "32000,113000" 7423 ] 7424 ) 7425 start &37 7426 end &93 7427 sat 32 7428 eat 1 7429 stc 0 7430 st 0 7431 sf 1 7432 si 0 7433 tg (WTG 7434 uid 2427,0 7435 ps "ConnStartEndStrategy" 7436 stg "STSignalDisplayStrategy" 7437 f (Text 7438 uid 2428,0 7439 va (VaSet 7440 isHidden 1 7441 ) 7442 xt "66250,109000,69250,110000" 7443 st "SRCLK" 7444 blo "66250,109800" 7445 tm "WireNameMgr" 7446 ) 7447 ) 7448 on &65 7449 ) 7450 *246 (Wire 7451 uid 3009,0 7452 shape (OrthoPolyLine 7453 uid 3010,0 7454 va (VaSet 7455 vasetType 3 7456 ) 7457 xt "80750,98000,111000,98000" 7458 pts [ 7459 "80750,98000" 7460 "111000,98000" 7461 ] 7462 ) 7463 start &39 7464 end &126 7465 sat 32 7466 eat 32 7467 stc 0 7468 st 0 7469 sf 1 7470 si 0 7471 tg (WTG 7472 uid 3011,0 7473 ps "ConnStartEndStrategy" 7474 stg "STSignalDisplayStrategy" 7475 f (Text 7476 uid 3012,0 7477 va (VaSet 7478 isHidden 1 7479 ) 7480 xt "82000,97000,84800,98000" 7481 st "S_CLK" 7482 blo "82000,97800" 7483 tm "WireNameMgr" 7484 ) 7485 ) 7486 on &127 7487 ) 7488 *247 (Wire 7489 uid 3015,0 7490 shape (OrthoPolyLine 7491 uid 3016,0 7492 va (VaSet 7493 vasetType 3 7494 ) 7495 xt "80750,99000,111000,99000" 7496 pts [ 7497 "80750,99000" 7498 "111000,99000" 7499 ] 7500 ) 7501 start &41 7502 end &135 7503 sat 32 7504 eat 32 7505 stc 0 7506 st 0 7507 sf 1 7508 si 0 7509 tg (WTG 7510 uid 3017,0 7511 ps "ConnStartEndStrategy" 7512 stg "STSignalDisplayStrategy" 7513 f (Text 7514 uid 3018,0 7515 va (VaSet 7516 isHidden 1 7517 ) 7518 xt "82750,98000,85150,99000" 7519 st "MISO" 7520 blo "82750,98800" 7521 tm "WireNameMgr" 7522 ) 7523 ) 7524 on &138 7525 ) 7526 *248 (Wire 7527 uid 3021,0 7528 shape (OrthoPolyLine 7529 uid 3022,0 7530 va (VaSet 7531 vasetType 3 7532 lineWidth 2 7533 ) 7534 xt "80750,89000,100000,89000" 7535 pts [ 7536 "80750,89000" 7537 "100000,89000" 7538 ] 7539 ) 7540 start &40 7541 end &114 7542 sat 32 7543 eat 1 7544 sty 1 7545 st 0 7546 sf 1 7547 si 0 7548 tg (WTG 7549 uid 3023,0 7550 ps "ConnStartEndStrategy" 7551 stg "STSignalDisplayStrategy" 7552 f (Text 7553 uid 3024,0 7554 va (VaSet 7555 ) 7556 xt "92000,88000,98500,89000" 7557 st "sensor_cs : (3:0)" 7558 blo "92000,88800" 7559 tm "WireNameMgr" 7560 ) 7561 ) 7562 on &66 7563 ) 7564 *249 (Wire 7565 uid 3027,0 7566 shape (OrthoPolyLine 7567 uid 3028,0 7568 va (VaSet 7569 vasetType 3 7570 ) 7571 xt "94000,87000,111000,87000" 7572 pts [ 7573 "94000,87000" 7574 "111000,87000" 7575 ] 7576 ) 7577 start &211 7578 end &113 7579 ss 0 7580 sat 32 7581 eat 32 7582 stc 0 7583 st 0 7584 sf 1 7585 si 0 7586 tg (WTG 7587 uid 3031,0 7588 ps "ConnStartEndStrategy" 7589 stg "STSignalDisplayStrategy" 7590 f (Text 7591 uid 3032,0 7592 va (VaSet 7593 isHidden 1 7594 ) 7595 xt "95000,86000,98600,87000" 7596 st "DAC_CS" 7597 blo "95000,86800" 7598 tm "WireNameMgr" 7599 ) 7600 ) 7601 on &67 7602 ) 7603 *250 (Wire 7604 uid 3218,0 7605 shape (OrthoPolyLine 7606 uid 3219,0 7607 va (VaSet 7608 vasetType 3 7609 ) 7610 xt "11000,77000,13000,77000" 7611 pts [ 7612 "11000,77000" 7613 "13000,77000" 7614 ] 7615 ) 7616 start &47 7617 end &176 7618 sat 32 7619 eat 32 7620 stc 0 7621 st 0 7622 sf 1 7623 si 0 7624 tg (WTG 7625 uid 3220,0 7626 ps "ConnStartEndStrategy" 7627 stg "STSignalDisplayStrategy" 7628 f (Text 7629 uid 3221,0 7630 va (VaSet 7631 isHidden 1 7632 ) 7633 xt "22000,76000,24100,77000" 7634 st "TRG" 7635 blo "22000,76800" 7636 tm "WireNameMgr" 7637 ) 7638 ) 7639 on &70 7640 ) 7641 *251 (Wire 7642 uid 3260,0 7643 shape (OrthoPolyLine 7644 uid 3261,0 7645 va (VaSet 7646 vasetType 3 7647 lineWidth 2 7648 ) 7649 xt "21000,70000,24000,70000" 7650 pts [ 7651 "21000,70000" 7652 "24000,70000" 7653 ] 7654 ) 7655 start &68 7656 end &71 7657 sat 32 7658 eat 2 7659 sty 1 7660 stc 0 7661 st 0 7662 sf 1 7663 si 0 7664 tg (WTG 7665 uid 3264,0 7666 ps "ConnStartEndStrategy" 7667 stg "STSignalDisplayStrategy" 7668 f (Text 7669 uid 3265,0 7670 va (VaSet 7671 isHidden 1 7672 ) 7673 xt "23000,69000,25800,70000" 7674 st "A_CLK" 7675 blo "23000,69800" 7676 tm "WireNameMgr" 7677 ) 7678 ) 7679 on &75 7680 ) 7681 *252 (Wire 7682 uid 3270,0 7683 shape (OrthoPolyLine 7684 uid 3271,0 7685 va (VaSet 7686 vasetType 3 7687 ) 7688 xt "32000,70000,51250,70000" 7689 pts [ 7690 "51250,70000" 7691 "32000,70000" 7692 ] 7693 ) 7694 start &25 7695 end &71 7696 sat 32 7697 eat 1 7698 st 0 7699 sf 1 7700 si 0 7701 tg (WTG 7702 uid 3274,0 7703 ps "ConnStartEndStrategy" 7704 stg "STSignalDisplayStrategy" 7705 f (Text 7706 uid 3275,0 7707 va (VaSet 7708 ) 7709 xt "46000,69000,50500,70000" 7710 st "CLK_25_PS" 7711 blo "46000,69800" 7712 tm "WireNameMgr" 7713 ) 7714 ) 7715 on &76 7716 ) 7717 *253 (Wire 7718 uid 3318,0 7719 shape (OrthoPolyLine 7720 uid 3319,0 7721 va (VaSet 7722 vasetType 3 7723 lineWidth 2 7724 ) 7725 xt "21000,95000,24000,95000" 7726 pts [ 7727 "21000,95000" 7728 "24000,95000" 7729 ] 7730 ) 7731 start &85 7732 end &81 7733 sat 32 7734 eat 1 7735 sty 1 7736 stc 0 7737 st 0 7738 sf 1 7739 si 0 7740 tg (WTG 7741 uid 3322,0 7742 ps "ConnStartEndStrategy" 7743 stg "STSignalDisplayStrategy" 7744 f (Text 7745 uid 3323,0 7746 va (VaSet 7747 isHidden 1 7748 ) 7749 xt "23000,94000,25300,95000" 7750 st "A0_D" 7751 blo "23000,94800" 7752 tm "WireNameMgr" 7753 ) 7754 ) 7755 on &89 7756 ) 7757 *254 (Wire 7758 uid 3352,0 7759 shape (OrthoPolyLine 7760 uid 3353,0 7761 va (VaSet 7762 vasetType 3 7763 lineWidth 2 7764 ) 7765 xt "21000,96000,24000,96000" 7766 pts [ 7767 "21000,96000" 7768 "24000,96000" 7769 ] 7770 ) 7771 start &86 7772 end &81 7773 sat 32 7774 eat 1 7775 sty 1 7776 stc 0 7777 st 0 7778 sf 1 7779 si 0 7780 tg (WTG 7781 uid 3356,0 7782 ps "ConnStartEndStrategy" 7783 stg "STSignalDisplayStrategy" 7784 f (Text 7785 uid 3357,0 7786 va (VaSet 7787 isHidden 1 7788 ) 7789 xt "23000,95000,25300,96000" 7790 st "A1_D" 7791 blo "23000,95800" 7792 tm "WireNameMgr" 7793 ) 7794 ) 7795 on &90 7796 ) 7797 *255 (Wire 7798 uid 3360,0 7799 shape (OrthoPolyLine 7800 uid 3361,0 7801 va (VaSet 7802 vasetType 3 7803 lineWidth 2 7804 ) 7805 xt "21000,97000,24000,97000" 7806 pts [ 7807 "21000,97000" 7808 "24000,97000" 7809 ] 7810 ) 7811 start &87 7812 end &81 7813 sat 32 7814 eat 1 7815 sty 1 7816 stc 0 7817 st 0 7818 sf 1 7819 si 0 7820 tg (WTG 7821 uid 3364,0 7822 ps "ConnStartEndStrategy" 7823 stg "STSignalDisplayStrategy" 7824 f (Text 7825 uid 3365,0 7826 va (VaSet 7827 isHidden 1 7828 ) 7829 xt "23000,96000,25300,97000" 7830 st "A2_D" 7831 blo "23000,96800" 7832 tm "WireNameMgr" 7833 ) 7834 ) 7835 on &91 7836 ) 7837 *256 (Wire 7838 uid 3368,0 7839 shape (OrthoPolyLine 7840 uid 3369,0 7841 va (VaSet 7842 vasetType 3 7843 lineWidth 2 7844 ) 7845 xt "21000,98000,24000,98000" 7846 pts [ 7847 "21000,98000" 7848 "24000,98000" 7849 ] 7850 ) 7851 start &88 7852 end &81 7853 sat 32 7854 eat 1 7855 sty 1 7856 stc 0 7857 st 0 7858 sf 1 7859 si 0 7860 tg (WTG 7861 uid 3372,0 7862 ps "ConnStartEndStrategy" 7863 stg "STSignalDisplayStrategy" 7864 f (Text 7865 uid 3373,0 7866 va (VaSet 7867 isHidden 1 7868 ) 7869 xt "23000,97000,25300,98000" 7870 st "A3_D" 7871 blo "23000,97800" 7872 tm "WireNameMgr" 7873 ) 7874 ) 7875 on &92 7876 ) 7877 *257 (Wire 7878 uid 3430,0 7879 shape (OrthoPolyLine 7880 uid 3431,0 7881 va (VaSet 7882 vasetType 3 7883 ) 7884 xt "21000,113000,24000,113000" 7885 pts [ 7886 "21000,113000" 7887 "24000,113000" 7888 ] 7889 ) 7890 start &161 7891 end &93 7892 sat 32 7893 eat 2 7894 stc 0 7895 st 0 7896 sf 1 7897 si 0 7898 tg (WTG 7899 uid 3434,0 7900 ps "ConnStartEndStrategy" 7901 stg "STSignalDisplayStrategy" 7902 f (Text 7903 uid 3435,0 7904 va (VaSet 7905 isHidden 1 7906 ) 7907 xt "23000,112000,27400,113000" 7908 st "D0_SRCLK" 7909 blo "23000,112800" 7910 tm "WireNameMgr" 7911 ) 7912 ) 7913 on &97 7914 ) 7915 *258 (Wire 7916 uid 3438,0 7917 shape (OrthoPolyLine 7918 uid 3439,0 7919 va (VaSet 7920 vasetType 3 7921 ) 7922 xt "21000,114000,24000,114000" 7923 pts [ 7924 "21000,114000" 7925 "24000,114000" 7926 ] 7927 ) 7928 start &162 7929 end &93 7930 sat 32 7931 eat 2 7932 stc 0 7933 st 0 7934 sf 1 7935 si 0 7936 tg (WTG 7937 uid 3442,0 7938 ps "ConnStartEndStrategy" 7939 stg "STSignalDisplayStrategy" 7940 f (Text 7941 uid 3443,0 7942 va (VaSet 7943 isHidden 1 7944 ) 7945 xt "23000,113000,27400,114000" 7946 st "D1_SRCLK" 7947 blo "23000,113800" 7948 tm "WireNameMgr" 7949 ) 7950 ) 7951 on &98 7952 ) 7953 *259 (Wire 7954 uid 3446,0 7955 shape (OrthoPolyLine 7956 uid 3447,0 7957 va (VaSet 7958 vasetType 3 7959 ) 7960 xt "21000,115000,24000,115000" 7961 pts [ 7962 "21000,115000" 7963 "24000,115000" 7964 ] 7965 ) 7966 start &163 7967 end &93 7968 sat 32 7969 eat 2 7970 stc 0 7971 st 0 7972 sf 1 7973 si 0 7974 tg (WTG 7975 uid 3450,0 7976 ps "ConnStartEndStrategy" 7977 stg "STSignalDisplayStrategy" 7978 f (Text 7979 uid 3451,0 7980 va (VaSet 7981 isHidden 1 7982 ) 7983 xt "23000,114000,27400,115000" 7984 st "D2_SRCLK" 7985 blo "23000,114800" 7986 tm "WireNameMgr" 7987 ) 7988 ) 7989 on &99 7990 ) 7991 *260 (Wire 7992 uid 3454,0 7993 shape (OrthoPolyLine 7994 uid 3455,0 7995 va (VaSet 7996 vasetType 3 7997 ) 7998 xt "21000,116000,24000,116000" 7999 pts [ 8000 "21000,116000" 8001 "24000,116000" 8002 ] 8003 ) 8004 start &164 8005 end &93 8006 sat 32 8007 eat 2 8008 stc 0 8009 st 0 8010 sf 1 8011 si 0 8012 tg (WTG 8013 uid 3458,0 8014 ps "ConnStartEndStrategy" 8015 stg "STSignalDisplayStrategy" 8016 f (Text 8017 uid 3459,0 8018 va (VaSet 8019 isHidden 1 8020 ) 8021 xt "23000,115000,27400,116000" 8022 st "D3_SRCLK" 8023 blo "23000,115800" 8024 tm "WireNameMgr" 8025 ) 8026 ) 8027 on &100 8028 ) 8029 *261 (Wire 8030 uid 3574,0 8031 shape (OrthoPolyLine 8032 uid 3575,0 8033 va (VaSet 8034 vasetType 3 8035 ) 8036 xt "108000,89000,111000,89000" 8037 pts [ 8038 "111000,89000" 8039 "108000,89000" 8040 ] 8041 ) 8042 start &118 8043 end &114 8044 sat 32 8045 eat 2 8046 stc 0 8047 st 0 8048 sf 1 8049 si 0 8050 tg (WTG 8051 uid 3578,0 8052 ps "ConnStartEndStrategy" 8053 stg "STSignalDisplayStrategy" 8054 f (Text 8055 uid 3579,0 8056 va (VaSet 8057 isHidden 1 8058 ) 8059 xt "108000,88000,110800,89000" 8060 st "T0_CS" 8061 blo "108000,88800" 8062 tm "WireNameMgr" 8063 ) 8064 ) 8065 on &122 8066 ) 8067 *262 (Wire 8068 uid 3582,0 8069 shape (OrthoPolyLine 8070 uid 3583,0 8071 va (VaSet 8072 vasetType 3 8073 ) 8074 xt "108000,90000,111000,90000" 8075 pts [ 8076 "111000,90000" 8077 "108000,90000" 8078 ] 8079 ) 8080 start &119 8081 end &114 8082 sat 32 8083 eat 2 8084 stc 0 8085 st 0 8086 sf 1 8087 si 0 8088 tg (WTG 8089 uid 3586,0 8090 ps "ConnStartEndStrategy" 8091 stg "STSignalDisplayStrategy" 8092 f (Text 8093 uid 3587,0 8094 va (VaSet 8095 isHidden 1 8096 ) 8097 xt "108000,89000,110800,90000" 8098 st "T1_CS" 8099 blo "108000,89800" 8100 tm "WireNameMgr" 8101 ) 8102 ) 8103 on &123 8104 ) 8105 *263 (Wire 8106 uid 3590,0 8107 shape (OrthoPolyLine 8108 uid 3591,0 8109 va (VaSet 8110 vasetType 3 8111 ) 8112 xt "108000,91000,111000,91000" 8113 pts [ 8114 "111000,91000" 8115 "108000,91000" 8116 ] 8117 ) 8118 start &120 8119 end &114 8120 sat 32 8121 eat 2 8122 stc 0 8123 st 0 8124 sf 1 8125 si 0 8126 tg (WTG 8127 uid 3594,0 8128 ps "ConnStartEndStrategy" 8129 stg "STSignalDisplayStrategy" 8130 f (Text 8131 uid 3595,0 8132 va (VaSet 8133 isHidden 1 8134 ) 8135 xt "108000,90000,110800,91000" 8136 st "T2_CS" 8137 blo "108000,90800" 8138 tm "WireNameMgr" 8139 ) 8140 ) 8141 on &124 8142 ) 8143 *264 (Wire 8144 uid 3598,0 8145 shape (OrthoPolyLine 8146 uid 3599,0 8147 va (VaSet 8148 vasetType 3 8149 ) 8150 xt "108000,92000,111000,92000" 8151 pts [ 8152 "111000,92000" 8153 "108000,92000" 8154 ] 8155 ) 8156 start &121 8157 end &114 8158 sat 32 8159 eat 2 8160 stc 0 8161 st 0 8162 sf 1 8163 si 0 8164 tg (WTG 8165 uid 3602,0 8166 ps "ConnStartEndStrategy" 8167 stg "STSignalDisplayStrategy" 8168 f (Text 8169 uid 3603,0 8170 va (VaSet 8171 isHidden 1 8172 ) 8173 xt "108000,91000,110800,92000" 8174 st "T3_CS" 8175 blo "108000,91800" 8176 tm "WireNameMgr" 8177 ) 8178 ) 8179 on &125 8180 ) 8181 *265 (Wire 8182 uid 3682,0 8183 shape (OrthoPolyLine 8184 uid 3683,0 8185 va (VaSet 8186 vasetType 3 8187 ) 8188 xt "80750,100000,111000,100000" 8189 pts [ 8190 "80750,100000" 8191 "111000,100000" 8192 ] 8193 ) 8194 start &42 8195 end &137 8196 sat 32 8197 eat 32 8198 stc 0 8199 st 0 8200 sf 1 8201 si 0 8202 tg (WTG 8203 uid 3686,0 8204 ps "ConnStartEndStrategy" 8205 stg "STSignalDisplayStrategy" 8206 f (Text 8207 uid 3687,0 8208 va (VaSet 8209 isHidden 1 8210 ) 8211 xt "82000,99000,84400,100000" 8212 st "MOSI" 8213 blo "82000,99800" 8214 tm "WireNameMgr" 8215 ) 8216 ) 8217 on &136 8218 ) 8219 *266 (Wire 8220 uid 3778,0 8221 shape (OrthoPolyLine 8222 uid 3779,0 8223 va (VaSet 8224 vasetType 3 8225 ) 8226 xt "108000,103000,111000,103000" 8227 pts [ 8228 "111000,103000" 8229 "108000,103000" 8230 ] 8231 ) 8232 start &143 8233 end &139 8234 sat 32 8235 eat 2 8236 stc 0 8237 st 0 8238 sf 1 8239 si 0 8240 tg (WTG 8241 uid 3782,0 8242 ps "ConnStartEndStrategy" 8243 stg "STSignalDisplayStrategy" 8244 f (Text 8245 uid 3783,0 8246 va (VaSet 8247 isHidden 1 8248 ) 8249 xt "108000,102000,111000,103000" 8250 st "TRG_V" 8251 blo "108000,102800" 8252 tm "WireNameMgr" 8253 ) 8254 ) 8255 on &152 8256 ) 8257 *267 (Wire 8258 uid 3786,0 8259 shape (OrthoPolyLine 8260 uid 3787,0 8261 va (VaSet 8262 vasetType 3 8263 ) 8264 xt "108000,104000,111000,104000" 8265 pts [ 8266 "111000,104000" 8267 "108000,104000" 8268 ] 8269 ) 8270 start &144 8271 end &139 8272 sat 32 8273 eat 2 8274 stc 0 8275 st 0 8276 sf 1 8277 si 0 8278 tg (WTG 8279 uid 3790,0 8280 ps "ConnStartEndStrategy" 8281 stg "STSignalDisplayStrategy" 8282 f (Text 8283 uid 3791,0 8284 va (VaSet 8285 isHidden 1 8286 ) 8287 xt "108000,103000,113600,104000" 8288 st "RS485_C_RE" 8289 blo "108000,103800" 8290 tm "WireNameMgr" 8291 ) 8292 ) 8293 on &153 8294 ) 8295 *268 (Wire 8296 uid 3794,0 8297 shape (OrthoPolyLine 8298 uid 3795,0 8299 va (VaSet 8300 vasetType 3 8301 ) 8302 xt "108000,105000,111000,105000" 8303 pts [ 8304 "111000,105000" 8305 "108000,105000" 8306 ] 8307 ) 8308 start &145 8309 end &139 8310 sat 32 8311 eat 2 8312 stc 0 8313 st 0 8314 sf 1 8315 si 0 8316 tg (WTG 8317 uid 3798,0 8318 ps "ConnStartEndStrategy" 8319 stg "STSignalDisplayStrategy" 8320 f (Text 8321 uid 3799,0 8322 va (VaSet 8323 isHidden 1 8324 ) 8325 xt "108000,104000,113600,105000" 8326 st "RS485_C_DE" 8327 blo "108000,104800" 8328 tm "WireNameMgr" 8329 ) 8330 ) 8331 on &154 8332 ) 8333 *269 (Wire 8334 uid 3802,0 8335 shape (OrthoPolyLine 8336 uid 3803,0 8337 va (VaSet 8338 vasetType 3 8339 ) 8340 xt "108000,106000,111000,106000" 8341 pts [ 8342 "111000,106000" 8343 "108000,106000" 8344 ] 8345 ) 8346 start &146 8347 end &139 8348 sat 32 8349 eat 2 8350 stc 0 8351 st 0 8352 sf 1 8353 si 0 8354 tg (WTG 8355 uid 3806,0 8356 ps "ConnStartEndStrategy" 8357 stg "STSignalDisplayStrategy" 8358 f (Text 8359 uid 3807,0 8360 va (VaSet 8361 isHidden 1 8362 ) 8363 xt "108000,105000,113500,106000" 8364 st "RS485_E_RE" 8365 blo "108000,105800" 8366 tm "WireNameMgr" 8367 ) 8368 ) 8369 on &155 8370 ) 8371 *270 (Wire 8372 uid 3810,0 8373 shape (OrthoPolyLine 8374 uid 3811,0 8375 va (VaSet 8376 vasetType 3 8377 ) 8378 xt "108000,107000,111000,107000" 8379 pts [ 8380 "111000,107000" 8381 "108000,107000" 8382 ] 8383 ) 8384 start &147 8385 end &139 8386 sat 32 8387 eat 2 8388 stc 0 8389 st 0 8390 sf 1 8391 si 0 8392 tg (WTG 8393 uid 3814,0 8394 ps "ConnStartEndStrategy" 8395 stg "STSignalDisplayStrategy" 8396 f (Text 8397 uid 3815,0 8398 va (VaSet 8399 isHidden 1 8400 ) 8401 xt "108000,106000,113500,107000" 8402 st "RS485_E_DE" 8403 blo "108000,106800" 8404 tm "WireNameMgr" 8405 ) 8406 ) 8407 on &156 8408 ) 8409 *271 (Wire 8410 uid 3826,0 8411 shape (OrthoPolyLine 8412 uid 3827,0 8413 va (VaSet 8414 vasetType 3 8415 ) 8416 xt "108000,109000,111000,109000" 8417 pts [ 8418 "111000,109000" 8419 "108000,109000" 8420 ] 8421 ) 8422 start &149 8423 end &139 8424 sat 32 8425 eat 2 8426 stc 0 8427 st 0 8428 sf 1 8429 si 0 8430 tg (WTG 8431 uid 3830,0 8432 ps "ConnStartEndStrategy" 8433 stg "STSignalDisplayStrategy" 8434 f (Text 8435 uid 3831,0 8436 va (VaSet 8437 isHidden 1 8438 ) 8439 xt "108000,108000,110300,109000" 8440 st "SRIN" 8441 blo "108000,108800" 8442 tm "WireNameMgr" 8443 ) 8444 ) 8445 on &158 8446 ) 8447 *272 (Wire 8448 uid 3834,0 8449 shape (OrthoPolyLine 8450 uid 3835,0 8451 va (VaSet 8452 vasetType 3 8453 ) 8454 xt "108000,110000,111000,110000" 8455 pts [ 8456 "111000,110000" 8457 "108000,110000" 8458 ] 8459 ) 8460 start &150 8461 end &139 8462 sat 32 8463 eat 2 8464 stc 0 8465 st 0 8466 sf 1 8467 si 0 8468 tg (WTG 8469 uid 3838,0 8470 ps "ConnStartEndStrategy" 8471 stg "STSignalDisplayStrategy" 8472 f (Text 8473 uid 3839,0 8474 va (VaSet 8475 isHidden 1 8476 ) 8477 xt "108000,109000,110900,110000" 8478 st "EE_CS" 8479 blo "108000,109800" 8480 tm "WireNameMgr" 8481 ) 8482 ) 8483 on &159 8484 ) 8485 *273 (Wire 8486 uid 3842,0 8487 shape (OrthoPolyLine 8488 uid 3843,0 8489 va (VaSet 8490 vasetType 3 8491 lineWidth 2 8492 ) 8493 xt "108000,111000,111000,111000" 8494 pts [ 8495 "111000,111000" 8496 "108000,111000" 8497 ] 8498 ) 8499 start &151 8500 end &139 8501 sat 32 8502 eat 2 8503 sty 1 8504 stc 0 8505 st 0 8506 sf 1 8507 si 0 8508 tg (WTG 8509 uid 3846,0 8510 ps "ConnStartEndStrategy" 8511 stg "STSignalDisplayStrategy" 8512 f (Text 8513 uid 3847,0 8514 va (VaSet 8515 isHidden 1 8516 ) 8517 xt "108000,110000,109900,111000" 8518 st "LED" 8519 blo "108000,110800" 8520 tm "WireNameMgr" 8521 ) 8522 ) 8523 on &160 8524 ) 8525 *274 (Wire 8526 uid 4942,0 8527 shape (OrthoPolyLine 8528 uid 4943,0 8529 va (VaSet 8530 vasetType 3 8531 lineWidth 2 8532 ) 8533 xt "80750,120000,111000,120000" 8534 pts [ 8535 "80750,120000" 8536 "111000,120000" 8537 ] 8538 ) 8539 start &14 8540 end &165 7590 8541 sat 32 7591 8542 eat 32 … … 7596 8547 si 0 7597 8548 tg (WTG 7598 uid 1837,08549 uid 4948,0 7599 8550 ps "ConnStartEndStrategy" 7600 8551 stg "STSignalDisplayStrategy" 7601 8552 f (Text 7602 uid 1838,08553 uid 4949,0 7603 8554 va (VaSet 7604 8555 isHidden 1 7605 8556 ) 7606 xt " 22000,108000,23900,109000"7607 st "D_ A"7608 blo " 22000,108800"7609 tm "WireNameMgr" 7610 ) 7611 ) 7612 on &1 117613 ) 7614 *2 55 (Wire7615 uid 1841,08557 xt "82750,117000,84650,118000" 8558 st "D_T" 8559 blo "82750,117800" 8560 tm "WireNameMgr" 8561 ) 8562 ) 8563 on &166 8564 ) 8565 *275 (Wire 8566 uid 6130,0 7616 8567 shape (OrthoPolyLine 7617 uid 1842,08568 uid 6131,0 7618 8569 va (VaSet 7619 8570 vasetType 3 7620 8571 ) 7621 xt "21000,110000,51250,110000" 7622 pts [ 7623 "51250,110000" 7624 "21000,110000" 7625 ] 7626 ) 7627 start &31 7628 end &112 8572 xt "19000,78000,51250,78000" 8573 pts [ 8574 "19000,78000" 8575 "51250,78000" 8576 ] 8577 ) 8578 start &173 8579 end &15 8580 sat 32 8581 eat 32 8582 st 0 8583 sf 1 8584 si 0 8585 tg (WTG 8586 uid 6136,0 8587 ps "ConnStartEndStrategy" 8588 stg "STSignalDisplayStrategy" 8589 f (Text 8590 uid 6137,0 8591 va (VaSet 8592 ) 8593 xt "21000,77000,24700,78000" 8594 st "TRG_OR" 8595 blo "21000,77800" 8596 tm "WireNameMgr" 8597 ) 8598 ) 8599 on &169 8600 ) 8601 *276 (Wire 8602 uid 6306,0 8603 shape (OrthoPolyLine 8604 uid 6307,0 8605 va (VaSet 8606 vasetType 3 8607 ) 8608 xt "11000,79000,13000,79000" 8609 pts [ 8610 "11000,79000" 8611 "13000,79000" 8612 ] 8613 ) 8614 start &167 8615 end &171 7629 8616 sat 32 7630 8617 eat 32 … … 7634 8621 si 0 7635 8622 tg (WTG 7636 uid 1845,08623 uid 6312,0 7637 8624 ps "ConnStartEndStrategy" 7638 8625 stg "STSignalDisplayStrategy" 7639 8626 f (Text 7640 uid 1846,08627 uid 6313,0 7641 8628 va (VaSet 7642 8629 isHidden 1 7643 8630 ) 7644 xt " 22000,109000,25500,110000"7645 st " DWRITE"7646 blo " 22000,109800"7647 tm "WireNameMgr" 7648 ) 7649 ) 7650 on &1 137651 ) 7652 *2 56(Wire7653 uid 1865,08631 xt "13000,78000,17500,79000" 8632 st "TEST_TRG" 8633 blo "13000,78800" 8634 tm "WireNameMgr" 8635 ) 8636 ) 8637 on &168 8638 ) 8639 *277 (Wire 8640 uid 6431,0 7654 8641 shape (OrthoPolyLine 7655 uid 1866,08642 uid 6432,0 7656 8643 va (VaSet 7657 8644 vasetType 3 7658 8645 ) 7659 xt " 21000,105000,51250,105000"7660 pts [ 7661 " 21000,105000"7662 " 51250,105000"7663 ] 7664 ) 7665 start & 1027666 end & 328646 xt "80750,121000,111000,121000" 8647 pts [ 8648 "80750,121000" 8649 "111000,121000" 8650 ] 8651 ) 8652 start &43 8653 end &148 7667 8654 sat 32 7668 8655 eat 32 … … 7672 8659 si 0 7673 8660 tg (WTG 7674 uid 1869,08661 uid 6435,0 7675 8662 ps "ConnStartEndStrategy" 7676 8663 stg "STSignalDisplayStrategy" 7677 8664 f (Text 7678 uid 1870,08665 uid 6436,0 7679 8666 va (VaSet 7680 8667 isHidden 1 7681 8668 ) 7682 xt " 22000,104000,26600,105000"7683 st "D 0_SROUT"7684 blo " 22000,104800"7685 tm "WireNameMgr" 7686 ) 7687 ) 7688 on &1 067689 ) 7690 *2 57(Wire7691 uid 1873,08669 xt "92000,120000,96000,121000" 8670 st "DENABLE" 8671 blo "92000,120800" 8672 tm "WireNameMgr" 8673 ) 8674 ) 8675 on &157 8676 ) 8677 *278 (Wire 8678 uid 6787,0 7692 8679 shape (OrthoPolyLine 7693 uid 1874,0 7694 va (VaSet 7695 vasetType 3 7696 ) 7697 xt "21000,106000,51250,106000" 7698 pts [ 7699 "21000,106000" 7700 "51250,106000" 7701 ] 7702 ) 7703 start &103 7704 end &33 7705 sat 32 7706 eat 32 7707 stc 0 7708 st 0 7709 sf 1 7710 si 0 7711 tg (WTG 7712 uid 1877,0 7713 ps "ConnStartEndStrategy" 7714 stg "STSignalDisplayStrategy" 7715 f (Text 7716 uid 1878,0 7717 va (VaSet 7718 isHidden 1 7719 ) 7720 xt "22000,105000,26600,106000" 7721 st "D1_SROUT" 7722 blo "22000,105800" 7723 tm "WireNameMgr" 7724 ) 7725 ) 7726 on &107 7727 ) 7728 *258 (Wire 7729 uid 1881,0 7730 shape (OrthoPolyLine 7731 uid 1882,0 7732 va (VaSet 7733 vasetType 3 7734 ) 7735 xt "21000,107000,51250,107000" 7736 pts [ 7737 "21000,107000" 7738 "51250,107000" 7739 ] 7740 ) 7741 start &104 7742 end &34 7743 sat 32 7744 eat 32 7745 stc 0 7746 st 0 7747 sf 1 7748 si 0 7749 tg (WTG 7750 uid 1885,0 7751 ps "ConnStartEndStrategy" 7752 stg "STSignalDisplayStrategy" 7753 f (Text 7754 uid 1886,0 7755 va (VaSet 7756 isHidden 1 7757 ) 7758 xt "22000,106000,26600,107000" 7759 st "D2_SROUT" 7760 blo "22000,106800" 7761 tm "WireNameMgr" 7762 ) 7763 ) 7764 on &108 7765 ) 7766 *259 (Wire 7767 uid 1889,0 7768 shape (OrthoPolyLine 7769 uid 1890,0 7770 va (VaSet 7771 vasetType 3 7772 ) 7773 xt "21000,108000,51250,108000" 7774 pts [ 7775 "21000,108000" 7776 "51250,108000" 7777 ] 7778 ) 7779 start &105 7780 end &35 7781 sat 32 7782 eat 32 7783 stc 0 7784 st 0 7785 sf 1 7786 si 0 7787 tg (WTG 7788 uid 1893,0 7789 ps "ConnStartEndStrategy" 7790 stg "STSignalDisplayStrategy" 7791 f (Text 7792 uid 1894,0 7793 va (VaSet 7794 isHidden 1 7795 ) 7796 xt "22000,107000,26600,108000" 7797 st "D3_SROUT" 7798 blo "22000,107800" 7799 tm "WireNameMgr" 7800 ) 7801 ) 7802 on &109 7803 ) 7804 *260 (Wire 7805 uid 2269,0 7806 shape (OrthoPolyLine 7807 uid 2270,0 7808 va (VaSet 7809 vasetType 3 7810 ) 7811 xt "-15000,69000,51250,88000" 7812 pts [ 7813 "51250,69000" 7814 "-15000,69000" 7815 "-15000,88000" 7816 "-11750,88000" 7817 ] 7818 ) 7819 start &26 7820 end &172 7821 sat 32 7822 eat 32 7823 stc 0 7824 st 0 7825 sf 1 7826 si 0 7827 tg (WTG 7828 uid 2273,0 7829 ps "ConnStartEndStrategy" 7830 stg "STSignalDisplayStrategy" 7831 f (Text 7832 uid 2274,0 7833 va (VaSet 7834 isHidden 1 7835 ) 7836 xt "50250,68000,53350,69000" 7837 st "CLK_50" 7838 blo "50250,68800" 7839 tm "WireNameMgr" 7840 ) 7841 ) 7842 on &63 7843 ) 7844 *261 (Wire 7845 uid 2409,0 7846 shape (OrthoPolyLine 7847 uid 2410,0 7848 va (VaSet 7849 vasetType 3 7850 ) 7851 xt "21000,111000,51250,111000" 7852 pts [ 7853 "51250,111000" 7854 "21000,111000" 7855 ] 7856 ) 7857 start &36 7858 end &65 7859 sat 32 7860 eat 32 7861 stc 0 7862 st 0 7863 sf 1 7864 si 0 7865 tg (WTG 7866 uid 2413,0 7867 ps "ConnStartEndStrategy" 7868 stg "STSignalDisplayStrategy" 7869 f (Text 7870 uid 2414,0 7871 va (VaSet 7872 isHidden 1 7873 ) 7874 xt "22000,110000,26200,111000" 7875 st "RSRLOAD" 7876 blo "22000,110800" 7877 tm "WireNameMgr" 7878 ) 7879 ) 7880 on &64 7881 ) 7882 *262 (Wire 7883 uid 2423,0 7884 shape (OrthoPolyLine 7885 uid 2424,0 7886 va (VaSet 7887 vasetType 3 7888 ) 7889 xt "32000,113000,51250,113000" 7890 pts [ 7891 "51250,113000" 7892 "32000,113000" 7893 ] 7894 ) 7895 start &37 7896 end &94 7897 sat 32 7898 eat 1 7899 stc 0 7900 st 0 7901 sf 1 7902 si 0 7903 tg (WTG 7904 uid 2427,0 7905 ps "ConnStartEndStrategy" 7906 stg "STSignalDisplayStrategy" 7907 f (Text 7908 uid 2428,0 7909 va (VaSet 7910 isHidden 1 7911 ) 7912 xt "66250,109000,69250,110000" 7913 st "SRCLK" 7914 blo "66250,109800" 7915 tm "WireNameMgr" 7916 ) 7917 ) 7918 on &66 7919 ) 7920 *263 (Wire 7921 uid 3009,0 7922 shape (OrthoPolyLine 7923 uid 3010,0 7924 va (VaSet 7925 vasetType 3 7926 ) 7927 xt "80750,98000,111000,98000" 7928 pts [ 7929 "80750,98000" 7930 "111000,98000" 7931 ] 7932 ) 7933 start &39 7934 end &127 7935 sat 32 7936 eat 32 7937 stc 0 7938 st 0 7939 sf 1 7940 si 0 7941 tg (WTG 7942 uid 3011,0 7943 ps "ConnStartEndStrategy" 7944 stg "STSignalDisplayStrategy" 7945 f (Text 7946 uid 3012,0 7947 va (VaSet 7948 isHidden 1 7949 ) 7950 xt "82000,97000,84800,98000" 7951 st "S_CLK" 7952 blo "82000,97800" 7953 tm "WireNameMgr" 7954 ) 7955 ) 7956 on &128 7957 ) 7958 *264 (Wire 7959 uid 3015,0 7960 shape (OrthoPolyLine 7961 uid 3016,0 7962 va (VaSet 7963 vasetType 3 7964 ) 7965 xt "80750,99000,111000,99000" 7966 pts [ 7967 "80750,99000" 7968 "111000,99000" 7969 ] 7970 ) 7971 start &41 7972 end &136 7973 sat 32 7974 eat 32 7975 stc 0 7976 st 0 7977 sf 1 7978 si 0 7979 tg (WTG 7980 uid 3017,0 7981 ps "ConnStartEndStrategy" 7982 stg "STSignalDisplayStrategy" 7983 f (Text 7984 uid 3018,0 7985 va (VaSet 7986 isHidden 1 7987 ) 7988 xt "82750,98000,85150,99000" 7989 st "MISO" 7990 blo "82750,98800" 7991 tm "WireNameMgr" 7992 ) 7993 ) 7994 on &139 7995 ) 7996 *265 (Wire 7997 uid 3021,0 7998 shape (OrthoPolyLine 7999 uid 3022,0 8680 uid 6788,0 8000 8681 va (VaSet 8001 8682 vasetType 3 8002 8683 lineWidth 2 8003 8684 ) 8004 xt " 80750,89000,100000,89000"8005 pts [ 8006 " 80750,89000"8007 " 100000,89000"8008 ] 8009 ) 8010 start & 408011 end &1 158685 xt "93000,132000,99000,132000" 8686 pts [ 8687 "93000,132000" 8688 "99000,132000" 8689 ] 8690 ) 8691 start &193 8692 end &197 8012 8693 sat 32 8013 8694 eat 1 … … 8017 8698 si 0 8018 8699 tg (WTG 8019 uid 3023,08700 uid 6791,0 8020 8701 ps "ConnStartEndStrategy" 8021 8702 stg "STSignalDisplayStrategy" 8022 8703 f (Text 8023 uid 3024,0 8024 va (VaSet 8025 ) 8026 xt "92000,88000,98500,89000" 8027 st "sensor_cs : (3:0)" 8028 blo "92000,88800" 8029 tm "WireNameMgr" 8030 ) 8031 ) 8032 on &67 8033 ) 8034 *266 (Wire 8035 uid 3027,0 8704 uid 6792,0 8705 va (VaSet 8706 isHidden 1 8707 ) 8708 xt "95000,131000,101800,132000" 8709 st "D_PLLLCK : (3:0)" 8710 blo "95000,131800" 8711 tm "WireNameMgr" 8712 ) 8713 ) 8714 on &194 8715 ) 8716 *279 (Wire 8717 uid 6880,0 8036 8718 shape (OrthoPolyLine 8037 uid 3028,0 8038 va (VaSet 8039 vasetType 3 8040 ) 8041 xt "94000,87000,111000,87000" 8042 pts [ 8043 "94000,87000" 8044 "111000,87000" 8045 ] 8046 ) 8047 start &231 8048 end &114 8049 ss 0 8050 sat 32 8051 eat 32 8052 stc 0 8053 st 0 8054 sf 1 8055 si 0 8056 tg (WTG 8057 uid 3031,0 8058 ps "ConnStartEndStrategy" 8059 stg "STSignalDisplayStrategy" 8060 f (Text 8061 uid 3032,0 8062 va (VaSet 8063 isHidden 1 8064 ) 8065 xt "95000,86000,98600,87000" 8066 st "DAC_CS" 8067 blo "95000,86800" 8068 tm "WireNameMgr" 8069 ) 8070 ) 8071 on &68 8072 ) 8073 *267 (Wire 8074 uid 3218,0 8075 shape (OrthoPolyLine 8076 uid 3219,0 8077 va (VaSet 8078 vasetType 3 8079 ) 8080 xt "11000,77000,13000,77000" 8081 pts [ 8082 "11000,77000" 8083 "13000,77000" 8084 ] 8085 ) 8086 start &47 8087 end &196 8088 sat 32 8089 eat 32 8090 stc 0 8091 st 0 8092 sf 1 8093 si 0 8094 tg (WTG 8095 uid 3220,0 8096 ps "ConnStartEndStrategy" 8097 stg "STSignalDisplayStrategy" 8098 f (Text 8099 uid 3221,0 8100 va (VaSet 8101 isHidden 1 8102 ) 8103 xt "22000,76000,24100,77000" 8104 st "TRG" 8105 blo "22000,76800" 8106 tm "WireNameMgr" 8107 ) 8108 ) 8109 on &71 8110 ) 8111 *268 (Wire 8112 uid 3260,0 8113 shape (OrthoPolyLine 8114 uid 3261,0 8719 uid 6881,0 8115 8720 va (VaSet 8116 8721 vasetType 3 8117 8722 lineWidth 2 8118 8723 ) 8119 xt " 21000,70000,24000,70000"8120 pts [ 8121 " 21000,70000"8122 " 24000,70000"8123 ] 8124 ) 8125 start & 698126 end & 728127 sat 328128 eat 28724 xt "102000,132000,109000,132000" 8725 pts [ 8726 "102000,132000" 8727 "109000,132000" 8728 ] 8729 ) 8730 start &197 8731 end &195 8732 sat 2 8733 eat 32 8129 8734 sty 1 8130 stc 08131 8735 st 0 8132 8736 sf 1 8133 8737 si 0 8134 8738 tg (WTG 8135 uid 3264,08739 uid 6884,0 8136 8740 ps "ConnStartEndStrategy" 8137 8741 stg "STSignalDisplayStrategy" 8138 8742 f (Text 8139 uid 3265,08743 uid 6885,0 8140 8744 va (VaSet 8141 8745 isHidden 1 8142 8746 ) 8143 xt " 23000,69000,25800,70000"8144 st " A_CLK"8145 blo " 23000,69800"8146 tm "WireNameMgr" 8147 ) 8148 ) 8149 on & 768150 ) 8151 *2 69(Wire8152 uid 3270,08747 xt "104000,131000,108900,132000" 8748 st "D_T2 : (3:0)" 8749 blo "104000,131800" 8750 tm "WireNameMgr" 8751 ) 8752 ) 8753 on &196 8754 ) 8755 *280 (Wire 8756 uid 7144,0 8153 8757 shape (OrthoPolyLine 8154 uid 3271,0 8155 va (VaSet 8156 vasetType 3 8157 ) 8158 xt "32000,70000,51250,70000" 8159 pts [ 8160 "51250,70000" 8161 "32000,70000" 8162 ] 8163 ) 8164 start &25 8165 end &72 8166 sat 32 8167 eat 1 8168 st 0 8169 sf 1 8170 si 0 8171 tg (WTG 8172 uid 3274,0 8173 ps "ConnStartEndStrategy" 8174 stg "STSignalDisplayStrategy" 8175 f (Text 8176 uid 3275,0 8177 va (VaSet 8178 ) 8179 xt "46000,69000,50500,70000" 8180 st "CLK_25_PS" 8181 blo "46000,69800" 8182 tm "WireNameMgr" 8183 ) 8184 ) 8185 on &77 8186 ) 8187 *270 (Wire 8188 uid 3318,0 8189 shape (OrthoPolyLine 8190 uid 3319,0 8758 uid 7145,0 8191 8759 va (VaSet 8192 8760 vasetType 3 8193 8761 lineWidth 2 8194 8762 ) 8195 xt "21000,95000,24000,95000" 8196 pts [ 8197 "21000,95000" 8198 "24000,95000" 8199 ] 8200 ) 8201 start &86 8202 end &82 8203 sat 32 8204 eat 1 8205 sty 1 8206 stc 0 8207 st 0 8208 sf 1 8209 si 0 8210 tg (WTG 8211 uid 3322,0 8212 ps "ConnStartEndStrategy" 8213 stg "STSignalDisplayStrategy" 8214 f (Text 8215 uid 3323,0 8216 va (VaSet 8217 isHidden 1 8218 ) 8219 xt "23000,94000,25300,95000" 8220 st "A0_D" 8221 blo "23000,94800" 8222 tm "WireNameMgr" 8223 ) 8224 ) 8225 on &90 8226 ) 8227 *271 (Wire 8228 uid 3352,0 8229 shape (OrthoPolyLine 8230 uid 3353,0 8231 va (VaSet 8232 vasetType 3 8233 lineWidth 2 8234 ) 8235 xt "21000,96000,24000,96000" 8236 pts [ 8237 "21000,96000" 8238 "24000,96000" 8239 ] 8240 ) 8241 start &87 8242 end &82 8243 sat 32 8244 eat 1 8245 sty 1 8246 stc 0 8247 st 0 8248 sf 1 8249 si 0 8250 tg (WTG 8251 uid 3356,0 8252 ps "ConnStartEndStrategy" 8253 stg "STSignalDisplayStrategy" 8254 f (Text 8255 uid 3357,0 8256 va (VaSet 8257 isHidden 1 8258 ) 8259 xt "23000,95000,25300,96000" 8260 st "A1_D" 8261 blo "23000,95800" 8262 tm "WireNameMgr" 8263 ) 8264 ) 8265 on &91 8266 ) 8267 *272 (Wire 8268 uid 3360,0 8269 shape (OrthoPolyLine 8270 uid 3361,0 8271 va (VaSet 8272 vasetType 3 8273 lineWidth 2 8274 ) 8275 xt "21000,97000,24000,97000" 8276 pts [ 8277 "21000,97000" 8278 "24000,97000" 8279 ] 8280 ) 8281 start &88 8282 end &82 8283 sat 32 8284 eat 1 8285 sty 1 8286 stc 0 8287 st 0 8288 sf 1 8289 si 0 8290 tg (WTG 8291 uid 3364,0 8292 ps "ConnStartEndStrategy" 8293 stg "STSignalDisplayStrategy" 8294 f (Text 8295 uid 3365,0 8296 va (VaSet 8297 isHidden 1 8298 ) 8299 xt "23000,96000,25300,97000" 8300 st "A2_D" 8301 blo "23000,96800" 8302 tm "WireNameMgr" 8303 ) 8304 ) 8305 on &92 8306 ) 8307 *273 (Wire 8308 uid 3368,0 8309 shape (OrthoPolyLine 8310 uid 3369,0 8311 va (VaSet 8312 vasetType 3 8313 lineWidth 2 8314 ) 8315 xt "21000,98000,24000,98000" 8316 pts [ 8317 "21000,98000" 8318 "24000,98000" 8319 ] 8320 ) 8321 start &89 8322 end &82 8323 sat 32 8324 eat 1 8325 sty 1 8326 stc 0 8327 st 0 8328 sf 1 8329 si 0 8330 tg (WTG 8331 uid 3372,0 8332 ps "ConnStartEndStrategy" 8333 stg "STSignalDisplayStrategy" 8334 f (Text 8335 uid 3373,0 8336 va (VaSet 8337 isHidden 1 8338 ) 8339 xt "23000,97000,25300,98000" 8340 st "A3_D" 8341 blo "23000,97800" 8342 tm "WireNameMgr" 8343 ) 8344 ) 8345 on &93 8346 ) 8347 *274 (Wire 8348 uid 3430,0 8349 shape (OrthoPolyLine 8350 uid 3431,0 8351 va (VaSet 8352 vasetType 3 8353 ) 8354 xt "21000,113000,24000,113000" 8355 pts [ 8356 "21000,113000" 8357 "24000,113000" 8358 ] 8359 ) 8360 start &162 8361 end &94 8362 sat 32 8363 eat 2 8364 stc 0 8365 st 0 8366 sf 1 8367 si 0 8368 tg (WTG 8369 uid 3434,0 8370 ps "ConnStartEndStrategy" 8371 stg "STSignalDisplayStrategy" 8372 f (Text 8373 uid 3435,0 8374 va (VaSet 8375 isHidden 1 8376 ) 8377 xt "23000,112000,27400,113000" 8378 st "D0_SRCLK" 8379 blo "23000,112800" 8380 tm "WireNameMgr" 8381 ) 8382 ) 8383 on &98 8384 ) 8385 *275 (Wire 8386 uid 3438,0 8387 shape (OrthoPolyLine 8388 uid 3439,0 8389 va (VaSet 8390 vasetType 3 8391 ) 8392 xt "21000,114000,24000,114000" 8393 pts [ 8394 "21000,114000" 8395 "24000,114000" 8396 ] 8397 ) 8398 start &163 8399 end &94 8400 sat 32 8401 eat 2 8402 stc 0 8403 st 0 8404 sf 1 8405 si 0 8406 tg (WTG 8407 uid 3442,0 8408 ps "ConnStartEndStrategy" 8409 stg "STSignalDisplayStrategy" 8410 f (Text 8411 uid 3443,0 8412 va (VaSet 8413 isHidden 1 8414 ) 8415 xt "23000,113000,27400,114000" 8416 st "D1_SRCLK" 8417 blo "23000,113800" 8418 tm "WireNameMgr" 8419 ) 8420 ) 8421 on &99 8422 ) 8423 *276 (Wire 8424 uid 3446,0 8425 shape (OrthoPolyLine 8426 uid 3447,0 8427 va (VaSet 8428 vasetType 3 8429 ) 8430 xt "21000,115000,24000,115000" 8431 pts [ 8432 "21000,115000" 8433 "24000,115000" 8434 ] 8435 ) 8436 start &164 8437 end &94 8438 sat 32 8439 eat 2 8440 stc 0 8441 st 0 8442 sf 1 8443 si 0 8444 tg (WTG 8445 uid 3450,0 8446 ps "ConnStartEndStrategy" 8447 stg "STSignalDisplayStrategy" 8448 f (Text 8449 uid 3451,0 8450 va (VaSet 8451 isHidden 1 8452 ) 8453 xt "23000,114000,27400,115000" 8454 st "D2_SRCLK" 8455 blo "23000,114800" 8456 tm "WireNameMgr" 8457 ) 8458 ) 8459 on &100 8460 ) 8461 *277 (Wire 8462 uid 3454,0 8463 shape (OrthoPolyLine 8464 uid 3455,0 8465 va (VaSet 8466 vasetType 3 8467 ) 8468 xt "21000,116000,24000,116000" 8469 pts [ 8470 "21000,116000" 8471 "24000,116000" 8472 ] 8473 ) 8474 start &165 8475 end &94 8476 sat 32 8477 eat 2 8478 stc 0 8479 st 0 8480 sf 1 8481 si 0 8482 tg (WTG 8483 uid 3458,0 8484 ps "ConnStartEndStrategy" 8485 stg "STSignalDisplayStrategy" 8486 f (Text 8487 uid 3459,0 8488 va (VaSet 8489 isHidden 1 8490 ) 8491 xt "23000,115000,27400,116000" 8492 st "D3_SRCLK" 8493 blo "23000,115800" 8494 tm "WireNameMgr" 8495 ) 8496 ) 8497 on &101 8498 ) 8499 *278 (Wire 8500 uid 3574,0 8501 shape (OrthoPolyLine 8502 uid 3575,0 8503 va (VaSet 8504 vasetType 3 8505 ) 8506 xt "108000,89000,111000,89000" 8507 pts [ 8508 "111000,89000" 8509 "108000,89000" 8510 ] 8511 ) 8512 start &119 8513 end &115 8514 sat 32 8515 eat 2 8516 stc 0 8517 st 0 8518 sf 1 8519 si 0 8520 tg (WTG 8521 uid 3578,0 8522 ps "ConnStartEndStrategy" 8523 stg "STSignalDisplayStrategy" 8524 f (Text 8525 uid 3579,0 8526 va (VaSet 8527 isHidden 1 8528 ) 8529 xt "108000,88000,110800,89000" 8530 st "T0_CS" 8531 blo "108000,88800" 8532 tm "WireNameMgr" 8533 ) 8534 ) 8535 on &123 8536 ) 8537 *279 (Wire 8538 uid 3582,0 8539 shape (OrthoPolyLine 8540 uid 3583,0 8541 va (VaSet 8542 vasetType 3 8543 ) 8544 xt "108000,90000,111000,90000" 8545 pts [ 8546 "111000,90000" 8547 "108000,90000" 8548 ] 8549 ) 8550 start &120 8551 end &115 8552 sat 32 8553 eat 2 8554 stc 0 8555 st 0 8556 sf 1 8557 si 0 8558 tg (WTG 8559 uid 3586,0 8560 ps "ConnStartEndStrategy" 8561 stg "STSignalDisplayStrategy" 8562 f (Text 8563 uid 3587,0 8564 va (VaSet 8565 isHidden 1 8566 ) 8567 xt "108000,89000,110800,90000" 8568 st "T1_CS" 8569 blo "108000,89800" 8570 tm "WireNameMgr" 8571 ) 8572 ) 8573 on &124 8574 ) 8575 *280 (Wire 8576 uid 3590,0 8577 shape (OrthoPolyLine 8578 uid 3591,0 8579 va (VaSet 8580 vasetType 3 8581 ) 8582 xt "108000,91000,111000,91000" 8583 pts [ 8584 "111000,91000" 8585 "108000,91000" 8586 ] 8587 ) 8588 start &121 8589 end &115 8590 sat 32 8591 eat 2 8592 stc 0 8593 st 0 8594 sf 1 8595 si 0 8596 tg (WTG 8597 uid 3594,0 8598 ps "ConnStartEndStrategy" 8599 stg "STSignalDisplayStrategy" 8600 f (Text 8601 uid 3595,0 8602 va (VaSet 8603 isHidden 1 8604 ) 8605 xt "108000,90000,110800,91000" 8606 st "T2_CS" 8607 blo "108000,90800" 8608 tm "WireNameMgr" 8609 ) 8610 ) 8611 on &125 8612 ) 8613 *281 (Wire 8614 uid 3598,0 8615 shape (OrthoPolyLine 8616 uid 3599,0 8617 va (VaSet 8618 vasetType 3 8619 ) 8620 xt "108000,92000,111000,92000" 8621 pts [ 8622 "111000,92000" 8623 "108000,92000" 8624 ] 8625 ) 8626 start &122 8627 end &115 8628 sat 32 8629 eat 2 8630 stc 0 8631 st 0 8632 sf 1 8633 si 0 8634 tg (WTG 8635 uid 3602,0 8636 ps "ConnStartEndStrategy" 8637 stg "STSignalDisplayStrategy" 8638 f (Text 8639 uid 3603,0 8640 va (VaSet 8641 isHidden 1 8642 ) 8643 xt "108000,91000,110800,92000" 8644 st "T3_CS" 8645 blo "108000,91800" 8646 tm "WireNameMgr" 8647 ) 8648 ) 8649 on &126 8650 ) 8651 *282 (Wire 8652 uid 3682,0 8653 shape (OrthoPolyLine 8654 uid 3683,0 8655 va (VaSet 8656 vasetType 3 8657 ) 8658 xt "80750,100000,111000,100000" 8659 pts [ 8660 "80750,100000" 8661 "111000,100000" 8662 ] 8663 ) 8664 start &42 8665 end &138 8666 sat 32 8667 eat 32 8668 stc 0 8669 st 0 8670 sf 1 8671 si 0 8672 tg (WTG 8673 uid 3686,0 8674 ps "ConnStartEndStrategy" 8675 stg "STSignalDisplayStrategy" 8676 f (Text 8677 uid 3687,0 8678 va (VaSet 8679 isHidden 1 8680 ) 8681 xt "82000,99000,84400,100000" 8682 st "MOSI" 8683 blo "82000,99800" 8684 tm "WireNameMgr" 8685 ) 8686 ) 8687 on &137 8688 ) 8689 *283 (Wire 8690 uid 3778,0 8691 shape (OrthoPolyLine 8692 uid 3779,0 8693 va (VaSet 8694 vasetType 3 8695 ) 8696 xt "108000,103000,111000,103000" 8697 pts [ 8698 "111000,103000" 8699 "108000,103000" 8700 ] 8701 ) 8702 start &144 8703 end &140 8704 sat 32 8705 eat 2 8706 stc 0 8707 st 0 8708 sf 1 8709 si 0 8710 tg (WTG 8711 uid 3782,0 8712 ps "ConnStartEndStrategy" 8713 stg "STSignalDisplayStrategy" 8714 f (Text 8715 uid 3783,0 8716 va (VaSet 8717 isHidden 1 8718 ) 8719 xt "108000,102000,111000,103000" 8720 st "TRG_V" 8721 blo "108000,102800" 8722 tm "WireNameMgr" 8723 ) 8724 ) 8725 on &153 8726 ) 8727 *284 (Wire 8728 uid 3786,0 8729 shape (OrthoPolyLine 8730 uid 3787,0 8731 va (VaSet 8732 vasetType 3 8733 ) 8734 xt "108000,104000,111000,104000" 8735 pts [ 8736 "111000,104000" 8737 "108000,104000" 8738 ] 8739 ) 8740 start &145 8741 end &140 8742 sat 32 8743 eat 2 8744 stc 0 8745 st 0 8746 sf 1 8747 si 0 8748 tg (WTG 8749 uid 3790,0 8750 ps "ConnStartEndStrategy" 8751 stg "STSignalDisplayStrategy" 8752 f (Text 8753 uid 3791,0 8754 va (VaSet 8755 isHidden 1 8756 ) 8757 xt "108000,103000,113600,104000" 8758 st "RS485_C_RE" 8759 blo "108000,103800" 8760 tm "WireNameMgr" 8761 ) 8762 ) 8763 on &154 8764 ) 8765 *285 (Wire 8766 uid 3794,0 8767 shape (OrthoPolyLine 8768 uid 3795,0 8769 va (VaSet 8770 vasetType 3 8771 ) 8772 xt "108000,105000,111000,105000" 8773 pts [ 8774 "111000,105000" 8775 "108000,105000" 8776 ] 8777 ) 8778 start &146 8779 end &140 8780 sat 32 8781 eat 2 8782 stc 0 8783 st 0 8784 sf 1 8785 si 0 8786 tg (WTG 8787 uid 3798,0 8788 ps "ConnStartEndStrategy" 8789 stg "STSignalDisplayStrategy" 8790 f (Text 8791 uid 3799,0 8792 va (VaSet 8793 isHidden 1 8794 ) 8795 xt "108000,104000,113600,105000" 8796 st "RS485_C_DE" 8797 blo "108000,104800" 8798 tm "WireNameMgr" 8799 ) 8800 ) 8801 on &155 8802 ) 8803 *286 (Wire 8804 uid 3802,0 8805 shape (OrthoPolyLine 8806 uid 3803,0 8807 va (VaSet 8808 vasetType 3 8809 ) 8810 xt "108000,106000,111000,106000" 8811 pts [ 8812 "111000,106000" 8813 "108000,106000" 8814 ] 8815 ) 8816 start &147 8817 end &140 8818 sat 32 8819 eat 2 8820 stc 0 8821 st 0 8822 sf 1 8823 si 0 8824 tg (WTG 8825 uid 3806,0 8826 ps "ConnStartEndStrategy" 8827 stg "STSignalDisplayStrategy" 8828 f (Text 8829 uid 3807,0 8830 va (VaSet 8831 isHidden 1 8832 ) 8833 xt "108000,105000,113500,106000" 8834 st "RS485_E_RE" 8835 blo "108000,105800" 8836 tm "WireNameMgr" 8837 ) 8838 ) 8839 on &156 8840 ) 8841 *287 (Wire 8842 uid 3810,0 8843 shape (OrthoPolyLine 8844 uid 3811,0 8845 va (VaSet 8846 vasetType 3 8847 ) 8848 xt "108000,107000,111000,107000" 8849 pts [ 8850 "111000,107000" 8851 "108000,107000" 8852 ] 8853 ) 8854 start &148 8855 end &140 8856 sat 32 8857 eat 2 8858 stc 0 8859 st 0 8860 sf 1 8861 si 0 8862 tg (WTG 8863 uid 3814,0 8864 ps "ConnStartEndStrategy" 8865 stg "STSignalDisplayStrategy" 8866 f (Text 8867 uid 3815,0 8868 va (VaSet 8869 isHidden 1 8870 ) 8871 xt "108000,106000,113500,107000" 8872 st "RS485_E_DE" 8873 blo "108000,106800" 8874 tm "WireNameMgr" 8875 ) 8876 ) 8877 on &157 8878 ) 8879 *288 (Wire 8880 uid 3826,0 8881 shape (OrthoPolyLine 8882 uid 3827,0 8883 va (VaSet 8884 vasetType 3 8885 ) 8886 xt "108000,109000,111000,109000" 8887 pts [ 8888 "111000,109000" 8889 "108000,109000" 8890 ] 8891 ) 8892 start &150 8893 end &140 8894 sat 32 8895 eat 2 8896 stc 0 8897 st 0 8898 sf 1 8899 si 0 8900 tg (WTG 8901 uid 3830,0 8902 ps "ConnStartEndStrategy" 8903 stg "STSignalDisplayStrategy" 8904 f (Text 8905 uid 3831,0 8906 va (VaSet 8907 isHidden 1 8908 ) 8909 xt "108000,108000,110300,109000" 8910 st "SRIN" 8911 blo "108000,108800" 8912 tm "WireNameMgr" 8913 ) 8914 ) 8915 on &159 8916 ) 8917 *289 (Wire 8918 uid 3834,0 8919 shape (OrthoPolyLine 8920 uid 3835,0 8921 va (VaSet 8922 vasetType 3 8923 ) 8924 xt "108000,110000,111000,110000" 8925 pts [ 8926 "111000,110000" 8927 "108000,110000" 8928 ] 8929 ) 8930 start &151 8931 end &140 8932 sat 32 8933 eat 2 8934 stc 0 8935 st 0 8936 sf 1 8937 si 0 8938 tg (WTG 8939 uid 3838,0 8940 ps "ConnStartEndStrategy" 8941 stg "STSignalDisplayStrategy" 8942 f (Text 8943 uid 3839,0 8944 va (VaSet 8945 isHidden 1 8946 ) 8947 xt "108000,109000,110900,110000" 8948 st "EE_CS" 8949 blo "108000,109800" 8950 tm "WireNameMgr" 8951 ) 8952 ) 8953 on &160 8954 ) 8955 *290 (Wire 8956 uid 3842,0 8957 shape (OrthoPolyLine 8958 uid 3843,0 8959 va (VaSet 8960 vasetType 3 8961 lineWidth 2 8962 ) 8963 xt "108000,111000,111000,111000" 8964 pts [ 8965 "111000,111000" 8966 "108000,111000" 8967 ] 8968 ) 8969 start &152 8970 end &140 8971 sat 32 8972 eat 2 8973 sty 1 8974 stc 0 8975 st 0 8976 sf 1 8977 si 0 8978 tg (WTG 8979 uid 3846,0 8980 ps "ConnStartEndStrategy" 8981 stg "STSignalDisplayStrategy" 8982 f (Text 8983 uid 3847,0 8984 va (VaSet 8985 isHidden 1 8986 ) 8987 xt "108000,110000,109900,111000" 8988 st "LED" 8989 blo "108000,110800" 8990 tm "WireNameMgr" 8991 ) 8992 ) 8993 on &161 8994 ) 8995 *291 (Wire 8996 uid 4942,0 8997 shape (OrthoPolyLine 8998 uid 4943,0 8999 va (VaSet 9000 vasetType 3 9001 lineWidth 2 9002 ) 9003 xt "80750,120000,111000,120000" 9004 pts [ 9005 "80750,120000" 9006 "111000,120000" 9007 ] 9008 ) 9009 start &14 9010 end &166 9011 sat 32 8763 xt "39000,132000,44000,132000" 8764 pts [ 8765 "39000,132000" 8766 "44000,132000" 8767 ] 8768 ) 8769 start &201 8770 end &205 8771 sat 2 9012 8772 eat 32 9013 8773 sty 1 9014 stc 09015 8774 st 0 9016 8775 sf 1 9017 8776 si 0 9018 8777 tg (WTG 9019 uid 4948,08778 uid 7148,0 9020 8779 ps "ConnStartEndStrategy" 9021 8780 stg "STSignalDisplayStrategy" 9022 8781 f (Text 9023 uid 4949,08782 uid 7149,0 9024 8783 va (VaSet 9025 8784 isHidden 1 9026 8785 ) 9027 xt " 82750,117000,84650,118000"9028 st " D_T"9029 blo " 82750,117800"9030 tm "WireNameMgr" 9031 ) 9032 ) 9033 on & 1679034 ) 9035 *2 92(Wire9036 uid 6130,08786 xt "41000,131000,45800,132000" 8787 st "A1_T : (7:0)" 8788 blo "41000,131800" 8789 tm "WireNameMgr" 8790 ) 8791 ) 8792 on &206 8793 ) 8794 *281 (Wire 8795 uid 7477,0 9037 8796 shape (OrthoPolyLine 9038 uid 6131,08797 uid 7478,0 9039 8798 va (VaSet 9040 8799 vasetType 3 9041 8800 ) 9042 xt "19000,78000,51250,78000" 9043 pts [ 9044 "19000,78000" 9045 "51250,78000" 9046 ] 9047 ) 9048 start &193 9049 end &15 9050 sat 32 9051 eat 32 9052 st 0 9053 sf 1 9054 si 0 9055 tg (WTG 9056 uid 6136,0 9057 ps "ConnStartEndStrategy" 9058 stg "STSignalDisplayStrategy" 9059 f (Text 9060 uid 6137,0 9061 va (VaSet 9062 ) 9063 xt "21000,77000,24700,78000" 9064 st "TRG_OR" 9065 blo "21000,77800" 9066 tm "WireNameMgr" 9067 ) 9068 ) 9069 on &170 9070 ) 9071 *293 (Wire 9072 uid 6288,0 9073 shape (OrthoPolyLine 9074 uid 6289,0 9075 va (VaSet 9076 vasetType 3 9077 ) 9078 xt "1750,79000,13000,89000" 9079 pts [ 9080 "1750,89000" 9081 "9000,89000" 9082 "9000,86000" 9083 "9000,79000" 9084 "13000,79000" 9085 ] 9086 ) 9087 start &174 9088 end &191 9089 sat 32 9090 eat 32 9091 st 0 9092 sf 1 9093 si 0 9094 tg (WTG 9095 uid 6294,0 9096 ps "ConnStartEndStrategy" 9097 stg "STSignalDisplayStrategy" 9098 f (Text 9099 uid 6295,0 9100 va (VaSet 9101 ) 9102 xt "4000,88000,8600,89000" 9103 st "trigger_out" 9104 blo "4000,88800" 9105 tm "WireNameMgr" 9106 ) 9107 ) 9108 on &178 9109 ) 9110 *294 (Wire 9111 uid 6306,0 9112 shape (OrthoPolyLine 9113 uid 6307,0 9114 va (VaSet 9115 vasetType 3 9116 ) 9117 xt "-28000,89000,-22000,89000" 9118 pts [ 9119 "-28000,89000" 9120 "-22000,89000" 9121 ] 9122 ) 9123 start &168 9124 end &181 8801 xt "80750,87000,91000,87000" 8802 pts [ 8803 "80750,87000" 8804 "91000,87000" 8805 ] 8806 ) 8807 start &38 8808 end &209 9125 8809 es 0 9126 8810 sat 32 … … 9130 8814 si 0 9131 8815 tg (WTG 9132 uid 6312,08816 uid 7483,0 9133 8817 ps "ConnStartEndStrategy" 9134 8818 stg "STSignalDisplayStrategy" 9135 8819 f (Text 9136 uid 6313,09137 va (VaSet 9138 ) 9139 xt " -26000,88000,-21500,89000"9140 st " TEST_TRG"9141 blo " -26000,88800"9142 tm "WireNameMgr" 9143 ) 9144 ) 9145 on & 1699146 ) 9147 *2 95(Wire9148 uid 6328,08820 uid 7484,0 8821 va (VaSet 8822 ) 8823 xt "83000,86000,85700,87000" 8824 st "dummy" 8825 blo "83000,86800" 8826 tm "WireNameMgr" 8827 ) 8828 ) 8829 on &207 8830 ) 8831 *282 (Wire 8832 uid 8853,0 9149 8833 shape (OrthoPolyLine 9150 uid 6329,0 9151 va (VaSet 9152 vasetType 3 9153 ) 9154 xt "-17000,89000,-11750,89000" 9155 pts [ 9156 "-17000,89000" 9157 "-11750,89000" 9158 ] 9159 ) 9160 start &183 9161 end &173 9162 sat 32 9163 eat 32 9164 st 0 9165 sf 1 9166 si 0 9167 tg (WTG 9168 uid 6334,0 9169 ps "ConnStartEndStrategy" 9170 stg "STSignalDisplayStrategy" 9171 f (Text 9172 uid 6335,0 9173 va (VaSet 9174 ) 9175 xt "-18000,92000,-11700,93000" 9176 st "not_TEST_TRG" 9177 blo "-18000,92800" 9178 tm "WireNameMgr" 9179 ) 9180 ) 9181 on &179 9182 ) 9183 *296 (Wire 9184 uid 6431,0 9185 shape (OrthoPolyLine 9186 uid 6432,0 9187 va (VaSet 9188 vasetType 3 9189 ) 9190 xt "80750,121000,111000,121000" 9191 pts [ 9192 "80750,121000" 9193 "111000,121000" 9194 ] 9195 ) 9196 start &43 9197 end &149 9198 sat 32 9199 eat 32 9200 stc 0 9201 st 0 9202 sf 1 9203 si 0 9204 tg (WTG 9205 uid 6435,0 9206 ps "ConnStartEndStrategy" 9207 stg "STSignalDisplayStrategy" 9208 f (Text 9209 uid 6436,0 9210 va (VaSet 9211 isHidden 1 9212 ) 9213 xt "92000,120000,96000,121000" 9214 st "DENABLE" 9215 blo "92000,120800" 9216 tm "WireNameMgr" 9217 ) 9218 ) 9219 on &158 9220 ) 9221 *297 (Wire 9222 uid 6787,0 9223 shape (OrthoPolyLine 9224 uid 6788,0 8834 uid 8854,0 9225 8835 va (VaSet 9226 8836 vasetType 3 9227 8837 lineWidth 2 9228 8838 ) 9229 xt "93000,132000,99000,132000" 9230 pts [ 9231 "93000,132000" 9232 "99000,132000" 9233 ] 9234 ) 9235 start &213 9236 end &217 8839 xt "10000,109000,51250,132000" 8840 pts [ 8841 "51250,109000" 8842 "10000,109000" 8843 "10000,132000" 8844 "31000,132000" 8845 ] 8846 ) 8847 start &30 8848 end &201 9237 8849 sat 32 9238 8850 eat 1 … … 9242 8854 si 0 9243 8855 tg (WTG 9244 uid 6791,08856 uid 8857,0 9245 8857 ps "ConnStartEndStrategy" 9246 8858 stg "STSignalDisplayStrategy" 9247 8859 f (Text 9248 uid 6792,0 9249 va (VaSet 9250 isHidden 1 9251 ) 9252 xt "95000,131000,101800,132000" 9253 st "D_PLLLCK : (3:0)" 9254 blo "95000,131800" 9255 tm "WireNameMgr" 9256 ) 9257 ) 9258 on &214 9259 ) 9260 *298 (Wire 9261 uid 6880,0 8860 uid 8858,0 8861 va (VaSet 8862 ) 8863 xt "42000,108000,50500,109000" 8864 st "drs_channel_id : (3:0)" 8865 blo "42000,108800" 8866 tm "WireNameMgr" 8867 ) 8868 ) 8869 on &221 8870 ) 8871 *283 (Wire 8872 uid 9193,0 9262 8873 shape (OrthoPolyLine 9263 uid 6881,08874 uid 9194,0 9264 8875 va (VaSet 9265 8876 vasetType 3 9266 8877 lineWidth 2 9267 8878 ) 9268 xt "102000,132000,109000,132000" 9269 pts [ 9270 "102000,132000" 9271 "109000,132000" 9272 ] 9273 ) 9274 start &217 9275 end &215 9276 sat 2 8879 xt "93000,136000,103000,136000" 8880 pts [ 8881 "93000,136000" 8882 "103000,136000" 8883 ] 8884 ) 8885 sat 16 8886 eat 16 8887 sty 1 8888 st 0 8889 sf 1 8890 si 0 8891 tg (WTG 8892 uid 9199,0 8893 ps "ConnStartEndStrategy" 8894 stg "STSignalDisplayStrategy" 8895 f (Text 8896 uid 9200,0 8897 va (VaSet 8898 ) 8899 xt "95000,135000,99800,136000" 8900 st "A0_T : (7:0)" 8901 blo "95000,135800" 8902 tm "WireNameMgr" 8903 ) 8904 ) 8905 on &222 8906 ) 8907 *284 (Wire 8908 uid 9300,0 8909 shape (OrthoPolyLine 8910 uid 9301,0 8911 va (VaSet 8912 vasetType 3 8913 lineWidth 2 8914 ) 8915 xt "54000,140000,64000,140000" 8916 pts [ 8917 "54000,140000" 8918 "64000,140000" 8919 ] 8920 ) 8921 end &223 8922 sat 16 9277 8923 eat 32 9278 8924 sty 1 … … 9281 8927 si 0 9282 8928 tg (WTG 9283 uid 6884,08929 uid 9304,0 9284 8930 ps "ConnStartEndStrategy" 9285 8931 stg "STSignalDisplayStrategy" 9286 8932 f (Text 9287 uid 6885,08933 uid 9305,0 9288 8934 va (VaSet 9289 8935 isHidden 1 9290 8936 ) 9291 xt " 104000,131000,108900,132000"9292 st " D_T2 : (3:0)"9293 blo " 104000,131800"9294 tm "WireNameMgr" 9295 ) 9296 ) 9297 on &2 169298 ) 9299 *2 99(Wire9300 uid 7102,08937 xt "56000,139000,60800,140000" 8938 st "A0_T : (7:0)" 8939 blo "56000,139800" 8940 tm "WireNameMgr" 8941 ) 8942 ) 8943 on &222 8944 ) 8945 *285 (Wire 8946 uid 9492,0 9301 8947 shape (OrthoPolyLine 9302 uid 7103,08948 uid 9493,0 9303 8949 va (VaSet 9304 8950 vasetType 3 9305 8951 ) 9306 xt "21000,13 2000,31000,132000"9307 pts [ 9308 "21000,13 2000"9309 "31000,13 2000"9310 ] 9311 ) 9312 end &2 218952 xt "21000,135000,31000,135000" 8953 pts [ 8954 "21000,135000" 8955 "31000,135000" 8956 ] 8957 ) 8958 end &201 9313 8959 sat 16 9314 8960 eat 1 … … 9317 8963 si 0 9318 8964 tg (WTG 9319 uid 7108,08965 uid 9498,0 9320 8966 ps "ConnStartEndStrategy" 9321 8967 stg "STSignalDisplayStrategy" 9322 8968 f (Text 9323 uid 7109,09324 va (VaSet 9325 ) 9326 xt "23000,13 1000,27600,132000"9327 st " D0_SROUT"9328 blo "23000,13 1800"9329 tm "WireNameMgr" 9330 ) 9331 ) 9332 on &1 069333 ) 9334 * 300(Wire9335 uid 7110,08969 uid 9499,0 8970 va (VaSet 8971 ) 8972 xt "23000,134000,26700,135000" 8973 st "TRG_OR" 8974 blo "23000,134800" 8975 tm "WireNameMgr" 8976 ) 8977 ) 8978 on &169 8979 ) 8980 *286 (Wire 8981 uid 9502,0 9336 8982 shape (OrthoPolyLine 9337 uid 7111,08983 uid 9503,0 9338 8984 va (VaSet 9339 8985 vasetType 3 9340 8986 ) 9341 xt " 21000,133000,31000,133000"9342 pts [ 9343 " 21000,133000"9344 " 31000,133000"9345 ] 9346 ) 9347 end &221 9348 sat 169349 eat 1 8987 xt "46000,69000,51250,69000" 8988 pts [ 8989 "51250,69000" 8990 "46000,69000" 8991 ] 8992 ) 8993 start &26 8994 sat 32 8995 eat 16 9350 8996 st 0 9351 8997 sf 1 9352 8998 si 0 9353 8999 tg (WTG 9354 uid 7116,09000 uid 9506,0 9355 9001 ps "ConnStartEndStrategy" 9356 9002 stg "STSignalDisplayStrategy" 9357 9003 f (Text 9358 uid 7117,0 9359 va (VaSet 9360 ) 9361 xt "23000,132000,27600,133000" 9362 st "D1_SROUT" 9363 blo "23000,132800" 9364 tm "WireNameMgr" 9365 ) 9366 ) 9367 on &107 9368 ) 9369 *301 (Wire 9370 uid 7118,0 9371 shape (OrthoPolyLine 9372 uid 7119,0 9373 va (VaSet 9374 vasetType 3 9375 ) 9376 xt "21000,134000,31000,134000" 9377 pts [ 9378 "21000,134000" 9379 "31000,134000" 9380 ] 9381 ) 9382 end &221 9383 sat 16 9384 eat 1 9385 st 0 9386 sf 1 9387 si 0 9388 tg (WTG 9389 uid 7124,0 9390 ps "ConnStartEndStrategy" 9391 stg "STSignalDisplayStrategy" 9392 f (Text 9393 uid 7125,0 9394 va (VaSet 9395 ) 9396 xt "23000,133000,27200,134000" 9397 st "RSRLOAD" 9398 blo "23000,133800" 9399 tm "WireNameMgr" 9400 ) 9401 ) 9402 on &64 9403 ) 9404 *302 (Wire 9405 uid 7144,0 9406 shape (OrthoPolyLine 9407 uid 7145,0 9408 va (VaSet 9409 vasetType 3 9410 lineWidth 2 9411 ) 9412 xt "39000,132000,44000,132000" 9413 pts [ 9414 "39000,132000" 9415 "44000,132000" 9416 ] 9417 ) 9418 start &221 9419 end &225 9420 sat 2 9421 eat 32 9422 sty 1 9423 st 0 9424 sf 1 9425 si 0 9426 tg (WTG 9427 uid 7148,0 9428 ps "ConnStartEndStrategy" 9429 stg "STSignalDisplayStrategy" 9430 f (Text 9431 uid 7149,0 9432 va (VaSet 9433 isHidden 1 9434 ) 9435 xt "41000,131000,45800,132000" 9436 st "A1_T : (3:0)" 9437 blo "41000,131800" 9438 tm "WireNameMgr" 9439 ) 9440 ) 9441 on &226 9442 ) 9443 *303 (Wire 9444 uid 7477,0 9445 shape (OrthoPolyLine 9446 uid 7478,0 9447 va (VaSet 9448 vasetType 3 9449 ) 9450 xt "80750,87000,91000,87000" 9451 pts [ 9452 "80750,87000" 9453 "91000,87000" 9454 ] 9455 ) 9456 start &38 9457 end &229 9458 es 0 9459 sat 32 9460 eat 32 9461 st 0 9462 sf 1 9463 si 0 9464 tg (WTG 9465 uid 7483,0 9466 ps "ConnStartEndStrategy" 9467 stg "STSignalDisplayStrategy" 9468 f (Text 9469 uid 7484,0 9470 va (VaSet 9471 ) 9472 xt "83000,86000,85700,87000" 9473 st "dummy" 9474 blo "83000,86800" 9475 tm "WireNameMgr" 9476 ) 9477 ) 9478 on &227 9479 ) 9480 *304 (Wire 9481 uid 7487,0 9482 shape (OrthoPolyLine 9483 uid 7488,0 9484 va (VaSet 9485 vasetType 3 9486 ) 9487 xt "21000,135000,31000,135000" 9488 pts [ 9489 "21000,135000" 9490 "31000,135000" 9491 ] 9492 ) 9493 end &221 9494 sat 16 9495 eat 1 9496 st 0 9497 sf 1 9498 si 0 9499 tg (WTG 9500 uid 7493,0 9501 ps "ConnStartEndStrategy" 9502 stg "STSignalDisplayStrategy" 9503 f (Text 9504 uid 7494,0 9505 va (VaSet 9506 ) 9507 xt "23000,134000,25700,135000" 9508 st "dummy" 9509 blo "23000,134800" 9510 tm "WireNameMgr" 9511 ) 9512 ) 9513 on &227 9004 uid 9507,0 9005 va (VaSet 9006 ) 9007 xt "47000,68000,50100,69000" 9008 st "CLK_50" 9009 blo "47000,68800" 9010 tm "WireNameMgr" 9011 ) 9012 ) 9013 on &224 9514 9014 ) 9515 9015 ] … … 9525 9025 color "26368,26368,26368" 9526 9026 ) 9527 packageList * 305(PackageList9027 packageList *287 (PackageList 9528 9028 uid 41,0 9529 9029 stg "VerticalLayoutStrategy" 9530 9030 textVec [ 9531 * 306(Text9031 *288 (Text 9532 9032 uid 42,0 9533 9033 va (VaSet … … 9538 9038 blo "0,800" 9539 9039 ) 9540 * 307(MLText9040 *289 (MLText 9541 9041 uid 43,0 9542 9042 va (VaSet … … 9559 9059 stg "VerticalLayoutStrategy" 9560 9060 textVec [ 9561 * 308(Text9061 *290 (Text 9562 9062 uid 45,0 9563 9063 va (VaSet … … 9569 9069 blo "20000,800" 9570 9070 ) 9571 * 309(Text9071 *291 (Text 9572 9072 uid 46,0 9573 9073 va (VaSet … … 9579 9079 blo "20000,1800" 9580 9080 ) 9581 * 310(MLText9081 *292 (MLText 9582 9082 uid 47,0 9583 9083 va (VaSet … … 9589 9089 tm "BdCompilerDirectivesTextMgr" 9590 9090 ) 9591 * 311(Text9091 *293 (Text 9592 9092 uid 48,0 9593 9093 va (VaSet … … 9599 9099 blo "20000,4800" 9600 9100 ) 9601 * 312(MLText9101 *294 (MLText 9602 9102 uid 49,0 9603 9103 va (VaSet … … 9607 9107 tm "BdCompilerDirectivesTextMgr" 9608 9108 ) 9609 * 313(Text9109 *295 (Text 9610 9110 uid 50,0 9611 9111 va (VaSet … … 9617 9117 blo "20000,5800" 9618 9118 ) 9619 * 314(MLText9119 *296 (MLText 9620 9120 uid 51,0 9621 9121 va (VaSet … … 9628 9128 associable 1 9629 9129 ) 9630 windowSize "0, 0,1281,1002"9631 viewArea "- 23100,-5300,61780,62940"9632 cachedDiagramExtent " -35500,0,699000,450107"9130 windowSize "0,22,1281,1024" 9131 viewArea "-13800,92200,71080,160440" 9132 cachedDiagramExtent "0,0,699000,450107" 9633 9133 pageSetupInfo (PageSetupInfo 9634 9134 ptrCmd "" … … 9641 9141 ) 9642 9142 hasePageBreakOrigin 1 9643 pageBreakOrigin " -73000,0"9644 lastUid 8652,09143 pageBreakOrigin "0,0" 9144 lastUid 9715,0 9645 9145 defaultCommentText (CommentText 9646 9146 shape (Rectangle … … 9704 9204 stg "VerticalLayoutStrategy" 9705 9205 textVec [ 9706 * 315(Text9206 *297 (Text 9707 9207 va (VaSet 9708 9208 font "Arial,8,1" … … 9713 9213 tm "BdLibraryNameMgr" 9714 9214 ) 9715 * 316(Text9215 *298 (Text 9716 9216 va (VaSet 9717 9217 font "Arial,8,1" … … 9722 9222 tm "BlkNameMgr" 9723 9223 ) 9724 * 317(Text9224 *299 (Text 9725 9225 va (VaSet 9726 9226 font "Arial,8,1" … … 9773 9273 stg "VerticalLayoutStrategy" 9774 9274 textVec [ 9775 *3 18(Text9275 *300 (Text 9776 9276 va (VaSet 9777 9277 font "Arial,8,1" … … 9781 9281 blo "550,4300" 9782 9282 ) 9783 *3 19(Text9283 *301 (Text 9784 9284 va (VaSet 9785 9285 font "Arial,8,1" … … 9789 9289 blo "550,5300" 9790 9290 ) 9791 *3 20(Text9291 *302 (Text 9792 9292 va (VaSet 9793 9293 font "Arial,8,1" … … 9838 9338 stg "VerticalLayoutStrategy" 9839 9339 textVec [ 9840 *3 21(Text9340 *303 (Text 9841 9341 va (VaSet 9842 9342 font "Arial,8,1" … … 9847 9347 tm "BdLibraryNameMgr" 9848 9348 ) 9849 *3 22(Text9349 *304 (Text 9850 9350 va (VaSet 9851 9351 font "Arial,8,1" … … 9856 9356 tm "CptNameMgr" 9857 9357 ) 9858 *3 23(Text9358 *305 (Text 9859 9359 va (VaSet 9860 9360 font "Arial,8,1" … … 9910 9410 stg "VerticalLayoutStrategy" 9911 9411 textVec [ 9912 *3 24(Text9412 *306 (Text 9913 9413 va (VaSet 9914 9414 font "Arial,8,1" … … 9918 9418 blo "500,4300" 9919 9419 ) 9920 *3 25(Text9420 *307 (Text 9921 9421 va (VaSet 9922 9422 font "Arial,8,1" … … 9926 9426 blo "500,5300" 9927 9427 ) 9928 *3 26(Text9428 *308 (Text 9929 9429 va (VaSet 9930 9430 font "Arial,8,1" … … 9971 9471 stg "VerticalLayoutStrategy" 9972 9472 textVec [ 9973 *3 27(Text9473 *309 (Text 9974 9474 va (VaSet 9975 9475 font "Arial,8,1" … … 9979 9479 blo "50,4300" 9980 9480 ) 9981 *3 28(Text9481 *310 (Text 9982 9482 va (VaSet 9983 9483 font "Arial,8,1" … … 9987 9487 blo "50,5300" 9988 9488 ) 9989 *3 29(Text9489 *311 (Text 9990 9490 va (VaSet 9991 9491 font "Arial,8,1" … … 10028 9528 stg "VerticalLayoutStrategy" 10029 9529 textVec [ 10030 *3 30(Text9530 *312 (Text 10031 9531 va (VaSet 10032 9532 font "Arial,8,1" … … 10037 9537 tm "HdlTextNameMgr" 10038 9538 ) 10039 *3 31(Text9539 *313 (Text 10040 9540 va (VaSet 10041 9541 font "Arial,8,1" … … 10440 9940 stg "VerticalLayoutStrategy" 10441 9941 textVec [ 10442 *3 32(Text9942 *314 (Text 10443 9943 va (VaSet 10444 9944 font "Arial,8,1" … … 10448 9948 blo "14100,20800" 10449 9949 ) 10450 *3 33(MLText9950 *315 (MLText 10451 9951 va (VaSet 10452 9952 ) … … 10500 10000 stg "VerticalLayoutStrategy" 10501 10001 textVec [ 10502 *3 34(Text10002 *316 (Text 10503 10003 va (VaSet 10504 10004 font "Arial,8,1" … … 10508 10008 blo "14100,20800" 10509 10009 ) 10510 *3 35(MLText10010 *317 (MLText 10511 10011 va (VaSet 10512 10012 ) … … 10626 10126 font "Arial,8,1" 10627 10127 ) 10628 xt "37000,43 000,44100,44000"10128 xt "37000,43800,44100,44800" 10629 10129 st "Diagram Signals:" 10630 blo "37000,4 3800"10130 blo "37000,44600" 10631 10131 ) 10632 10132 postUserLabel (Text … … 10652 10152 commonDM (CommonDM 10653 10153 ldm (LogicalDM 10654 suid 1 58,010154 suid 163,0 10655 10155 usingSuid 1 10656 emptyRow *3 36(LEmptyRow10156 emptyRow *318 (LEmptyRow 10657 10157 ) 10658 10158 uid 54,0 10659 10159 optionalChildren [ 10660 *3 37(RefLabelRowHdr10661 ) 10662 *3 38(TitleRowHdr10663 ) 10664 *3 39(FilterRowHdr10665 ) 10666 *3 40(RefLabelColHdr10160 *319 (RefLabelRowHdr 10161 ) 10162 *320 (TitleRowHdr 10163 ) 10164 *321 (FilterRowHdr 10165 ) 10166 *322 (RefLabelColHdr 10667 10167 tm "RefLabelColHdrMgr" 10668 10168 ) 10669 *3 41(RowExpandColHdr10169 *323 (RowExpandColHdr 10670 10170 tm "RowExpandColHdrMgr" 10671 10171 ) 10672 *3 42(GroupColHdr10172 *324 (GroupColHdr 10673 10173 tm "GroupColHdrMgr" 10674 10174 ) 10675 *3 43(NameColHdr10175 *325 (NameColHdr 10676 10176 tm "BlockDiagramNameColHdrMgr" 10677 10177 ) 10678 *3 44(ModeColHdr10178 *326 (ModeColHdr 10679 10179 tm "BlockDiagramModeColHdrMgr" 10680 10180 ) 10681 *3 45(TypeColHdr10181 *327 (TypeColHdr 10682 10182 tm "BlockDiagramTypeColHdrMgr" 10683 10183 ) 10684 *3 46(BoundsColHdr10184 *328 (BoundsColHdr 10685 10185 tm "BlockDiagramBoundsColHdrMgr" 10686 10186 ) 10687 *3 47(InitColHdr10187 *329 (InitColHdr 10688 10188 tm "BlockDiagramInitColHdrMgr" 10689 10189 ) 10690 *3 48(EolColHdr10190 *330 (EolColHdr 10691 10191 tm "BlockDiagramEolColHdrMgr" 10692 10192 ) 10693 *3 49(LeafLogPort10193 *331 (LeafLogPort 10694 10194 port (LogicalPort 10695 10195 m 4 … … 10700 10200 preAdd 0 10701 10201 posAdd 0 10702 o 5 510202 o 56 10703 10203 suid 5,0 10704 10204 ) … … 10706 10206 uid 327,0 10707 10207 ) 10708 *3 50(LeafLogPort10208 *332 (LeafLogPort 10709 10209 port (LogicalPort 10710 10210 m 4 … … 10713 10213 t "std_logic_vector" 10714 10214 b "(1 downto 0)" 10715 o 5 610215 o 57 10716 10216 suid 6,0 10717 10217 ) … … 10719 10219 uid 329,0 10720 10220 ) 10721 *3 51(LeafLogPort10221 *333 (LeafLogPort 10722 10222 port (LogicalPort 10723 10223 m 4 … … 10725 10225 n "adc_data_array" 10726 10226 t "adc_data_array_type" 10727 o 5 410227 o 55 10728 10228 suid 29,0 10729 10229 ) … … 10731 10231 uid 1491,0 10732 10232 ) 10733 *352 (LeafLogPort 10233 *334 (LeafLogPort 10234 port (LogicalPort 10235 m 1 10236 decl (Decl 10237 n "RSRLOAD" 10238 t "std_logic" 10239 o 36 10240 suid 57,0 10241 i "'0'" 10242 ) 10243 ) 10244 uid 2435,0 10245 ) 10246 *335 (LeafLogPort 10734 10247 port (LogicalPort 10735 10248 m 4 10736 10249 decl (Decl 10737 n "CLK_50"10738 t "std_logic"10739 preAdd 010740 posAdd 010741 o 5110742 suid 54,010743 )10744 )10745 uid 2275,010746 )10747 *353 (LeafLogPort10748 port (LogicalPort10749 m 110750 decl (Decl10751 n "RSRLOAD"10752 t "std_logic"10753 o 3510754 suid 57,010755 i "'0'"10756 )10757 )10758 uid 2435,010759 )10760 *354 (LeafLogPort10761 port (LogicalPort10762 m 410763 decl (Decl10764 10250 n "SRCLK" 10765 10251 t "std_logic" 10766 o 5 210252 o 53 10767 10253 suid 58,0 10768 10254 i "'0'" … … 10771 10257 uid 2437,0 10772 10258 ) 10773 *3 55(LeafLogPort10259 *336 (LeafLogPort 10774 10260 port (LogicalPort 10775 10261 m 4 … … 10778 10264 t "std_logic_vector" 10779 10265 b "(3 DOWNTO 0)" 10780 o 5910266 o 60 10781 10267 suid 65,0 10782 10268 ) … … 10784 10270 uid 3037,0 10785 10271 ) 10786 *3 56(LeafLogPort10272 *337 (LeafLogPort 10787 10273 port (LogicalPort 10788 10274 m 1 … … 10790 10276 n "DAC_CS" 10791 10277 t "std_logic" 10792 o 2 110278 o 22 10793 10279 suid 66,0 10794 10280 ) … … 10796 10282 uid 3039,0 10797 10283 ) 10798 *3 57(LeafLogPort10284 *338 (LeafLogPort 10799 10285 port (LogicalPort 10800 10286 decl (Decl … … 10809 10295 uid 3276,0 10810 10296 ) 10811 *3 58(LeafLogPort10297 *339 (LeafLogPort 10812 10298 port (LogicalPort 10813 10299 decl (Decl … … 10820 10306 uid 3278,0 10821 10307 ) 10822 *3 59(LeafLogPort10308 *340 (LeafLogPort 10823 10309 port (LogicalPort 10824 10310 m 1 … … 10827 10313 t "std_logic_vector" 10828 10314 b "(3 downto 0)" 10829 o 1 610315 o 17 10830 10316 suid 71,0 10831 10317 ) … … 10833 10319 uid 3280,0 10834 10320 ) 10835 *3 60(LeafLogPort10321 *341 (LeafLogPort 10836 10322 port (LogicalPort 10837 10323 m 4 … … 10839 10325 n "CLK_25_PS" 10840 10326 t "std_logic" 10841 o 5 010327 o 51 10842 10328 suid 72,0 10843 10329 ) … … 10845 10331 uid 3282,0 10846 10332 ) 10847 *3 61(LeafLogPort10333 *342 (LeafLogPort 10848 10334 port (LogicalPort 10849 10335 m 1 … … 10853 10339 preAdd 0 10854 10340 posAdd 0 10855 o 3 010341 o 31 10856 10342 suid 73,0 10857 10343 ) … … 10859 10345 uid 3382,0 10860 10346 ) 10861 *3 62(LeafLogPort10347 *343 (LeafLogPort 10862 10348 port (LogicalPort 10863 10349 decl (Decl … … 10871 10357 uid 3384,0 10872 10358 ) 10873 *3 63(LeafLogPort10359 *344 (LeafLogPort 10874 10360 port (LogicalPort 10875 10361 decl (Decl … … 10883 10369 uid 3386,0 10884 10370 ) 10885 *3 64(LeafLogPort10371 *345 (LeafLogPort 10886 10372 port (LogicalPort 10887 10373 decl (Decl … … 10895 10381 uid 3388,0 10896 10382 ) 10897 *3 65(LeafLogPort10383 *346 (LeafLogPort 10898 10384 port (LogicalPort 10899 10385 decl (Decl … … 10907 10393 uid 3390,0 10908 10394 ) 10909 *3 66(LeafLogPort10395 *347 (LeafLogPort 10910 10396 port (LogicalPort 10911 10397 decl (Decl … … 10919 10405 uid 3392,0 10920 10406 ) 10921 *3 67(LeafLogPort10407 *348 (LeafLogPort 10922 10408 port (LogicalPort 10923 10409 m 1 … … 10925 10411 n "D0_SRCLK" 10926 10412 t "STD_LOGIC" 10927 o 1 710413 o 18 10928 10414 suid 87,0 10929 10415 ) … … 10931 10417 uid 3468,0 10932 10418 ) 10933 *3 68(LeafLogPort10419 *349 (LeafLogPort 10934 10420 port (LogicalPort 10935 10421 m 1 … … 10937 10423 n "D1_SRCLK" 10938 10424 t "STD_LOGIC" 10939 o 1 810425 o 19 10940 10426 suid 88,0 10941 10427 ) … … 10943 10429 uid 3470,0 10944 10430 ) 10945 *3 69(LeafLogPort10431 *350 (LeafLogPort 10946 10432 port (LogicalPort 10947 10433 m 1 … … 10949 10435 n "D2_SRCLK" 10950 10436 t "STD_LOGIC" 10951 o 1910437 o 20 10952 10438 suid 89,0 10953 10439 ) … … 10955 10441 uid 3472,0 10956 10442 ) 10957 *3 70(LeafLogPort10443 *351 (LeafLogPort 10958 10444 port (LogicalPort 10959 10445 m 1 … … 10961 10447 n "D3_SRCLK" 10962 10448 t "STD_LOGIC" 10963 o 2 010449 o 21 10964 10450 suid 90,0 10965 10451 ) … … 10967 10453 uid 3474,0 10968 10454 ) 10969 *3 71(LeafLogPort10455 *352 (LeafLogPort 10970 10456 port (LogicalPort 10971 10457 decl (Decl … … 10978 10464 uid 3524,0 10979 10465 ) 10980 *3 72(LeafLogPort10466 *353 (LeafLogPort 10981 10467 port (LogicalPort 10982 10468 decl (Decl … … 10989 10475 uid 3526,0 10990 10476 ) 10991 *3 73(LeafLogPort10477 *354 (LeafLogPort 10992 10478 port (LogicalPort 10993 10479 decl (Decl … … 11000 10486 uid 3528,0 11001 10487 ) 11002 *3 74(LeafLogPort10488 *355 (LeafLogPort 11003 10489 port (LogicalPort 11004 10490 decl (Decl … … 11011 10497 uid 3530,0 11012 10498 ) 11013 *3 75(LeafLogPort10499 *356 (LeafLogPort 11014 10500 port (LogicalPort 11015 10501 m 1 … … 11018 10504 t "std_logic_vector" 11019 10505 b "(3 DOWNTO 0)" 11020 o 2 410506 o 25 11021 10507 suid 95,0 11022 10508 i "(others => '0')" … … 11025 10511 uid 3532,0 11026 10512 ) 11027 *3 76(LeafLogPort10513 *357 (LeafLogPort 11028 10514 port (LogicalPort 11029 10515 m 1 … … 11031 10517 n "DWRITE" 11032 10518 t "std_logic" 11033 o 2 310519 o 24 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104,0 11084 10570 ) … … 11086 10572 uid 3652,0 11087 10573 ) 11088 *3 81(LeafLogPort10574 *362 (LeafLogPort 11089 10575 port (LogicalPort 11090 10576 m 1 … … 11092 10578 n "S_CLK" 11093 10579 t "std_logic" 11094 o 3 710580 o 38 11095 10581 suid 105,0 11096 10582 ) … … 11098 10584 uid 3654,0 11099 10585 ) 11100 *3 82(LeafLogPort10586 *363 (LeafLogPort 11101 10587 port (LogicalPort 11102 10588 m 1 … … 11105 10591 t "std_logic_vector" 11106 10592 b "(9 DOWNTO 0)" 11107 o 4 310593 o 44 11108 10594 suid 106,0 11109 10595 ) … … 11111 10597 uid 3656,0 11112 10598 ) 11113 *3 83(LeafLogPort10599 *364 (LeafLogPort 11114 10600 port (LogicalPort 11115 10601 m 2 … … 11118 10604 t "std_logic_vector" 11119 10605 b "(15 DOWNTO 0)" 11120 o 4910606 o 50 11121 10607 suid 107,0 11122 10608 ) … … 11124 10610 uid 3658,0 11125 10611 ) 11126 *3 84(LeafLogPort10612 *365 (LeafLogPort 11127 10613 port (LogicalPort 11128 10614 m 1 … … 11130 10616 n "W_RES" 11131 10617 t "std_logic" 11132 o 4 610618 o 47 11133 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11241 10727 port (LogicalPort 11242 10728 m 1 … … 11244 10730 n "RS485_C_DE" 11245 10731 t "std_logic" 11246 o 3 110732 o 32 11247 10733 suid 128,0 11248 10734 ) … … 11250 10736 uid 3890,0 11251 10737 ) 11252 *3 94(LeafLogPort10738 *375 (LeafLogPort 11253 10739 port (LogicalPort 11254 10740 m 1 … … 11256 10742 n "RS485_E_RE" 11257 10743 t "std_logic" 11258 o 3 410744 o 35 11259 10745 suid 129,0 11260 10746 ) … … 11262 10748 uid 3892,0 11263 10749 ) 11264 *3 95(LeafLogPort10750 *376 (LeafLogPort 11265 10751 port (LogicalPort 11266 10752 m 1 … … 11268 10754 n "RS485_E_DE" 11269 10755 t "std_logic" 11270 o 3 310756 o 34 11271 10757 suid 130,0 11272 10758 ) … … 11274 10760 uid 3894,0 11275 10761 ) 11276 *3 96(LeafLogPort10762 *377 (LeafLogPort 11277 10763 port (LogicalPort 11278 10764 m 1 … … 11280 10766 n "DENABLE" 11281 10767 t "std_logic" 11282 o 2 210768 o 23 11283 10769 suid 131,0 11284 10770 i "'0'" … … 11287 10773 uid 3896,0 11288 10774 ) 11289 *3 97(LeafLogPort10775 *378 (LeafLogPort 11290 10776 port (LogicalPort 11291 10777 m 1 … … 11293 10779 n "SRIN" 11294 10780 t "std_logic" 11295 o 3 610781 o 37 11296 10782 suid 132,0 11297 10783 ) … … 11299 10785 uid 3898,0 11300 10786 ) 11301 *3 98(LeafLogPort10787 *379 (LeafLogPort 11302 10788 port (LogicalPort 11303 10789 m 1 … … 11305 10791 n "EE_CS" 11306 10792 t "std_logic" 11307 o 2 710793 o 28 11308 10794 suid 133,0 11309 10795 ) … … 11311 10797 uid 3900,0 11312 10798 ) 11313 *3 99(LeafLogPort10799 *380 (LeafLogPort 11314 10800 port (LogicalPort 11315 10801 m 1 … … 11318 10804 t "std_logic_vector" 11319 10805 b "( 2 DOWNTO 0 )" 11320 o 2 810806 o 29 11321 10807 suid 134,0 11322 10808 i "(others => '1')" … … 11325 10811 uid 3902,0 11326 10812 ) 11327 * 400(LeafLogPort10813 *381 (LeafLogPort 11328 10814 port (LogicalPort 11329 10815 m 1 … … 11332 10818 t "std_logic_vector" 11333 10819 b "(7 DOWNTO 0)" 11334 o 2 510820 o 26 11335 10821 suid 141,0 11336 10822 i "(OTHERS => '0')" … … 11339 10825 uid 5322,0 11340 10826 ) 11341 * 401(LeafLogPort10827 *382 (LeafLogPort 11342 10828 port (LogicalPort 11343 10829 decl (Decl … … 11351 10837 scheme 0 11352 10838 ) 11353 * 402(LeafLogPort10839 *383 (LeafLogPort 11354 10840 port (LogicalPort 11355 10841 m 4 … … 11357 10843 n "TRG_OR" 11358 10844 t "std_logic" 11359 o 5 310845 o 54 11360 10846 suid 146,0 11361 10847 ) … … 11364 10850 scheme 0 11365 10851 ) 11366 *403 (LeafLogPort 11367 port (LogicalPort 11368 m 4 11369 decl (Decl 11370 n "trigger_out" 11371 t "STD_LOGIC" 11372 preAdd 0 11373 posAdd 0 11374 o 60 11375 suid 147,0 11376 i "'0'" 11377 ) 11378 ) 11379 uid 6286,0 11380 ) 11381 *404 (LeafLogPort 11382 port (LogicalPort 11383 m 4 11384 decl (Decl 11385 n "not_TEST_TRG" 11386 t "STD_LOGIC" 11387 o 58 11388 suid 148,0 11389 ) 11390 ) 11391 uid 6314,0 11392 scheme 0 11393 ) 11394 *405 (LeafLogPort 10852 *384 (LeafLogPort 11395 10853 port (LogicalPort 11396 10854 decl (Decl … … 11405 10863 scheme 0 11406 10864 ) 11407 * 406(LeafLogPort10865 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pos 0 11873 11373 dimension 20 11874 11374 uid 74,0 11875 11375 ) 11876 *4 75(MRCItem11877 litem &3 4211376 *457 (MRCItem 11377 litem &324 11878 11378 pos 1 11879 11379 dimension 50 11880 11380 uid 75,0 11881 11381 ) 11882 *4 76(MRCItem11883 litem &3 4311382 *458 (MRCItem 11383 litem &325 11884 11384 pos 2 11885 11385 dimension 100 11886 11386 uid 76,0 11887 11387 ) 11888 *4 77(MRCItem11889 litem &3 4411388 *459 (MRCItem 11389 litem &326 11890 11390 pos 3 11891 11391 dimension 50 11892 11392 uid 77,0 11893 11393 ) 11894 *4 78(MRCItem11895 litem &3 4511394 *460 (MRCItem 11395 litem &327 11896 11396 pos 4 11897 11397 dimension 100 11898 11398 uid 78,0 11899 11399 ) 11900 *4 79(MRCItem11901 litem &3 4611400 *461 (MRCItem 11401 litem &328 11902 11402 pos 5 11903 11403 dimension 100 11904 11404 uid 79,0 11905 11405 ) 11906 *4 80(MRCItem11907 litem &3 4711406 *462 (MRCItem 11407 litem &329 11908 11408 pos 6 11909 11409 dimension 92 11910 11410 uid 80,0 11911 11411 ) 11912 *4 81(MRCItem11913 litem &3 4811412 *463 (MRCItem 11413 litem &330 11914 11414 pos 7 11915 11415 dimension 80 … … 11931 11431 genericsCommonDM (CommonDM 11932 11432 ldm (LogicalDM 11933 emptyRow *4 82(LEmptyRow11433 emptyRow *464 (LEmptyRow 11934 11434 ) 11935 11435 uid 83,0 11936 11436 optionalChildren [ 11937 *4 83(RefLabelRowHdr11938 ) 11939 *4 84(TitleRowHdr11940 ) 11941 *4 85(FilterRowHdr11942 ) 11943 *4 86(RefLabelColHdr11437 *465 (RefLabelRowHdr 11438 ) 11439 *466 (TitleRowHdr 11440 ) 11441 *467 (FilterRowHdr 11442 ) 11443 *468 (RefLabelColHdr 11944 11444 tm "RefLabelColHdrMgr" 11945 11445 ) 11946 *4 87(RowExpandColHdr11446 *469 (RowExpandColHdr 11947 11447 tm "RowExpandColHdrMgr" 11948 11448 ) 11949 *4 88(GroupColHdr11449 *470 (GroupColHdr 11950 11450 tm "GroupColHdrMgr" 11951 11451 ) 11952 *4 89(NameColHdr11452 *471 (NameColHdr 11953 11453 tm "GenericNameColHdrMgr" 11954 11454 ) 11955 *4 90(TypeColHdr11455 *472 (TypeColHdr 11956 11456 tm "GenericTypeColHdrMgr" 11957 11457 ) 11958 *4 91(InitColHdr11458 *473 (InitColHdr 11959 11459 tm "GenericValueColHdrMgr" 11960 11460 ) 11961 *4 92(PragmaColHdr11461 *474 (PragmaColHdr 11962 11462 tm "GenericPragmaColHdrMgr" 11963 11463 ) 11964 *4 93(EolColHdr11464 *475 (EolColHdr 11965 11465 tm "GenericEolColHdrMgr" 11966 11466 ) … … 11972 11472 uid 95,0 11973 11473 optionalChildren [ 11974 *4 94(Sheet11474 *476 (Sheet 11975 11475 sheetRow (SheetRow 11976 11476 headerVa (MVa … … 11989 11489 font "Tahoma,10,0" 11990 11490 ) 11991 emptyMRCItem *4 95(MRCItem11992 litem &4 8211491 emptyMRCItem *477 (MRCItem 11492 litem &464 11993 11493 pos 0 11994 11494 dimension 20 … … 11996 11496 uid 97,0 11997 11497 optionalChildren [ 11998 *4 96(MRCItem11999 litem &4 8311498 *478 (MRCItem 11499 litem &465 12000 11500 pos 0 12001 11501 dimension 20 12002 11502 uid 98,0 12003 11503 ) 12004 *4 97(MRCItem12005 litem &4 8411504 *479 (MRCItem 11505 litem &466 12006 11506 pos 1 12007 11507 dimension 23 12008 11508 uid 99,0 12009 11509 ) 12010 *4 98(MRCItem12011 litem &4 8511510 *480 (MRCItem 11511 litem &467 12012 11512 pos 2 12013 11513 hidden 1 … … 12026 11526 uid 101,0 12027 11527 optionalChildren [ 12028 *4 99(MRCItem12029 litem &4 8611528 *481 (MRCItem 11529 litem &468 12030 11530 pos 0 12031 11531 dimension 20 12032 11532 uid 102,0 12033 11533 ) 12034 * 500(MRCItem12035 litem &4 8811534 *482 (MRCItem 11535 litem &470 12036 11536 pos 1 12037 11537 dimension 50 12038 11538 uid 103,0 12039 11539 ) 12040 * 501(MRCItem12041 litem &4 8911540 *483 (MRCItem 11541 litem &471 12042 11542 pos 2 12043 11543 dimension 100 12044 11544 uid 104,0 12045 11545 ) 12046 * 502(MRCItem12047 litem &4 9011546 *484 (MRCItem 11547 litem &472 12048 11548 pos 3 12049 11549 dimension 100 12050 11550 uid 105,0 12051 11551 ) 12052 * 503(MRCItem12053 litem &4 9111552 *485 (MRCItem 11553 litem &473 12054 11554 pos 4 12055 11555 dimension 50 12056 11556 uid 106,0 12057 11557 ) 12058 * 504(MRCItem12059 litem &4 9211558 *486 (MRCItem 11559 litem &474 12060 11560 pos 5 12061 11561 dimension 50 12062 11562 uid 107,0 12063 11563 ) 12064 * 505(MRCItem12065 litem &4 9311564 *487 (MRCItem 11565 litem &475 12066 11566 pos 6 12067 11567 dimension 80 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_@board/symbol.sb
r246 r252 21 21 commonDM (CommonDM 22 22 ldm (LogicalDM 23 suid 6 6,023 suid 67,0 24 24 usingSuid 1 25 25 emptyRow *1 (LEmptyRow … … 659 659 n "A1_T" 660 660 t "std_logic_vector" 661 b "( 3DOWNTO 0)"661 b "(7 DOWNTO 0)" 662 662 o 15 663 663 suid 66,0 664 i "(OTHERS => '0')" 664 665 ) 665 666 ) … … 1239 1240 (vvPair 1240 1241 variable "HDLDir" 1241 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hdl"1242 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 1242 1243 ) 1243 1244 (vvPair 1244 1245 variable "HDSDir" 1245 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds"1246 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 1246 1247 ) 1247 1248 (vvPair 1248 1249 variable "SideDataDesignDir" 1249 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info"1250 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.info" 1250 1251 ) 1251 1252 (vvPair 1252 1253 variable "SideDataUserDir" 1253 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user"1254 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb.user" 1254 1255 ) 1255 1256 (vvPair 1256 1257 variable "SourceDir" 1257 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds"1258 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 1258 1259 ) 1259 1260 (vvPair … … 1271 1272 (vvPair 1272 1273 variable "d" 1273 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board"1274 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board" 1274 1275 ) 1275 1276 (vvPair 1276 1277 variable "d_logical" 1277 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board"1278 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board" 1278 1279 ) 1279 1280 (vvPair 1280 1281 variable "date" 1281 value "1 6.06.2010"1282 value "14.07.2010" 1282 1283 ) 1283 1284 (vvPair … … 1291 1292 (vvPair 1292 1293 variable "dd" 1293 value "1 6"1294 value "14" 1294 1295 ) 1295 1296 (vvPair … … 1319 1320 (vvPair 1320 1321 variable "host" 1321 value " TU-CC4900F8C7D2"1322 value "E5B-LABOR6" 1322 1323 ) 1323 1324 (vvPair … … 1330 1331 ) 1331 1332 (vvPair 1333 variable "library_downstream_HdsLintPlugin" 1334 value "$HDS_PROJECT_DIR\\FACT_FAD_lib\\designcheck" 1335 ) 1336 (vvPair 1332 1337 variable "library_downstream_ISEPARInvoke" 1333 1338 value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" … … 1347 1352 (vvPair 1348 1353 variable "mm" 1349 value "0 6"1354 value "07" 1350 1355 ) 1351 1356 (vvPair … … 1355 1360 (vvPair 1356 1361 variable "month" 1357 value "Ju n"1362 value "Jul" 1358 1363 ) 1359 1364 (vvPair 1360 1365 variable "month_long" 1361 value "Ju ni"1366 value "Juli" 1362 1367 ) 1363 1368 (vvPair 1364 1369 variable "p" 1365 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb"1370 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_@board\\symbol.sb" 1366 1371 ) 1367 1372 (vvPair 1368 1373 variable "p_logical" 1369 value "C:\\FPGA_projects\\ FACT_FAD_backup\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb"1374 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_Board\\symbol.sb" 1370 1375 ) 1371 1376 (vvPair … … 1423 1428 (vvPair 1424 1429 variable "time" 1425 value "15: 30:04"1430 value "15:25:08" 1426 1431 ) 1427 1432 (vvPair … … 1500 1505 ) 1501 1506 xt "44000,29200,76000,30000" 1502 st "RSRLOAD : OUT std_logic := '0' ;" 1507 st "RSRLOAD : OUT std_logic := '0' ; 1508 " 1503 1509 ) 1504 1510 thePort (LogicalPort … … 1545 1551 ) 1546 1552 xt "44000,12400,61500,13200" 1547 st "X_50M : IN STD_LOGIC ;" 1553 st "X_50M : IN STD_LOGIC ; 1554 " 1548 1555 ) 1549 1556 thePort (LogicalPort … … 1590 1597 ) 1591 1598 xt "44000,10800,61500,11600" 1592 st "TRG : IN STD_LOGIC ;" 1599 st "TRG : IN STD_LOGIC ; 1600 " 1593 1601 ) 1594 1602 thePort (LogicalPort … … 1634 1642 ) 1635 1643 xt "44000,14000,71500,14800" 1636 st "A_CLK : OUT std_logic_vector (3 downto 0) ;" 1644 st "A_CLK : OUT std_logic_vector (3 downto 0) ; 1645 " 1637 1646 ) 1638 1647 thePort (LogicalPort … … 1680 1689 ) 1681 1690 xt "44000,25200,61500,26000" 1682 st "OE_ADC : OUT STD_LOGIC ;" 1691 st "OE_ADC : OUT STD_LOGIC ; 1692 " 1683 1693 ) 1684 1694 thePort (LogicalPort … … 1726 1736 ) 1727 1737 xt "44000,5200,71500,6000" 1728 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ;" 1738 st "A_OTR : IN std_logic_vector (3 DOWNTO 0) ; 1739 " 1729 1740 ) 1730 1741 thePort (LogicalPort … … 1770 1781 ) 1771 1782 xt "44000,2000,72000,2800" 1772 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ;" 1783 st "A0_D : IN std_logic_vector (11 DOWNTO 0) ; 1784 " 1773 1785 ) 1774 1786 thePort (LogicalPort … … 1814 1826 ) 1815 1827 xt "44000,2800,72000,3600" 1816 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ;" 1828 st "A1_D : IN std_logic_vector (11 DOWNTO 0) ; 1829 " 1817 1830 ) 1818 1831 thePort (LogicalPort … … 1858 1871 ) 1859 1872 xt "44000,3600,72000,4400" 1860 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ;" 1873 st "A2_D : IN std_logic_vector (11 DOWNTO 0) ; 1874 " 1861 1875 ) 1862 1876 thePort (LogicalPort … … 1902 1916 ) 1903 1917 xt "44000,4400,72000,5200" 1904 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ;" 1918 st "A3_D : IN std_logic_vector (11 DOWNTO 0) ; 1919 " 1905 1920 ) 1906 1921 thePort (LogicalPort … … 1947 1962 ) 1948 1963 xt "44000,14800,61500,15600" 1949 st "D0_SRCLK : OUT STD_LOGIC ;" 1964 st "D0_SRCLK : OUT STD_LOGIC ; 1965 " 1950 1966 ) 1951 1967 thePort (LogicalPort … … 1992 2008 ) 1993 2009 xt "44000,15600,61500,16400" 1994 st "D1_SRCLK : OUT STD_LOGIC ;" 2010 st "D1_SRCLK : OUT STD_LOGIC ; 2011 " 1995 2012 ) 1996 2013 thePort (LogicalPort … … 2037 2054 ) 2038 2055 xt "44000,16400,61500,17200" 2039 st "D2_SRCLK : OUT STD_LOGIC ;" 2056 st "D2_SRCLK : OUT STD_LOGIC ; 2057 " 2040 2058 ) 2041 2059 thePort (LogicalPort … … 2082 2100 ) 2083 2101 xt "44000,17200,61500,18000" 2084 st "D3_SRCLK : OUT STD_LOGIC ;" 2102 st "D3_SRCLK : OUT STD_LOGIC ; 2103 " 2085 2104 ) 2086 2105 thePort (LogicalPort … … 2126 2145 ) 2127 2146 xt "44000,6000,61500,6800" 2128 st "D0_SROUT : IN std_logic ;" 2147 st "D0_SROUT : IN std_logic ; 2148 " 2129 2149 ) 2130 2150 thePort (LogicalPort … … 2169 2189 ) 2170 2190 xt "44000,6800,61500,7600" 2171 st "D1_SROUT : IN std_logic ;" 2191 st "D1_SROUT : IN std_logic ; 2192 " 2172 2193 ) 2173 2194 thePort (LogicalPort … … 2212 2233 ) 2213 2234 xt "44000,7600,61500,8400" 2214 st "D2_SROUT : IN std_logic ;" 2235 st "D2_SROUT : IN std_logic ; 2236 " 2215 2237 ) 2216 2238 thePort (LogicalPort … … 2255 2277 ) 2256 2278 xt "44000,8400,61500,9200" 2257 st "D3_SROUT : IN std_logic ;" 2279 st "D3_SROUT : IN std_logic ; 2280 " 2258 2281 ) 2259 2282 thePort (LogicalPort … … 2309 2332 ) 2310 2333 xt "44000,20400,82000,21200" 2311 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 2334 st "D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 2335 " 2312 2336 ) 2313 2337 thePort (LogicalPort … … 2366 2390 ) 2367 2391 xt "44000,19600,76000,20400" 2368 st "DWRITE : OUT std_logic := '0' ;" 2392 st "DWRITE : OUT std_logic := '0' ; 2393 " 2369 2394 ) 2370 2395 thePort (LogicalPort … … 2412 2437 ) 2413 2438 xt "44000,18000,61500,18800" 2414 st "DAC_CS : OUT std_logic ;" 2439 st "DAC_CS : OUT std_logic ; 2440 " 2415 2441 ) 2416 2442 thePort (LogicalPort … … 2457 2483 ) 2458 2484 xt "44000,31600,61500,32400" 2459 st "T0_CS : OUT std_logic ;" 2485 st "T0_CS : OUT std_logic ; 2486 " 2460 2487 ) 2461 2488 thePort (LogicalPort … … 2502 2529 ) 2503 2530 xt "44000,32400,61500,33200" 2504 st "T1_CS : OUT std_logic ;" 2531 st "T1_CS : OUT std_logic ; 2532 " 2505 2533 ) 2506 2534 thePort (LogicalPort … … 2547 2575 ) 2548 2576 xt "44000,33200,61500,34000" 2549 st "T2_CS : OUT std_logic ;" 2577 st "T2_CS : OUT std_logic ; 2578 " 2550 2579 ) 2551 2580 thePort (LogicalPort … … 2592 2621 ) 2593 2622 xt "44000,34000,61500,34800" 2594 st "T3_CS : OUT std_logic ;" 2623 st "T3_CS : OUT std_logic ; 2624 " 2595 2625 ) 2596 2626 thePort (LogicalPort … … 2637 2667 ) 2638 2668 xt "44000,30800,61500,31600" 2639 st "S_CLK : OUT std_logic ;" 2669 st "S_CLK : OUT std_logic ; 2670 " 2640 2671 ) 2641 2672 thePort (LogicalPort … … 2682 2713 ) 2683 2714 xt "44000,35600,71500,36400" 2684 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ;" 2715 st "W_A : OUT std_logic_vector (9 DOWNTO 0) ; 2716 " 2685 2717 ) 2686 2718 thePort (LogicalPort … … 2728 2760 ) 2729 2761 xt "44000,40400,71000,41200" 2730 st "W_D : INOUT std_logic_vector (15 DOWNTO 0)" 2762 st "W_D : INOUT std_logic_vector (15 DOWNTO 0) 2763 " 2731 2764 ) 2732 2765 thePort (LogicalPort … … 2784 2817 ) 2785 2818 xt "44000,38000,76000,38800" 2786 st "W_RES : OUT std_logic := '1' ;" 2819 st "W_RES : OUT std_logic := '1' ; 2820 " 2787 2821 ) 2788 2822 thePort (LogicalPort … … 2840 2874 ) 2841 2875 xt "44000,37200,76000,38000" 2842 st "W_RD : OUT std_logic := '1' ;" 2876 st "W_RD : OUT std_logic := '1' ; 2877 " 2843 2878 ) 2844 2879 thePort (LogicalPort … … 2896 2931 ) 2897 2932 xt "44000,38800,76000,39600" 2898 st "W_WR : OUT std_logic := '1' ;" 2933 st "W_WR : OUT std_logic := '1' ; 2934 " 2899 2935 ) 2900 2936 thePort (LogicalPort … … 2941 2977 ) 2942 2978 xt "44000,11600,61500,12400" 2943 st "W_INT : IN std_logic ;" 2979 st "W_INT : IN std_logic ; 2980 " 2944 2981 ) 2945 2982 thePort (LogicalPort … … 2995 3032 ) 2996 3033 xt "44000,36400,76000,37200" 2997 st "W_CS : OUT std_logic := '1' ;" 3034 st "W_CS : OUT std_logic := '1' ; 3035 " 2998 3036 ) 2999 3037 thePort (LogicalPort … … 3051 3089 ) 3052 3090 xt "44000,24400,76000,25200" 3053 st "MOSI : OUT std_logic := '0' ;" 3091 st "MOSI : OUT std_logic := '0' ; 3092 " 3054 3093 ) 3055 3094 thePort (LogicalPort … … 3097 3136 ) 3098 3137 xt "44000,39600,61500,40400" 3099 st "MISO : INOUT std_logic ;" 3138 st "MISO : INOUT std_logic ; 3139 " 3100 3140 ) 3101 3141 thePort (LogicalPort … … 3144 3184 ) 3145 3185 xt "44000,34800,61500,35600" 3146 st "TRG_V : OUT std_logic ;" 3186 st "TRG_V : OUT std_logic ; 3187 " 3147 3188 ) 3148 3189 thePort (LogicalPort … … 3189 3230 ) 3190 3231 xt "44000,26800,61500,27600" 3191 st "RS485_C_RE : OUT std_logic ;" 3232 st "RS485_C_RE : OUT std_logic ; 3233 " 3192 3234 ) 3193 3235 thePort (LogicalPort … … 3234 3276 ) 3235 3277 xt "44000,26000,61500,26800" 3236 st "RS485_C_DE : OUT std_logic ;" 3278 st "RS485_C_DE : OUT std_logic ; 3279 " 3237 3280 ) 3238 3281 thePort (LogicalPort … … 3279 3322 ) 3280 3323 xt "44000,28400,61500,29200" 3281 st "RS485_E_RE : OUT std_logic ;" 3324 st "RS485_E_RE : OUT std_logic ; 3325 " 3282 3326 ) 3283 3327 thePort (LogicalPort … … 3324 3368 ) 3325 3369 xt "44000,27600,61500,28400" 3326 st "RS485_E_DE : OUT std_logic ;" 3370 st "RS485_E_DE : OUT std_logic ; 3371 " 3327 3372 ) 3328 3373 thePort (LogicalPort … … 3379 3424 ) 3380 3425 xt "44000,18800,76000,19600" 3381 st "DENABLE : OUT std_logic := '0' ;" 3426 st "DENABLE : OUT std_logic := '0' ; 3427 " 3382 3428 ) 3383 3429 thePort (LogicalPort … … 3425 3471 ) 3426 3472 xt "44000,30000,61500,30800" 3427 st "SRIN : OUT std_logic ;" 3473 st "SRIN : OUT std_logic ; 3474 " 3428 3475 ) 3429 3476 thePort (LogicalPort … … 3470 3517 ) 3471 3518 xt "44000,22800,61500,23600" 3472 st "EE_CS : OUT std_logic ;" 3519 st "EE_CS : OUT std_logic ; 3520 " 3473 3521 ) 3474 3522 thePort (LogicalPort … … 3525 3573 ) 3526 3574 xt "44000,21200,82000,22000" 3527 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ;" 3575 st "D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3576 " 3528 3577 ) 3529 3578 thePort (LogicalPort … … 3582 3631 ) 3583 3632 xt "44000,23600,82000,24400" 3584 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ;" 3633 st "LED : OUT std_logic_vector ( 2 DOWNTO 0 ) := (others => '1') ; 3634 " 3585 3635 ) 3586 3636 thePort (LogicalPort … … 3628 3678 ) 3629 3679 xt "44000,10000,61500,10800" 3630 st "TEST_TRG : IN std_logic ;" 3680 st "TEST_TRG : IN std_logic ; 3681 " 3631 3682 ) 3632 3683 thePort (LogicalPort … … 3671 3722 ) 3672 3723 xt "44000,9200,71500,10000" 3673 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ;" 3724 st "D_PLLLCK : IN std_logic_vector (3 DOWNTO 0) ; 3725 " 3674 3726 ) 3675 3727 thePort (LogicalPort … … 3726 3778 ) 3727 3779 xt "44000,22000,82000,22800" 3728 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ;" 3780 st "D_T2 : OUT std_logic_vector (3 DOWNTO 0) := (others => '0') ; 3781 " 3729 3782 ) 3730 3783 thePort (LogicalPort … … 3761 3814 ) 3762 3815 xt "27200,97500,32000,98500" 3763 st "A1_T : ( 3:0)"3816 st "A1_T : (7:0)" 3764 3817 ju 2 3765 3818 blo "32000,98300" 3766 3819 tm "CptPortNameMgr" 3767 3820 ) 3821 t (Text 3822 uid 3123,0 3823 va (VaSet 3824 ) 3825 xt "25100,98500,32000,99500" 3826 st "(OTHERS => '0')" 3827 ju 2 3828 blo "32000,99300" 3829 tm "InitValueDelayMgr" 3830 ) 3768 3831 ) 3769 3832 dt (MLText … … 3772 3835 font "Courier New,8,0" 3773 3836 ) 3774 xt "44000,13200,71500,14000" 3775 st "A1_T : OUT std_logic_vector (3 DOWNTO 0) ;" 3837 xt "44000,13200,82000,14000" 3838 st "A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; 3839 " 3776 3840 ) 3777 3841 thePort (LogicalPort … … 3780 3844 n "A1_T" 3781 3845 t "std_logic_vector" 3782 b "( 3DOWNTO 0)"3846 b "(7 DOWNTO 0)" 3783 3847 o 15 3784 3848 suid 66,0 3849 i "(OTHERS => '0')" 3785 3850 ) 3786 3851 ) … … 3795 3860 lineWidth 2 3796 3861 ) 3797 xt "15000,6000,33000, 99000"3862 xt "15000,6000,33000,101000" 3798 3863 ) 3799 3864 oxt "15000,6000,33000,26000" … … 3869 3934 bg "0,0,32768" 3870 3935 ) 3871 xt "36200,48000,45 700,49000"3936 xt "36200,48000,45500,49000" 3872 3937 st " 3873 3938 by %user on %dd %month %year … … 4452 4517 ) 4453 4518 ) 4454 lastUid 3 076,04519 lastUid 3292,0 4455 4520 activeModelName "Symbol:CDM" 4456 4521 ) -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd
r249 r252 152 152 uid 8277,0 153 153 ) 154 (Instance 155 name "U_0" 156 duLibraryName "moduleware" 157 duName "mux" 158 elements [ 159 ] 160 mwi 1 161 uid 8562,0 162 ) 154 163 ] 155 164 libraryRefs [ … … 359 368 (vvPair 360 369 variable "time" 361 value "1 1:42:03"370 value "14:21:30" 362 371 ) 363 372 (vvPair … … 450 459 font "Courier New,8,0" 451 460 ) 452 xt "-85000,84200,-41500,85000" 453 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" 461 xt "-85000,86600,-41500,87400" 462 st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" 463 " 454 464 ) 455 465 ) … … 469 479 ) 470 480 xt "-85000,47400,-45000,48200" 471 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 481 st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 482 " 472 483 ) 473 484 ) … … 487 498 ) 488 499 xt "-85000,61800,-52500,62600" 489 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" 500 st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) 501 " 490 502 ) 491 503 ) … … 504 516 font "Courier New,8,0" 505 517 ) 506 xt "-85000,69000,-45000,69800" 507 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" 518 xt "-85000,71400,-45000,72200" 519 st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) 520 " 508 521 ) 509 522 ) … … 522 535 font "Courier New,8,0" 523 536 ) 524 xt "-85000,69800,-52500,70600" 525 st "SIGNAL ram_data : std_logic_vector(15 downto 0)" 537 xt "-85000,72200,-52500,73000" 538 st "SIGNAL ram_data : std_logic_vector(15 downto 0) 539 " 526 540 ) 527 541 ) … … 541 555 ) 542 556 xt "-85000,39800,-45000,40600" 543 st "wiz_reset : std_logic := '1'" 557 st "wiz_reset : std_logic := '1' 558 " 544 559 ) 545 560 ) … … 559 574 ) 560 575 xt "-85000,37400,-56500,38200" 561 st "wiz_addr : std_logic_vector(9 DOWNTO 0)" 576 st "wiz_addr : std_logic_vector(9 DOWNTO 0) 577 " 562 578 ) 563 579 ) … … 577 593 ) 578 594 xt "-85000,42200,-56000,43000" 579 st "wiz_data : std_logic_vector(15 DOWNTO 0)" 595 st "wiz_data : std_logic_vector(15 DOWNTO 0) 596 " 580 597 ) 581 598 ) … … 595 612 ) 596 613 xt "-85000,38200,-45000,39000" 597 st "wiz_cs : std_logic := '1'" 614 st "wiz_cs : std_logic := '1' 615 " 598 616 ) 599 617 ) … … 613 631 ) 614 632 xt "-85000,40600,-45000,41400" 615 st "wiz_wr : std_logic := '1'" 633 st "wiz_wr : std_logic := '1' 634 " 616 635 ) 617 636 ) … … 631 650 ) 632 651 xt "-85000,39000,-45000,39800" 633 st "wiz_rd : std_logic := '1'" 652 st "wiz_rd : std_logic := '1' 653 " 634 654 ) 635 655 ) … … 648 668 ) 649 669 xt "-85000,26200,-66500,27000" 650 st "wiz_int : std_logic" 670 st "wiz_int : std_logic 671 " 651 672 ) 652 673 ) … … 2473 2494 ) 2474 2495 xt "-85000,23800,-56500,24600" 2475 st "board_id : std_logic_vector(3 downto 0)" 2496 st "board_id : std_logic_vector(3 downto 0) 2497 " 2476 2498 ) 2477 2499 ) … … 2492 2514 ) 2493 2515 xt "-85000,25400,-66500,26200" 2494 st "trigger : std_logic" 2516 st "trigger : std_logic 2517 " 2495 2518 ) 2496 2519 ) … … 3720 3743 ) 3721 3744 xt "-85000,24600,-56500,25400" 3722 st "crate_id : std_logic_vector(1 downto 0)" 3745 st "crate_id : std_logic_vector(1 downto 0) 3746 " 3723 3747 ) 3724 3748 ) … … 3940 3964 font "Courier New,8,0" 3941 3965 ) 3942 xt "-85000,77000,-52500,77800" 3943 st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" 3966 xt "-85000,79400,-52500,80200" 3967 st "SIGNAL trigger_id : std_logic_vector(47 downto 0) 3968 " 3944 3969 ) 3945 3970 ) … … 3960 3985 font "Courier New,8,0" 3961 3986 ) 3962 xt "-85000,70600,-45000,71400" 3963 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" 3987 xt "-85000,73000,-45000,73800" 3988 st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) 3989 " 3964 3990 ) 3965 3991 ) … … 4766 4792 font "Courier New,8,0" 4767 4793 ) 4768 xt "-85000,78600,-62500,79400" 4769 st "SIGNAL wiz_busy : std_logic" 4794 xt "-85000,81000,-62500,81800" 4795 st "SIGNAL wiz_busy : std_logic 4796 " 4770 4797 ) 4771 4798 ) … … 4785 4812 font "Courier New,8,0" 4786 4813 ) 4787 xt "-85000,81000,-41500,81800" 4788 st "SIGNAL wiz_write_ea : std_logic := '0'" 4814 xt "-85000,83400,-41500,84200" 4815 st "SIGNAL wiz_write_ea : std_logic := '0' 4816 " 4789 4817 ) 4790 4818 ) … … 4805 4833 font "Courier New,8,0" 4806 4834 ) 4807 xt "-85000,83400,-35500,84200" 4808 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" 4835 xt "-85000,85800,-35500,86600" 4836 st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') 4837 " 4809 4838 ) 4810 4839 ) … … 4826 4855 font "Courier New,8,0" 4827 4856 ) 4828 xt "-85000,80200,-35500,81000" 4829 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" 4857 xt "-85000,82600,-35500,83400" 4858 st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') 4859 " 4830 4860 ) 4831 4861 ) … … 4846 4876 font "Courier New,8,0" 4847 4877 ) 4848 xt "-85000,79400,-35500,80200" 4849 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" 4878 xt "-85000,81800,-35500,82600" 4879 st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') 4880 " 4850 4881 ) 4851 4882 ) … … 4865 4896 font "Courier New,8,0" 4866 4897 ) 4867 xt "-85000,81800,-41500,82600" 4868 st "SIGNAL wiz_write_end : std_logic := '0'" 4898 xt "-85000,84200,-41500,85000" 4899 st "SIGNAL wiz_write_end : std_logic := '0' 4900 " 4869 4901 ) 4870 4902 ) … … 4884 4916 font "Courier New,8,0" 4885 4917 ) 4886 xt "-85000,82600,-41500,83400" 4887 st "SIGNAL wiz_write_header : std_logic := '0'" 4918 xt "-85000,85000,-41500,85800" 4919 st "SIGNAL wiz_write_header : std_logic := '0' 4920 " 4888 4921 ) 4889 4922 ) … … 4901 4934 font "Courier New,8,0" 4902 4935 ) 4903 xt "-85000,71400,-62500,72200" 4904 st "SIGNAL ram_write_ea : std_logic" 4936 xt "-85000,73800,-62500,74600" 4937 st "SIGNAL ram_write_ea : std_logic 4938 " 4905 4939 ) 4906 4940 ) … … 4919 4953 font "Courier New,8,0" 4920 4954 ) 4921 xt "-85000,72200,-41500,73000" 4922 st "SIGNAL ram_write_ready : std_logic := '0'" 4955 xt "-85000,74600,-41500,75400" 4956 st "SIGNAL ram_write_ready : std_logic := '0' 4957 " 4923 4958 ) 4924 4959 ) … … 4938 4973 ) 4939 4974 xt "-85000,54600,-41500,55400" 4940 st "SIGNAL config_start : std_logic := '0'" 4975 st "SIGNAL config_start : std_logic := '0' 4976 " 4941 4977 ) 4942 4978 ) … … 4955 4991 ) 4956 4992 xt "-85000,52200,-62500,53000" 4957 st "SIGNAL config_ready : std_logic" 4993 st "SIGNAL config_ready : std_logic 4994 " 4958 4995 ) 4959 4996 ) … … 4971 5008 font "Courier New,8,0" 4972 5009 ) 4973 xt "-85000,73800,-61000,74600" 4974 st "SIGNAL roi_max : roi_max_type" 5010 xt "-85000,76200,-61000,77000" 5011 st "SIGNAL roi_max : roi_max_type 5012 " 4975 5013 ) 4976 5014 ) … … 4989 5027 font "Courier New,8,0" 4990 5028 ) 4991 xt "-85000,68200,-52500,69000" 4992 st "SIGNAL package_length : std_logic_vector(15 downto 0)" 5029 xt "-85000,70600,-52500,71400" 5030 st "SIGNAL package_length : std_logic_vector(15 downto 0) 5031 " 4993 5032 ) 4994 5033 ) … … 5008 5047 ) 5009 5048 xt "-85000,30200,-45000,31000" 5010 st "adc_oeb : std_logic := '1'" 5049 st "adc_oeb : std_logic := '1' 5050 " 5011 5051 ) 5012 5052 ) … … 5114 5154 font "Courier New,8,0" 5115 5155 ) 5116 xt "-85000,73000,-60000,73800" 5117 st "SIGNAL roi_array : roi_array_type" 5156 xt "-85000,75400,-60000,76200" 5157 st "SIGNAL roi_array : roi_array_type 5158 " 5118 5159 ) 5119 5160 ) … … 5548 5589 ) 5549 5590 xt "-85000,27000,-66500,27800" 5550 st "CLK_25_PS : std_logic" 5591 st "CLK_25_PS : std_logic 5592 " 5551 5593 ) 5552 5594 ) … … 5610 5652 ) 5611 5653 xt "-85000,27800,-66500,28600" 5612 st "CLK_50 : std_logic" 5654 st "CLK_50 : std_logic 5655 " 5613 5656 ) 5614 5657 ) … … 5860 5903 ) 5861 5904 xt "-85000,45000,-62500,45800" 5862 st "SIGNAL CLK_25 : std_logic" 5905 st "SIGNAL CLK_25 : std_logic 5906 " 5863 5907 ) 5864 5908 ) … … 5922 5966 ) 5923 5967 xt "-85000,18200,-66500,19000" 5924 st "CLK : std_logic" 5968 st "CLK : std_logic 5969 " 5925 5970 ) 5926 5971 ) … … 5940 5985 ) 5941 5986 xt "-85000,23000,-56500,23800" 5942 st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" 5987 st "adc_otr_array : std_logic_vector(3 DOWNTO 0) 5988 " 5943 5989 ) 5944 5990 ) … … 5957 6003 ) 5958 6004 xt "-85000,22200,-61000,23000" 5959 st "adc_data_array : adc_data_array_type" 6005 st "adc_data_array : adc_data_array_type 6006 " 5960 6007 ) 5961 6008 ) … … 6019 6066 font "Courier New,8,0" 6020 6067 ) 6021 xt "-85000,62600,-41500,63400" 6022 st "SIGNAL drs_clk_en : std_logic := '0'" 6068 xt "-85000,65000,-41500,65800" 6069 st "SIGNAL drs_clk_en : std_logic := '0' 6070 " 6023 6071 ) 6024 6072 ) … … 6036 6084 font "Courier New,8,0" 6037 6085 ) 6038 xt "-85000,65000,-56500,65800" 6039 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" 6086 xt "-85000,67400,-56500,68200" 6087 st "SIGNAL drs_s_cell_array : drs_s_cell_array_type 6088 " 6040 6089 ) 6041 6090 ) … … 6054 6103 font "Courier New,8,0" 6055 6104 ) 6056 xt "-85000,63400,-41500,64200" 6057 st "SIGNAL drs_read_s_cell : std_logic := '0'" 6105 xt "-85000,65800,-41500,66600" 6106 st "SIGNAL drs_read_s_cell : std_logic := '0' 6107 " 6058 6108 ) 6059 6109 ) … … 6074 6124 ) 6075 6125 xt "-85000,32600,-39000,33400" 6076 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 6126 st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') 6127 " 6077 6128 ) 6078 6129 ) … … 6092 6143 ) 6093 6144 xt "-85000,33400,-45000,34200" 6094 st "drs_dwrite : std_logic := '1'" 6145 st "drs_dwrite : std_logic := '1' 6146 " 6095 6147 ) 6096 6148 ) … … 6108 6160 sl 0 6109 6161 ro 90 6110 xt "- 28000,56625,-26500,57375"6162 xt "-39000,99625,-37500,100375" 6111 6163 ) 6112 6164 (Line … … 6114 6166 sl 0 6115 6167 ro 90 6116 xt "- 26500,57000,-26000,57000"6168 xt "-37500,100000,-37000,100000" 6117 6169 pts [ 6118 "- 26000,57000"6119 "- 26500,57000"6170 "-37000,100000" 6171 "-37500,100000" 6120 6172 ] 6121 6173 ) … … 6132 6184 va (VaSet 6133 6185 ) 6134 xt "- 34900,56500,-29000,57500"6186 xt "-45900,99500,-40000,100500" 6135 6187 st "drs_channel_id" 6136 6188 ju 2 6137 blo "- 29000,57300"6189 blo "-40000,100300" 6138 6190 tm "WireNameMgr" 6139 6191 ) … … 6199 6251 ) 6200 6252 xt "-85000,19000,-66500,19800" 6201 st "SROUT_in_0 : std_logic" 6253 st "SROUT_in_0 : std_logic 6254 " 6202 6255 ) 6203 6256 ) … … 6216 6269 ) 6217 6270 xt "-85000,19800,-66500,20600" 6218 st "SROUT_in_1 : std_logic" 6271 st "SROUT_in_1 : std_logic 6272 " 6219 6273 ) 6220 6274 ) … … 6233 6287 ) 6234 6288 xt "-85000,20600,-66500,21400" 6235 st "SROUT_in_2 : std_logic" 6289 st "SROUT_in_2 : std_logic 6290 " 6236 6291 ) 6237 6292 ) … … 6250 6305 ) 6251 6306 xt "-85000,21400,-66500,22200" 6252 st "SROUT_in_3 : std_logic" 6307 st "SROUT_in_3 : std_logic 6308 " 6253 6309 ) 6254 6310 ) … … 6446 6502 font "Courier New,8,0" 6447 6503 ) 6448 xt "-85000,64200,-62500,65000" 6449 st "SIGNAL drs_read_s_cell_ready : std_logic" 6504 xt "-85000,66600,-62500,67400" 6505 st "SIGNAL drs_read_s_cell_ready : std_logic 6506 " 6450 6507 ) 6451 6508 ) … … 6926 6983 ) 6927 6984 xt "-85000,28600,-45000,29400" 6928 st "RSRLOAD : std_logic := '0'" 6985 st "RSRLOAD : std_logic := '0' 6986 " 6929 6987 ) 6930 6988 ) … … 6989 7047 ) 6990 7048 xt "-85000,29400,-45000,30200" 6991 st "SRCLK : std_logic := '0'" 7049 st "SRCLK : std_logic := '0' 7050 " 6992 7051 ) 6993 7052 ) … … 7214 7273 t "std_logic_vector" 7215 7274 b "(15 DOWNTO 0)" 7216 o 1 27275 o 14 7217 7276 suid 5,0 7218 7277 ) … … 7249 7308 n "roi_array" 7250 7309 t "roi_array_type" 7251 o 1 17310 o 13 7252 7311 suid 6,0 7253 7312 ) … … 7464 7523 ) 7465 7524 ) 7525 *227 (CptPort 7526 uid 8500,0 7527 ps "OnEdgeStrategy" 7528 shape (Triangle 7529 uid 8501,0 7530 ro 90 7531 va (VaSet 7532 vasetType 1 7533 fg "0,65535,0" 7534 ) 7535 xt "92000,109625,92750,110375" 7536 ) 7537 tg (CPTG 7538 uid 8502,0 7539 ps "CptPortTextPlaceStrategy" 7540 stg "RightVerticalLayoutStrategy" 7541 f (Text 7542 uid 8503,0 7543 va (VaSet 7544 ) 7545 xt "83800,109500,91000,110500" 7546 st "drs_address : (3:0)" 7547 ju 2 7548 blo "91000,110300" 7549 ) 7550 ) 7551 thePort (LogicalPort 7552 m 1 7553 decl (Decl 7554 n "drs_address" 7555 t "std_logic_vector" 7556 b "(3 DOWNTO 0)" 7557 o 11 7558 suid 13,0 7559 ) 7560 ) 7561 ) 7562 *228 (CptPort 7563 uid 8504,0 7564 ps "OnEdgeStrategy" 7565 shape (Triangle 7566 uid 8505,0 7567 ro 90 7568 va (VaSet 7569 vasetType 1 7570 fg "0,65535,0" 7571 ) 7572 xt "92000,110625,92750,111375" 7573 ) 7574 tg (CPTG 7575 uid 8506,0 7576 ps "CptPortTextPlaceStrategy" 7577 stg "RightVerticalLayoutStrategy" 7578 f (Text 7579 uid 8507,0 7580 va (VaSet 7581 ) 7582 xt "83800,110500,91000,111500" 7583 st "drs_address_mode" 7584 ju 2 7585 blo "91000,111300" 7586 ) 7587 ) 7588 thePort (LogicalPort 7589 m 1 7590 decl (Decl 7591 n "drs_address_mode" 7592 t "std_logic" 7593 o 12 7594 suid 14,0 7595 ) 7596 ) 7597 ) 7466 7598 ] 7467 7599 shape (Rectangle … … 7481 7613 stg "VerticalLayoutStrategy" 7482 7614 textVec [ 7483 *22 7(Text7615 *229 (Text 7484 7616 uid 5075,0 7485 7617 va (VaSet … … 7491 7623 tm "BdLibraryNameMgr" 7492 7624 ) 7493 *2 28(Text7625 *230 (Text 7494 7626 uid 5076,0 7495 7627 va (VaSet … … 7501 7633 tm "CptNameMgr" 7502 7634 ) 7503 *2 29(Text7635 *231 (Text 7504 7636 uid 5077,0 7505 7637 va (VaSet … … 7547 7679 archFileType "UNKNOWN" 7548 7680 ) 7549 *23 0(Net7681 *232 (Net 7550 7682 uid 5088,0 7551 7683 decl (Decl … … 7562 7694 ) 7563 7695 xt "-85000,48200,-53000,49000" 7564 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" 7565 ) 7566 ) 7567 *231 (Net 7696 st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) 7697 " 7698 ) 7699 ) 7700 *233 (Net 7568 7701 uid 5096,0 7569 7702 decl (Decl … … 7579 7712 ) 7580 7713 xt "-85000,50600,-62500,51400" 7581 st "SIGNAL config_data_valid : std_logic" 7582 ) 7583 ) 7584 *232 (Net 7714 st "SIGNAL config_data_valid : std_logic 7715 " 7716 ) 7717 ) 7718 *234 (Net 7585 7719 uid 5104,0 7586 7720 decl (Decl … … 7596 7730 ) 7597 7731 xt "-85000,49000,-62500,49800" 7598 st "SIGNAL config_busy : std_logic" 7599 ) 7600 ) 7601 *233 (Net 7732 st "SIGNAL config_busy : std_logic 7733 " 7734 ) 7735 ) 7736 *235 (Net 7602 7737 uid 5112,0 7603 7738 decl (Decl … … 7614 7749 ) 7615 7750 xt "-85000,49800,-52500,50600" 7616 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" 7617 ) 7618 ) 7619 *234 (Net 7751 st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) 7752 " 7753 ) 7754 ) 7755 *236 (Net 7620 7756 uid 5120,0 7621 7757 decl (Decl … … 7631 7767 ) 7632 7768 xt "-85000,60200,-62500,61000" 7633 st "SIGNAL config_wr_en : std_logic" 7634 ) 7635 ) 7636 *235 (Net 7769 st "SIGNAL config_wr_en : std_logic 7770 " 7771 ) 7772 ) 7773 *237 (Net 7637 7774 uid 5128,0 7638 7775 decl (Decl … … 7648 7785 ) 7649 7786 xt "-85000,51400,-62500,52200" 7650 st "SIGNAL config_rd_en : std_logic" 7651 ) 7652 ) 7653 *236 (Net 7787 st "SIGNAL config_rd_en : std_logic 7788 " 7789 ) 7790 ) 7791 *238 (Net 7654 7792 uid 5144,0 7655 7793 decl (Decl … … 7665 7803 ) 7666 7804 xt "-85000,61000,-60000,61800" 7667 st "SIGNAL dac_array : dac_array_type" 7668 ) 7669 ) 7670 *237 (Net 7805 st "SIGNAL dac_array : dac_array_type 7806 " 7807 ) 7808 ) 7809 *239 (Net 7671 7810 uid 5194,0 7672 7811 decl (Decl … … 7682 7821 ) 7683 7822 xt "-85000,55400,-62500,56200" 7684 st "SIGNAL config_start_cm : std_logic" 7685 ) 7686 ) 7687 *238 (Net 7823 st "SIGNAL config_start_cm : std_logic 7824 " 7825 ) 7826 ) 7827 *240 (Net 7688 7828 uid 5196,0 7689 7829 decl (Decl … … 7699 7839 ) 7700 7840 xt "-85000,53000,-62500,53800" 7701 st "SIGNAL config_ready_cm : std_logic" 7702 ) 7703 ) 7704 *239 (Net 7841 st "SIGNAL config_ready_cm : std_logic 7842 " 7843 ) 7844 ) 7845 *241 (Net 7705 7846 uid 5220,0 7706 7847 decl (Decl … … 7719 7860 ) 7720 7861 xt "-85000,34200,-39000,35000" 7721 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 7722 ) 7723 ) 7724 *240 (Net 7862 st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') 7863 " 7864 ) 7865 ) 7866 *242 (Net 7725 7867 uid 5279,0 7726 7868 decl (Decl … … 7736 7878 font "Courier New,8,0" 7737 7879 ) 7738 xt "-85000,74600,-41500,75400" 7739 st "SIGNAL s_trigger : std_logic := '0'" 7740 ) 7741 ) 7742 *241 (Net 7880 xt "-85000,77000,-41500,77800" 7881 st "SIGNAL s_trigger : std_logic := '0' 7882 " 7883 ) 7884 ) 7885 *243 (Net 7743 7886 uid 5472,0 7744 7887 decl (Decl … … 7753 7896 font "Courier New,8,0" 7754 7897 ) 7755 xt "-85000,76200,-62500,77000" 7756 st "SIGNAL sensor_ready : std_logic" 7757 ) 7758 ) 7759 *242 (Net 7898 xt "-85000,78600,-62500,79400" 7899 st "SIGNAL sensor_ready : std_logic 7900 " 7901 ) 7902 ) 7903 *244 (Net 7760 7904 uid 5478,0 7761 7905 decl (Decl … … 7770 7914 font "Courier New,8,0" 7771 7915 ) 7772 xt "-85000,75400,-58500,76200" 7773 st "SIGNAL sensor_array : sensor_array_type" 7774 ) 7775 ) 7776 *243 (Net 7916 xt "-85000,77800,-58500,78600" 7917 st "SIGNAL sensor_array : sensor_array_type 7918 " 7919 ) 7920 ) 7921 *245 (Net 7777 7922 uid 5588,0 7778 7923 decl (Decl … … 7788 7933 ) 7789 7934 xt "-85000,53800,-62500,54600" 7790 st "SIGNAL config_ready_spi : std_logic" 7791 ) 7792 ) 7793 *244 (Net 7935 st "SIGNAL config_ready_spi : std_logic 7936 " 7937 ) 7938 ) 7939 *246 (Net 7794 7940 uid 5632,0 7795 7941 lang 10 … … 7807 7953 ) 7808 7954 xt "-85000,46600,-53000,47400" 7809 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" 7810 ) 7811 ) 7812 *245 (Net 7955 st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) 7956 " 7957 ) 7958 ) 7959 *247 (Net 7813 7960 uid 5640,0 7814 7961 decl (Decl … … 7824 7971 ) 7825 7972 xt "-85000,45800,-57500,46600" 7826 st "SIGNAL adc_data_array_int : adc_data_array_type" 7827 ) 7828 ) 7829 *246 (SaComponent 7973 st "SIGNAL adc_data_array_int : adc_data_array_type 7974 " 7975 ) 7976 ) 7977 *248 (SaComponent 7830 7978 uid 5678,0 7831 7979 optionalChildren [ 7832 *24 7(CptPort7980 *249 (CptPort 7833 7981 uid 5658,0 7834 7982 ps "OnEdgeStrategy" … … 7865 8013 ) 7866 8014 ) 7867 *2 48(CptPort8015 *250 (CptPort 7868 8016 uid 5662,0 7869 8017 ps "OnEdgeStrategy" … … 7902 8050 ) 7903 8051 ) 7904 *2 49(CptPort8052 *251 (CptPort 7905 8053 uid 5666,0 7906 8054 ps "OnEdgeStrategy" … … 7941 8089 ) 7942 8090 ) 7943 *25 0(CptPort8091 *252 (CptPort 7944 8092 uid 5670,0 7945 8093 ps "OnEdgeStrategy" … … 7977 8125 ) 7978 8126 ) 7979 *25 1(CptPort8127 *253 (CptPort 7980 8128 uid 5674,0 7981 8129 ps "OnEdgeStrategy" … … 8030 8178 stg "VerticalLayoutStrategy" 8031 8179 textVec [ 8032 *25 2(Text8180 *254 (Text 8033 8181 uid 5681,0 8034 8182 va (VaSet … … 8040 8188 tm "BdLibraryNameMgr" 8041 8189 ) 8042 *25 3(Text8190 *255 (Text 8043 8191 uid 5682,0 8044 8192 va (VaSet … … 8050 8198 tm "CptNameMgr" 8051 8199 ) 8052 *25 4(Text8200 *256 (Text 8053 8201 uid 5683,0 8054 8202 va (VaSet … … 8099 8247 archFileType "UNKNOWN" 8100 8248 ) 8101 *25 5(Net8249 *257 (Net 8102 8250 uid 5743,0 8103 8251 decl (Decl … … 8114 8262 ) 8115 8263 xt "-85000,56200,-41500,57000" 8116 st "SIGNAL config_start_spi : std_logic := '0'" 8117 ) 8118 ) 8119 *256 (SaComponent 8264 st "SIGNAL config_start_spi : std_logic := '0' 8265 " 8266 ) 8267 ) 8268 *258 (SaComponent 8120 8269 uid 5793,0 8121 8270 optionalChildren [ 8122 *25 7(CptPort8271 *259 (CptPort 8123 8272 uid 5753,0 8124 8273 ps "OnEdgeStrategy" … … 8155 8304 ) 8156 8305 ) 8157 *2 58(CptPort8306 *260 (CptPort 8158 8307 uid 5761,0 8159 8308 ps "OnEdgeStrategy" … … 8190 8339 ) 8191 8340 ) 8192 *2 59(CptPort8341 *261 (CptPort 8193 8342 uid 5765,0 8194 8343 ps "OnEdgeStrategy" … … 8226 8375 ) 8227 8376 ) 8228 *26 0(CptPort8377 *262 (CptPort 8229 8378 uid 5769,0 8230 8379 ps "OnEdgeStrategy" … … 8261 8410 ) 8262 8411 ) 8263 *26 1(CptPort8412 *263 (CptPort 8264 8413 uid 5773,0 8265 8414 ps "OnEdgeStrategy" … … 8297 8446 ) 8298 8447 ) 8299 *26 2(CptPort8448 *264 (CptPort 8300 8449 uid 5777,0 8301 8450 ps "OnEdgeStrategy" … … 8333 8482 ) 8334 8483 ) 8335 *26 3(CptPort8484 *265 (CptPort 8336 8485 uid 5781,0 8337 8486 ps "OnEdgeStrategy" … … 8368 8517 ) 8369 8518 ) 8370 *26 4(CptPort8519 *266 (CptPort 8371 8520 uid 5785,0 8372 8521 ps "OnEdgeStrategy" … … 8404 8553 ) 8405 8554 ) 8406 *26 5(CptPort8555 *267 (CptPort 8407 8556 uid 5789,0 8408 8557 ps "OnEdgeStrategy" … … 8440 8589 ) 8441 8590 ) 8442 *26 6(CptPort8591 *268 (CptPort 8443 8592 uid 5986,0 8444 8593 ps "OnEdgeStrategy" … … 8477 8626 ) 8478 8627 ) 8479 *26 7(CptPort8628 *269 (CptPort 8480 8629 uid 6154,0 8481 8630 ps "OnEdgeStrategy" … … 8513 8662 ) 8514 8663 ) 8515 *2 68(CptPort8664 *270 (CptPort 8516 8665 uid 6317,0 8517 8666 ps "OnEdgeStrategy" … … 8567 8716 stg "VerticalLayoutStrategy" 8568 8717 textVec [ 8569 *2 69(Text8718 *271 (Text 8570 8719 uid 5796,0 8571 8720 va (VaSet … … 8577 8726 tm "BdLibraryNameMgr" 8578 8727 ) 8579 *27 0(Text8728 *272 (Text 8580 8729 uid 5797,0 8581 8730 va (VaSet … … 8587 8736 tm "CptNameMgr" 8588 8737 ) 8589 *27 1(Text8738 *273 (Text 8590 8739 uid 5798,0 8591 8740 va (VaSet … … 8633 8782 archFileType "UNKNOWN" 8634 8783 ) 8635 *27 2(Net8784 *274 (Net 8636 8785 uid 5811,0 8637 8786 decl (Decl … … 8647 8796 ) 8648 8797 xt "-85000,35800,-66500,36600" 8649 st "sclk : std_logic" 8650 ) 8651 ) 8652 *273 (Net 8798 st "sclk : std_logic 8799 " 8800 ) 8801 ) 8802 *275 (Net 8653 8803 uid 5819,0 8654 8804 decl (Decl … … 8666 8816 ) 8667 8817 xt "-85000,41400,-66500,42200" 8668 st "sio : std_logic" 8669 ) 8670 ) 8671 *274 (Net 8818 st "sio : std_logic 8819 " 8820 ) 8821 ) 8822 *276 (Net 8672 8823 uid 5827,0 8673 8824 decl (Decl … … 8683 8834 ) 8684 8835 xt "-85000,31000,-66500,31800" 8685 st "dac_cs : std_logic" 8686 ) 8687 ) 8688 *275 (Net 8836 st "dac_cs : std_logic 8837 " 8838 ) 8839 ) 8840 *277 (Net 8689 8841 uid 5835,0 8690 8842 decl (Decl … … 8701 8853 ) 8702 8854 xt "-85000,36600,-56500,37400" 8703 st "sensor_cs : std_logic_vector(3 DOWNTO 0)" 8704 ) 8705 ) 8706 *276 (PortIoOut 8855 st "sensor_cs : std_logic_vector(3 DOWNTO 0) 8856 " 8857 ) 8858 ) 8859 *278 (PortIoOut 8707 8860 uid 5843,0 8708 8861 shape (CompositeShape … … 8749 8902 ) 8750 8903 ) 8751 *27 7(PortIoInOut8904 *279 (PortIoInOut 8752 8905 uid 5849,0 8753 8906 shape (CompositeShape … … 8794 8947 ) 8795 8948 ) 8796 *2 78(PortIoOut8949 *280 (PortIoOut 8797 8950 uid 5855,0 8798 8951 shape (CompositeShape … … 8839 8992 ) 8840 8993 ) 8841 *2 79(PortIoOut8994 *281 (PortIoOut 8842 8995 uid 5861,0 8843 8996 shape (CompositeShape … … 8884 9037 ) 8885 9038 ) 8886 *28 0(Net9039 *282 (Net 8887 9040 uid 5948,0 8888 9041 decl (Decl … … 8898 9051 font "Courier New,8,0" 8899 9052 ) 8900 xt "-85000,67400,-41500,68200" 8901 st "SIGNAL new_config : std_logic := '0'" 8902 ) 8903 ) 8904 *281 (Net 9053 xt "-85000,69800,-41500,70600" 9054 st "SIGNAL new_config : std_logic := '0' 9055 " 9056 ) 9057 ) 9058 *283 (Net 8905 9059 uid 5960,0 8906 9060 decl (Decl … … 8916 9070 ) 8917 9071 xt "-85000,57000,-62500,57800" 8918 st "SIGNAL config_started : std_logic" 8919 ) 8920 ) 8921 *282 (Net 9072 st "SIGNAL config_started : std_logic 9073 " 9074 ) 9075 ) 9076 *284 (Net 8922 9077 uid 6012,0 8923 9078 decl (Decl … … 8934 9089 ) 8935 9090 xt "-85000,59400,-41500,60200" 8936 st "SIGNAL config_started_spi : std_logic := '0'" 8937 ) 8938 ) 8939 *283 (Net 9091 st "SIGNAL config_started_spi : std_logic := '0' 9092 " 9093 ) 9094 ) 9095 *285 (Net 8940 9096 uid 6014,0 8941 9097 decl (Decl … … 8952 9108 ) 8953 9109 xt "-85000,57800,-41500,58600" 8954 st "SIGNAL config_started_cu : std_logic := '0'" 8955 ) 8956 ) 8957 *284 (Net 9110 st "SIGNAL config_started_cu : std_logic := '0' 9111 " 9112 ) 9113 ) 9114 *286 (Net 8958 9115 uid 6016,0 8959 9116 decl (Decl … … 8969 9126 ) 8970 9127 xt "-85000,58600,-62500,59400" 8971 st "SIGNAL config_started_mm : std_logic" 8972 ) 8973 ) 8974 *285 (Net 9128 st "SIGNAL config_started_mm : std_logic 9129 " 9130 ) 9131 ) 9132 *287 (Net 8975 9133 uid 6158,0 8976 9134 decl (Decl … … 8987 9145 ) 8988 9146 xt "-85000,35000,-45000,35800" 8989 st "mosi : std_logic := '0'" 8990 ) 8991 ) 8992 *286 (PortIoOut 9147 st "mosi : std_logic := '0' 9148 " 9149 ) 9150 ) 9151 *288 (PortIoOut 8993 9152 uid 6166,0 8994 9153 shape (CompositeShape … … 9035 9194 ) 9036 9195 ) 9037 *28 7(Net9196 *289 (Net 9038 9197 uid 6360,0 9039 9198 decl (Decl … … 9052 9211 ) 9053 9212 xt "-85000,31800,-31500,32600" 9054 st "denable : std_logic := '0' -- default domino wave off" 9055 ) 9056 ) 9057 *288 (PortIoOut 9213 st "denable : std_logic := '0' -- default domino wave off 9214 " 9215 ) 9216 ) 9217 *290 (PortIoOut 9058 9218 uid 6368,0 9059 9219 shape (CompositeShape … … 9099 9259 ) 9100 9260 ) 9101 *2 89(Net9261 *291 (Net 9102 9262 uid 6450,0 9103 9263 decl (Decl … … 9113 9273 font "Courier New,8,0" 9114 9274 ) 9115 xt "-85000,66600,-41500,67400" 9116 st "SIGNAL dwrite_enable : std_logic := '1'" 9117 ) 9118 ) 9119 *290 (MWC 9275 xt "-85000,69000,-41500,69800" 9276 st "SIGNAL dwrite_enable : std_logic := '1' 9277 " 9278 ) 9279 ) 9280 *292 (MWC 9120 9281 uid 6529,0 9121 9282 optionalChildren [ 9122 *29 1(CptPort9283 *293 (CptPort 9123 9284 uid 6501,0 9124 9285 optionalChildren [ 9125 *29 2(Line9286 *294 (Line 9126 9287 uid 6505,0 9127 9288 layer 5 … … 9136 9297 ] 9137 9298 ) 9138 *29 3(Property9299 *295 (Property 9139 9300 uid 6506,0 9140 9301 pclass "_MW_GEOM_" … … 9181 9342 ) 9182 9343 ) 9183 *29 4(CptPort9344 *296 (CptPort 9184 9345 uid 6507,0 9185 9346 optionalChildren [ 9186 *29 5(Line9347 *297 (Line 9187 9348 uid 6511,0 9188 9349 layer 5 … … 9236 9397 ) 9237 9398 ) 9238 *29 6(CptPort9399 *298 (CptPort 9239 9400 uid 6512,0 9240 9401 optionalChildren [ 9241 *29 7(Line9402 *299 (Line 9242 9403 uid 6516,0 9243 9404 layer 5 … … 9291 9452 ) 9292 9453 ) 9293 * 298(CommentGraphic9454 *300 (CommentGraphic 9294 9455 uid 6517,0 9295 9456 optionalChildren [ 9296 * 299(Property9457 *301 (Property 9297 9458 uid 6519,0 9298 9459 pclass "_MW_GEOM_" … … 9318 9479 oxt "11000,10000,11000,10000" 9319 9480 ) 9320 *30 0(CommentGraphic9481 *302 (CommentGraphic 9321 9482 uid 6520,0 9322 9483 optionalChildren [ 9323 *30 1(Property9484 *303 (Property 9324 9485 uid 6522,0 9325 9486 pclass "_MW_GEOM_" … … 9345 9506 oxt "11000,6000,11000,6000" 9346 9507 ) 9347 *30 2(Grouping9508 *304 (Grouping 9348 9509 uid 6523,0 9349 9510 optionalChildren [ 9350 *30 3(CommentGraphic9511 *305 (CommentGraphic 9351 9512 uid 6525,0 9352 9513 shape (PolyLine2D … … 9369 9530 oxt "9000,6000,11000,10000" 9370 9531 ) 9371 *30 4(CommentGraphic9532 *306 (CommentGraphic 9372 9533 uid 6527,0 9373 9534 shape (Arc2D … … 9422 9583 stg "VerticalLayoutStrategy" 9423 9584 textVec [ 9424 *30 5(Text9585 *307 (Text 9425 9586 uid 6532,0 9426 9587 va (VaSet … … 9432 9593 blo "3500,59300" 9433 9594 ) 9434 *30 6(Text9595 *308 (Text 9435 9596 uid 6533,0 9436 9597 va (VaSet … … 9441 9602 blo "3500,60300" 9442 9603 ) 9443 *30 7(Text9604 *309 (Text 9444 9605 uid 6534,0 9445 9606 va (VaSet … … 9486 9647 ) 9487 9648 ) 9488 *3 08(Net9649 *310 (Net 9489 9650 uid 6544,0 9490 9651 decl (Decl … … 9500 9661 font "Courier New,8,0" 9501 9662 ) 9502 xt "-85000,65800,-41500,66600" 9503 st "SIGNAL dwrite : std_logic := '1'" 9504 ) 9505 ) 9506 *309 (SaComponent 9663 xt "-85000,68200,-41500,69000" 9664 st "SIGNAL dwrite : std_logic := '1' 9665 " 9666 ) 9667 ) 9668 *311 (SaComponent 9507 9669 uid 8277,0 9508 9670 optionalChildren [ 9509 *31 0(CptPort9671 *312 (CptPort 9510 9672 uid 8246,0 9511 9673 ps "OnEdgeStrategy" … … 9544 9706 ) 9545 9707 ) 9546 *31 1(CptPort9708 *313 (CptPort 9547 9709 uid 8250,0 9548 9710 ps "OnEdgeStrategy" … … 9582 9744 ) 9583 9745 ) 9584 *31 2(CptPort9746 *314 (CptPort 9585 9747 uid 8254,0 9586 9748 ps "OnEdgeStrategy" … … 9620 9782 ) 9621 9783 ) 9622 *31 3(CptPort9784 *315 (CptPort 9623 9785 uid 8258,0 9624 9786 ps "OnEdgeStrategy" … … 9658 9820 ) 9659 9821 ) 9660 *31 4(CptPort9822 *316 (CptPort 9661 9823 uid 8262,0 9662 9824 ps "OnEdgeStrategy" … … 9696 9858 ) 9697 9859 ) 9698 *31 5(CptPort9860 *317 (CptPort 9699 9861 uid 8266,0 9700 9862 ps "OnEdgeStrategy" … … 9735 9897 ) 9736 9898 ) 9737 *31 6(CptPort9899 *318 (CptPort 9738 9900 uid 8270,0 9739 9901 ps "OnEdgeStrategy" … … 9792 9954 stg "VerticalLayoutStrategy" 9793 9955 textVec [ 9794 *31 7(Text9956 *319 (Text 9795 9957 uid 8280,0 9796 9958 va (VaSet … … 9802 9964 tm "BdLibraryNameMgr" 9803 9965 ) 9804 *3 18(Text9966 *320 (Text 9805 9967 uid 8281,0 9806 9968 va (VaSet … … 9812 9974 tm "CptNameMgr" 9813 9975 ) 9814 *3 19(Text9976 *321 (Text 9815 9977 uid 8282,0 9816 9978 va (VaSet … … 9860 10022 archFileType "UNKNOWN" 9861 10023 ) 9862 *32 0(Net10024 *322 (Net 9863 10025 uid 8414,0 9864 10026 lang 2 … … 9874 10036 font "Courier New,8,0" 9875 10037 ) 9876 xt "-85000,77800,-62500,78600" 9877 st "SIGNAL wiz_ack : std_logic" 9878 ) 9879 ) 9880 *321 (Wire 10038 xt "-85000,80200,-62500,81000" 10039 st "SIGNAL wiz_ack : std_logic 10040 " 10041 ) 10042 ) 10043 *323 (Net 10044 uid 8508,0 10045 decl (Decl 10046 n "drs_address" 10047 t "std_logic_vector" 10048 b "(3 DOWNTO 0)" 10049 o 82 10050 suid 184,0 10051 i "(others => '0')" 10052 ) 10053 declText (MLText 10054 uid 8509,0 10055 va (VaSet 10056 font "Courier New,8,0" 10057 ) 10058 xt "-85000,62600,-35500,63400" 10059 st "SIGNAL drs_address : std_logic_vector(3 DOWNTO 0) := (others => '0') 10060 " 10061 ) 10062 ) 10063 *324 (Net 10064 uid 8516,0 10065 decl (Decl 10066 n "drs_address_mode" 10067 t "std_logic" 10068 o 83 10069 suid 185,0 10070 ) 10071 declText (MLText 10072 uid 8517,0 10073 va (VaSet 10074 font "Courier New,8,0" 10075 ) 10076 xt "-85000,63400,-62500,64200" 10077 st "SIGNAL drs_address_mode : std_logic 10078 " 10079 ) 10080 ) 10081 *325 (MWC 10082 uid 8562,0 10083 optionalChildren [ 10084 *326 (CptPort 10085 uid 8524,0 10086 optionalChildren [ 10087 *327 (Line 10088 uid 8528,0 10089 layer 5 10090 sl 0 10091 va (VaSet 10092 vasetType 3 10093 lineWidth 2 10094 ) 10095 xt "-29999,101000,-29000,101000" 10096 pts [ 10097 "-29000,101000" 10098 "-29999,101000" 10099 ] 10100 ) 10101 ] 10102 ps "OnEdgeStrategy" 10103 shape (Triangle 10104 uid 8525,0 10105 ro 270 10106 va (VaSet 10107 vasetType 1 10108 isHidden 1 10109 fg "0,65535,65535" 10110 ) 10111 xt "-29000,100625,-28250,101375" 10112 ) 10113 tg (CPTG 10114 uid 8526,0 10115 ps "CptPortTextPlaceStrategy" 10116 stg "RightVerticalLayoutStrategy" 10117 f (Text 10118 uid 8527,0 10119 sl 0 10120 va (VaSet 10121 isHidden 1 10122 font "arial,8,0" 10123 ) 10124 xt "-98971,288551,-97171,289551" 10125 st "din0" 10126 ju 2 10127 blo "-97171,289351" 10128 ) 10129 s (Text 10130 uid 8571,0 10131 sl 0 10132 va (VaSet 10133 font "arial,8,0" 10134 ) 10135 xt "-97171,289551,-97171,289551" 10136 ju 2 10137 blo "-97171,289551" 10138 ) 10139 ) 10140 thePort (LogicalPort 10141 decl (Decl 10142 n "din0" 10143 t "std_logic_vector" 10144 b "(3 DOWNTO 0)" 10145 o 84 10146 suid 1,0 10147 i "(others => '0')" 10148 ) 10149 ) 10150 ) 10151 *328 (CptPort 10152 uid 8529,0 10153 optionalChildren [ 10154 *329 (Line 10155 uid 8533,0 10156 layer 5 10157 sl 0 10158 va (VaSet 10159 vasetType 3 10160 lineWidth 2 10161 ) 10162 xt "-33000,100000,-31999,100000" 10163 pts [ 10164 "-33000,100000" 10165 "-31999,100000" 10166 ] 10167 ) 10168 *330 (Property 10169 uid 8534,0 10170 pclass "_MW_GEOM_" 10171 pname "fixed" 10172 ptn "String" 10173 ) 10174 ] 10175 ps "OnEdgeStrategy" 10176 shape (Triangle 10177 uid 8530,0 10178 ro 270 10179 va (VaSet 10180 vasetType 1 10181 isHidden 1 10182 fg "0,65535,65535" 10183 ) 10184 xt "-33750,99625,-33000,100375" 10185 ) 10186 tg (CPTG 10187 uid 8531,0 10188 ps "CptPortTextPlaceStrategy" 10189 stg "VerticalLayoutStrategy" 10190 f (Text 10191 uid 8532,0 10192 sl 0 10193 va (VaSet 10194 isHidden 1 10195 font "arial,8,0" 10196 ) 10197 xt "-100999,287527,-99199,288527" 10198 st "dout" 10199 blo "-100999,288327" 10200 ) 10201 s (Text 10202 uid 8572,0 10203 sl 0 10204 va (VaSet 10205 font "arial,8,0" 10206 ) 10207 xt "-100999,288527,-100999,288527" 10208 blo "-100999,288527" 10209 ) 10210 ) 10211 thePort (LogicalPort 10212 m 1 10213 decl (Decl 10214 n "dout" 10215 t "std_logic_vector" 10216 b "(3 DOWNTO 0)" 10217 o 19 10218 suid 2,0 10219 i "(others => '0')" 10220 ) 10221 ) 10222 ) 10223 *331 (CptPort 10224 uid 8535,0 10225 optionalChildren [ 10226 *332 (Line 10227 uid 8539,0 10228 layer 5 10229 sl 0 10230 va (VaSet 10231 vasetType 3 10232 lineWidth 2 10233 ) 10234 xt "-29999,99000,-29000,99000" 10235 pts [ 10236 "-29000,99000" 10237 "-29999,99000" 10238 ] 10239 ) 10240 ] 10241 ps "OnEdgeStrategy" 10242 shape (Triangle 10243 uid 8536,0 10244 ro 270 10245 va (VaSet 10246 vasetType 1 10247 isHidden 1 10248 fg "0,65535,65535" 10249 ) 10250 xt "-29000,98625,-28250,99375" 10251 ) 10252 tg (CPTG 10253 uid 8537,0 10254 ps "CptPortTextPlaceStrategy" 10255 stg "RightVerticalLayoutStrategy" 10256 f (Text 10257 uid 8538,0 10258 sl 0 10259 va (VaSet 10260 isHidden 1 10261 font "arial,8,0" 10262 ) 10263 xt "-98971,286503,-97171,287503" 10264 st "din1" 10265 ju 2 10266 blo "-97171,287303" 10267 ) 10268 s (Text 10269 uid 8573,0 10270 sl 0 10271 va (VaSet 10272 font "arial,8,0" 10273 ) 10274 xt "-97171,287503,-97171,287503" 10275 ju 2 10276 blo "-97171,287503" 10277 ) 10278 ) 10279 thePort (LogicalPort 10280 decl (Decl 10281 n "din1" 10282 t "std_logic_vector" 10283 b "(3 DOWNTO 0)" 10284 o 82 10285 suid 3,0 10286 i "(others => '0')" 10287 ) 10288 ) 10289 ) 10290 *333 (CptPort 10291 uid 8540,0 10292 optionalChildren [ 10293 *334 (Line 10294 uid 8544,0 10295 layer 5 10296 sl 0 10297 va (VaSet 10298 vasetType 3 10299 ) 10300 xt "-31000,101333,-31000,103000" 10301 pts [ 10302 "-31000,103000" 10303 "-31000,101333" 10304 ] 10305 ) 10306 ] 10307 ps "OnEdgeStrategy" 10308 shape (Triangle 10309 uid 8541,0 10310 va (VaSet 10311 vasetType 1 10312 isHidden 1 10313 fg "0,65535,65535" 10314 ) 10315 xt "-31375,103000,-30625,103750" 10316 ) 10317 tg (CPTG 10318 uid 8542,0 10319 ps "CptPortTextPlaceStrategy" 10320 stg "VerticalLayoutStrategy" 10321 f (Text 10322 uid 8543,0 10323 sl 0 10324 ro 270 10325 va (VaSet 10326 isHidden 1 10327 font "arial,8,0" 10328 ) 10329 xt "-99473,289183,-98473,290583" 10330 st "sel" 10331 blo "-98673,290583" 10332 ) 10333 s (Text 10334 uid 8574,0 10335 sl 0 10336 ro 270 10337 va (VaSet 10338 font "arial,8,0" 10339 ) 10340 xt "-98473,290583,-98473,290583" 10341 blo "-98473,290583" 10342 ) 10343 ) 10344 thePort (LogicalPort 10345 decl (Decl 10346 n "sel" 10347 t "std_logic" 10348 o 83 10349 suid 4,0 10350 ) 10351 ) 10352 ) 10353 *335 (CommentGraphic 10354 uid 8545,0 10355 shape (CustomPolygon 10356 pts [ 10357 "-30000,102000" 10358 "-32000,100666" 10359 "-32000,99334" 10360 "-30000,98000" 10361 "-30000,102000" 10362 ] 10363 uid 8546,0 10364 layer 0 10365 sl 0 10366 va (VaSet 10367 vasetType 1 10368 fg "0,65535,65535" 10369 bg "0,65535,65535" 10370 lineColor "26368,26368,26368" 10371 ) 10372 xt "-32000,98000,-30000,102000" 10373 ) 10374 oxt "7000,7000,9000,11000" 10375 ) 10376 *336 (CommentGraphic 10377 uid 8547,0 10378 optionalChildren [ 10379 *337 (Property 10380 uid 8549,0 10381 pclass "_MW_GEOM_" 10382 pname "expand" 10383 ptn "String" 10384 ) 10385 ] 10386 shape (PolyLine2D 10387 pts [ 10388 "-30000,98000" 10389 "-30000,98000" 10390 ] 10391 uid 8548,0 10392 layer 0 10393 sl 0 10394 va (VaSet 10395 vasetType 1 10396 transparent 1 10397 fg "49152,49152,49152" 10398 ) 10399 xt "-30000,98000,-30000,98000" 10400 ) 10401 oxt "9000,7000,9000,7000" 10402 ) 10403 *338 (CommentGraphic 10404 uid 8550,0 10405 optionalChildren [ 10406 *339 (Property 10407 uid 8552,0 10408 pclass "_MW_GEOM_" 10409 pname "expand" 10410 ptn "String" 10411 ) 10412 ] 10413 shape (PolyLine2D 10414 pts [ 10415 "-30000,102000" 10416 "-30000,102000" 10417 ] 10418 uid 8551,0 10419 layer 0 10420 sl 0 10421 va (VaSet 10422 vasetType 1 10423 transparent 1 10424 fg "49152,49152,49152" 10425 ) 10426 xt "-30000,102000,-30000,102000" 10427 ) 10428 oxt "9000,11000,9000,11000" 10429 ) 10430 *340 (CommentText 10431 uid 8553,0 10432 shape (Rectangle 10433 uid 8554,0 10434 sl 0 10435 va (VaSet 10436 vasetType 1 10437 transparent 1 10438 fg "65535,65535,65535" 10439 lineColor "65535,65535,65535" 10440 lineWidth -1 10441 ) 10442 xt "-32000,100000,-30000,101506" 10443 ) 10444 oxt "7000,9000,9000,10506" 10445 text (MLText 10446 uid 8555,0 10447 sl 0 10448 va (VaSet 10449 font "arial,8,0" 10450 ) 10451 xt "-31800,100200,-30600,101200" 10452 st " 10453 Lo 10454 " 10455 tm "CommentText" 10456 wrapOption 3 10457 visibleHeight 1506 10458 visibleWidth 2000 10459 ) 10460 ) 10461 *341 (CommentText 10462 uid 8556,0 10463 shape (Rectangle 10464 uid 8557,0 10465 layer 8 10466 sl 0 10467 va (VaSet 10468 vasetType 1 10469 transparent 1 10470 fg "65535,65535,65535" 10471 lineColor "65535,65535,65535" 10472 lineWidth -1 10473 ) 10474 xt "-32000,98000,-30002,99556" 10475 ) 10476 oxt "7000,7000,8998,8556" 10477 text (MLText 10478 uid 8558,0 10479 sl 0 10480 va (VaSet 10481 font "arial,8,0" 10482 ) 10483 xt "-31800,98200,-30600,99200" 10484 st " 10485 Hi 10486 " 10487 tm "CommentText" 10488 wrapOption 3 10489 visibleHeight 1556 10490 visibleWidth 1998 10491 ) 10492 ) 10493 *342 (CommentText 10494 uid 8559,0 10495 shape (Rectangle 10496 uid 8560,0 10497 layer 0 10498 sl 0 10499 va (VaSet 10500 vasetType 1 10501 transparent 1 10502 fg "65535,65535,65535" 10503 lineColor "65535,65535,65535" 10504 lineWidth -1 10505 ) 10506 xt "-32111,99517,-30111,100517" 10507 ) 10508 oxt "6889,8517,8889,9517" 10509 text (MLText 10510 uid 8561,0 10511 sl 0 10512 va (VaSet 10513 font "arial,8,0" 10514 ) 10515 xt "-31911,99717,-30211,100717" 10516 st " 10517 mux 10518 " 10519 tm "CommentText" 10520 wrapOption 3 10521 visibleHeight 1000 10522 visibleWidth 2000 10523 ) 10524 ) 10525 ] 10526 shape (Rectangle 10527 uid 8563,0 10528 va (VaSet 10529 vasetType 1 10530 transparent 1 10531 fg "65535,65535,65535" 10532 lineWidth -1 10533 ) 10534 xt "-33000,97000,-29000,103000" 10535 fos 1 10536 ) 10537 showPorts 0 10538 oxt "6000,6000,10000,12000" 10539 ttg (MlTextGroup 10540 uid 8564,0 10541 ps "CenterOffsetStrategy" 10542 stg "VerticalLayoutStrategy" 10543 textVec [ 10544 *343 (Text 10545 uid 8565,0 10546 va (VaSet 10547 isHidden 1 10548 font "arial,8,0" 10549 ) 10550 xt "-30650,102100,-25850,103100" 10551 st "moduleware" 10552 blo "-30650,102900" 10553 ) 10554 *344 (Text 10555 uid 8566,0 10556 va (VaSet 10557 font "arial,8,0" 10558 ) 10559 xt "-30650,103100,-28950,104100" 10560 st "mux" 10561 blo "-30650,103900" 10562 ) 10563 *345 (Text 10564 uid 8567,0 10565 va (VaSet 10566 font "arial,8,0" 10567 ) 10568 xt "-30650,104100,-28850,105100" 10569 st "U_0" 10570 blo "-30650,104900" 10571 tm "InstanceNameMgr" 10572 ) 10573 ] 10574 ) 10575 ga (GenericAssociation 10576 uid 8568,0 10577 ps "EdgeToEdgeStrategy" 10578 matrix (Matrix 10579 uid 8569,0 10580 text (MLText 10581 uid 8570,0 10582 va (VaSet 10583 font "arial,8,0" 10584 ) 10585 xt "-36000,79400,-36000,79400" 10586 ) 10587 header "" 10588 ) 10589 elements [ 10590 ] 10591 ) 10592 sed 1 10593 awe 1 10594 portVis (PortSigDisplay 10595 disp 1 10596 sN 0 10597 sTC 0 10598 selT 0 10599 ) 10600 prms (Property 10601 pclass "params" 10602 pname "params" 10603 ptn "String" 10604 ) 10605 de 1 10606 visOptions (mwParamsVisibilityOptions 10607 ) 10608 ) 10609 *346 (Net 10610 uid 8583,0 10611 decl (Decl 10612 n "drs_channel_internal" 10613 t "std_logic_vector" 10614 b "(3 DOWNTO 0)" 10615 o 84 10616 suid 187,0 10617 i "(others => '0')" 10618 ) 10619 declText (MLText 10620 uid 8584,0 10621 va (VaSet 10622 font "Courier New,8,0" 10623 ) 10624 xt "-85000,64200,-35500,65000" 10625 st "SIGNAL drs_channel_internal : std_logic_vector(3 DOWNTO 0) := (others => '0') 10626 " 10627 ) 10628 ) 10629 *347 (Wire 9881 10630 uid 322,0 9882 10631 shape (OrthoPolyLine … … 9894 10643 ) 9895 10644 start &26 9896 end &31 310645 end &315 9897 10646 sat 32 9898 10647 eat 32 … … 9917 10666 on &2 9918 10667 ) 9919 *3 22(Wire10668 *348 (Wire 9920 10669 uid 328,0 9921 10670 shape (OrthoPolyLine … … 9933 10682 ) 9934 10683 start &25 9935 end &31 210684 end &314 9936 10685 sat 32 9937 10686 eat 32 … … 9956 10705 on &3 9957 10706 ) 9958 *3 23(Wire10707 *349 (Wire 9959 10708 uid 334,0 9960 10709 shape (OrthoPolyLine … … 9972 10721 ) 9973 10722 start &24 9974 end &31 110723 end &313 9975 10724 sat 32 9976 10725 eat 32 … … 9995 10744 on &4 9996 10745 ) 9997 *3 24(Wire10746 *350 (Wire 9998 10747 uid 364,0 9999 10748 shape (OrthoPolyLine … … 10012 10761 ) 10013 10762 start &79 10014 end &31 510763 end &317 10015 10764 sat 32 10016 10765 eat 32 … … 10035 10784 on &5 10036 10785 ) 10037 *3 25(Wire10786 *351 (Wire 10038 10787 uid 370,0 10039 10788 shape (OrthoPolyLine … … 10052 10801 ) 10053 10802 start &78 10054 end &31 610803 end &318 10055 10804 sat 32 10056 10805 eat 32 … … 10075 10824 on &6 10076 10825 ) 10077 *3 26(Wire10826 *352 (Wire 10078 10827 uid 376,0 10079 10828 shape (OrthoPolyLine … … 10113 10862 on &7 10114 10863 ) 10115 *3 27(Wire10864 *353 (Wire 10116 10865 uid 384,0 10117 10866 shape (OrthoPolyLine … … 10153 10902 on &8 10154 10903 ) 10155 *3 28(Wire10904 *354 (Wire 10156 10905 uid 392,0 10157 10906 shape (OrthoPolyLine … … 10193 10942 on &9 10194 10943 ) 10195 *3 29(Wire10944 *355 (Wire 10196 10945 uid 400,0 10197 10946 shape (OrthoPolyLine … … 10231 10980 on &10 10232 10981 ) 10233 *3 30(Wire10982 *356 (Wire 10234 10983 uid 408,0 10235 10984 shape (OrthoPolyLine … … 10269 11018 on &11 10270 11019 ) 10271 *3 31(Wire11020 *357 (Wire 10272 11021 uid 424,0 10273 11022 shape (OrthoPolyLine … … 10307 11056 on &12 10308 11057 ) 10309 *3 32(Wire11058 *358 (Wire 10310 11059 uid 432,0 10311 11060 shape (OrthoPolyLine … … 10345 11094 on &13 10346 11095 ) 10347 *3 33(Wire11096 *359 (Wire 10348 11097 uid 1411,0 10349 11098 shape (OrthoPolyLine … … 10384 11133 on &64 10385 11134 ) 10386 *3 34(Wire11135 *360 (Wire 10387 11136 uid 1425,0 10388 11137 optionalChildren [ 10389 *3 35(BdJunction11138 *361 (BdJunction 10390 11139 uid 4391,0 10391 11140 ps "OnConnectorStrategy" … … 10437 11186 on &65 10438 11187 ) 10439 *3 36(Wire11188 *362 (Wire 10440 11189 uid 1682,0 10441 11190 shape (OrthoPolyLine … … 10476 11225 on &100 10477 11226 ) 10478 *3 37(Wire11227 *363 (Wire 10479 11228 uid 1983,0 10480 11229 shape (OrthoPolyLine … … 10515 11264 on &108 10516 11265 ) 10517 *3 38(Wire11266 *364 (Wire 10518 11267 uid 2299,0 10519 11268 shape (OrthoPolyLine … … 10555 11304 on &109 10556 11305 ) 10557 *3 39(Wire11306 *365 (Wire 10558 11307 uid 2470,0 10559 11308 shape (OrthoPolyLine … … 10592 11341 on &132 10593 11342 ) 10594 *3 40(Wire11343 *366 (Wire 10595 11344 uid 2476,0 10596 11345 shape (OrthoPolyLine … … 10629 11378 on &133 10630 11379 ) 10631 *3 41(Wire11380 *367 (Wire 10632 11381 uid 2482,0 10633 11382 shape (OrthoPolyLine … … 10668 11417 on &134 10669 11418 ) 10670 *3 42(Wire11419 *368 (Wire 10671 11420 uid 2488,0 10672 11421 shape (OrthoPolyLine … … 10707 11456 on &135 10708 11457 ) 10709 *3 43(Wire11458 *369 (Wire 10710 11459 uid 2494,0 10711 11460 shape (OrthoPolyLine … … 10746 11495 on &136 10747 11496 ) 10748 *3 44(Wire11497 *370 (Wire 10749 11498 uid 2500,0 10750 11499 shape (OrthoPolyLine … … 10783 11532 on &137 10784 11533 ) 10785 *3 45(Wire11534 *371 (Wire 10786 11535 uid 2506,0 10787 11536 shape (OrthoPolyLine … … 10820 11569 on &138 10821 11570 ) 10822 *3 46(Wire11571 *372 (Wire 10823 11572 uid 2576,0 10824 11573 shape (OrthoPolyLine … … 10858 11607 on &139 10859 11608 ) 10860 *3 47(Wire11609 *373 (Wire 10861 11610 uid 2582,0 10862 11611 shape (OrthoPolyLine … … 10896 11645 on &140 10897 11646 ) 10898 *3 48(Wire11647 *374 (Wire 10899 11648 uid 2588,0 10900 11649 shape (OrthoPolyLine … … 10935 11684 on &141 10936 11685 ) 10937 *3 49(Wire11686 *375 (Wire 10938 11687 uid 2594,0 10939 11688 shape (OrthoPolyLine … … 10973 11722 on &142 10974 11723 ) 10975 *3 50(Wire11724 *376 (Wire 10976 11725 uid 2600,0 10977 11726 shape (OrthoPolyLine … … 11011 11760 on &143 11012 11761 ) 11013 *3 51(Wire11762 *377 (Wire 11014 11763 uid 2642,0 11015 11764 shape (OrthoPolyLine … … 11051 11800 on &144 11052 11801 ) 11053 *3 52(Wire11802 *378 (Wire 11054 11803 uid 2778,0 11055 11804 shape (OrthoPolyLine … … 11089 11838 on &145 11090 11839 ) 11091 *3 53(Wire11840 *379 (Wire 11092 11841 uid 2786,0 11093 11842 shape (OrthoPolyLine … … 11104 11853 ) 11105 11854 start &147 11106 end &25 011855 end &252 11107 11856 sat 32 11108 11857 eat 32 … … 11129 11878 on &176 11130 11879 ) 11131 *3 54(Wire11880 *380 (Wire 11132 11881 uid 2876,0 11133 11882 shape (OrthoPolyLine … … 11143 11892 ] 11144 11893 ) 11145 start &3 3511894 start &361 11146 11895 end &103 11147 11896 es 0 … … 11167 11916 on &65 11168 11917 ) 11169 *3 55(Wire11918 *381 (Wire 11170 11919 uid 3888,0 11171 11920 optionalChildren [ 11172 *3 56(BdJunction11921 *382 (BdJunction 11173 11922 uid 4230,0 11174 11923 ps "OnConnectorStrategy" … … 11182 11931 ) 11183 11932 ) 11184 *3 57(BdJunction11933 *383 (BdJunction 11185 11934 uid 4244,0 11186 11935 ps "OnConnectorStrategy" … … 11233 11982 on &164 11234 11983 ) 11235 *3 58(Wire11984 *384 (Wire 11236 11985 uid 3984,0 11237 11986 shape (OrthoPolyLine … … 11274 12023 on &162 11275 12024 ) 11276 *3 59(Wire12025 *385 (Wire 11277 12026 uid 4042,0 11278 12027 shape (OrthoPolyLine … … 11312 12061 on &175 11313 12062 ) 11314 *3 60(Wire12063 *386 (Wire 11315 12064 uid 4226,0 11316 12065 shape (OrthoPolyLine … … 11328 12077 ) 11329 12078 start &174 11330 end &3 5612079 end &382 11331 12080 sat 32 11332 12081 eat 32 … … 11352 12101 on &164 11353 12102 ) 11354 *3 61(Wire12103 *387 (Wire 11355 12104 uid 4240,0 11356 12105 shape (OrthoPolyLine … … 11367 12116 ] 11368 12117 ) 11369 start &31 411370 end &3 5712118 start &316 12119 end &383 11371 12120 sat 32 11372 12121 eat 32 … … 11391 12140 on &164 11392 12141 ) 11393 *3 62(Wire12142 *388 (Wire 11394 12143 uid 4272,0 11395 12144 shape (OrthoPolyLine … … 11405 12154 ) 11406 12155 start &178 11407 end &24 712156 end &249 11408 12157 sat 32 11409 12158 eat 32 … … 11429 12178 on &177 11430 12179 ) 11431 *3 63(Wire12180 *389 (Wire 11432 12181 uid 4401,0 11433 12182 shape (OrthoPolyLine … … 11465 12214 on &179 11466 12215 ) 11467 *3 64(Wire12216 *390 (Wire 11468 12217 uid 4407,0 11469 12218 shape (OrthoPolyLine … … 11501 12250 on &180 11502 12251 ) 11503 *3 65(Wire12252 *391 (Wire 11504 12253 uid 4419,0 11505 12254 shape (OrthoPolyLine … … 11537 12286 on &181 11538 12287 ) 11539 *3 66(Wire12288 *392 (Wire 11540 12289 uid 4537,0 11541 12290 shape (OrthoPolyLine … … 11545 12294 lineWidth 2 11546 12295 ) 11547 xt "- 26000,57000,18250,57000"12296 xt "-37000,100000,-33000,100000" 11548 12297 pts [ 11549 " 18250,57000"11550 "- 26000,57000"11551 ] 11552 ) 11553 start &3 912298 "-33000,100000" 12299 "-37000,100000" 12300 ] 12301 ) 12302 start &328 11554 12303 end &184 11555 12304 sat 32 … … 11569 12318 isHidden 1 11570 12319 ) 11571 xt "- 20000,56000,-14100,57000"12320 xt "-71000,99000,-65100,100000" 11572 12321 st "drs_channel_id" 11573 blo "- 20000,56800"12322 blo "-71000,99800" 11574 12323 tm "WireNameMgr" 11575 12324 ) … … 11577 12326 on &182 11578 12327 ) 11579 *3 67(Wire12328 *393 (Wire 11580 12329 uid 4545,0 11581 12330 shape (OrthoPolyLine … … 11590 12339 ] 11591 12340 ) 11592 start &29 112341 start &293 11593 12342 end &185 11594 12343 sat 32 … … 11614 12363 on &183 11615 12364 ) 11616 *3 68(Wire12365 *394 (Wire 11617 12366 uid 4671,0 11618 12367 shape (OrthoPolyLine … … 11652 12401 on &186 11653 12402 ) 11654 *3 69(Wire12403 *395 (Wire 11655 12404 uid 4679,0 11656 12405 shape (OrthoPolyLine … … 11690 12439 on &187 11691 12440 ) 11692 *3 70(Wire12441 *396 (Wire 11693 12442 uid 4687,0 11694 12443 shape (OrthoPolyLine … … 11728 12477 on &188 11729 12478 ) 11730 *3 71(Wire12479 *397 (Wire 11731 12480 uid 4695,0 11732 12481 shape (OrthoPolyLine … … 11766 12515 on &189 11767 12516 ) 11768 *3 72(Wire12517 *398 (Wire 11769 12518 uid 4743,0 11770 12519 shape (OrthoPolyLine … … 11802 12551 on &194 11803 12552 ) 11804 *3 73(Wire12553 *399 (Wire 11805 12554 uid 4757,0 11806 12555 optionalChildren [ 11807 * 374(BdJunction12556 *400 (BdJunction 11808 12557 uid 6076,0 11809 12558 ps "OnConnectorStrategy" … … 11833 12582 ) 11834 12583 start &196 11835 end * 375(BdJunction12584 end *401 (BdJunction 11836 12585 uid 6080,0 11837 12586 ps "OnConnectorStrategy" … … 11867 12616 on &173 11868 12617 ) 11869 * 376(Wire12618 *402 (Wire 11870 12619 uid 4948,0 11871 12620 shape (OrthoPolyLine … … 11905 12654 on &210 11906 12655 ) 11907 * 377(Wire12656 *403 (Wire 11908 12657 uid 4962,0 11909 12658 shape (OrthoPolyLine … … 11943 12692 on &212 11944 12693 ) 11945 * 378(Wire12694 *404 (Wire 11946 12695 uid 5090,0 11947 12696 shape (OrthoPolyLine … … 11980 12729 ) 11981 12730 ) 11982 on &23 011983 ) 11984 * 379(Wire12731 on &232 12732 ) 12733 *405 (Wire 11985 12734 uid 5098,0 11986 12735 shape (OrthoPolyLine … … 12014 12763 ) 12015 12764 ) 12016 on &23 112017 ) 12018 * 380(Wire12765 on &233 12766 ) 12767 *406 (Wire 12019 12768 uid 5106,0 12020 12769 shape (OrthoPolyLine … … 12051 12800 ) 12052 12801 ) 12053 on &23 212054 ) 12055 * 381(Wire12802 on &234 12803 ) 12804 *407 (Wire 12056 12805 uid 5114,0 12057 12806 shape (OrthoPolyLine … … 12090 12839 ) 12091 12840 ) 12092 on &23 312093 ) 12094 * 382(Wire12841 on &235 12842 ) 12843 *408 (Wire 12095 12844 uid 5122,0 12096 12845 shape (OrthoPolyLine … … 12127 12876 ) 12128 12877 ) 12129 on &23 412130 ) 12131 * 383(Wire12878 on &236 12879 ) 12880 *409 (Wire 12132 12881 uid 5130,0 12133 12882 shape (OrthoPolyLine … … 12164 12913 ) 12165 12914 ) 12166 on &23 512167 ) 12168 * 384(Wire12915 on &237 12916 ) 12917 *410 (Wire 12169 12918 uid 5138,0 12170 12919 optionalChildren [ 12171 * 385(BdJunction12920 *411 (BdJunction 12172 12921 uid 5400,0 12173 12922 ps "OnConnectorStrategy" … … 12219 12968 on &148 12220 12969 ) 12221 * 386(Wire12970 *412 (Wire 12222 12971 uid 5146,0 12223 12972 shape (OrthoPolyLine … … 12233 12982 ) 12234 12983 start &222 12235 end &2 5812984 end &260 12236 12985 es 0 12237 12986 sat 32 … … 12253 13002 ) 12254 13003 ) 12255 on &23 612256 ) 12257 * 387(Wire13004 on &238 13005 ) 13006 *413 (Wire 12258 13007 uid 5168,0 12259 13008 shape (OrthoPolyLine … … 12268 13017 ] 12269 13018 ) 12270 start & 38513019 start &411 12271 13020 end &125 12272 13021 sat 32 … … 12291 13040 on &148 12292 13041 ) 12293 * 388(Wire13042 *414 (Wire 12294 13043 uid 5184,0 12295 13044 shape (OrthoPolyLine … … 12326 13075 ) 12327 13076 ) 12328 on &23 712329 ) 12330 * 389(Wire13077 on &239 13078 ) 13079 *415 (Wire 12331 13080 uid 5190,0 12332 13081 shape (OrthoPolyLine … … 12363 13112 ) 12364 13113 ) 12365 on &2 3812366 ) 12367 * 390(Wire13114 on &240 13115 ) 13116 *416 (Wire 12368 13117 uid 5222,0 12369 13118 shape (OrthoPolyLine … … 12403 13152 ) 12404 13153 ) 12405 on &2 3912406 ) 12407 * 391(Wire13154 on &241 13155 ) 13156 *417 (Wire 12408 13157 uid 5281,0 12409 13158 shape (OrthoPolyLine … … 12441 13190 ) 12442 13191 ) 12443 on &24 012444 ) 12445 * 392(Wire13192 on &242 13193 ) 13194 *418 (Wire 12446 13195 uid 5404,0 12447 13196 shape (OrthoPolyLine … … 12458 13207 ] 12459 13208 ) 12460 start &2 5913209 start &261 12461 13210 end &50 12462 13211 sat 32 … … 12478 13227 ) 12479 13228 ) 12480 on &24 312481 ) 12482 * 393(Wire13229 on &245 13230 ) 13231 *419 (Wire 12483 13232 uid 5474,0 12484 13233 shape (OrthoPolyLine … … 12495 13244 ] 12496 13245 ) 12497 start &26 213246 start &264 12498 13247 end &52 12499 13248 sat 32 … … 12515 13264 ) 12516 13265 ) 12517 on &24 112518 ) 12519 * 394(Wire13266 on &243 13267 ) 13268 *420 (Wire 12520 13269 uid 5480,0 12521 13270 shape (OrthoPolyLine … … 12532 13281 ] 12533 13282 ) 12534 start &26 113283 start &263 12535 13284 end &51 12536 13285 sat 32 … … 12552 13301 ) 12553 13302 ) 12554 on &24 212555 ) 12556 * 395(Wire13303 on &244 13304 ) 13305 *421 (Wire 12557 13306 uid 5582,0 12558 13307 shape (OrthoPolyLine … … 12589 13338 on &164 12590 13339 ) 12591 * 396(Wire13340 *422 (Wire 12592 13341 uid 5602,0 12593 13342 optionalChildren [ 12594 & 37512595 * 397(BdJunction13343 &401 13344 *423 (BdJunction 12596 13345 uid 6086,0 12597 13346 ps "OnConnectorStrategy" … … 12623 13372 ) 12624 13373 start &23 12625 end &31 013374 end &312 12626 13375 sat 32 12627 13376 eat 32 … … 12646 13395 on &173 12647 13396 ) 12648 * 398(Wire13397 *424 (Wire 12649 13398 uid 5626,0 12650 13399 shape (OrthoPolyLine … … 12660 13409 ) 12661 13410 start &45 12662 end &2 4813411 end &250 12663 13412 sat 32 12664 13413 eat 32 … … 12680 13429 ) 12681 13430 ) 12682 on &24 512683 ) 12684 * 399(Wire13431 on &247 13432 ) 13433 *425 (Wire 12685 13434 uid 5634,0 12686 13435 shape (OrthoPolyLine … … 12697 13446 ) 12698 13447 start &38 12699 end &2 4913448 end &251 12700 13449 sat 32 12701 13450 eat 32 … … 12718 13467 ) 12719 13468 ) 12720 on &24 412721 ) 12722 *4 00(Wire13469 on &246 13470 ) 13471 *426 (Wire 12723 13472 uid 5646,0 12724 13473 shape (OrthoPolyLine … … 12734 13483 ] 12735 13484 ) 12736 end &25 113485 end &253 12737 13486 sat 16 12738 13487 eat 32 … … 12756 13505 on &162 12757 13506 ) 12758 *4 01(Wire13507 *427 (Wire 12759 13508 uid 5745,0 12760 13509 shape (OrthoPolyLine … … 12772 13521 ) 12773 13522 start &54 12774 end &26 013523 end &262 12775 13524 sat 32 12776 13525 eat 32 … … 12792 13541 ) 12793 13542 ) 12794 on &25 512795 ) 12796 *4 02(Wire13543 on &257 13544 ) 13545 *428 (Wire 12797 13546 uid 5805,0 12798 13547 shape (OrthoPolyLine … … 12807 13556 ] 12808 13557 ) 12809 end &26 513558 end &267 12810 13559 sat 16 12811 13560 eat 32 … … 12828 13577 on &164 12829 13578 ) 12830 *4 03(Wire13579 *429 (Wire 12831 13580 uid 5813,0 12832 13581 shape (OrthoPolyLine … … 12841 13590 ] 12842 13591 ) 12843 start &25 712844 end &27 613592 start &259 13593 end &278 12845 13594 sat 32 12846 13595 eat 32 … … 12864 13613 ) 12865 13614 ) 12866 on &27 212867 ) 12868 *4 04(Wire13615 on &274 13616 ) 13617 *430 (Wire 12869 13618 uid 5821,0 12870 13619 shape (OrthoPolyLine … … 12879 13628 ] 12880 13629 ) 12881 start &2 6812882 end &27 713630 start &270 13631 end &279 12883 13632 sat 32 12884 13633 eat 32 … … 12902 13651 ) 12903 13652 ) 12904 on &27 312905 ) 12906 *4 05(Wire13653 on &275 13654 ) 13655 *431 (Wire 12907 13656 uid 5829,0 12908 13657 shape (OrthoPolyLine … … 12917 13666 ] 12918 13667 ) 12919 start &26 312920 end &2 7813668 start &265 13669 end &280 12921 13670 sat 32 12922 13671 eat 32 … … 12940 13689 ) 12941 13690 ) 12942 on &27 412943 ) 12944 *4 06(Wire13691 on &276 13692 ) 13693 *432 (Wire 12945 13694 uid 5837,0 12946 13695 shape (OrthoPolyLine … … 12956 13705 ] 12957 13706 ) 12958 start &26 412959 end &2 7913707 start &266 13708 end &281 12960 13709 sat 32 12961 13710 eat 32 … … 12980 13729 ) 12981 13730 ) 12982 on &27 512983 ) 12984 *4 07(Wire13731 on &277 13732 ) 13733 *433 (Wire 12985 13734 uid 5950,0 12986 13735 shape (OrthoPolyLine … … 13018 13767 ) 13019 13768 ) 13020 on &28 013021 ) 13022 *4 08(Wire13769 on &282 13770 ) 13771 *434 (Wire 13023 13772 uid 5962,0 13024 13773 shape (OrthoPolyLine … … 13056 13805 ) 13057 13806 ) 13058 on &28 113059 ) 13060 *4 09(Wire13807 on &283 13808 ) 13809 *435 (Wire 13061 13810 uid 6002,0 13062 13811 shape (OrthoPolyLine … … 13094 13843 ) 13095 13844 ) 13096 on &28 313097 ) 13098 *4 10(Wire13845 on &285 13846 ) 13847 *436 (Wire 13099 13848 uid 6008,0 13100 13849 shape (OrthoPolyLine … … 13111 13860 ] 13112 13861 ) 13113 start &26 613862 start &268 13114 13863 end &59 13115 13864 sat 32 … … 13132 13881 ) 13133 13882 ) 13134 on &28 213135 ) 13136 *4 11(Wire13883 on &284 13884 ) 13885 *437 (Wire 13137 13886 uid 6018,0 13138 13887 shape (OrthoPolyLine … … 13170 13919 ) 13171 13920 ) 13172 on &28 413173 ) 13174 *4 12(Wire13921 on &286 13922 ) 13923 *438 (Wire 13175 13924 uid 6064,0 13176 13925 shape (OrthoPolyLine … … 13205 13954 ) 13206 13955 ) 13207 on &23 613208 ) 13209 *4 13(Wire13956 on &238 13957 ) 13958 *439 (Wire 13210 13959 uid 6072,0 13211 13960 shape (OrthoPolyLine … … 13223 13972 ) 13224 13973 start &167 13225 end & 37413974 end &400 13226 13975 sat 32 13227 13976 eat 32 … … 13246 13995 on &173 13247 13996 ) 13248 *4 14(Wire13997 *440 (Wire 13249 13998 uid 6082,0 13250 13999 shape (OrthoPolyLine … … 13262 14011 ) 13263 14012 start &112 13264 end & 39714013 end &423 13265 14014 sat 32 13266 14015 eat 32 … … 13285 14034 on &173 13286 14035 ) 13287 *4 15(Wire14036 *441 (Wire 13288 14037 uid 6160,0 13289 14038 shape (OrthoPolyLine … … 13298 14047 ] 13299 14048 ) 13300 start &26 713301 end &28 614049 start &269 14050 end &288 13302 14051 sat 32 13303 14052 eat 32 … … 13321 14070 ) 13322 14071 ) 13323 on &28 513324 ) 13325 *4 16(Wire14072 on &287 14073 ) 14074 *442 (Wire 13326 14075 uid 6276,0 13327 14076 shape (OrthoPolyLine … … 13357 14106 on &162 13358 14107 ) 13359 *4 17(Wire14108 *443 (Wire 13360 14109 uid 6362,0 13361 14110 shape (OrthoPolyLine … … 13371 14120 ) 13372 14121 start &94 13373 end &2 8814122 end &290 13374 14123 sat 32 13375 14124 eat 32 … … 13393 14142 ) 13394 14143 ) 13395 on &28 713396 ) 13397 *4 18(Wire14144 on &289 14145 ) 14146 *444 (Wire 13398 14147 uid 6452,0 13399 14148 shape (OrthoPolyLine … … 13430 14179 ) 13431 14180 ) 13432 on &2 8913433 ) 13434 *4 19(Wire14181 on &291 14182 ) 14183 *445 (Wire 13435 14184 uid 6540,0 13436 14185 shape (OrthoPolyLine … … 13445 14194 ] 13446 14195 ) 13447 start &29 414196 start &296 13448 14197 end &41 13449 14198 sat 32 … … 13467 14216 ) 13468 14217 ) 13469 on &3 0813470 ) 13471 *4 20(Wire14218 on &310 14219 ) 14220 *446 (Wire 13472 14221 uid 6548,0 13473 14222 shape (OrthoPolyLine … … 13482 14231 ] 13483 14232 ) 13484 start &29 614233 start &298 13485 14234 sat 32 13486 14235 eat 16 … … 13503 14252 ) 13504 14253 ) 13505 on &2 8913506 ) 13507 *4 21(Wire14254 on &291 14255 ) 14256 *447 (Wire 13508 14257 uid 8416,0 13509 14258 shape (OrthoPolyLine … … 13539 14288 ) 13540 14289 ) 13541 on &320 14290 on &322 14291 ) 14292 *448 (Wire 14293 uid 8510,0 14294 shape (OrthoPolyLine 14295 uid 8511,0 14296 va (VaSet 14297 vasetType 3 14298 lineWidth 2 14299 ) 14300 xt "92750,110000,102000,110000" 14301 pts [ 14302 "92750,110000" 14303 "102000,110000" 14304 ] 14305 ) 14306 start &227 14307 sat 32 14308 eat 16 14309 sty 1 14310 st 0 14311 sf 1 14312 si 0 14313 tg (WTG 14314 uid 8514,0 14315 ps "ConnStartEndStrategy" 14316 stg "STSignalDisplayStrategy" 14317 f (Text 14318 uid 8515,0 14319 va (VaSet 14320 ) 14321 xt "94000,109000,101200,110000" 14322 st "drs_address : (3:0)" 14323 blo "94000,109800" 14324 tm "WireNameMgr" 14325 ) 14326 ) 14327 on &323 14328 ) 14329 *449 (Wire 14330 uid 8518,0 14331 shape (OrthoPolyLine 14332 uid 8519,0 14333 va (VaSet 14334 vasetType 3 14335 ) 14336 xt "92750,111000,102000,111000" 14337 pts [ 14338 "92750,111000" 14339 "102000,111000" 14340 ] 14341 ) 14342 start &228 14343 sat 32 14344 eat 16 14345 st 0 14346 sf 1 14347 si 0 14348 tg (WTG 14349 uid 8522,0 14350 ps "ConnStartEndStrategy" 14351 stg "STSignalDisplayStrategy" 14352 f (Text 14353 uid 8523,0 14354 va (VaSet 14355 ) 14356 xt "94000,110000,101200,111000" 14357 st "drs_address_mode" 14358 blo "94000,110800" 14359 tm "WireNameMgr" 14360 ) 14361 ) 14362 on &324 14363 ) 14364 *450 (Wire 14365 uid 8577,0 14366 shape (OrthoPolyLine 14367 uid 8578,0 14368 va (VaSet 14369 vasetType 3 14370 lineWidth 2 14371 ) 14372 xt "7000,57000,18250,57000" 14373 pts [ 14374 "18250,57000" 14375 "7000,57000" 14376 ] 14377 ) 14378 start &39 14379 sat 32 14380 eat 16 14381 sty 1 14382 st 0 14383 sf 1 14384 si 0 14385 tg (WTG 14386 uid 8581,0 14387 ps "ConnStartEndStrategy" 14388 stg "STSignalDisplayStrategy" 14389 f (Text 14390 uid 8582,0 14391 va (VaSet 14392 ) 14393 xt "8000,56000,18400,57000" 14394 st "drs_channel_internal : (3:0)" 14395 blo "8000,56800" 14396 tm "WireNameMgr" 14397 ) 14398 ) 14399 on &346 14400 ) 14401 *451 (Wire 14402 uid 8587,0 14403 shape (OrthoPolyLine 14404 uid 8588,0 14405 va (VaSet 14406 vasetType 3 14407 lineWidth 2 14408 ) 14409 xt "-29000,101000,-20000,101000" 14410 pts [ 14411 "-20000,101000" 14412 "-29000,101000" 14413 ] 14414 ) 14415 end &326 14416 sat 16 14417 eat 32 14418 sty 1 14419 stc 0 14420 st 0 14421 sf 1 14422 si 0 14423 tg (WTG 14424 uid 8591,0 14425 ps "ConnStartEndStrategy" 14426 stg "STSignalDisplayStrategy" 14427 f (Text 14428 uid 8592,0 14429 va (VaSet 14430 ) 14431 xt "-29000,100000,-20800,101000" 14432 st "drs_channel_internal" 14433 blo "-29000,100800" 14434 tm "WireNameMgr" 14435 ) 14436 ) 14437 on &346 14438 ) 14439 *452 (Wire 14440 uid 8595,0 14441 shape (OrthoPolyLine 14442 uid 8596,0 14443 va (VaSet 14444 vasetType 3 14445 lineWidth 2 14446 ) 14447 xt "-29000,99000,-20000,99000" 14448 pts [ 14449 "-20000,99000" 14450 "-29000,99000" 14451 ] 14452 ) 14453 end &331 14454 sat 16 14455 eat 32 14456 sty 1 14457 stc 0 14458 st 0 14459 sf 1 14460 si 0 14461 tg (WTG 14462 uid 8599,0 14463 ps "ConnStartEndStrategy" 14464 stg "VerticalLayoutStrategy" 14465 f (Text 14466 uid 8600,0 14467 va (VaSet 14468 ) 14469 xt "-29000,98000,-24000,99000" 14470 st "drs_address" 14471 blo "-29000,98800" 14472 tm "WireNameMgr" 14473 ) 14474 ) 14475 on &323 14476 ) 14477 *453 (Wire 14478 uid 8603,0 14479 shape (OrthoPolyLine 14480 uid 8604,0 14481 va (VaSet 14482 vasetType 3 14483 ) 14484 xt "-31000,103000,-20000,107000" 14485 pts [ 14486 "-20000,107000" 14487 "-31000,107000" 14488 "-31000,103000" 14489 ] 14490 ) 14491 end &333 14492 sat 16 14493 eat 32 14494 stc 0 14495 st 0 14496 sf 1 14497 si 0 14498 tg (WTG 14499 uid 8607,0 14500 ps "ConnStartEndStrategy" 14501 stg "VerticalLayoutStrategy" 14502 f (Text 14503 uid 8608,0 14504 va (VaSet 14505 ) 14506 xt "-29000,106000,-21800,107000" 14507 st "drs_address_mode" 14508 blo "-29000,106800" 14509 tm "WireNameMgr" 14510 ) 14511 ) 14512 on &324 13542 14513 ) 13543 14514 ] … … 13553 14524 color "26368,26368,26368" 13554 14525 ) 13555 packageList *4 22(PackageList14526 packageList *454 (PackageList 13556 14527 uid 41,0 13557 14528 stg "VerticalLayoutStrategy" 13558 14529 textVec [ 13559 *4 23(Text14530 *455 (Text 13560 14531 uid 42,0 13561 14532 va (VaSet … … 13566 14537 blo "-87000,1800" 13567 14538 ) 13568 *4 24(MLText14539 *456 (MLText 13569 14540 uid 43,0 13570 14541 va (VaSet … … 13591 14562 stg "VerticalLayoutStrategy" 13592 14563 textVec [ 13593 *4 25(Text14564 *457 (Text 13594 14565 uid 45,0 13595 14566 va (VaSet … … 13601 14572 blo "20000,800" 13602 14573 ) 13603 *4 26(Text14574 *458 (Text 13604 14575 uid 46,0 13605 14576 va (VaSet … … 13611 14582 blo "20000,1800" 13612 14583 ) 13613 *4 27(MLText14584 *459 (MLText 13614 14585 uid 47,0 13615 14586 va (VaSet … … 13621 14592 tm "BdCompilerDirectivesTextMgr" 13622 14593 ) 13623 *4 28(Text14594 *460 (Text 13624 14595 uid 48,0 13625 14596 va (VaSet … … 13631 14602 blo "20000,4800" 13632 14603 ) 13633 *4 29(MLText14604 *461 (MLText 13634 14605 uid 49,0 13635 14606 va (VaSet … … 13639 14610 tm "BdCompilerDirectivesTextMgr" 13640 14611 ) 13641 *4 30(Text14612 *462 (Text 13642 14613 uid 50,0 13643 14614 va (VaSet … … 13649 14620 blo "20000,5800" 13650 14621 ) 13651 *4 31(MLText14622 *463 (MLText 13652 14623 uid 51,0 13653 14624 va (VaSet … … 13661 14632 ) 13662 14633 windowSize "0,0,1281,1024" 13663 viewArea "- 62364,34906,23843,105999"13664 cachedDiagramExtent "- 87000,0,162300,301700"14634 viewArea "-73966,37109,33461,125703" 14635 cachedDiagramExtent "-100999,0,162300,301700" 13665 14636 pageSetupInfo (PageSetupInfo 13666 14637 ptrCmd "eDocPrintPro,winspool," … … 13687 14658 hasePageBreakOrigin 1 13688 14659 pageBreakOrigin "-73000,0" 13689 lastUid 8 460,014660 lastUid 8614,0 13690 14661 defaultCommentText (CommentText 13691 14662 shape (Rectangle … … 13749 14720 stg "VerticalLayoutStrategy" 13750 14721 textVec [ 13751 *4 32(Text14722 *464 (Text 13752 14723 va (VaSet 13753 14724 font "Arial,8,1" … … 13758 14729 tm "BdLibraryNameMgr" 13759 14730 ) 13760 *4 33(Text14731 *465 (Text 13761 14732 va (VaSet 13762 14733 font "Arial,8,1" … … 13767 14738 tm "BlkNameMgr" 13768 14739 ) 13769 *4 34(Text14740 *466 (Text 13770 14741 va (VaSet 13771 14742 font "Arial,8,1" … … 13818 14789 stg "VerticalLayoutStrategy" 13819 14790 textVec [ 13820 *4 35(Text14791 *467 (Text 13821 14792 va (VaSet 13822 14793 font "Arial,8,1" … … 13826 14797 blo "550,4300" 13827 14798 ) 13828 *4 36(Text14799 *468 (Text 13829 14800 va (VaSet 13830 14801 font "Arial,8,1" … … 13834 14805 blo "550,5300" 13835 14806 ) 13836 *4 37(Text14807 *469 (Text 13837 14808 va (VaSet 13838 14809 font "Arial,8,1" … … 13883 14854 stg "VerticalLayoutStrategy" 13884 14855 textVec [ 13885 *4 38(Text14856 *470 (Text 13886 14857 va (VaSet 13887 14858 font "Arial,8,1" … … 13892 14863 tm "BdLibraryNameMgr" 13893 14864 ) 13894 *4 39(Text14865 *471 (Text 13895 14866 va (VaSet 13896 14867 font "Arial,8,1" … … 13901 14872 tm "CptNameMgr" 13902 14873 ) 13903 *4 40(Text14874 *472 (Text 13904 14875 va (VaSet 13905 14876 font "Arial,8,1" … … 13955 14926 stg "VerticalLayoutStrategy" 13956 14927 textVec [ 13957 *4 41(Text14928 *473 (Text 13958 14929 va (VaSet 13959 14930 font "Arial,8,1" … … 13963 14934 blo "500,4300" 13964 14935 ) 13965 *4 42(Text14936 *474 (Text 13966 14937 va (VaSet 13967 14938 font "Arial,8,1" … … 13971 14942 blo "500,5300" 13972 14943 ) 13973 *4 43(Text14944 *475 (Text 13974 14945 va (VaSet 13975 14946 font "Arial,8,1" … … 14016 14987 stg "VerticalLayoutStrategy" 14017 14988 textVec [ 14018 *4 44(Text14989 *476 (Text 14019 14990 va (VaSet 14020 14991 font "Arial,8,1" … … 14024 14995 blo "50,4300" 14025 14996 ) 14026 *4 45(Text14997 *477 (Text 14027 14998 va (VaSet 14028 14999 font "Arial,8,1" … … 14032 15003 blo "50,5300" 14033 15004 ) 14034 *4 46(Text15005 *478 (Text 14035 15006 va (VaSet 14036 15007 font "Arial,8,1" … … 14073 15044 stg "VerticalLayoutStrategy" 14074 15045 textVec [ 14075 *4 47(Text15046 *479 (Text 14076 15047 va (VaSet 14077 15048 font "Arial,8,1" … … 14082 15053 tm "HdlTextNameMgr" 14083 15054 ) 14084 *4 48(Text15055 *480 (Text 14085 15056 va (VaSet 14086 15057 font "Arial,8,1" … … 14485 15456 stg "VerticalLayoutStrategy" 14486 15457 textVec [ 14487 *4 49(Text15458 *481 (Text 14488 15459 va (VaSet 14489 15460 font "Arial,8,1" … … 14493 15464 blo "14100,20800" 14494 15465 ) 14495 *4 50(MLText15466 *482 (MLText 14496 15467 va (VaSet 14497 15468 ) … … 14545 15516 stg "VerticalLayoutStrategy" 14546 15517 textVec [ 14547 *4 51(Text15518 *483 (Text 14548 15519 va (VaSet 14549 15520 font "Arial,8,1" … … 14553 15524 blo "14100,20800" 14554 15525 ) 14555 *4 52(MLText15526 *484 (MLText 14556 15527 va (VaSet 14557 15528 ) … … 14678 15649 font "Arial,8,1" 14679 15650 ) 14680 xt "-87000,8 5000,-82300,86000"15651 xt "-87000,87400,-82300,88400" 14681 15652 st "Post User:" 14682 blo "-87000,8 5800"15653 blo "-87000,88200" 14683 15654 ) 14684 15655 postUserText (MLText … … 14693 15664 commonDM (CommonDM 14694 15665 ldm (LogicalDM 14695 suid 1 83,015666 suid 190,0 14696 15667 usingSuid 1 14697 emptyRow *4 53(LEmptyRow15668 emptyRow *485 (LEmptyRow 14698 15669 ) 14699 15670 uid 54,0 14700 15671 optionalChildren [ 14701 *4 54(RefLabelRowHdr14702 ) 14703 *4 55(TitleRowHdr14704 ) 14705 *4 56(FilterRowHdr14706 ) 14707 *4 57(RefLabelColHdr15672 *486 (RefLabelRowHdr 15673 ) 15674 *487 (TitleRowHdr 15675 ) 15676 *488 (FilterRowHdr 15677 ) 15678 *489 (RefLabelColHdr 14708 15679 tm "RefLabelColHdrMgr" 14709 15680 ) 14710 *4 58(RowExpandColHdr15681 *490 (RowExpandColHdr 14711 15682 tm "RowExpandColHdrMgr" 14712 15683 ) 14713 *4 59(GroupColHdr15684 *491 (GroupColHdr 14714 15685 tm "GroupColHdrMgr" 14715 15686 ) 14716 *4 60(NameColHdr15687 *492 (NameColHdr 14717 15688 tm "BlockDiagramNameColHdrMgr" 14718 15689 ) 14719 *4 61(ModeColHdr15690 *493 (ModeColHdr 14720 15691 tm "BlockDiagramModeColHdrMgr" 14721 15692 ) 14722 *4 62(TypeColHdr15693 *494 (TypeColHdr 14723 15694 tm "BlockDiagramTypeColHdrMgr" 14724 15695 ) 14725 *4 63(BoundsColHdr15696 *495 (BoundsColHdr 14726 15697 tm "BlockDiagramBoundsColHdrMgr" 14727 15698 ) 14728 *4 64(InitColHdr15699 *496 (InitColHdr 14729 15700 tm "BlockDiagramInitColHdrMgr" 14730 15701 ) 14731 *4 65(EolColHdr15702 *497 (EolColHdr 14732 15703 tm "BlockDiagramEolColHdrMgr" 14733 15704 ) 14734 *4 66(LeafLogPort15705 *498 (LeafLogPort 14735 15706 port (LogicalPort 14736 15707 m 4 … … 14746 15717 uid 516,0 14747 15718 ) 14748 *4 67(LeafLogPort15719 *499 (LeafLogPort 14749 15720 port (LogicalPort 14750 15721 m 4 … … 14759 15730 uid 518,0 14760 15731 ) 14761 * 468(LeafLogPort15732 *500 (LeafLogPort 14762 15733 port (LogicalPort 14763 15734 m 4 … … 14772 15743 uid 520,0 14773 15744 ) 14774 * 469(LeafLogPort15745 *501 (LeafLogPort 14775 15746 port (LogicalPort 14776 15747 m 4 … … 14785 15756 uid 530,0 14786 15757 ) 14787 * 470(LeafLogPort15758 *502 (LeafLogPort 14788 15759 port (LogicalPort 14789 15760 m 4 … … 14798 15769 uid 532,0 14799 15770 ) 14800 * 471(LeafLogPort15771 *503 (LeafLogPort 14801 15772 port (LogicalPort 14802 15773 m 1 … … 14811 15782 uid 534,0 14812 15783 ) 14813 * 472(LeafLogPort15784 *504 (LeafLogPort 14814 15785 port (LogicalPort 14815 15786 m 1 … … 14824 15795 uid 536,0 14825 15796 ) 14826 * 473(LeafLogPort15797 *505 (LeafLogPort 14827 15798 port (LogicalPort 14828 15799 m 2 … … 14837 15808 uid 538,0 14838 15809 ) 14839 * 474(LeafLogPort15810 *506 (LeafLogPort 14840 15811 port (LogicalPort 14841 15812 m 1 … … 14850 15821 uid 540,0 14851 15822 ) 14852 * 475(LeafLogPort15823 *507 (LeafLogPort 14853 15824 port (LogicalPort 14854 15825 m 1 … … 14863 15834 uid 542,0 14864 15835 ) 14865 * 476(LeafLogPort15836 *508 (LeafLogPort 14866 15837 port (LogicalPort 14867 15838 m 1 … … 14876 15847 uid 546,0 14877 15848 ) 14878 * 477(LeafLogPort15849 *509 (LeafLogPort 14879 15850 port (LogicalPort 14880 15851 decl (Decl … … 14887 15858 uid 548,0 14888 15859 ) 14889 * 478(LeafLogPort15860 *510 (LeafLogPort 14890 15861 port (LogicalPort 14891 15862 decl (Decl … … 14901 15872 uid 1455,0 14902 15873 ) 14903 * 479(LeafLogPort15874 *511 (LeafLogPort 14904 15875 port (LogicalPort 14905 15876 decl (Decl … … 14914 15885 uid 1457,0 14915 15886 ) 14916 * 480(LeafLogPort15887 *512 (LeafLogPort 14917 15888 port (LogicalPort 14918 15889 decl (Decl … … 14926 15897 uid 1694,0 14927 15898 ) 14928 * 481(LeafLogPort15899 *513 (LeafLogPort 14929 15900 port (LogicalPort 14930 15901 lang 2 … … 14942 15913 uid 1993,0 14943 15914 ) 14944 * 482(LeafLogPort15915 *514 (LeafLogPort 14945 15916 port (LogicalPort 14946 15917 m 4 … … 14957 15928 uid 2305,0 14958 15929 ) 14959 * 483(LeafLogPort15930 *515 (LeafLogPort 14960 15931 port (LogicalPort 14961 15932 lang 2 … … 14970 15941 uid 2510,0 14971 15942 ) 14972 * 484(LeafLogPort15943 *516 (LeafLogPort 14973 15944 port (LogicalPort 14974 15945 lang 2 … … 14984 15955 uid 2512,0 14985 15956 ) 14986 * 485(LeafLogPort15957 *517 (LeafLogPort 14987 15958 port (LogicalPort 14988 15959 lang 2 … … 14999 15970 uid 2514,0 15000 15971 ) 15001 * 486(LeafLogPort15972 *518 (LeafLogPort 15002 15973 port (LogicalPort 15003 15974 lang 2 … … 15015 15986 uid 2516,0 15016 15987 ) 15017 * 487(LeafLogPort15988 *519 (LeafLogPort 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*6 32(MRCItem16302 litem &5 4617312 *667 (MRCItem 17313 litem &578 16303 17314 pos 80 16304 17315 dimension 20 16305 17316 uid 8421,0 17317 ) 17318 *668 (MRCItem 17319 litem &579 17320 pos 81 17321 dimension 20 17322 uid 8610,0 17323 ) 17324 *669 (MRCItem 17325 litem &580 17326 pos 82 17327 dimension 20 17328 uid 8612,0 17329 ) 17330 *670 (MRCItem 17331 litem &581 17332 pos 83 17333 dimension 20 17334 uid 8614,0 16306 17335 ) 16307 17336 ] … … 16316 17345 uid 73,0 16317 17346 optionalChildren [ 16318 *6 33(MRCItem16319 litem &4 5717347 *671 (MRCItem 17348 litem &489 16320 17349 pos 0 16321 17350 dimension 20 16322 17351 uid 74,0 16323 17352 ) 16324 *6 34(MRCItem16325 litem &4 5917353 *672 (MRCItem 17354 litem &491 16326 17355 pos 1 16327 17356 dimension 50 16328 17357 uid 75,0 16329 17358 ) 16330 *6 35(MRCItem16331 litem &4 6017359 *673 (MRCItem 17360 litem &492 16332 17361 pos 2 16333 17362 dimension 100 16334 17363 uid 76,0 16335 17364 ) 16336 *6 36(MRCItem16337 litem &4 6117365 *674 (MRCItem 17366 litem &493 16338 17367 pos 3 16339 17368 dimension 50 16340 17369 uid 77,0 16341 17370 ) 16342 *6 37(MRCItem16343 litem &4 6217371 *675 (MRCItem 17372 litem &494 16344 17373 pos 4 16345 17374 dimension 100 16346 17375 uid 78,0 16347 17376 ) 16348 *6 38(MRCItem16349 litem &4 6317377 *676 (MRCItem 17378 litem &495 16350 17379 pos 5 16351 17380 dimension 100 16352 17381 uid 79,0 16353 17382 ) 16354 *6 39(MRCItem16355 litem &4 6417383 *677 (MRCItem 17384 litem &496 16356 17385 pos 6 16357 17386 dimension 50 16358 17387 uid 80,0 16359 17388 ) 16360 *6 40(MRCItem16361 litem &4 6517389 *678 (MRCItem 17390 litem &497 16362 17391 pos 7 16363 17392 dimension 80 … … 16379 17408 genericsCommonDM (CommonDM 16380 17409 ldm (LogicalDM 16381 emptyRow *6 41(LEmptyRow17410 emptyRow *679 (LEmptyRow 16382 17411 ) 16383 17412 uid 83,0 16384 17413 optionalChildren [ 16385 *6 42(RefLabelRowHdr16386 ) 16387 *6 43(TitleRowHdr16388 ) 16389 *6 44(FilterRowHdr16390 ) 16391 *6 45(RefLabelColHdr17414 *680 (RefLabelRowHdr 17415 ) 17416 *681 (TitleRowHdr 17417 ) 17418 *682 (FilterRowHdr 17419 ) 17420 *683 (RefLabelColHdr 16392 17421 tm "RefLabelColHdrMgr" 16393 17422 ) 16394 *6 46(RowExpandColHdr17423 *684 (RowExpandColHdr 16395 17424 tm "RowExpandColHdrMgr" 16396 17425 ) 16397 *6 47(GroupColHdr17426 *685 (GroupColHdr 16398 17427 tm "GroupColHdrMgr" 16399 17428 ) 16400 *6 48(NameColHdr17429 *686 (NameColHdr 16401 17430 tm "GenericNameColHdrMgr" 16402 17431 ) 16403 *6 49(TypeColHdr17432 *687 (TypeColHdr 16404 17433 tm "GenericTypeColHdrMgr" 16405 17434 ) 16406 *6 50(InitColHdr17435 *688 (InitColHdr 16407 17436 tm "GenericValueColHdrMgr" 16408 17437 ) 16409 *6 51(PragmaColHdr17438 *689 (PragmaColHdr 16410 17439 tm "GenericPragmaColHdrMgr" 16411 17440 ) 16412 *6 52(EolColHdr17441 *690 (EolColHdr 16413 17442 tm "GenericEolColHdrMgr" 16414 17443 ) 16415 *6 53(LogGeneric17444 *691 (LogGeneric 16416 17445 generic (GiElement 16417 17446 name "RAMADDRWIDTH64b" … … 16428 17457 uid 95,0 16429 17458 optionalChildren [ 16430 *6 54(Sheet17459 *692 (Sheet 16431 17460 sheetRow (SheetRow 16432 17461 headerVa (MVa … … 16445 17474 font "Tahoma,10,0" 16446 17475 ) 16447 emptyMRCItem *6 55(MRCItem16448 litem &6 4117476 emptyMRCItem *693 (MRCItem 17477 litem &679 16449 17478 pos 1 16450 17479 dimension 20 … … 16452 17481 uid 97,0 16453 17482 optionalChildren [ 16454 *6 56(MRCItem16455 litem &6 4217483 *694 (MRCItem 17484 litem &680 16456 17485 pos 0 16457 17486 dimension 20 16458 17487 uid 98,0 16459 17488 ) 16460 *6 57(MRCItem16461 litem &6 4317489 *695 (MRCItem 17490 litem &681 16462 17491 pos 1 16463 17492 dimension 23 16464 17493 uid 99,0 16465 17494 ) 16466 *6 58(MRCItem16467 litem &6 4417495 *696 (MRCItem 17496 litem &682 16468 17497 pos 2 16469 17498 hidden 1 … … 16471 17500 uid 100,0 16472 17501 ) 16473 *6 59(MRCItem16474 litem &6 5317502 *697 (MRCItem 17503 litem &691 16475 17504 pos 0 16476 17505 dimension 20 … … 16488 17517 uid 101,0 16489 17518 optionalChildren [ 16490 *6 60(MRCItem16491 litem &6 4517519 *698 (MRCItem 17520 litem &683 16492 17521 pos 0 16493 17522 dimension 20 16494 17523 uid 102,0 16495 17524 ) 16496 *6 61(MRCItem16497 litem &6 4717525 *699 (MRCItem 17526 litem &685 16498 17527 pos 1 16499 17528 dimension 50 16500 17529 uid 103,0 16501 17530 ) 16502 * 662(MRCItem16503 litem &6 4817531 *700 (MRCItem 17532 litem &686 16504 17533 pos 2 16505 17534 dimension 186 16506 17535 uid 104,0 16507 17536 ) 16508 * 663(MRCItem16509 litem &6 4917537 *701 (MRCItem 17538 litem &687 16510 17539 pos 3 16511 17540 dimension 96 16512 17541 uid 105,0 16513 17542 ) 16514 * 664(MRCItem16515 litem &6 5017543 *702 (MRCItem 17544 litem &688 16516 17545 pos 4 16517 17546 dimension 50 16518 17547 uid 106,0 16519 17548 ) 16520 * 665(MRCItem16521 litem &6 5117549 *703 (MRCItem 17550 litem &689 16522 17551 pos 5 16523 17552 dimension 50 16524 17553 uid 107,0 16525 17554 ) 16526 * 666(MRCItem16527 litem &6 5217555 *704 (MRCItem 17556 litem &690 16528 17557 pos 6 16529 17558 dimension 80 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak
r246 r252 167 167 (vvPair 168 168 variable "HDLDir" 169 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"169 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 170 170 ) 171 171 (vvPair 172 172 variable "HDSDir" 173 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"173 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 174 174 ) 175 175 (vvPair 176 176 variable "SideDataDesignDir" 177 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"177 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info" 178 178 ) 179 179 (vvPair 180 180 variable "SideDataUserDir" 181 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"181 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user" 182 182 ) 183 183 (vvPair 184 184 variable "SourceDir" 185 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"185 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 186 186 ) 187 187 (vvPair … … 199 199 (vvPair 200 200 variable "d" 201 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"201 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main" 202 202 ) 203 203 (vvPair 204 204 variable "d_logical" 205 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"205 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main" 206 206 ) 207 207 (vvPair 208 208 variable "date" 209 value " 02.07.2010"209 value "12.07.2010" 210 210 ) 211 211 (vvPair 212 212 variable "day" 213 value " Fr"213 value "Mo" 214 214 ) 215 215 (vvPair 216 216 variable "day_long" 217 value " Freitag"217 value "Montag" 218 218 ) 219 219 (vvPair 220 220 variable "dd" 221 value " 02"221 value "12" 222 222 ) 223 223 (vvPair … … 299 299 (vvPair 300 300 variable "p" 301 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"301 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd" 302 302 ) 303 303 (vvPair 304 304 variable "p_logical" 305 value "C:\\FPGA_projects\\ FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"305 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd" 306 306 ) 307 307 (vvPair … … 359 359 (vvPair 360 360 variable "time" 361 value "1 0:38:34"361 value "11:42:03" 362 362 ) 363 363 (vvPair … … 12748 12748 va (VaSet 12749 12749 ) 12750 xt "-25000,7 4000,-20500,75000"12750 xt "-25000,73000,-20500,74000" 12751 12751 st "CLK_25_PS" 12752 blo "-25000,7 4800"12752 blo "-25000,73800" 12753 12753 tm "WireNameMgr" 12754 12754 ) … … 13330 13330 vasetType 3 13331 13331 ) 13332 xt "-2 3000,63000,-18750,63000"13332 xt "-27000,63000,-18750,63000" 13333 13333 pts [ 13334 "-2 3000,63000"13334 "-27000,63000" 13335 13335 "-18750,63000" 13336 13336 ] … … 13349 13349 va (VaSet 13350 13350 ) 13351 xt "-2 2000,62000,-17500,63000"13351 xt "-24000,62000,-19500,63000" 13352 13352 st "CLK_25_PS" 13353 blo "-2 2000,62800"13353 blo "-24000,62800" 13354 13354 tm "WireNameMgr" 13355 13355 ) … … 13661 13661 ) 13662 13662 windowSize "0,0,1281,1024" 13663 viewArea " 63050,40700,132015,97575"13663 viewArea "-62364,34906,23843,105999" 13664 13664 cachedDiagramExtent "-87000,0,162300,301700" 13665 13665 pageSetupInfo (PageSetupInfo … … 13687 13687 hasePageBreakOrigin 1 13688 13688 pageBreakOrigin "-73000,0" 13689 lastUid 84 21,013689 lastUid 8460,0 13690 13690 defaultCommentText (CommentText 13691 13691 shape (Rectangle -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_manager/symbol.sb
r246 r252 30 30 ) 31 31 version "24.1" 32 appVersion "2009. 1 (Build 12)"32 appVersion "2009.2 (Build 10)" 33 33 model (Symbol 34 34 commonDM (CommonDM 35 35 ldm (LogicalDM 36 36 ordering 1 37 suid 2 3,037 suid 25,0 38 38 usingSuid 1 39 39 emptyRow *1 (LEmptyRow … … 293 293 uid 497,0 294 294 ) 295 *30 (LogPort 296 port (LogicalPort 297 m 1 298 decl (Decl 299 n "drs_address" 300 t "std_logic_vector" 301 b "(3 DOWNTO 0)" 302 o 17 303 suid 24,0 304 ) 305 ) 306 uid 538,0 307 ) 308 *31 (LogPort 309 port (LogicalPort 310 m 1 311 decl (Decl 312 n "drs_address_mode" 313 t "std_logic" 314 o 18 315 suid 25,0 316 ) 317 ) 318 uid 540,0 319 ) 295 320 ] 296 321 ) … … 300 325 uid 187,0 301 326 optionalChildren [ 302 *3 0(Sheet327 *32 (Sheet 303 328 sheetRow (SheetRow 304 329 headerVa (MVa … … 317 342 font "Tahoma,10,0" 318 343 ) 319 emptyMRCItem *3 1(MRCItem344 emptyMRCItem *33 (MRCItem 320 345 litem &1 321 346 pos 3 … … 324 349 uid 189,0 325 350 optionalChildren [ 326 *3 2(MRCItem351 *34 (MRCItem 327 352 litem &2 328 353 pos 0 … … 330 355 uid 190,0 331 356 ) 332 *3 3(MRCItem357 *35 (MRCItem 333 358 litem &3 334 359 pos 1 … … 336 361 uid 191,0 337 362 ) 338 *3 4(MRCItem363 *36 (MRCItem 339 364 litem &4 340 365 pos 2 … … 343 368 uid 192,0 344 369 ) 345 *3 5(MRCItem370 *37 (MRCItem 346 371 litem &14 347 372 pos 0 … … 349 374 uid 138,0 350 375 ) 351 *3 6(MRCItem376 *38 (MRCItem 352 377 litem &15 353 378 pos 1 … … 355 380 uid 142,0 356 381 ) 357 *3 7(MRCItem382 *39 (MRCItem 358 383 litem &16 359 384 pos 2 … … 361 386 uid 144,0 362 387 ) 363 * 38(MRCItem388 *40 (MRCItem 364 389 litem &17 365 390 pos 3 … … 367 392 uid 146,0 368 393 ) 369 * 39(MRCItem394 *41 (MRCItem 370 395 litem &18 371 396 pos 4 … … 373 398 uid 148,0 374 399 ) 375 *4 0(MRCItem400 *42 (MRCItem 376 401 litem &19 377 402 pos 5 … … 379 404 uid 150,0 380 405 ) 381 *4 1(MRCItem406 *43 (MRCItem 382 407 litem &20 383 408 pos 6 … … 385 410 uid 152,0 386 411 ) 387 *4 2(MRCItem412 *44 (MRCItem 388 413 litem &21 389 414 pos 7 … … 391 416 uid 154,0 392 417 ) 393 *4 3(MRCItem418 *45 (MRCItem 394 419 litem &22 395 420 pos 8 … … 397 422 uid 156,0 398 423 ) 399 *4 4(MRCItem424 *46 (MRCItem 400 425 litem &23 401 426 pos 9 … … 403 428 uid 166,0 404 429 ) 405 *4 5(MRCItem430 *47 (MRCItem 406 431 litem &24 407 432 pos 10 … … 409 434 uid 168,0 410 435 ) 411 *4 6(MRCItem436 *48 (MRCItem 412 437 litem &25 413 438 pos 11 … … 415 440 uid 278,0 416 441 ) 417 *4 7(MRCItem442 *49 (MRCItem 418 443 litem &26 419 444 pos 12 … … 421 446 uid 280,0 422 447 ) 423 * 48(MRCItem448 *50 (MRCItem 424 449 litem &27 425 450 pos 13 … … 427 452 uid 316,0 428 453 ) 429 * 49(MRCItem454 *51 (MRCItem 430 455 litem &28 431 456 pos 14 … … 433 458 uid 352,0 434 459 ) 435 *5 0(MRCItem460 *52 (MRCItem 436 461 litem &29 437 462 pos 15 438 463 dimension 20 439 464 uid 498,0 465 ) 466 *53 (MRCItem 467 litem &30 468 pos 16 469 dimension 20 470 uid 539,0 471 ) 472 *54 (MRCItem 473 litem &31 474 pos 17 475 dimension 20 476 uid 541,0 440 477 ) 441 478 ] … … 450 487 uid 193,0 451 488 optionalChildren [ 452 *5 1(MRCItem489 *55 (MRCItem 453 490 litem &5 454 491 pos 0 … … 456 493 uid 194,0 457 494 ) 458 *5 2(MRCItem495 *56 (MRCItem 459 496 litem &7 460 497 pos 1 … … 462 499 uid 195,0 463 500 ) 464 *5 3(MRCItem501 *57 (MRCItem 465 502 litem &8 466 503 pos 2 … … 468 505 uid 196,0 469 506 ) 470 *5 4(MRCItem507 *58 (MRCItem 471 508 litem &9 472 509 pos 3 … … 474 511 uid 197,0 475 512 ) 476 *5 5(MRCItem513 *59 (MRCItem 477 514 litem &10 478 515 pos 4 … … 480 517 uid 198,0 481 518 ) 482 * 56(MRCItem519 *60 (MRCItem 483 520 litem &11 484 521 pos 5 … … 486 523 uid 199,0 487 524 ) 488 * 57(MRCItem525 *61 (MRCItem 489 526 litem &12 490 527 pos 6 … … 492 529 uid 200,0 493 530 ) 494 * 58(MRCItem531 *62 (MRCItem 495 532 litem &13 496 533 pos 7 … … 513 550 genericsCommonDM (CommonDM 514 551 ldm (LogicalDM 515 emptyRow * 59(LEmptyRow552 emptyRow *63 (LEmptyRow 516 553 ) 517 554 uid 203,0 518 555 optionalChildren [ 519 *6 0(RefLabelRowHdr520 ) 521 *6 1(TitleRowHdr522 ) 523 *6 2(FilterRowHdr524 ) 525 *6 3(RefLabelColHdr556 *64 (RefLabelRowHdr 557 ) 558 *65 (TitleRowHdr 559 ) 560 *66 (FilterRowHdr 561 ) 562 *67 (RefLabelColHdr 526 563 tm "RefLabelColHdrMgr" 527 564 ) 528 *6 4(RowExpandColHdr565 *68 (RowExpandColHdr 529 566 tm "RowExpandColHdrMgr" 530 567 ) 531 *6 5(GroupColHdr568 *69 (GroupColHdr 532 569 tm "GroupColHdrMgr" 533 570 ) 534 * 66(NameColHdr571 *70 (NameColHdr 535 572 tm "GenericNameColHdrMgr" 536 573 ) 537 * 67(TypeColHdr574 *71 (TypeColHdr 538 575 tm "GenericTypeColHdrMgr" 539 576 ) 540 * 68(InitColHdr577 *72 (InitColHdr 541 578 tm "GenericValueColHdrMgr" 542 579 ) 543 * 69(PragmaColHdr580 *73 (PragmaColHdr 544 581 tm "GenericPragmaColHdrMgr" 545 582 ) 546 *7 0(EolColHdr583 *74 (EolColHdr 547 584 tm "GenericEolColHdrMgr" 548 585 ) 549 *7 1(LogGeneric586 *75 (LogGeneric 550 587 generic (GiElement 551 588 name "NO_OF_ROI" … … 553 590 value "36" 554 591 ) 555 uid 499,0556 ) 557 *7 2(LogGeneric592 uid 542,0 593 ) 594 *76 (LogGeneric 558 595 generic (GiElement 559 596 name "NO_OF_DAC" … … 561 598 value "8" 562 599 ) 563 uid 5 01,0564 ) 565 *7 3(LogGeneric600 uid 544,0 601 ) 602 *77 (LogGeneric 566 603 generic (GiElement 567 604 name "ADDR_WIDTH" … … 569 606 value "8" 570 607 ) 571 uid 5 03,0608 uid 546,0 572 609 ) 573 610 ] … … 578 615 uid 215,0 579 616 optionalChildren [ 580 *7 4(Sheet617 *78 (Sheet 581 618 sheetRow (SheetRow 582 619 headerVa (MVa … … 595 632 font "Tahoma,10,0" 596 633 ) 597 emptyMRCItem *7 5(MRCItem598 litem & 59634 emptyMRCItem *79 (MRCItem 635 litem &63 599 636 pos 3 600 637 dimension 20 … … 602 639 uid 217,0 603 640 optionalChildren [ 604 * 76(MRCItem605 litem &6 0641 *80 (MRCItem 642 litem &64 606 643 pos 0 607 644 dimension 20 608 645 uid 218,0 609 646 ) 610 * 77(MRCItem611 litem &6 1647 *81 (MRCItem 648 litem &65 612 649 pos 1 613 650 dimension 23 614 651 uid 219,0 615 652 ) 616 * 78(MRCItem617 litem &6 2653 *82 (MRCItem 654 litem &66 618 655 pos 2 619 656 hidden 1 … … 621 658 uid 220,0 622 659 ) 623 * 79(MRCItem624 litem &7 1660 *83 (MRCItem 661 litem &75 625 662 pos 0 626 663 dimension 20 627 uid 5 00,0628 ) 629 *8 0(MRCItem630 litem &7 2664 uid 543,0 665 ) 666 *84 (MRCItem 667 litem &76 631 668 pos 1 632 669 dimension 20 633 uid 5 02,0634 ) 635 *8 1(MRCItem636 litem &7 3670 uid 545,0 671 ) 672 *85 (MRCItem 673 litem &77 637 674 pos 2 638 675 dimension 20 639 uid 5 04,0676 uid 547,0 640 677 ) 641 678 ] … … 650 687 uid 221,0 651 688 optionalChildren [ 652 *8 2(MRCItem653 litem &6 3689 *86 (MRCItem 690 litem &67 654 691 pos 0 655 692 dimension 20 656 693 uid 222,0 657 694 ) 658 *8 3(MRCItem659 litem &6 5695 *87 (MRCItem 696 litem &69 660 697 pos 1 661 698 dimension 50 662 699 uid 223,0 663 700 ) 664 *8 4(MRCItem665 litem & 66701 *88 (MRCItem 702 litem &70 666 703 pos 2 667 704 dimension 100 668 705 uid 224,0 669 706 ) 670 *8 5(MRCItem671 litem & 67707 *89 (MRCItem 708 litem &71 672 709 pos 3 673 710 dimension 100 674 711 uid 225,0 675 712 ) 676 * 86(MRCItem677 litem & 68713 *90 (MRCItem 714 litem &72 678 715 pos 4 679 716 dimension 50 680 717 uid 226,0 681 718 ) 682 * 87(MRCItem683 litem & 69719 *91 (MRCItem 720 litem &73 684 721 pos 5 685 722 dimension 50 686 723 uid 227,0 687 724 ) 688 * 88(MRCItem689 litem &7 0725 *92 (MRCItem 726 litem &74 690 727 pos 6 691 728 dimension 80 … … 710 747 (vvPair 711 748 variable "HDLDir" 712 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hdl"749 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 713 750 ) 714 751 (vvPair 715 752 variable "HDSDir" 716 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"753 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 717 754 ) 718 755 (vvPair 719 756 variable "SideDataDesignDir" 720 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info"757 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.info" 721 758 ) 722 759 (vvPair 723 760 variable "SideDataUserDir" 724 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user"761 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb.user" 725 762 ) 726 763 (vvPair 727 764 variable "SourceDir" 728 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds"765 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 729 766 ) 730 767 (vvPair … … 742 779 (vvPair 743 780 variable "d" 744 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"781 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" 745 782 ) 746 783 (vvPair 747 784 variable "d_logical" 748 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager"785 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager" 749 786 ) 750 787 (vvPair 751 788 variable "date" 752 value " 07.05.2010"789 value "12.07.2010" 753 790 ) 754 791 (vvPair 755 792 variable "day" 756 value " Fr"793 value "Mo" 757 794 ) 758 795 (vvPair 759 796 variable "day_long" 760 value " Freitag"797 value "Montag" 761 798 ) 762 799 (vvPair 763 800 variable "dd" 764 value " 07"801 value "12" 765 802 ) 766 803 (vvPair … … 790 827 (vvPair 791 828 variable "host" 792 value " E5PCXX"829 value "TU-CC4900F8C7D2" 793 830 ) 794 831 (vvPair … … 818 855 (vvPair 819 856 variable "mm" 820 value "0 5"857 value "07" 821 858 ) 822 859 (vvPair … … 826 863 (vvPair 827 864 variable "month" 828 value " Mai"865 value "Jul" 829 866 ) 830 867 (vvPair 831 868 variable "month_long" 832 value " Mai"869 value "Juli" 833 870 ) 834 871 (vvPair 835 872 variable "p" 836 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"873 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" 837 874 ) 838 875 (vvPair 839 876 variable "p_logical" 840 value " D:\\Kai\\FPGA\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb"877 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_manager\\symbol.sb" 841 878 ) 842 879 (vvPair … … 858 895 (vvPair 859 896 variable "task_LeonardoPath" 860 value " $HDS_HOME/../Exemplar/bin/win32"897 value "<TBD>" 861 898 ) 862 899 (vvPair 863 900 variable "task_ModelSimPath" 864 value " D:\\Programme\\FPGAdv82LSPS\\Modeltech\\win32"901 value "<TBD>" 865 902 ) 866 903 (vvPair … … 870 907 (vvPair 871 908 variable "task_PrecisionRTLPath" 872 value " $HDS_HOME/../Precision/Mgc_home/bin"909 value "<TBD>" 873 910 ) 874 911 (vvPair … … 894 931 (vvPair 895 932 variable "time" 896 value "1 2:45:37"933 value "14:11:44" 897 934 ) 898 935 (vvPair … … 902 939 (vvPair 903 940 variable "user" 904 value " kai"941 value "dneise" 905 942 ) 906 943 (vvPair 907 944 variable "version" 908 value "2009. 1 (Build 12)"945 value "2009.2 (Build 10)" 909 946 ) 910 947 (vvPair … … 925 962 uid 172,0 926 963 optionalChildren [ 927 * 89(SymbolBody964 *93 (SymbolBody 928 965 uid 8,0 929 966 optionalChildren [ 930 *9 0(CptPort967 *94 (CptPort 931 968 uid 48,0 932 969 ps "OnEdgeStrategy" … … 974 1011 ) 975 1012 ) 976 *9 1(CptPort1013 *95 (CptPort 977 1014 uid 58,0 978 1015 ps "OnEdgeStrategy" … … 1023 1060 ) 1024 1061 ) 1025 *9 2(CptPort1062 *96 (CptPort 1026 1063 uid 63,0 1027 1064 ps "OnEdgeStrategy" … … 1070 1107 ) 1071 1108 ) 1072 *9 3(CptPort1109 *97 (CptPort 1073 1110 uid 68,0 1074 1111 ps "OnEdgeStrategy" … … 1120 1157 ) 1121 1158 ) 1122 *9 4(CptPort1159 *98 (CptPort 1123 1160 uid 73,0 1124 1161 ps "OnEdgeStrategy" … … 1168 1205 ) 1169 1206 ) 1170 *9 5(CptPort1207 *99 (CptPort 1171 1208 uid 78,0 1172 1209 ps "OnEdgeStrategy" … … 1215 1252 ) 1216 1253 ) 1217 * 96(CptPort1254 *100 (CptPort 1218 1255 uid 83,0 1219 1256 ps "OnEdgeStrategy" … … 1262 1299 ) 1263 1300 ) 1264 * 97(CptPort1301 *101 (CptPort 1265 1302 uid 88,0 1266 1303 ps "OnEdgeStrategy" … … 1311 1348 ) 1312 1349 ) 1313 * 98(CptPort1350 *102 (CptPort 1314 1351 uid 93,0 1315 1352 ps "OnEdgeStrategy" … … 1360 1397 ) 1361 1398 ) 1362 * 99(CptPort1399 *103 (CptPort 1363 1400 uid 118,0 1364 1401 ps "OnEdgeStrategy" … … 1408 1445 ) 1409 1446 ) 1410 *10 0(CptPort1447 *104 (CptPort 1411 1448 uid 123,0 1412 1449 ps "OnEdgeStrategy" … … 1440 1477 font "Courier New,8,0" 1441 1478 ) 1442 xt "2000,23000,2 5000,23800"1443 st "roi_array : OUT roi_array_type 1479 xt "2000,23000,26000,23800" 1480 st "roi_array : OUT roi_array_type ; 1444 1481 " 1445 1482 ) … … 1456 1493 ) 1457 1494 ) 1458 *10 1(CptPort1495 *105 (CptPort 1459 1496 uid 263,0 1460 1497 ps "OnEdgeStrategy" … … 1503 1540 ) 1504 1541 ) 1505 *10 2(CptPort1542 *106 (CptPort 1506 1543 uid 268,0 1507 1544 ps "OnEdgeStrategy" … … 1550 1587 ) 1551 1588 ) 1552 *10 3(CptPort1589 *107 (CptPort 1553 1590 uid 310,0 1554 1591 ps "OnEdgeStrategy" … … 1595 1632 ) 1596 1633 ) 1597 *10 4(CptPort1634 *108 (CptPort 1598 1635 uid 346,0 1599 1636 ps "OnEdgeStrategy" … … 1642 1679 ) 1643 1680 ) 1644 *10 5(CptPort1681 *109 (CptPort 1645 1682 uid 492,0 1646 1683 ps "OnEdgeStrategy" … … 1689 1726 ) 1690 1727 ) 1728 *110 (CptPort 1729 uid 528,0 1730 ps "OnEdgeStrategy" 1731 shape (Triangle 1732 uid 529,0 1733 ro 90 1734 va (VaSet 1735 vasetType 1 1736 fg "0,65535,0" 1737 ) 1738 xt "67000,32625,67750,33375" 1739 ) 1740 tg (CPTG 1741 uid 530,0 1742 ps "CptPortTextPlaceStrategy" 1743 stg "RightVerticalLayoutStrategy" 1744 f (Text 1745 uid 531,0 1746 va (VaSet 1747 ) 1748 xt "58800,32500,66000,33500" 1749 st "drs_address : (3:0)" 1750 ju 2 1751 blo "66000,33300" 1752 tm "CptPortNameMgr" 1753 ) 1754 ) 1755 dt (MLText 1756 uid 532,0 1757 va (VaSet 1758 font "Courier New,8,0" 1759 ) 1760 xt "2000,23800,33000,24600" 1761 st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; 1762 " 1763 ) 1764 thePort (LogicalPort 1765 m 1 1766 decl (Decl 1767 n "drs_address" 1768 t "std_logic_vector" 1769 b "(3 DOWNTO 0)" 1770 o 17 1771 suid 24,0 1772 ) 1773 ) 1774 ) 1775 *111 (CptPort 1776 uid 533,0 1777 ps "OnEdgeStrategy" 1778 shape (Triangle 1779 uid 534,0 1780 ro 90 1781 va (VaSet 1782 vasetType 1 1783 fg "0,65535,0" 1784 ) 1785 xt "67000,33625,67750,34375" 1786 ) 1787 tg (CPTG 1788 uid 535,0 1789 ps "CptPortTextPlaceStrategy" 1790 stg "RightVerticalLayoutStrategy" 1791 f (Text 1792 uid 536,0 1793 va (VaSet 1794 ) 1795 xt "58800,33500,66000,34500" 1796 st "drs_address_mode" 1797 ju 2 1798 blo "66000,34300" 1799 tm "CptPortNameMgr" 1800 ) 1801 ) 1802 dt (MLText 1803 uid 537,0 1804 va (VaSet 1805 font "Courier New,8,0" 1806 ) 1807 xt "2000,24600,22000,25400" 1808 st "drs_address_mode : OUT std_logic 1809 " 1810 ) 1811 thePort (LogicalPort 1812 m 1 1813 decl (Decl 1814 n "drs_address_mode" 1815 t "std_logic" 1816 o 18 1817 suid 25,0 1818 ) 1819 ) 1820 ) 1691 1821 ] 1692 1822 shape (Rectangle … … 1698 1828 lineWidth 2 1699 1829 ) 1700 xt "42000,14000,67000,3 3000"1830 xt "42000,14000,67000,35000" 1701 1831 ) 1702 1832 oxt "42000,14000,66000,27000" … … 1724 1854 ) 1725 1855 ) 1726 gi *1 06(GenericInterface1856 gi *112 (GenericInterface 1727 1857 uid 13,0 1728 1858 ps "CenterOffsetStrategy" … … 1769 1899 ) 1770 1900 ) 1771 *1 07(Grouping1901 *113 (Grouping 1772 1902 uid 16,0 1773 1903 optionalChildren [ 1774 *1 08(CommentText1904 *114 (CommentText 1775 1905 uid 18,0 1776 1906 shape (Rectangle … … 1803 1933 titleBlock 1 1804 1934 ) 1805 *1 09(CommentText1935 *115 (CommentText 1806 1936 uid 21,0 1807 1937 shape (Rectangle … … 1834 1964 titleBlock 1 1835 1965 ) 1836 *11 0(CommentText1966 *116 (CommentText 1837 1967 uid 24,0 1838 1968 shape (Rectangle … … 1865 1995 titleBlock 1 1866 1996 ) 1867 *11 1(CommentText1997 *117 (CommentText 1868 1998 uid 27,0 1869 1999 shape (Rectangle … … 1896 2026 titleBlock 1 1897 2027 ) 1898 *11 2(CommentText2028 *118 (CommentText 1899 2029 uid 30,0 1900 2030 shape (Rectangle … … 1926 2056 titleBlock 1 1927 2057 ) 1928 *11 3(CommentText2058 *119 (CommentText 1929 2059 uid 33,0 1930 2060 shape (Rectangle … … 1957 2087 titleBlock 1 1958 2088 ) 1959 *1 14(CommentText2089 *120 (CommentText 1960 2090 uid 36,0 1961 2091 shape (Rectangle … … 1989 2119 titleBlock 1 1990 2120 ) 1991 *1 15(CommentText2121 *121 (CommentText 1992 2122 uid 39,0 1993 2123 shape (Rectangle … … 2020 2150 titleBlock 1 2021 2151 ) 2022 *1 16(CommentText2152 *122 (CommentText 2023 2153 uid 42,0 2024 2154 shape (Rectangle … … 2051 2181 titleBlock 1 2052 2182 ) 2053 *1 17(CommentText2183 *123 (CommentText 2054 2184 uid 45,0 2055 2185 shape (Rectangle … … 2095 2225 oxt "14000,66000,55000,71000" 2096 2226 ) 2097 *1 18(CommentText2227 *124 (CommentText 2098 2228 uid 134,0 2099 2229 shape (Rectangle … … 2138 2268 color "26368,26368,26368" 2139 2269 ) 2140 packageList *1 19(PackageList2270 packageList *125 (PackageList 2141 2271 uid 169,0 2142 2272 stg "VerticalLayoutStrategy" 2143 2273 textVec [ 2144 *12 0(Text2274 *126 (Text 2145 2275 uid 170,0 2146 2276 va (VaSet … … 2151 2281 blo "0,1800" 2152 2282 ) 2153 *12 1(MLText2283 *127 (MLText 2154 2284 uid 171,0 2155 2285 va (VaSet … … 2252 2382 ) 2253 2383 ) 2254 gi *12 2(GenericInterface2384 gi *128 (GenericInterface 2255 2385 ps "CenterOffsetStrategy" 2256 2386 matrix (Matrix … … 2349 2479 ) 2350 2480 ) 2351 DeclarativeBlock *12 3(SymDeclBlock2481 DeclarativeBlock *129 (SymDeclBlock 2352 2482 uid 1,0 2353 2483 stg "SymDeclLayoutStrategy" … … 2375 2505 font "Arial,8,1" 2376 2506 ) 2377 xt "0,2 3800,2400,24800"2507 xt "0,25400,2400,26400" 2378 2508 st "User:" 2379 blo "0,2 4600"2509 blo "0,26200" 2380 2510 ) 2381 2511 internalLabel (Text … … 2394 2524 font "Courier New,8,0" 2395 2525 ) 2396 xt "2000,2 4800,2000,24800"2526 xt "2000,26400,2000,26400" 2397 2527 tm "SyDeclarativeTextMgr" 2398 2528 ) … … 2407 2537 ) 2408 2538 ) 2409 lastUid 5 04,02539 lastUid 547,0 2410 2540 activeModelName "Symbol:CDM" 2411 2541 ) -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd
r246 r252 60 60 ) 61 61 version "29.1" 62 appVersion "2009. 1 (Build 12)"62 appVersion "2009.2 (Build 10)" 63 63 noEmbeddedEditors 1 64 64 model (BlockDiag … … 67 67 (vvPair 68 68 variable "HDLDir" 69 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"69 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 70 70 ) 71 71 (vvPair 72 72 variable "HDSDir" 73 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"73 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 74 74 ) 75 75 (vvPair 76 76 variable "SideDataDesignDir" 77 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"77 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" 78 78 ) 79 79 (vvPair 80 80 variable "SideDataUserDir" 81 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"81 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" 82 82 ) 83 83 (vvPair 84 84 variable "SourceDir" 85 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"85 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 86 86 ) 87 87 (vvPair … … 99 99 (vvPair 100 100 variable "d" 101 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"101 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 102 102 ) 103 103 (vvPair 104 104 variable "d_logical" 105 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"105 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 106 106 ) 107 107 (vvPair 108 108 variable "date" 109 value " 27.05.2010"109 value "12.07.2010" 110 110 ) 111 111 (vvPair 112 112 variable "day" 113 value " Do"113 value "Mo" 114 114 ) 115 115 (vvPair 116 116 variable "day_long" 117 value " Donnerstag"117 value "Montag" 118 118 ) 119 119 (vvPair 120 120 variable "dd" 121 value " 27"121 value "12" 122 122 ) 123 123 (vvPair … … 147 147 (vvPair 148 148 variable "host" 149 value " IHP110"149 value "TU-CC4900F8C7D2" 150 150 ) 151 151 (vvPair … … 175 175 (vvPair 176 176 variable "mm" 177 value "0 5"177 value "07" 178 178 ) 179 179 (vvPair … … 183 183 (vvPair 184 184 variable "month" 185 value " Mai"185 value "Jul" 186 186 ) 187 187 (vvPair 188 188 variable "month_long" 189 value " Mai"189 value "Juli" 190 190 ) 191 191 (vvPair 192 192 variable "p" 193 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"193 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" 194 194 ) 195 195 (vvPair 196 196 variable "p_logical" 197 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"197 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" 198 198 ) 199 199 (vvPair … … 219 219 (vvPair 220 220 variable "task_ModelSimPath" 221 value " D:\\modeltech_6.5e\\win32"221 value "<TBD>" 222 222 ) 223 223 (vvPair … … 251 251 (vvPair 252 252 variable "time" 253 value "1 0:24:05"253 value "14:13:34" 254 254 ) 255 255 (vvPair … … 259 259 (vvPair 260 260 variable "user" 261 value "d aqct3"261 value "dneise" 262 262 ) 263 263 (vvPair 264 264 variable "version" 265 value "2009. 1 (Build 12)"265 value "2009.2 (Build 10)" 266 266 ) 267 267 (vvPair … … 303 303 bg "0,0,32768" 304 304 ) 305 xt "16200,76000,25 900,77000"305 xt "16200,76000,25500,77000" 306 306 st " 307 307 by %user on %dd %month %year … … 621 621 font "Courier New,8,0" 622 622 ) 623 xt "22000,2000,38000,2800" 624 st "clk : STD_LOGIC" 623 xt "29000,2200,45000,3000" 624 st "clk : STD_LOGIC 625 " 625 626 ) 626 627 ) … … 639 640 font "Courier New,8,0" 640 641 ) 641 xt "22000,15000,51500,15800" 642 st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)" 642 xt "29000,16800,58500,17600" 643 st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0) 644 " 643 645 ) 644 646 ) … … 657 659 font "Courier New,8,0" 658 660 ) 659 xt "22000,2800,48000,3600" 660 st "config_addr : std_logic_vector(7 DOWNTO 0)" 661 xt "29000,3000,55000,3800" 662 st "config_addr : std_logic_vector(7 DOWNTO 0) 663 " 661 664 ) 662 665 ) … … 675 678 font "Courier New,8,0" 676 679 ) 677 xt "22000,13400,52000,14200" 678 st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)" 680 xt "29000,15200,59000,16000" 681 st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0) 682 " 679 683 ) 680 684 ) … … 692 696 font "Courier New,8,0" 693 697 ) 694 xt "22000,6800,38000,7600" 695 st "config_data_valid : std_logic" 698 xt "29000,7000,45000,7800" 699 st "config_data_valid : std_logic 700 " 696 701 ) 697 702 ) … … 709 714 font "Courier New,8,0" 710 715 ) 711 xt "22000,6000,38000,6800" 712 st "config_busy : std_logic" 716 xt "29000,6200,45000,7000" 717 st "config_busy : std_logic 718 " 713 719 ) 714 720 ) … … 727 733 font "Courier New,8,0" 728 734 ) 729 xt "22000,10800,48500,11600" 730 st "config_data : std_logic_vector(15 DOWNTO 0)" 735 xt "29000,12600,55500,13400" 736 st "config_data : std_logic_vector(15 DOWNTO 0) 737 " 731 738 ) 732 739 ) … … 744 751 font "Courier New,8,0" 745 752 ) 746 xt "22000,10000,40500,10800" 747 st "roi_array : roi_array_type" 753 xt "29000,11800,47500,12600" 754 st "roi_array : roi_array_type 755 " 748 756 ) 749 757 ) … … 762 770 font "Courier New,8,0" 763 771 ) 764 xt "22000,12600,51500,13400" 765 st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)" 772 xt "29000,14400,58500,15200" 773 st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0) 774 " 766 775 ) 767 776 ) … … 779 788 font "Courier New,8,0" 780 789 ) 781 xt "22000,5200,38000,6000" 782 st "config_wr_en : std_logic" 790 xt "29000,5400,45000,6200" 791 st "config_wr_en : std_logic 792 " 783 793 ) 784 794 ) … … 797 807 font "Courier New,8,0" 798 808 ) 799 xt "22000,14200,52000,15000" 800 st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)" 809 xt "29000,16000,59000,16800" 810 st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0) 811 " 801 812 ) 802 813 ) … … 814 825 font "Courier New,8,0" 815 826 ) 816 xt "22000,9200,40500,10000" 817 st "dac_array : dac_array_type" 827 xt "29000,9400,47500,10200" 828 st "dac_array : dac_array_type 829 " 818 830 ) 819 831 ) … … 831 843 font "Courier New,8,0" 832 844 ) 833 xt "22000,3600,38000,4400" 834 st "config_rd_en : std_logic" 845 xt "29000,3800,45000,4600" 846 st "config_rd_en : std_logic 847 " 835 848 ) 836 849 ) … … 848 861 font "Courier New,8,0" 849 862 ) 850 xt "22000,4400,38000,5200" 851 st "config_start : std_logic" 863 xt "29000,4600,45000,5400" 864 st "config_start : std_logic 865 " 852 866 ) 853 867 ) … … 865 879 font "Courier New,8,0" 866 880 ) 867 xt "22000,7600,38000,8400" 868 st "config_ready : std_logic" 881 xt "29000,7800,45000,8600" 882 st "config_ready : std_logic 883 " 869 884 ) 870 885 ) … … 882 897 sl 0 883 898 ro 270 884 xt " 3000,23625,4500,24375"899 xt "2000,19625,3500,20375" 885 900 ) 886 901 (Line … … 888 903 sl 0 889 904 ro 270 890 xt " 4500,24000,5000,24000"905 xt "3500,20000,4000,20000" 891 906 pts [ 892 " 4500,24000"893 " 5000,24000"907 "3500,20000" 908 "4000,20000" 894 909 ] 895 910 ) … … 906 921 va (VaSet 907 922 ) 908 xt "700, 23500,2000,24500"923 xt "700,19500,2000,20500" 909 924 st "clk" 910 925 ju 2 911 blo "2000,2 4300"926 blo "2000,20300" 912 927 tm "WireNameMgr" 913 928 ) … … 927 942 sl 0 928 943 ro 270 929 xt " 42500,28625,44000,29375"944 xt "36500,28625,38000,29375" 930 945 ) 931 946 (Line … … 933 948 sl 0 934 949 ro 270 935 xt " 42000,29000,42500,29000"950 xt "36000,29000,36500,29000" 936 951 pts [ 937 " 42000,29000"938 " 42500,29000"952 "36000,29000" 953 "36500,29000" 939 954 ] 940 955 ) … … 951 966 va (VaSet 952 967 ) 953 xt " 45000,28500,50100,29500"968 xt "39000,28500,44100,29500" 954 969 st "config_ready" 955 blo " 45000,29300"970 blo "39000,29300" 956 971 tm "WireNameMgr" 957 972 ) … … 971 986 sl 0 972 987 ro 90 973 xt " 42500,29625,44000,30375"988 xt "36500,29625,38000,30375" 974 989 ) 975 990 (Line … … 977 992 sl 0 978 993 ro 90 979 xt " 42000,30000,42500,30000"994 xt "36000,30000,36500,30000" 980 995 pts [ 981 " 42500,30000"982 " 42000,30000"996 "36500,30000" 997 "36000,30000" 983 998 ] 984 999 ) … … 995 1010 va (VaSet 996 1011 ) 997 xt " 45000,29500,49800,30500"1012 xt "39000,29500,43800,30500" 998 1013 st "config_start" 999 blo " 45000,30300"1014 blo "39000,30300" 1000 1015 tm "WireNameMgr" 1001 1016 ) … … 1014 1029 uid 381,0 1015 1030 sl 0 1016 xt " 42500,24625,44000,25375"1031 xt "36500,24625,38000,25375" 1017 1032 ) 1018 1033 (Line 1019 1034 uid 382,0 1020 1035 sl 0 1021 xt " 42000,25000,42500,25000"1036 xt "36000,25000,36500,25000" 1022 1037 pts [ 1023 " 42000,25000"1024 " 42500,25000"1038 "36000,25000" 1039 "36500,25000" 1025 1040 ] 1026 1041 ) … … 1037 1052 va (VaSet 1038 1053 ) 1039 xt " 45000,24500,49700,25500"1054 xt "39000,24500,43700,25500" 1040 1055 st "config_data" 1041 blo " 45000,25300"1056 blo "39000,25300" 1042 1057 tm "WireNameMgr" 1043 1058 ) … … 1057 1072 sl 0 1058 1073 ro 90 1059 xt " 42500,23625,44000,24375"1074 xt "36500,23625,38000,24375" 1060 1075 ) 1061 1076 (Line … … 1063 1078 sl 0 1064 1079 ro 90 1065 xt " 42000,24000,42500,24000"1080 xt "36000,24000,36500,24000" 1066 1081 pts [ 1067 " 42500,24000"1068 " 42000,24000"1082 "36500,24000" 1083 "36000,24000" 1069 1084 ] 1070 1085 ) … … 1081 1096 va (VaSet 1082 1097 ) 1083 xt " 45000,23500,49800,24500"1098 xt "39000,23500,43800,24500" 1084 1099 st "config_addr" 1085 blo " 45000,24300"1100 blo "39000,24300" 1086 1101 tm "WireNameMgr" 1087 1102 ) … … 1101 1116 sl 0 1102 1117 ro 90 1103 xt " 42500,26625,44000,27375"1118 xt "36500,26625,38000,27375" 1104 1119 ) 1105 1120 (Line … … 1107 1122 sl 0 1108 1123 ro 90 1109 xt " 42000,27000,42500,27000"1124 xt "36000,27000,36500,27000" 1110 1125 pts [ 1111 " 42500,27000"1112 " 42000,27000"1126 "36500,27000" 1127 "36000,27000" 1113 1128 ] 1114 1129 ) … … 1125 1140 va (VaSet 1126 1141 ) 1127 xt " 45000,26500,50300,27500"1142 xt "39000,26500,44300,27500" 1128 1143 st "config_wr_en" 1129 blo " 45000,27300"1144 blo "39000,27300" 1130 1145 tm "WireNameMgr" 1131 1146 ) … … 1145 1160 sl 0 1146 1161 ro 90 1147 xt " 42500,27625,44000,28375"1162 xt "36500,27625,38000,28375" 1148 1163 ) 1149 1164 (Line … … 1151 1166 sl 0 1152 1167 ro 90 1153 xt " 42000,28000,42500,28000"1168 xt "36000,28000,36500,28000" 1154 1169 pts [ 1155 " 42500,28000"1156 " 42000,28000"1170 "36500,28000" 1171 "36000,28000" 1157 1172 ] 1158 1173 ) … … 1169 1184 va (VaSet 1170 1185 ) 1171 xt " 45000,27500,50200,28500"1186 xt "39000,27500,44200,28500" 1172 1187 st "config_rd_en" 1173 blo " 45000,28300"1188 blo "39000,28300" 1174 1189 tm "WireNameMgr" 1175 1190 ) … … 1189 1204 sl 0 1190 1205 ro 270 1191 xt " 42500,33625,44000,34375"1206 xt "36500,33625,38000,34375" 1192 1207 ) 1193 1208 (Line … … 1195 1210 sl 0 1196 1211 ro 270 1197 xt " 42000,34000,42500,34000"1212 xt "36000,34000,36500,34000" 1198 1213 pts [ 1199 " 42000,34000"1200 " 42500,34000"1214 "36000,34000" 1215 "36500,34000" 1201 1216 ] 1202 1217 ) … … 1213 1228 va (VaSet 1214 1229 ) 1215 xt " 45000,33500,48700,34500"1230 xt "39000,33500,42700,34500" 1216 1231 st "dac_array" 1217 blo " 45000,34300"1232 blo "39000,34300" 1218 1233 tm "WireNameMgr" 1219 1234 ) … … 1233 1248 sl 0 1234 1249 ro 270 1235 xt " 42500,34625,44000,35375"1250 xt "36500,34625,38000,35375" 1236 1251 ) 1237 1252 (Line … … 1239 1254 sl 0 1240 1255 ro 270 1241 xt " 42000,35000,42500,35000"1256 xt "36000,35000,36500,35000" 1242 1257 pts [ 1243 " 42000,35000"1244 " 42500,35000"1258 "36000,35000" 1259 "36500,35000" 1245 1260 ] 1246 1261 ) … … 1257 1272 va (VaSet 1258 1273 ) 1259 xt " 45000,34500,48400,35500"1274 xt "39000,34500,42400,35500" 1260 1275 st "roi_array" 1261 blo " 45000,35300"1276 blo "39000,35300" 1262 1277 tm "WireNameMgr" 1263 1278 ) … … 1277 1292 sl 0 1278 1293 ro 270 1279 xt " 42500,31625,44000,32375"1294 xt "36500,31625,38000,32375" 1280 1295 ) 1281 1296 (Line … … 1283 1298 sl 0 1284 1299 ro 270 1285 xt " 42000,32000,42500,32000"1300 xt "36000,32000,36500,32000" 1286 1301 pts [ 1287 " 42000,32000"1288 " 42500,32000"1302 "36000,32000" 1303 "36500,32000" 1289 1304 ] 1290 1305 ) … … 1301 1316 va (VaSet 1302 1317 ) 1303 xt " 45000,31500,51600,32500"1318 xt "39000,31500,45600,32500" 1304 1319 st "config_data_valid" 1305 blo " 45000,32300"1320 blo "39000,32300" 1306 1321 tm "WireNameMgr" 1307 1322 ) … … 1321 1336 sl 0 1322 1337 ro 270 1323 xt " 42500,32625,44000,33375"1338 xt "36500,32625,38000,33375" 1324 1339 ) 1325 1340 (Line … … 1327 1342 sl 0 1328 1343 ro 270 1329 xt " 42000,33000,42500,33000"1344 xt "36000,33000,36500,33000" 1330 1345 pts [ 1331 " 42000,33000"1332 " 42500,33000"1346 "36000,33000" 1347 "36500,33000" 1333 1348 ] 1334 1349 ) … … 1345 1360 va (VaSet 1346 1361 ) 1347 xt " 45000,32500,49800,33500"1362 xt "39000,32500,43800,33500" 1348 1363 st "config_busy" 1349 blo " 45000,33300"1364 blo "39000,33300" 1350 1365 tm "WireNameMgr" 1351 1366 ) … … 1365 1380 fg "0,65535,0" 1366 1381 ) 1367 xt " 12250,23625,13000,24375"1382 xt "6250,23625,7000,24375" 1368 1383 ) 1369 1384 tg (CPTG … … 1375 1390 va (VaSet 1376 1391 ) 1377 xt " 14000,23500,15300,24500"1392 xt "8000,23500,9300,24500" 1378 1393 st "clk" 1379 blo " 14000,24300"1394 blo "8000,24300" 1380 1395 ) 1381 1396 ) … … 1401 1416 fg "0,65535,0" 1402 1417 ) 1403 xt "3 8000,28625,38750,29375"1418 xt "32000,28625,32750,29375" 1404 1419 ) 1405 1420 tg (CPTG … … 1411 1426 va (VaSet 1412 1427 ) 1413 xt " 31900,28500,37000,29500"1428 xt "25900,28500,31000,29500" 1414 1429 st "config_ready" 1415 1430 ju 2 1416 blo "3 7000,29300"1431 blo "31000,29300" 1417 1432 ) 1418 1433 ) … … 1440 1455 fg "0,65535,0" 1441 1456 ) 1442 xt "3 8000,29625,38750,30375"1457 xt "32000,29625,32750,30375" 1443 1458 ) 1444 1459 tg (CPTG … … 1450 1465 va (VaSet 1451 1466 ) 1452 xt " 32200,29500,37000,30500"1467 xt "26200,29500,31000,30500" 1453 1468 st "config_start" 1454 1469 ju 2 1455 blo "3 7000,30300"1470 blo "31000,30300" 1456 1471 ) 1457 1472 ) … … 1477 1492 fg "0,65535,0" 1478 1493 ) 1479 xt "3 8000,24625,38750,25375"1494 xt "32000,24625,32750,25375" 1480 1495 ) 1481 1496 tg (CPTG … … 1487 1502 va (VaSet 1488 1503 ) 1489 xt "2 9300,24500,37000,25500"1504 xt "23300,24500,31000,25500" 1490 1505 st "config_data : (15:0)" 1491 1506 ju 2 1492 blo "3 7000,25300"1507 blo "31000,25300" 1493 1508 ) 1494 1509 ) … … 1517 1532 fg "0,65535,0" 1518 1533 ) 1519 xt "3 8000,23625,38750,24375"1534 xt "32000,23625,32750,24375" 1520 1535 ) 1521 1536 tg (CPTG … … 1527 1542 va (VaSet 1528 1543 ) 1529 xt " 23600,23500,37000,24500"1544 xt "17600,23500,31000,24500" 1530 1545 st "config_addr : (ADDR_WIDTH - 1:0)" 1531 1546 ju 2 1532 blo "3 7000,24300"1547 blo "31000,24300" 1533 1548 ) 1534 1549 ) … … 1555 1570 fg "0,65535,0" 1556 1571 ) 1557 xt "3 8000,26625,38750,27375"1572 xt "32000,26625,32750,27375" 1558 1573 ) 1559 1574 tg (CPTG … … 1565 1580 va (VaSet 1566 1581 ) 1567 xt " 31700,26500,37000,27500"1582 xt "25700,26500,31000,27500" 1568 1583 st "config_wr_en" 1569 1584 ju 2 1570 blo "3 7000,27300"1585 blo "31000,27300" 1571 1586 ) 1572 1587 ) … … 1592 1607 fg "0,65535,0" 1593 1608 ) 1594 xt "3 8000,27625,38750,28375"1609 xt "32000,27625,32750,28375" 1595 1610 ) 1596 1611 tg (CPTG … … 1602 1617 va (VaSet 1603 1618 ) 1604 xt " 31800,27500,37000,28500"1619 xt "25800,27500,31000,28500" 1605 1620 st "config_rd_en" 1606 1621 ju 2 1607 blo "3 7000,28300"1622 blo "31000,28300" 1608 1623 ) 1609 1624 ) … … 1629 1644 fg "0,65535,0" 1630 1645 ) 1631 xt "3 8000,31625,38750,32375"1646 xt "32000,31625,32750,32375" 1632 1647 ) 1633 1648 tg (CPTG … … 1639 1654 va (VaSet 1640 1655 ) 1641 xt " 30400,31500,37000,32500"1656 xt "24400,31500,31000,32500" 1642 1657 st "config_data_valid" 1643 1658 ju 2 1644 blo "3 7000,32300"1659 blo "31000,32300" 1645 1660 ) 1646 1661 ) … … 1668 1683 fg "0,65535,0" 1669 1684 ) 1670 xt "3 8000,32625,38750,33375"1685 xt "32000,32625,32750,33375" 1671 1686 ) 1672 1687 tg (CPTG … … 1678 1693 va (VaSet 1679 1694 ) 1680 xt " 32200,32500,37000,33500"1695 xt "26200,32500,31000,33500" 1681 1696 st "config_busy" 1682 1697 ju 2 1683 blo "3 7000,33300"1698 blo "31000,33300" 1684 1699 ) 1685 1700 ) … … 1707 1722 fg "0,65535,0" 1708 1723 ) 1709 xt "3 8000,33625,38750,34375"1724 xt "32000,33625,32750,34375" 1710 1725 ) 1711 1726 tg (CPTG … … 1717 1732 va (VaSet 1718 1733 ) 1719 xt " 33300,33500,37000,34500"1734 xt "27300,33500,31000,34500" 1720 1735 st "dac_array" 1721 1736 ju 2 1722 blo "3 7000,34300"1737 blo "31000,34300" 1723 1738 ) 1724 1739 ) … … 1745 1760 fg "0,65535,0" 1746 1761 ) 1747 xt "3 8000,34625,38750,35375"1762 xt "32000,34625,32750,35375" 1748 1763 ) 1749 1764 tg (CPTG … … 1755 1770 va (VaSet 1756 1771 ) 1757 xt " 33600,34500,37000,35500"1772 xt "27600,34500,31000,35500" 1758 1773 st "roi_array" 1759 1774 ju 2 1760 blo "3 7000,35300"1775 blo "31000,35300" 1761 1776 ) 1762 1777 ) … … 1783 1798 fg "0,65535,0" 1784 1799 ) 1785 xt "3 8000,37625,38750,38375"1800 xt "32000,37625,32750,38375" 1786 1801 ) 1787 1802 tg (CPTG … … 1793 1808 va (VaSet 1794 1809 ) 1795 xt "2 9100,37500,37000,38500"1810 xt "23100,37500,31000,38500" 1796 1811 st "ram_data_in : (15:0)" 1797 1812 ju 2 1798 blo "3 7000,38300"1813 blo "31000,38300" 1799 1814 ) 1800 1815 ) … … 1820 1835 fg "0,65535,0" 1821 1836 ) 1822 xt "3 8000,38625,38750,39375"1837 xt "32000,38625,32750,39375" 1823 1838 ) 1824 1839 tg (CPTG … … 1830 1845 va (VaSet 1831 1846 ) 1832 xt "2 9100,38500,37000,39500"1847 xt "23100,38500,31000,39500" 1833 1848 st "ram_write_en : (0:0)" 1834 1849 ju 2 1835 blo "3 7000,39300"1850 blo "31000,39300" 1836 1851 ) 1837 1852 ) … … 1857 1872 fg "0,65535,0" 1858 1873 ) 1859 xt " 12250,24625,13000,25375"1874 xt "6250,38625,7000,39375" 1860 1875 ) 1861 1876 tg (CPTG … … 1867 1882 va (VaSet 1868 1883 ) 1869 xt " 14000,24500,22300,25500"1884 xt "8000,38500,16300,39500" 1870 1885 st "ram_data_out : (15:0)" 1871 blo " 14000,25300"1886 blo "8000,39300" 1872 1887 ) 1873 1888 ) … … 1892 1907 fg "0,65535,0" 1893 1908 ) 1894 xt "3 8000,39625,38750,40375"1909 xt "32000,39625,32750,40375" 1895 1910 ) 1896 1911 tg (CPTG … … 1902 1917 va (VaSet 1903 1918 ) 1904 xt " 24400,39500,37000,40500"1919 xt "18400,39500,31000,40500" 1905 1920 st "ram_addr : (ADDR_WIDTH - 1:0)" 1906 1921 ju 2 1907 blo "3 7000,40300"1922 blo "31000,40300" 1908 1923 ) 1909 1924 ) … … 1929 1944 fg "0,65535,0" 1930 1945 ) 1931 xt "3 8000,30625,38750,31375"1946 xt "32000,30625,32750,31375" 1932 1947 ) 1933 1948 tg (CPTG … … 1939 1954 va (VaSet 1940 1955 ) 1941 xt " 31400,30500,37000,31500"1956 xt "25400,30500,31000,31500" 1942 1957 st "config_started" 1943 1958 ju 2 1944 blo "3 7000,31300"1959 blo "31000,31300" 1945 1960 ) 1946 1961 ) … … 1956 1971 ) 1957 1972 ) 1973 *55 (CptPort 1974 uid 1198,0 1975 ps "OnEdgeStrategy" 1976 shape (Triangle 1977 uid 1199,0 1978 ro 90 1979 va (VaSet 1980 vasetType 1 1981 fg "0,65535,0" 1982 ) 1983 xt "32000,21625,32750,22375" 1984 ) 1985 tg (CPTG 1986 uid 1200,0 1987 ps "CptPortTextPlaceStrategy" 1988 stg "RightVerticalLayoutStrategy" 1989 f (Text 1990 uid 1201,0 1991 va (VaSet 1992 ) 1993 xt "23800,21500,31000,22500" 1994 st "drs_address : (3:0)" 1995 ju 2 1996 blo "31000,22300" 1997 ) 1998 ) 1999 thePort (LogicalPort 2000 m 1 2001 decl (Decl 2002 n "drs_address" 2003 t "std_logic_vector" 2004 b "(3 DOWNTO 0)" 2005 o 17 2006 suid 24,0 2007 ) 2008 ) 2009 ) 2010 *56 (CptPort 2011 uid 1202,0 2012 ps "OnEdgeStrategy" 2013 shape (Triangle 2014 uid 1203,0 2015 ro 90 2016 va (VaSet 2017 vasetType 1 2018 fg "0,65535,0" 2019 ) 2020 xt "32000,20625,32750,21375" 2021 ) 2022 tg (CPTG 2023 uid 1204,0 2024 ps "CptPortTextPlaceStrategy" 2025 stg "RightVerticalLayoutStrategy" 2026 f (Text 2027 uid 1205,0 2028 va (VaSet 2029 ) 2030 xt "23800,20500,31000,21500" 2031 st "drs_address_mode" 2032 ju 2 2033 blo "31000,21300" 2034 ) 2035 ) 2036 thePort (LogicalPort 2037 m 1 2038 decl (Decl 2039 n "drs_address_mode" 2040 t "std_logic" 2041 o 18 2042 suid 25,0 2043 ) 2044 ) 2045 ) 1958 2046 ] 1959 2047 shape (Rectangle … … 1965 2053 lineWidth 2 1966 2054 ) 1967 xt " 13000,23000,38000,42000"2055 xt "7000,20000,32000,41000" 1968 2056 ) 1969 2057 oxt "42000,14000,67000,32000" … … 1973 2061 stg "VerticalLayoutStrategy" 1974 2062 textVec [ 1975 *5 5(Text2063 *57 (Text 1976 2064 uid 963,0 1977 2065 va (VaSet 1978 2066 font "Arial,8,1" 1979 2067 ) 1980 xt " 12950,42000,19150,43000"2068 xt "6950,42000,13150,43000" 1981 2069 st "FACT_FAD_lib" 1982 blo " 12950,42800"2070 blo "6950,42800" 1983 2071 tm "BdLibraryNameMgr" 1984 2072 ) 1985 *5 6(Text2073 *58 (Text 1986 2074 uid 964,0 1987 2075 va (VaSet 1988 2076 font "Arial,8,1" 1989 2077 ) 1990 xt " 12950,43000,20050,44000"2078 xt "6950,43000,14050,44000" 1991 2079 st "control_manager" 1992 blo " 12950,43800"2080 blo "6950,43800" 1993 2081 tm "CptNameMgr" 1994 2082 ) 1995 *5 7(Text2083 *59 (Text 1996 2084 uid 965,0 1997 2085 va (VaSet 1998 2086 font "Arial,8,1" 1999 2087 ) 2000 xt " 12950,44000,20650,45000"2088 xt "6950,44000,14650,45000" 2001 2089 st "I_control_manager" 2002 blo " 12950,44800"2090 blo "6950,44800" 2003 2091 tm "InstanceNameMgr" 2004 2092 ) … … 2015 2103 font "Courier New,8,0" 2016 2104 ) 2017 xt "1 2500,10600,30000,13000"2105 xt "10000,17600,27500,20000" 2018 2106 st "NO_OF_ROI = 36 ( integer ) 2019 2107 NO_OF_DAC = 8 ( integer ) … … 2047 2135 fg "49152,49152,49152" 2048 2136 ) 2049 xt " 13250,40250,14750,41750"2137 xt "7250,39250,8750,40750" 2050 2138 iconName "VhdlFileViewIcon.png" 2051 2139 iconMaskName "VhdlFileViewIcon.msk" … … 2058 2146 archFileType "UNKNOWN" 2059 2147 ) 2060 * 58(SaComponent2148 *60 (SaComponent 2061 2149 uid 993,0 2062 2150 optionalChildren [ 2063 * 59(CptPort2151 *61 (CptPort 2064 2152 uid 970,0 2065 2153 ps "OnEdgeStrategy" 2066 2154 shape (Triangle 2067 2155 uid 971,0 2068 ro 902156 ro 180 2069 2157 va (VaSet 2070 2158 vasetType 1 2071 2159 fg "0,65535,0" 2072 2160 ) 2073 xt " 19250,50625,20000,51375"2161 xt "42625,41250,43375,42000" 2074 2162 ) 2075 2163 tg (CPTG 2076 2164 uid 972,0 2077 2165 ps "CptPortTextPlaceStrategy" 2078 stg " VerticalLayoutStrategy"2166 stg "RightVerticalLayoutStrategy" 2079 2167 f (Text 2080 2168 uid 973,0 2081 va (VaSet 2082 ) 2083 xt "21000,50500,22700,51500" 2169 ro 270 2170 va (VaSet 2171 ) 2172 xt "42500,43000,43500,44700" 2084 2173 st "clka" 2085 blo "21000,51300" 2174 ju 2 2175 blo "43300,43000" 2086 2176 ) 2087 2177 ) … … 2097 2187 ) 2098 2188 ) 2099 *6 0(CptPort2189 *62 (CptPort 2100 2190 uid 974,0 2101 2191 ps "OnEdgeStrategy" … … 2107 2197 fg "0,65535,0" 2108 2198 ) 2109 xt " 19250,52625,20000,53375"2199 xt "39250,45625,40000,46375" 2110 2200 ) 2111 2201 tg (CPTG … … 2117 2207 va (VaSet 2118 2208 ) 2119 xt " 21000,52500,25800,53500"2209 xt "41000,45500,45800,46500" 2120 2210 st "dina : (15:0)" 2121 blo " 21000,53300"2211 blo "41000,46300" 2122 2212 ) 2123 2213 ) … … 2134 2224 ) 2135 2225 ) 2136 *6 1(CptPort2226 *63 (CptPort 2137 2227 uid 978,0 2138 2228 ps "OnEdgeStrategy" … … 2144 2234 fg "0,65535,0" 2145 2235 ) 2146 xt " 19250,54625,20000,55375"2236 xt "39250,47625,40000,48375" 2147 2237 ) 2148 2238 tg (CPTG … … 2154 2244 va (VaSet 2155 2245 ) 2156 xt " 21000,54500,25900,55500"2246 xt "41000,47500,45900,48500" 2157 2247 st "addra : (7:0)" 2158 blo " 21000,55300"2248 blo "41000,48300" 2159 2249 ) 2160 2250 ) … … 2171 2261 ) 2172 2262 ) 2173 *6 2(CptPort2263 *64 (CptPort 2174 2264 uid 982,0 2175 2265 ps "OnEdgeStrategy" … … 2181 2271 fg "0,65535,0" 2182 2272 ) 2183 xt " 19250,53625,20000,54375"2273 xt "39250,46625,40000,47375" 2184 2274 ) 2185 2275 tg (CPTG … … 2191 2281 va (VaSet 2192 2282 ) 2193 xt " 21000,53500,25300,54500"2283 xt "41000,46500,45300,47500" 2194 2284 st "wea : (0:0)" 2195 blo " 21000,54300"2285 blo "41000,47300" 2196 2286 ) 2197 2287 ) … … 2208 2298 ) 2209 2299 ) 2210 *6 3(CptPort2300 *65 (CptPort 2211 2301 uid 986,0 2212 2302 ps "OnEdgeStrategy" … … 2218 2308 fg "0,65535,0" 2219 2309 ) 2220 xt " 30000,50625,30750,51375"2310 xt "50000,43625,50750,44375" 2221 2311 ) 2222 2312 tg (CPTG … … 2228 2318 va (VaSet 2229 2319 ) 2230 xt " 23800,50500,29000,51500"2320 xt "43800,43500,49000,44500" 2231 2321 st "douta : (15:0)" 2232 2322 ju 2 2233 blo " 29000,51300"2323 blo "49000,44300" 2234 2324 ) 2235 2325 ) … … 2256 2346 lineWidth 2 2257 2347 ) 2258 xt " 20000,49000,30000,59000"2348 xt "40000,42000,50000,52000" 2259 2349 ) 2260 2350 oxt "30000,7000,40000,17000" … … 2264 2354 stg "VerticalLayoutStrategy" 2265 2355 textVec [ 2266 *6 4(Text2356 *66 (Text 2267 2357 uid 996,0 2268 2358 va (VaSet 2269 2359 font "Arial,8,1" 2270 2360 ) 2271 xt " 20200,59000,26400,60000"2361 xt "40200,52000,46400,53000" 2272 2362 st "FACT_FAD_lib" 2273 blo " 20200,59800"2363 blo "40200,52800" 2274 2364 tm "BdLibraryNameMgr" 2275 2365 ) 2276 *6 5(Text2366 *67 (Text 2277 2367 uid 997,0 2278 2368 va (VaSet 2279 2369 font "Arial,8,1" 2280 2370 ) 2281 xt " 20200,60000,30100,61000"2371 xt "40200,53000,50100,54000" 2282 2372 st "controlRAM_16bit_x256" 2283 blo " 20200,60800"2373 blo "40200,53800" 2284 2374 tm "CptNameMgr" 2285 2375 ) 2286 *6 6(Text2376 *68 (Text 2287 2377 uid 998,0 2288 2378 va (VaSet 2289 2379 font "Arial,8,1" 2290 2380 ) 2291 xt " 20200,61000,26100,62000"2381 xt "40200,54000,46100,55000" 2292 2382 st "I_control_ram" 2293 blo " 20200,61800"2383 blo "40200,54800" 2294 2384 tm "InstanceNameMgr" 2295 2385 ) … … 2306 2396 font "Courier New,8,0" 2307 2397 ) 2308 xt " 19500,48000,19500,48000"2398 xt "39500,41000,39500,41000" 2309 2399 ) 2310 2400 header "" … … 2320 2410 fg "49152,49152,49152" 2321 2411 ) 2322 xt " 20250,57250,21750,58750"2412 xt "40250,50250,41750,51750" 2323 2413 iconName "VhdlFileViewIcon.png" 2324 2414 iconMaskName "VhdlFileViewIcon.msk" … … 2332 2422 archFileType "UNKNOWN" 2333 2423 ) 2334 *6 7(Net2424 *69 (Net 2335 2425 uid 1082,0 2336 2426 decl (Decl … … 2346 2436 font "Courier New,8,0" 2347 2437 ) 2348 xt "22000,8400,41500,9200" 2349 st "config_started : std_logic := '0'" 2350 ) 2351 ) 2352 *68 (PortIoOut 2438 xt "29000,8600,48500,9400" 2439 st "config_started : std_logic := '0' 2440 " 2441 ) 2442 ) 2443 *70 (PortIoOut 2353 2444 uid 1090,0 2354 2445 shape (CompositeShape … … 2363 2454 sl 0 2364 2455 ro 270 2365 xt " 42500,30625,44000,31375"2456 xt "36500,30625,38000,31375" 2366 2457 ) 2367 2458 (Line … … 2369 2460 sl 0 2370 2461 ro 270 2371 xt " 42000,31000,42500,31000"2462 xt "36000,31000,36500,31000" 2372 2463 pts [ 2373 " 42000,31000"2374 " 42500,31000"2464 "36000,31000" 2465 "36500,31000" 2375 2466 ] 2376 2467 ) … … 2387 2478 va (VaSet 2388 2479 ) 2389 xt " 45000,30500,50600,31500"2480 xt "39000,30500,44600,31500" 2390 2481 st "config_started" 2391 blo " 45000,31300"2482 blo "39000,31300" 2392 2483 tm "WireNameMgr" 2393 2484 ) 2394 2485 ) 2395 2486 ) 2396 *69 (Wire 2487 *71 (Net 2488 uid 1206,0 2489 decl (Decl 2490 n "drs_address" 2491 t "std_logic_vector" 2492 b "(3 DOWNTO 0)" 2493 o 17 2494 suid 19,0 2495 ) 2496 declText (MLText 2497 uid 1207,0 2498 va (VaSet 2499 font "Courier New,8,0" 2500 ) 2501 xt "29000,10200,55000,11000" 2502 st "drs_address : std_logic_vector(3 DOWNTO 0) 2503 " 2504 ) 2505 ) 2506 *72 (PortIoOut 2507 uid 1214,0 2508 shape (CompositeShape 2509 uid 1215,0 2510 va (VaSet 2511 vasetType 1 2512 fg "0,0,32768" 2513 ) 2514 optionalChildren [ 2515 (Pentagon 2516 uid 1216,0 2517 sl 0 2518 ro 270 2519 xt "36500,21625,38000,22375" 2520 ) 2521 (Line 2522 uid 1217,0 2523 sl 0 2524 ro 270 2525 xt "36000,22000,36500,22000" 2526 pts [ 2527 "36000,22000" 2528 "36500,22000" 2529 ] 2530 ) 2531 ] 2532 ) 2533 stc 0 2534 sf 1 2535 tg (WTG 2536 uid 1218,0 2537 ps "PortIoTextPlaceStrategy" 2538 stg "STSignalDisplayStrategy" 2539 f (Text 2540 uid 1219,0 2541 va (VaSet 2542 ) 2543 xt "39000,21500,44000,22500" 2544 st "drs_address" 2545 blo "39000,22300" 2546 tm "WireNameMgr" 2547 ) 2548 ) 2549 ) 2550 *73 (Net 2551 uid 1220,0 2552 decl (Decl 2553 n "drs_address_mode" 2554 t "std_logic" 2555 o 18 2556 suid 20,0 2557 ) 2558 declText (MLText 2559 uid 1221,0 2560 va (VaSet 2561 font "Courier New,8,0" 2562 ) 2563 xt "29000,11000,45000,11800" 2564 st "drs_address_mode : std_logic 2565 " 2566 ) 2567 ) 2568 *74 (PortIoOut 2569 uid 1228,0 2570 shape (CompositeShape 2571 uid 1229,0 2572 va (VaSet 2573 vasetType 1 2574 fg "0,0,32768" 2575 ) 2576 optionalChildren [ 2577 (Pentagon 2578 uid 1230,0 2579 sl 0 2580 ro 270 2581 xt "36500,20625,38000,21375" 2582 ) 2583 (Line 2584 uid 1231,0 2585 sl 0 2586 ro 270 2587 xt "36000,21000,36500,21000" 2588 pts [ 2589 "36000,21000" 2590 "36500,21000" 2591 ] 2592 ) 2593 ] 2594 ) 2595 stc 0 2596 sf 1 2597 tg (WTG 2598 uid 1232,0 2599 ps "PortIoTextPlaceStrategy" 2600 stg "STSignalDisplayStrategy" 2601 f (Text 2602 uid 1233,0 2603 va (VaSet 2604 ) 2605 xt "39000,20500,46200,21500" 2606 st "drs_address_mode" 2607 blo "39000,21300" 2608 tm "WireNameMgr" 2609 ) 2610 ) 2611 ) 2612 *75 (Wire 2397 2613 uid 227,0 2398 2614 shape (OrthoPolyLine … … 2402 2618 lineWidth 2 2403 2619 ) 2404 xt "3 8750,24000,42000,24000"2620 xt "32750,24000,36000,24000" 2405 2621 pts [ 2406 "42000,24000" 2407 "40000,24000" 2408 "38750,24000" 2622 "36000,24000" 2623 "32750,24000" 2409 2624 ] 2410 2625 ) … … 2427 2642 isHidden 1 2428 2643 ) 2429 xt " 45000,23000,49800,24000"2644 xt "39000,23000,43800,24000" 2430 2645 st "config_addr" 2431 blo " 45000,23800"2646 blo "39000,23800" 2432 2647 tm "WireNameMgr" 2433 2648 ) … … 2435 2650 on &14 2436 2651 ) 2437 *7 0(Wire2652 *76 (Wire 2438 2653 uid 233,0 2439 2654 shape (OrthoPolyLine … … 2443 2658 lineWidth 2 2444 2659 ) 2445 xt " 13000,39000,43000,54000"2660 xt "32750,39000,39250,47000" 2446 2661 pts [ 2447 "19250,54000" 2448 "13000,54000" 2449 "13000,47000" 2450 "43000,47000" 2451 "43000,39000" 2452 "38750,39000" 2453 ] 2454 ) 2455 start &62 2662 "39250,47000" 2663 "34000,47000" 2664 "34000,39000" 2665 "32750,39000" 2666 ] 2667 ) 2668 start &64 2456 2669 end &51 2457 2670 sat 32 … … 2469 2682 va (VaSet 2470 2683 ) 2471 xt " 23000,46000,29300,47000"2684 xt "34000,46000,40300,47000" 2472 2685 st "ram_wren : (0:0)" 2473 blo " 23000,46800"2686 blo "34000,46800" 2474 2687 tm "WireNameMgr" 2475 2688 ) … … 2477 2690 on &13 2478 2691 ) 2479 *7 1(Wire2692 *77 (Wire 2480 2693 uid 237,0 2481 2694 shape (OrthoPolyLine … … 2485 2698 lineWidth 2 2486 2699 ) 2487 xt " 14000,38000,44000,53000"2700 xt "32750,38000,39250,46000" 2488 2701 pts [ 2489 "19250,53000" 2490 "14000,53000" 2491 "14000,48000" 2492 "44000,48000" 2493 "44000,38000" 2494 "38750,38000" 2495 ] 2496 ) 2497 start &60 2702 "39250,46000" 2703 "35000,46000" 2704 "35000,38000" 2705 "32750,38000" 2706 ] 2707 ) 2708 start &62 2498 2709 end &50 2499 2710 sat 32 … … 2511 2722 va (VaSet 2512 2723 ) 2513 xt " 23000,47000,30900,48000"2724 xt "33000,37000,40900,38000" 2514 2725 st "ram_data_in : (15:0)" 2515 blo " 23000,47800"2726 blo "33000,37800" 2516 2727 tm "WireNameMgr" 2517 2728 ) … … 2519 2730 on &15 2520 2731 ) 2521 *7 2(Wire2732 *78 (Wire 2522 2733 uid 241,0 2523 2734 shape (OrthoPolyLine … … 2526 2737 vasetType 3 2527 2738 ) 2528 xt " 5000,24000,12250,24000"2739 xt "4000,20000,6250,24000" 2529 2740 pts [ 2741 "4000,20000" 2742 "5000,20000" 2530 2743 "5000,24000" 2531 " 12250,24000"2744 "6250,24000" 2532 2745 ] 2533 2746 ) … … 2549 2762 isHidden 1 2550 2763 ) 2551 xt " 7000,23000,8300,24000"2764 xt "6000,19000,7300,20000" 2552 2765 st "clk" 2553 blo " 7000,23800"2766 blo "6000,19800" 2554 2767 tm "WireNameMgr" 2555 2768 ) … … 2557 2770 on &12 2558 2771 ) 2559 *7 3(Wire2772 *79 (Wire 2560 2773 uid 255,0 2561 2774 shape (OrthoPolyLine … … 2564 2777 vasetType 3 2565 2778 ) 2566 xt "3 8750,32000,42000,32000"2779 xt "32750,32000,36000,32000" 2567 2780 pts [ 2568 "3 8750,32000"2569 " 42000,32000"2781 "32750,32000" 2782 "36000,32000" 2570 2783 ] 2571 2784 ) … … 2587 2800 isHidden 1 2588 2801 ) 2589 xt " 45000,30000,51600,31000"2802 xt "39000,30000,45600,31000" 2590 2803 st "config_data_valid" 2591 blo " 45000,30800"2804 blo "39000,30800" 2592 2805 tm "WireNameMgr" 2593 2806 ) … … 2595 2808 on &16 2596 2809 ) 2597 * 74(Wire2810 *80 (Wire 2598 2811 uid 261,0 2599 2812 shape (OrthoPolyLine … … 2602 2815 vasetType 3 2603 2816 ) 2604 xt "3 8750,33000,42000,33000"2817 xt "32750,33000,36000,33000" 2605 2818 pts [ 2606 "3 8750,33000"2607 " 42000,33000"2819 "32750,33000" 2820 "36000,33000" 2608 2821 ] 2609 2822 ) … … 2625 2838 isHidden 1 2626 2839 ) 2627 xt " 45000,31000,49800,32000"2840 xt "39000,31000,43800,32000" 2628 2841 st "config_busy" 2629 blo " 45000,31800"2842 blo "39000,31800" 2630 2843 tm "WireNameMgr" 2631 2844 ) … … 2633 2846 on &17 2634 2847 ) 2635 * 75(Wire2848 *81 (Wire 2636 2849 uid 267,0 2637 2850 shape (OrthoPolyLine … … 2641 2854 lineWidth 2 2642 2855 ) 2643 xt "3 8750,25000,42000,25000"2856 xt "32750,25000,36000,25000" 2644 2857 pts [ 2645 "42000,25000" 2646 "40000,25000" 2647 "38750,25000" 2858 "36000,25000" 2859 "32750,25000" 2648 2860 ] 2649 2861 ) … … 2666 2878 isHidden 1 2667 2879 ) 2668 xt " 45000,24000,49700,25000"2880 xt "39000,24000,43700,25000" 2669 2881 st "config_data" 2670 blo " 45000,24800"2882 blo "39000,24800" 2671 2883 tm "WireNameMgr" 2672 2884 ) … … 2674 2886 on &18 2675 2887 ) 2676 * 76(Wire2888 *82 (Wire 2677 2889 uid 273,0 2678 2890 shape (OrthoPolyLine … … 2681 2893 vasetType 3 2682 2894 ) 2683 xt "3 8750,35000,42000,35000"2895 xt "32750,35000,36000,35000" 2684 2896 pts [ 2685 "38750,35000" 2686 "40000,35000" 2687 "42000,35000" 2897 "32750,35000" 2898 "36000,35000" 2688 2899 ] 2689 2900 ) … … 2705 2916 isHidden 1 2706 2917 ) 2707 xt " 45000,34000,48400,35000"2918 xt "39000,34000,42400,35000" 2708 2919 st "roi_array" 2709 blo " 45000,34800"2920 blo "39000,34800" 2710 2921 tm "WireNameMgr" 2711 2922 ) … … 2713 2924 on &19 2714 2925 ) 2715 * 77(Wire2926 *83 (Wire 2716 2927 uid 279,0 2717 2928 shape (OrthoPolyLine … … 2720 2931 vasetType 3 2721 2932 ) 2722 xt " 17000,51000,19250,51000"2933 xt "43000,38000,43000,41250" 2723 2934 pts [ 2724 " 17000,51000"2725 " 19250,51000"2726 ] 2727 ) 2728 end & 592935 "43000,38000" 2936 "43000,41250" 2937 ] 2938 ) 2939 end &61 2729 2940 sat 16 2730 2941 eat 32 … … 2740 2951 va (VaSet 2741 2952 ) 2742 xt " 18000,50000,19300,51000"2953 xt "44000,37000,45300,38000" 2743 2954 st "clk" 2744 blo " 18000,50800"2955 blo "44000,37800" 2745 2956 tm "WireNameMgr" 2746 2957 ) … … 2748 2959 on &12 2749 2960 ) 2750 * 78(Wire2961 *84 (Wire 2751 2962 uid 285,0 2752 2963 shape (OrthoPolyLine … … 2756 2967 lineWidth 2 2757 2968 ) 2758 xt " 12000,40000,42000,55000"2969 xt "32750,40000,39250,48000" 2759 2970 pts [ 2760 "38750,40000" 2761 "42000,40000" 2762 "42000,46000" 2763 "12000,46000" 2764 "12000,55000" 2765 "19250,55000" 2971 "32750,40000" 2972 "33000,40000" 2973 "33000,48000" 2974 "39250,48000" 2766 2975 ] 2767 2976 ) 2768 2977 start &53 2769 end &6 12978 end &63 2770 2979 sat 32 2771 2980 eat 32 … … 2782 2991 va (VaSet 2783 2992 ) 2784 xt " 23000,45000,29200,46000"2993 xt "33000,47000,39200,48000" 2785 2994 st "ram_addr : (7:0)" 2786 blo " 23000,45800"2995 blo "33000,47800" 2787 2996 tm "WireNameMgr" 2788 2997 ) … … 2790 2999 on &20 2791 3000 ) 2792 * 79(Wire3001 *85 (Wire 2793 3002 uid 289,0 2794 3003 shape (OrthoPolyLine … … 2797 3006 vasetType 3 2798 3007 ) 2799 xt "3 8750,30000,42000,30000"3008 xt "32750,30000,36000,30000" 2800 3009 pts [ 2801 "42000,30000" 2802 "40000,30000" 2803 "38750,30000" 3010 "36000,30000" 3011 "32750,30000" 2804 3012 ] 2805 3013 ) … … 2821 3029 isHidden 1 2822 3030 ) 2823 xt " 45000,29000,49800,30000"3031 xt "39000,29000,43800,30000" 2824 3032 st "config_start" 2825 blo " 45000,29800"3033 blo "39000,29800" 2826 3034 tm "WireNameMgr" 2827 3035 ) … … 2829 3037 on &25 2830 3038 ) 2831 *8 0(Wire3039 *86 (Wire 2832 3040 uid 295,0 2833 3041 shape (OrthoPolyLine … … 2836 3044 vasetType 3 2837 3045 ) 2838 xt "3 8750,27000,42000,27000"3046 xt "32750,27000,36000,27000" 2839 3047 pts [ 2840 "42000,27000" 2841 "40000,27000" 2842 "38750,27000" 3048 "36000,27000" 3049 "32750,27000" 2843 3050 ] 2844 3051 ) … … 2860 3067 isHidden 1 2861 3068 ) 2862 xt " 45000,26000,50300,27000"3069 xt "39000,26000,44300,27000" 2863 3070 st "config_wr_en" 2864 blo " 45000,26800"3071 blo "39000,26800" 2865 3072 tm "WireNameMgr" 2866 3073 ) … … 2868 3075 on &21 2869 3076 ) 2870 *8 1(Wire3077 *87 (Wire 2871 3078 uid 301,0 2872 3079 shape (OrthoPolyLine … … 2876 3083 lineWidth 2 2877 3084 ) 2878 xt " 9000,25000,34000,64000"3085 xt "3000,39000,52000,56000" 2879 3086 pts [ 2880 " 12250,25000"2881 " 9000,25000"2882 " 9000,64000"2883 " 34000,64000"2884 " 34000,51000"2885 " 30750,51000"3087 "6250,39000" 3088 "3000,39000" 3089 "3000,56000" 3090 "52000,56000" 3091 "52000,44000" 3092 "50750,44000" 2886 3093 ] 2887 3094 ) 2888 3095 start &52 2889 end &6 33096 end &65 2890 3097 sat 32 2891 3098 eat 32 … … 2902 3109 va (VaSet 2903 3110 ) 2904 xt " 20000,63000,28300,64000"3111 xt "33000,55000,41300,56000" 2905 3112 st "ram_data_out : (15:0)" 2906 blo " 20000,63800"3113 blo "33000,55800" 2907 3114 tm "WireNameMgr" 2908 3115 ) … … 2910 3117 on &22 2911 3118 ) 2912 *8 2(Wire3119 *88 (Wire 2913 3120 uid 305,0 2914 3121 shape (OrthoPolyLine … … 2917 3124 vasetType 3 2918 3125 ) 2919 xt "3 8750,34000,42000,34000"3126 xt "32750,34000,36000,34000" 2920 3127 pts [ 2921 "38750,34000" 2922 "40000,34000" 2923 "42000,34000" 3128 "32750,34000" 3129 "36000,34000" 2924 3130 ] 2925 3131 ) … … 2941 3147 isHidden 1 2942 3148 ) 2943 xt " 45000,33000,48700,34000"3149 xt "39000,33000,42700,34000" 2944 3150 st "dac_array" 2945 blo " 45000,33800"3151 blo "39000,33800" 2946 3152 tm "WireNameMgr" 2947 3153 ) … … 2949 3155 on &23 2950 3156 ) 2951 *8 3(Wire3157 *89 (Wire 2952 3158 uid 311,0 2953 3159 shape (OrthoPolyLine … … 2956 3162 vasetType 3 2957 3163 ) 2958 xt "3 8750,28000,42000,28000"3164 xt "32750,28000,36000,28000" 2959 3165 pts [ 2960 "42000,28000" 2961 "40000,28000" 2962 "38750,28000" 3166 "36000,28000" 3167 "32750,28000" 2963 3168 ] 2964 3169 ) … … 2980 3185 isHidden 1 2981 3186 ) 2982 xt " 45000,27000,50200,28000"3187 xt "39000,27000,44200,28000" 2983 3188 st "config_rd_en" 2984 blo " 45000,27800"3189 blo "39000,27800" 2985 3190 tm "WireNameMgr" 2986 3191 ) … … 2988 3193 on &24 2989 3194 ) 2990 * 84(Wire3195 *90 (Wire 2991 3196 uid 321,0 2992 3197 shape (OrthoPolyLine … … 2995 3200 vasetType 3 2996 3201 ) 2997 xt "3 8750,29000,42000,29000"3202 xt "32750,29000,36000,29000" 2998 3203 pts [ 2999 "38750,29000" 3000 "40000,29000" 3001 "42000,29000" 3204 "32750,29000" 3205 "36000,29000" 3002 3206 ] 3003 3207 ) … … 3019 3223 isHidden 1 3020 3224 ) 3021 xt " 45000,28000,50100,29000"3225 xt "39000,28000,44100,29000" 3022 3226 st "config_ready" 3023 blo " 45000,28800"3227 blo "39000,28800" 3024 3228 tm "WireNameMgr" 3025 3229 ) … … 3027 3231 on &26 3028 3232 ) 3029 * 85(Wire3233 *91 (Wire 3030 3234 uid 1084,0 3031 3235 shape (OrthoPolyLine … … 3034 3238 vasetType 3 3035 3239 ) 3036 xt "3 8750,31000,42000,31000"3240 xt "32750,31000,36000,31000" 3037 3241 pts [ 3038 "3 8750,31000"3039 " 42000,31000"3242 "32750,31000" 3243 "36000,31000" 3040 3244 ] 3041 3245 ) 3042 3246 start &54 3043 end & 683247 end &70 3044 3248 sat 32 3045 3249 eat 32 … … 3057 3261 isHidden 1 3058 3262 ) 3059 xt " 40000,30000,45600,31000"3263 xt "34000,30000,39600,31000" 3060 3264 st "config_started" 3061 blo " 40000,30800"3265 blo "34000,30800" 3062 3266 tm "WireNameMgr" 3063 3267 ) 3064 3268 ) 3065 on &67 3269 on &69 3270 ) 3271 *92 (Wire 3272 uid 1208,0 3273 shape (OrthoPolyLine 3274 uid 1209,0 3275 va (VaSet 3276 vasetType 3 3277 lineWidth 2 3278 ) 3279 xt "32750,22000,36000,22000" 3280 pts [ 3281 "32750,22000" 3282 "36000,22000" 3283 ] 3284 ) 3285 start &55 3286 end &72 3287 sat 32 3288 eat 32 3289 sty 1 3290 stc 0 3291 st 0 3292 sf 1 3293 si 0 3294 tg (WTG 3295 uid 1212,0 3296 ps "ConnStartEndStrategy" 3297 stg "STSignalDisplayStrategy" 3298 f (Text 3299 uid 1213,0 3300 va (VaSet 3301 isHidden 1 3302 ) 3303 xt "34000,21000,39000,22000" 3304 st "drs_address" 3305 blo "34000,21800" 3306 tm "WireNameMgr" 3307 ) 3308 ) 3309 on &71 3310 ) 3311 *93 (Wire 3312 uid 1222,0 3313 shape (OrthoPolyLine 3314 uid 1223,0 3315 va (VaSet 3316 vasetType 3 3317 ) 3318 xt "32750,21000,36000,21000" 3319 pts [ 3320 "32750,21000" 3321 "36000,21000" 3322 ] 3323 ) 3324 start &56 3325 end &74 3326 sat 32 3327 eat 32 3328 stc 0 3329 st 0 3330 sf 1 3331 si 0 3332 tg (WTG 3333 uid 1226,0 3334 ps "ConnStartEndStrategy" 3335 stg "STSignalDisplayStrategy" 3336 f (Text 3337 uid 1227,0 3338 va (VaSet 3339 isHidden 1 3340 ) 3341 xt "34000,20000,41200,21000" 3342 st "drs_address_mode" 3343 blo "34000,20800" 3344 tm "WireNameMgr" 3345 ) 3346 ) 3347 on &73 3066 3348 ) 3067 3349 ] … … 3077 3359 color "26368,26368,26368" 3078 3360 ) 3079 packageList * 86(PackageList3361 packageList *94 (PackageList 3080 3362 uid 41,0 3081 3363 stg "VerticalLayoutStrategy" 3082 3364 textVec [ 3083 * 87(Text3365 *95 (Text 3084 3366 uid 42,0 3085 3367 va (VaSet 3086 3368 font "arial,8,1" 3087 3369 ) 3088 xt " 0,0,5400,1000"3370 xt "1000,1000,6400,2000" 3089 3371 st "Package List" 3090 blo " 0,800"3091 ) 3092 * 88(MLText3372 blo "1000,1800" 3373 ) 3374 *96 (MLText 3093 3375 uid 43,0 3094 3376 va (VaSet 3095 3377 ) 3096 xt " 0,1000,15300,6000"3378 xt "1000,2000,16300,7000" 3097 3379 st "LIBRARY ieee; 3098 3380 USE ieee.std_logic_1164.ALL; … … 3108 3390 stg "VerticalLayoutStrategy" 3109 3391 textVec [ 3110 * 89(Text3392 *97 (Text 3111 3393 uid 45,0 3112 3394 va (VaSet … … 3118 3400 blo "20000,800" 3119 3401 ) 3120 *9 0(Text3402 *98 (Text 3121 3403 uid 46,0 3122 3404 va (VaSet … … 3128 3410 blo "20000,1800" 3129 3411 ) 3130 *9 1(MLText3412 *99 (MLText 3131 3413 uid 47,0 3132 3414 va (VaSet … … 3138 3420 tm "BdCompilerDirectivesTextMgr" 3139 3421 ) 3140 * 92(Text3422 *100 (Text 3141 3423 uid 48,0 3142 3424 va (VaSet … … 3148 3430 blo "20000,4800" 3149 3431 ) 3150 * 93(MLText3432 *101 (MLText 3151 3433 uid 49,0 3152 3434 va (VaSet … … 3156 3438 tm "BdCompilerDirectivesTextMgr" 3157 3439 ) 3158 * 94(Text3440 *102 (Text 3159 3441 uid 50,0 3160 3442 va (VaSet … … 3166 3448 blo "20000,5800" 3167 3449 ) 3168 * 95(MLText3450 *103 (MLText 3169 3451 uid 51,0 3170 3452 va (VaSet … … 3177 3459 associable 1 3178 3460 ) 3179 windowSize "0, 22,1286,1024"3180 viewArea " 834,29654,54098,72685"3181 cachedDiagramExtent " 0,0,53000,77000"3461 windowSize "0,0,1281,1002" 3462 viewArea "-6400,12000,60443,65739" 3463 cachedDiagramExtent "700,0,59000,77000" 3182 3464 pageSetupInfo (PageSetupInfo 3183 3465 ptrCmd "Brother HL-5270DN series,winspool," … … 3205 3487 hasePageBreakOrigin 1 3206 3488 pageBreakOrigin "0,0" 3207 lastUid 1 122,03489 lastUid 1237,0 3208 3490 defaultCommentText (CommentText 3209 3491 shape (Rectangle … … 3267 3549 stg "VerticalLayoutStrategy" 3268 3550 textVec [ 3269 * 96(Text3551 *104 (Text 3270 3552 va (VaSet 3271 3553 font "Arial,8,1" … … 3276 3558 tm "BdLibraryNameMgr" 3277 3559 ) 3278 * 97(Text3560 *105 (Text 3279 3561 va (VaSet 3280 3562 font "Arial,8,1" … … 3285 3567 tm "BlkNameMgr" 3286 3568 ) 3287 * 98(Text3569 *106 (Text 3288 3570 va (VaSet 3289 3571 font "Arial,8,1" … … 3336 3618 stg "VerticalLayoutStrategy" 3337 3619 textVec [ 3338 * 99(Text3620 *107 (Text 3339 3621 va (VaSet 3340 3622 font "Arial,8,1" … … 3344 3626 blo "550,4300" 3345 3627 ) 3346 *10 0(Text3628 *108 (Text 3347 3629 va (VaSet 3348 3630 font "Arial,8,1" … … 3352 3634 blo "550,5300" 3353 3635 ) 3354 *10 1(Text3636 *109 (Text 3355 3637 va (VaSet 3356 3638 font "Arial,8,1" … … 3401 3683 stg "VerticalLayoutStrategy" 3402 3684 textVec [ 3403 *1 02(Text3685 *110 (Text 3404 3686 va (VaSet 3405 3687 font "Arial,8,1" … … 3410 3692 tm "BdLibraryNameMgr" 3411 3693 ) 3412 *1 03(Text3694 *111 (Text 3413 3695 va (VaSet 3414 3696 font "Arial,8,1" … … 3419 3701 tm "CptNameMgr" 3420 3702 ) 3421 *1 04(Text3703 *112 (Text 3422 3704 va (VaSet 3423 3705 font "Arial,8,1" … … 3473 3755 stg "VerticalLayoutStrategy" 3474 3756 textVec [ 3475 *1 05(Text3757 *113 (Text 3476 3758 va (VaSet 3477 3759 font "Arial,8,1" … … 3481 3763 blo "500,4300" 3482 3764 ) 3483 *1 06(Text3765 *114 (Text 3484 3766 va (VaSet 3485 3767 font "Arial,8,1" … … 3489 3771 blo "500,5300" 3490 3772 ) 3491 *1 07(Text3773 *115 (Text 3492 3774 va (VaSet 3493 3775 font "Arial,8,1" … … 3534 3816 stg "VerticalLayoutStrategy" 3535 3817 textVec [ 3536 *1 08(Text3818 *116 (Text 3537 3819 va (VaSet 3538 3820 font "Arial,8,1" … … 3542 3824 blo "50,4300" 3543 3825 ) 3544 *1 09(Text3826 *117 (Text 3545 3827 va (VaSet 3546 3828 font "Arial,8,1" … … 3550 3832 blo "50,5300" 3551 3833 ) 3552 *11 0(Text3834 *118 (Text 3553 3835 va (VaSet 3554 3836 font "Arial,8,1" … … 3591 3873 stg "VerticalLayoutStrategy" 3592 3874 textVec [ 3593 *11 1(Text3875 *119 (Text 3594 3876 va (VaSet 3595 3877 font "Arial,8,1" … … 3600 3882 tm "HdlTextNameMgr" 3601 3883 ) 3602 *1 12(Text3884 *120 (Text 3603 3885 va (VaSet 3604 3886 font "Arial,8,1" … … 4003 4285 stg "VerticalLayoutStrategy" 4004 4286 textVec [ 4005 *1 13(Text4287 *121 (Text 4006 4288 va (VaSet 4007 4289 font "Arial,8,1" … … 4011 4293 blo "14100,20800" 4012 4294 ) 4013 *1 14(MLText4295 *122 (MLText 4014 4296 va (VaSet 4015 4297 ) … … 4063 4345 stg "VerticalLayoutStrategy" 4064 4346 textVec [ 4065 *1 15(Text4347 *123 (Text 4066 4348 va (VaSet 4067 4349 font "Arial,8,1" … … 4071 4353 blo "14100,20800" 4072 4354 ) 4073 *1 16(MLText4355 *124 (MLText 4074 4356 va (VaSet 4075 4357 ) … … 4152 4434 font "Arial,8,1" 4153 4435 ) 4154 xt "2 0000,0,25400,1000"4436 xt "27000,200,32400,1200" 4155 4437 st "Declarations" 4156 blo "2 0000,800"4438 blo "27000,1000" 4157 4439 ) 4158 4440 portLabel (Text … … 4161 4443 font "Arial,8,1" 4162 4444 ) 4163 xt "2 0000,1000,22700,2000"4445 xt "27000,1200,29700,2200" 4164 4446 st "Ports:" 4165 blo "2 0000,1800"4447 blo "27000,2000" 4166 4448 ) 4167 4449 preUserLabel (Text … … 4171 4453 font "Arial,8,1" 4172 4454 ) 4173 xt "2 0000,0,23800,1000"4455 xt "27000,200,30800,1200" 4174 4456 st "Pre User:" 4175 blo "2 0000,800"4457 blo "27000,1000" 4176 4458 ) 4177 4459 preUserText (MLText … … 4181 4463 font "Courier New,8,0" 4182 4464 ) 4183 xt "2 0000,0,20000,0"4465 xt "27000,200,27000,200" 4184 4466 tm "BdDeclarativeTextMgr" 4185 4467 ) … … 4189 4471 font "Arial,8,1" 4190 4472 ) 4191 xt "2 0000,11600,27100,12600"4473 xt "27000,13400,34100,14400" 4192 4474 st "Diagram Signals:" 4193 blo "2 0000,12400"4475 blo "27000,14200" 4194 4476 ) 4195 4477 postUserLabel (Text … … 4199 4481 font "Arial,8,1" 4200 4482 ) 4201 xt "2 0000,0,24700,1000"4483 xt "27000,200,31700,1200" 4202 4484 st "Post User:" 4203 blo "2 0000,800"4485 blo "27000,1000" 4204 4486 ) 4205 4487 postUserText (MLText … … 4209 4491 font "Courier New,8,0" 4210 4492 ) 4211 xt "2 0000,0,20000,0"4493 xt "27000,200,27000,200" 4212 4494 tm "BdDeclarativeTextMgr" 4213 4495 ) … … 4215 4497 commonDM (CommonDM 4216 4498 ldm (LogicalDM 4217 suid 18,04499 suid 20,0 4218 4500 usingSuid 1 4219 emptyRow *1 17(LEmptyRow4501 emptyRow *125 (LEmptyRow 4220 4502 ) 4221 4503 uid 54,0 4222 4504 optionalChildren [ 4223 *1 18(RefLabelRowHdr4224 ) 4225 *1 19(TitleRowHdr4226 ) 4227 *12 0(FilterRowHdr4228 ) 4229 *12 1(RefLabelColHdr4505 *126 (RefLabelRowHdr 4506 ) 4507 *127 (TitleRowHdr 4508 ) 4509 *128 (FilterRowHdr 4510 ) 4511 *129 (RefLabelColHdr 4230 4512 tm "RefLabelColHdrMgr" 4231 4513 ) 4232 *1 22(RowExpandColHdr4514 *130 (RowExpandColHdr 4233 4515 tm "RowExpandColHdrMgr" 4234 4516 ) 4235 *1 23(GroupColHdr4517 *131 (GroupColHdr 4236 4518 tm "GroupColHdrMgr" 4237 4519 ) 4238 *1 24(NameColHdr4520 *132 (NameColHdr 4239 4521 tm "BlockDiagramNameColHdrMgr" 4240 4522 ) 4241 *1 25(ModeColHdr4523 *133 (ModeColHdr 4242 4524 tm "BlockDiagramModeColHdrMgr" 4243 4525 ) 4244 *1 26(TypeColHdr4526 *134 (TypeColHdr 4245 4527 tm "BlockDiagramTypeColHdrMgr" 4246 4528 ) 4247 *1 27(BoundsColHdr4529 *135 (BoundsColHdr 4248 4530 tm "BlockDiagramBoundsColHdrMgr" 4249 4531 ) 4250 *1 28(InitColHdr4532 *136 (InitColHdr 4251 4533 tm "BlockDiagramInitColHdrMgr" 4252 4534 ) 4253 *1 29(EolColHdr4535 *137 (EolColHdr 4254 4536 tm "BlockDiagramEolColHdrMgr" 4255 4537 ) 4256 *13 0(LeafLogPort4538 *138 (LeafLogPort 4257 4539 port (LogicalPort 4258 4540 decl (Decl … … 4265 4547 uid 427,0 4266 4548 ) 4267 *13 1(LeafLogPort4549 *139 (LeafLogPort 4268 4550 port (LogicalPort 4269 4551 m 4 … … 4278 4560 uid 429,0 4279 4561 ) 4280 *1 32(LeafLogPort4562 *140 (LeafLogPort 4281 4563 port (LogicalPort 4282 4564 decl (Decl … … 4290 4572 uid 431,0 4291 4573 ) 4292 *1 33(LeafLogPort4574 *141 (LeafLogPort 4293 4575 port (LogicalPort 4294 4576 m 4 … … 4303 4585 uid 433,0 4304 4586 ) 4305 *1 34(LeafLogPort4587 *142 (LeafLogPort 4306 4588 port (LogicalPort 4307 4589 m 1 … … 4315 4597 uid 435,0 4316 4598 ) 4317 *1 35(LeafLogPort4599 *143 (LeafLogPort 4318 4600 port (LogicalPort 4319 4601 m 1 … … 4327 4609 uid 437,0 4328 4610 ) 4329 *1 36(LeafLogPort4611 *144 (LeafLogPort 4330 4612 port (LogicalPort 4331 4613 m 2 … … 4340 4622 uid 439,0 4341 4623 ) 4342 *1 37(LeafLogPort4624 *145 (LeafLogPort 4343 4625 port (LogicalPort 4344 4626 m 1 … … 4352 4634 uid 441,0 4353 4635 ) 4354 *1 38(LeafLogPort4636 *146 (LeafLogPort 4355 4637 port (LogicalPort 4356 4638 m 4 … … 4365 4647 uid 443,0 4366 4648 ) 4367 *1 39(LeafLogPort4649 *147 (LeafLogPort 4368 4650 port (LogicalPort 4369 4651 decl (Decl … … 4376 4658 uid 445,0 4377 4659 ) 4378 *14 0(LeafLogPort4660 *148 (LeafLogPort 4379 4661 port (LogicalPort 4380 4662 m 4 … … 4389 4671 uid 447,0 4390 4672 ) 4391 *14 1(LeafLogPort4673 *149 (LeafLogPort 4392 4674 port (LogicalPort 4393 4675 m 1 … … 4401 4683 uid 449,0 4402 4684 ) 4403 *1 42(LeafLogPort4685 *150 (LeafLogPort 4404 4686 port (LogicalPort 4405 4687 decl (Decl … … 4412 4694 uid 451,0 4413 4695 ) 4414 *1 43(LeafLogPort4696 *151 (LeafLogPort 4415 4697 port (LogicalPort 4416 4698 decl (Decl … … 4423 4705 uid 453,0 4424 4706 ) 4425 *1 44(LeafLogPort4707 *152 (LeafLogPort 4426 4708 port (LogicalPort 4427 4709 m 1 … … 4435 4717 uid 457,0 4436 4718 ) 4437 *1 45(LeafLogPort4719 *153 (LeafLogPort 4438 4720 port (LogicalPort 4439 4721 m 1 … … 4448 4730 uid 1096,0 4449 4731 ) 4732 *154 (LeafLogPort 4733 port (LogicalPort 4734 m 1 4735 decl (Decl 4736 n "drs_address" 4737 t "std_logic_vector" 4738 b "(3 DOWNTO 0)" 4739 o 17 4740 suid 19,0 4741 ) 4742 ) 4743 uid 1234,0 4744 ) 4745 *155 (LeafLogPort 4746 port (LogicalPort 4747 m 1 4748 decl (Decl 4749 n "drs_address_mode" 4750 t "std_logic" 4751 o 18 4752 suid 20,0 4753 ) 4754 ) 4755 uid 1236,0 4756 ) 4450 4757 ] 4451 4758 ) … … 4455 4762 uid 67,0 4456 4763 optionalChildren [ 4457 *1 46 (Sheet4764 *156 (Sheet 4458 4765 sheetRow (SheetRow 4459 4766 headerVa (MVa … … 4472 4779 font "Tahoma,10,0" 4473 4780 ) 4474 emptyMRCItem *1 47 (MRCItem4475 litem &1 174476 pos 1 64781 emptyMRCItem *157 (MRCItem 4782 litem &125 4783 pos 18 4477 4784 dimension 20 4478 4785 ) 4479 4786 uid 69,0 4480 4787 optionalChildren [ 4481 *1 48 (MRCItem4482 litem &1 184788 *158 (MRCItem 4789 litem &126 4483 4790 pos 0 4484 4791 dimension 20 4485 4792 uid 70,0 4486 4793 ) 4487 *1 49 (MRCItem4488 litem &1 194794 *159 (MRCItem 4795 litem &127 4489 4796 pos 1 4490 4797 dimension 23 4491 4798 uid 71,0 4492 4799 ) 4493 *1 50 (MRCItem4494 litem &12 04800 *160 (MRCItem 4801 litem &128 4495 4802 pos 2 4496 4803 hidden 1 … … 4498 4805 uid 72,0 4499 4806 ) 4500 *1 51 (MRCItem4501 litem &13 04807 *161 (MRCItem 4808 litem &138 4502 4809 pos 0 4503 4810 dimension 20 4504 4811 uid 428,0 4505 4812 ) 4506 *1 52 (MRCItem4507 litem &13 14813 *162 (MRCItem 4814 litem &139 4508 4815 pos 11 4509 4816 dimension 20 4510 4817 uid 430,0 4511 4818 ) 4512 *1 53 (MRCItem4513 litem &1 324819 *163 (MRCItem 4820 litem &140 4514 4821 pos 1 4515 4822 dimension 20 4516 4823 uid 432,0 4517 4824 ) 4518 *1 54 (MRCItem4519 litem &1 334825 *164 (MRCItem 4826 litem &141 4520 4827 pos 12 4521 4828 dimension 20 4522 4829 uid 434,0 4523 4830 ) 4524 *1 55 (MRCItem4525 litem &1 344831 *165 (MRCItem 4832 litem &142 4526 4833 pos 2 4527 4834 dimension 20 4528 4835 uid 436,0 4529 4836 ) 4530 *1 56 (MRCItem4531 litem &1 354837 *166 (MRCItem 4838 litem &143 4532 4839 pos 3 4533 4840 dimension 20 4534 4841 uid 438,0 4535 4842 ) 4536 *1 57 (MRCItem4537 litem &1 364843 *167 (MRCItem 4844 litem &144 4538 4845 pos 4 4539 4846 dimension 20 4540 4847 uid 440,0 4541 4848 ) 4542 *1 58 (MRCItem4543 litem &1 374849 *168 (MRCItem 4850 litem &145 4544 4851 pos 5 4545 4852 dimension 20 4546 4853 uid 442,0 4547 4854 ) 4548 *1 59 (MRCItem4549 litem &1 384855 *169 (MRCItem 4856 litem &146 4550 4857 pos 13 4551 4858 dimension 20 4552 4859 uid 444,0 4553 4860 ) 4554 *1 60 (MRCItem4555 litem &1 394861 *170 (MRCItem 4862 litem &147 4556 4863 pos 6 4557 4864 dimension 20 4558 4865 uid 446,0 4559 4866 ) 4560 *1 61 (MRCItem4561 litem &14 04867 *171 (MRCItem 4868 litem &148 4562 4869 pos 14 4563 4870 dimension 20 4564 4871 uid 448,0 4565 4872 ) 4566 *1 62 (MRCItem4567 litem &14 14873 *172 (MRCItem 4874 litem &149 4568 4875 pos 7 4569 4876 dimension 20 4570 4877 uid 450,0 4571 4878 ) 4572 *1 63 (MRCItem4573 litem &1 424879 *173 (MRCItem 4880 litem &150 4574 4881 pos 8 4575 4882 dimension 20 4576 4883 uid 452,0 4577 4884 ) 4578 *1 64 (MRCItem4579 litem &1 434885 *174 (MRCItem 4886 litem &151 4580 4887 pos 9 4581 4888 dimension 20 4582 4889 uid 454,0 4583 4890 ) 4584 *1 65 (MRCItem4585 litem &1 444891 *175 (MRCItem 4892 litem &152 4586 4893 pos 10 4587 4894 dimension 20 4588 4895 uid 458,0 4589 4896 ) 4590 *1 66 (MRCItem4591 litem &1 454897 *176 (MRCItem 4898 litem &153 4592 4899 pos 15 4593 4900 dimension 20 4594 4901 uid 1097,0 4902 ) 4903 *177 (MRCItem 4904 litem &154 4905 pos 16 4906 dimension 20 4907 uid 1235,0 4908 ) 4909 *178 (MRCItem 4910 litem &155 4911 pos 17 4912 dimension 20 4913 uid 1237,0 4595 4914 ) 4596 4915 ] … … 4605 4924 uid 73,0 4606 4925 optionalChildren [ 4607 *1 67(MRCItem4608 litem &12 14926 *179 (MRCItem 4927 litem &129 4609 4928 pos 0 4610 4929 dimension 20 4611 4930 uid 74,0 4612 4931 ) 4613 *1 68(MRCItem4614 litem &1 234932 *180 (MRCItem 4933 litem &131 4615 4934 pos 1 4616 4935 dimension 50 4617 4936 uid 75,0 4618 4937 ) 4619 *1 69(MRCItem4620 litem &1 244938 *181 (MRCItem 4939 litem &132 4621 4940 pos 2 4622 4941 dimension 100 4623 4942 uid 76,0 4624 4943 ) 4625 *1 70(MRCItem4626 litem &1 254944 *182 (MRCItem 4945 litem &133 4627 4946 pos 3 4628 4947 dimension 50 4629 4948 uid 77,0 4630 4949 ) 4631 *1 71(MRCItem4632 litem &1 264950 *183 (MRCItem 4951 litem &134 4633 4952 pos 4 4634 4953 dimension 100 4635 4954 uid 78,0 4636 4955 ) 4637 *1 72(MRCItem4638 litem &1 274956 *184 (MRCItem 4957 litem &135 4639 4958 pos 5 4640 4959 dimension 100 4641 4960 uid 79,0 4642 4961 ) 4643 *1 73(MRCItem4644 litem &1 284962 *185 (MRCItem 4963 litem &136 4645 4964 pos 6 4646 4965 dimension 50 4647 4966 uid 80,0 4648 4967 ) 4649 *1 74(MRCItem4650 litem &1 294968 *186 (MRCItem 4969 litem &137 4651 4970 pos 7 4652 4971 dimension 80 … … 4668 4987 genericsCommonDM (CommonDM 4669 4988 ldm (LogicalDM 4670 emptyRow *1 75(LEmptyRow4989 emptyRow *187 (LEmptyRow 4671 4990 ) 4672 4991 uid 83,0 4673 4992 optionalChildren [ 4674 *1 76(RefLabelRowHdr4675 ) 4676 *1 77(TitleRowHdr4677 ) 4678 *1 78(FilterRowHdr4679 ) 4680 *1 79(RefLabelColHdr4993 *188 (RefLabelRowHdr 4994 ) 4995 *189 (TitleRowHdr 4996 ) 4997 *190 (FilterRowHdr 4998 ) 4999 *191 (RefLabelColHdr 4681 5000 tm "RefLabelColHdrMgr" 4682 5001 ) 4683 *1 80(RowExpandColHdr5002 *192 (RowExpandColHdr 4684 5003 tm "RowExpandColHdrMgr" 4685 5004 ) 4686 *1 81(GroupColHdr5005 *193 (GroupColHdr 4687 5006 tm "GroupColHdrMgr" 4688 5007 ) 4689 *1 82(NameColHdr5008 *194 (NameColHdr 4690 5009 tm "GenericNameColHdrMgr" 4691 5010 ) 4692 *1 83(TypeColHdr5011 *195 (TypeColHdr 4693 5012 tm "GenericTypeColHdrMgr" 4694 5013 ) 4695 *1 84(InitColHdr5014 *196 (InitColHdr 4696 5015 tm "GenericValueColHdrMgr" 4697 5016 ) 4698 *1 85(PragmaColHdr5017 *197 (PragmaColHdr 4699 5018 tm "GenericPragmaColHdrMgr" 4700 5019 ) 4701 *1 86(EolColHdr5020 *198 (EolColHdr 4702 5021 tm "GenericEolColHdrMgr" 4703 5022 ) … … 4709 5028 uid 95,0 4710 5029 optionalChildren [ 4711 *1 87(Sheet5030 *199 (Sheet 4712 5031 sheetRow (SheetRow 4713 5032 headerVa (MVa … … 4726 5045 font "Tahoma,10,0" 4727 5046 ) 4728 emptyMRCItem * 188(MRCItem4729 litem &1 755047 emptyMRCItem *200 (MRCItem 5048 litem &187 4730 5049 pos 0 4731 5050 dimension 20 … … 4733 5052 uid 97,0 4734 5053 optionalChildren [ 4735 * 189(MRCItem4736 litem &1 765054 *201 (MRCItem 5055 litem &188 4737 5056 pos 0 4738 5057 dimension 20 4739 5058 uid 98,0 4740 5059 ) 4741 * 190(MRCItem4742 litem &1 775060 *202 (MRCItem 5061 litem &189 4743 5062 pos 1 4744 5063 dimension 23 4745 5064 uid 99,0 4746 5065 ) 4747 * 191(MRCItem4748 litem &1 785066 *203 (MRCItem 5067 litem &190 4749 5068 pos 2 4750 5069 hidden 1 … … 4763 5082 uid 101,0 4764 5083 optionalChildren [ 4765 * 192(MRCItem4766 litem &1 795084 *204 (MRCItem 5085 litem &191 4767 5086 pos 0 4768 5087 dimension 20 4769 5088 uid 102,0 4770 5089 ) 4771 * 193(MRCItem4772 litem &1 815090 *205 (MRCItem 5091 litem &193 4773 5092 pos 1 4774 5093 dimension 50 4775 5094 uid 103,0 4776 5095 ) 4777 * 194(MRCItem4778 litem &1 825096 *206 (MRCItem 5097 litem &194 4779 5098 pos 2 4780 5099 dimension 100 4781 5100 uid 104,0 4782 5101 ) 4783 * 195(MRCItem4784 litem &1 835102 *207 (MRCItem 5103 litem &195 4785 5104 pos 3 4786 5105 dimension 100 4787 5106 uid 105,0 4788 5107 ) 4789 * 196(MRCItem4790 litem &1 845108 *208 (MRCItem 5109 litem &196 4791 5110 pos 4 4792 5111 dimension 50 4793 5112 uid 106,0 4794 5113 ) 4795 * 197(MRCItem4796 litem &1 855114 *209 (MRCItem 5115 litem &197 4797 5116 pos 5 4798 5117 dimension 50 4799 5118 uid 107,0 4800 5119 ) 4801 * 198(MRCItem4802 litem &1 865120 *210 (MRCItem 5121 litem &198 4803 5122 pos 6 4804 5123 dimension 80 -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/struct.bd.bak
r246 r252 60 60 ) 61 61 version "29.1" 62 appVersion "2009. 1 (Build 12)"62 appVersion "2009.2 (Build 10)" 63 63 noEmbeddedEditors 1 64 64 model (BlockDiag … … 67 67 (vvPair 68 68 variable "HDLDir" 69 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"69 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 70 70 ) 71 71 (vvPair 72 72 variable "HDSDir" 73 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"73 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 74 74 ) 75 75 (vvPair 76 76 variable "SideDataDesignDir" 77 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info"77 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.info" 78 78 ) 79 79 (vvPair 80 80 variable "SideDataUserDir" 81 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user"81 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd.user" 82 82 ) 83 83 (vvPair 84 84 variable "SourceDir" 85 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"85 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 86 86 ) 87 87 (vvPair … … 99 99 (vvPair 100 100 variable "d" 101 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"101 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 102 102 ) 103 103 (vvPair 104 104 variable "d_logical" 105 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"105 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 106 106 ) 107 107 (vvPair 108 108 variable "date" 109 value " 27.05.2010"109 value "12.07.2010" 110 110 ) 111 111 (vvPair 112 112 variable "day" 113 value " Do"113 value "Mo" 114 114 ) 115 115 (vvPair 116 116 variable "day_long" 117 value " Donnerstag"117 value "Montag" 118 118 ) 119 119 (vvPair 120 120 variable "dd" 121 value " 27"121 value "12" 122 122 ) 123 123 (vvPair … … 147 147 (vvPair 148 148 variable "host" 149 value " IHP110"149 value "TU-CC4900F8C7D2" 150 150 ) 151 151 (vvPair … … 175 175 (vvPair 176 176 variable "mm" 177 value "0 5"177 value "07" 178 178 ) 179 179 (vvPair … … 183 183 (vvPair 184 184 variable "month" 185 value " Mai"185 value "Jul" 186 186 ) 187 187 (vvPair 188 188 variable "month_long" 189 value " Mai"189 value "Juli" 190 190 ) 191 191 (vvPair 192 192 variable "p" 193 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"193 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" 194 194 ) 195 195 (vvPair 196 196 variable "p_logical" 197 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd"197 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\struct.bd" 198 198 ) 199 199 (vvPair … … 219 219 (vvPair 220 220 variable "task_ModelSimPath" 221 value " D:\\modeltech_6.5e\\win32"221 value "<TBD>" 222 222 ) 223 223 (vvPair … … 251 251 (vvPair 252 252 variable "time" 253 value "1 0:24:01"253 value "13:47:38" 254 254 ) 255 255 (vvPair … … 259 259 (vvPair 260 260 variable "user" 261 value "d aqct3"261 value "dneise" 262 262 ) 263 263 (vvPair 264 264 variable "version" 265 value "2009. 1 (Build 12)"265 value "2009.2 (Build 10)" 266 266 ) 267 267 (vvPair … … 303 303 bg "0,0,32768" 304 304 ) 305 xt "16200,76000,2 4500,77000"305 xt "16200,76000,25500,77000" 306 306 st " 307 307 by %user on %dd %month %year … … 621 621 font "Courier New,8,0" 622 622 ) 623 xt "22000,2000,38000,2800" 624 st "clk : STD_LOGIC 625 " 623 xt "29000,2200,45000,3000" 624 st "clk : STD_LOGIC" 626 625 ) 627 626 ) … … 640 639 font "Courier New,8,0" 641 640 ) 642 xt "22000,15000,51500,15800" 643 st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0) 644 " 641 xt "29000,15200,58500,16000" 642 st "SIGNAL ram_wren : std_logic_VECTOR(0 DOWNTO 0)" 645 643 ) 646 644 ) … … 659 657 font "Courier New,8,0" 660 658 ) 661 xt "22000,2800,48000,3600" 662 st "config_addr : std_logic_vector(7 DOWNTO 0) 663 " 659 xt "29000,3000,55000,3800" 660 st "config_addr : std_logic_vector(7 DOWNTO 0)" 664 661 ) 665 662 ) … … 678 675 font "Courier New,8,0" 679 676 ) 680 xt "22000,13400,52000,14200" 681 st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0) 682 " 677 xt "29000,13600,59000,14400" 678 st "SIGNAL ram_data_in : std_logic_VECTOR(15 DOWNTO 0)" 683 679 ) 684 680 ) … … 696 692 font "Courier New,8,0" 697 693 ) 698 xt "22000,6800,38000,7600" 699 st "config_data_valid : std_logic 700 " 694 xt "29000,7000,45000,7800" 695 st "config_data_valid : std_logic" 701 696 ) 702 697 ) … … 714 709 font "Courier New,8,0" 715 710 ) 716 xt "22000,6000,38000,6800" 717 st "config_busy : std_logic 718 " 711 xt "29000,6200,45000,7000" 712 st "config_busy : std_logic" 719 713 ) 720 714 ) … … 733 727 font "Courier New,8,0" 734 728 ) 735 xt "22000,10800,48500,11600" 736 st "config_data : std_logic_vector(15 DOWNTO 0) 737 " 729 xt "29000,11000,55500,11800" 730 st "config_data : std_logic_vector(15 DOWNTO 0)" 738 731 ) 739 732 ) … … 751 744 font "Courier New,8,0" 752 745 ) 753 xt "22000,10000,40500,10800" 754 st "roi_array : roi_array_type 755 " 746 xt "29000,10200,47500,11000" 747 st "roi_array : roi_array_type" 756 748 ) 757 749 ) … … 770 762 font "Courier New,8,0" 771 763 ) 772 xt "22000,12600,51500,13400" 773 st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0) 774 " 764 xt "29000,12800,58500,13600" 765 st "SIGNAL ram_addr : std_logic_VECTOR(7 DOWNTO 0)" 775 766 ) 776 767 ) … … 788 779 font "Courier New,8,0" 789 780 ) 790 xt "22000,5200,38000,6000" 791 st "config_wr_en : std_logic 792 " 781 xt "29000,5400,45000,6200" 782 st "config_wr_en : std_logic" 793 783 ) 794 784 ) … … 807 797 font "Courier New,8,0" 808 798 ) 809 xt "22000,14200,52000,15000" 810 st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0) 811 " 799 xt "29000,14400,59000,15200" 800 st "SIGNAL ram_data_out : std_logic_VECTOR(15 DOWNTO 0)" 812 801 ) 813 802 ) … … 825 814 font "Courier New,8,0" 826 815 ) 827 xt "22000,9200,40500,10000" 828 st "dac_array : dac_array_type 829 " 816 xt "29000,9400,47500,10200" 817 st "dac_array : dac_array_type" 830 818 ) 831 819 ) … … 843 831 font "Courier New,8,0" 844 832 ) 845 xt "22000,3600,38000,4400" 846 st "config_rd_en : std_logic 847 " 833 xt "29000,3800,45000,4600" 834 st "config_rd_en : std_logic" 848 835 ) 849 836 ) … … 861 848 font "Courier New,8,0" 862 849 ) 863 xt "22000,4400,38000,5200" 864 st "config_start : std_logic 865 " 850 xt "29000,4600,45000,5400" 851 st "config_start : std_logic" 866 852 ) 867 853 ) … … 879 865 font "Courier New,8,0" 880 866 ) 881 xt "22000,7600,38000,8400" 882 st "config_ready : std_logic 883 " 867 xt "29000,7800,45000,8600" 868 st "config_ready : std_logic" 884 869 ) 885 870 ) … … 897 882 sl 0 898 883 ro 270 899 xt " 3000,23625,4500,24375"884 xt "2000,19625,3500,20375" 900 885 ) 901 886 (Line … … 903 888 sl 0 904 889 ro 270 905 xt " 4500,24000,5000,24000"890 xt "3500,20000,4000,20000" 906 891 pts [ 907 " 4500,24000"908 " 5000,24000"892 "3500,20000" 893 "4000,20000" 909 894 ] 910 895 ) … … 921 906 va (VaSet 922 907 ) 923 xt "700, 23500,2000,24500"908 xt "700,19500,2000,20500" 924 909 st "clk" 925 910 ju 2 926 blo "2000,2 4300"911 blo "2000,20300" 927 912 tm "WireNameMgr" 928 913 ) … … 942 927 sl 0 943 928 ro 270 944 xt " 42500,28625,44000,29375"929 xt "36500,28625,38000,29375" 945 930 ) 946 931 (Line … … 948 933 sl 0 949 934 ro 270 950 xt " 42000,29000,42500,29000"935 xt "36000,29000,36500,29000" 951 936 pts [ 952 " 42000,29000"953 " 42500,29000"937 "36000,29000" 938 "36500,29000" 954 939 ] 955 940 ) … … 966 951 va (VaSet 967 952 ) 968 xt " 45000,28500,50100,29500"953 xt "39000,28500,44100,29500" 969 954 st "config_ready" 970 blo " 45000,29300"955 blo "39000,29300" 971 956 tm "WireNameMgr" 972 957 ) … … 986 971 sl 0 987 972 ro 90 988 xt " 42500,29625,44000,30375"973 xt "36500,29625,38000,30375" 989 974 ) 990 975 (Line … … 992 977 sl 0 993 978 ro 90 994 xt " 42000,30000,42500,30000"979 xt "36000,30000,36500,30000" 995 980 pts [ 996 " 42500,30000"997 " 42000,30000"981 "36500,30000" 982 "36000,30000" 998 983 ] 999 984 ) … … 1010 995 va (VaSet 1011 996 ) 1012 xt " 45000,29500,49800,30500"997 xt "39000,29500,43800,30500" 1013 998 st "config_start" 1014 blo " 45000,30300"999 blo "39000,30300" 1015 1000 tm "WireNameMgr" 1016 1001 ) … … 1029 1014 uid 381,0 1030 1015 sl 0 1031 xt " 42500,24625,44000,25375"1016 xt "36500,24625,38000,25375" 1032 1017 ) 1033 1018 (Line 1034 1019 uid 382,0 1035 1020 sl 0 1036 xt " 42000,25000,42500,25000"1021 xt "36000,25000,36500,25000" 1037 1022 pts [ 1038 " 42000,25000"1039 " 42500,25000"1023 "36000,25000" 1024 "36500,25000" 1040 1025 ] 1041 1026 ) … … 1052 1037 va (VaSet 1053 1038 ) 1054 xt " 45000,24500,49700,25500"1039 xt "39000,24500,43700,25500" 1055 1040 st "config_data" 1056 blo " 45000,25300"1041 blo "39000,25300" 1057 1042 tm "WireNameMgr" 1058 1043 ) … … 1072 1057 sl 0 1073 1058 ro 90 1074 xt " 42500,23625,44000,24375"1059 xt "36500,23625,38000,24375" 1075 1060 ) 1076 1061 (Line … … 1078 1063 sl 0 1079 1064 ro 90 1080 xt " 42000,24000,42500,24000"1065 xt "36000,24000,36500,24000" 1081 1066 pts [ 1082 " 42500,24000"1083 " 42000,24000"1067 "36500,24000" 1068 "36000,24000" 1084 1069 ] 1085 1070 ) … … 1096 1081 va (VaSet 1097 1082 ) 1098 xt " 45000,23500,49800,24500"1083 xt "39000,23500,43800,24500" 1099 1084 st "config_addr" 1100 blo " 45000,24300"1085 blo "39000,24300" 1101 1086 tm "WireNameMgr" 1102 1087 ) … … 1116 1101 sl 0 1117 1102 ro 90 1118 xt " 42500,26625,44000,27375"1103 xt "36500,26625,38000,27375" 1119 1104 ) 1120 1105 (Line … … 1122 1107 sl 0 1123 1108 ro 90 1124 xt " 42000,27000,42500,27000"1109 xt "36000,27000,36500,27000" 1125 1110 pts [ 1126 " 42500,27000"1127 " 42000,27000"1111 "36500,27000" 1112 "36000,27000" 1128 1113 ] 1129 1114 ) … … 1140 1125 va (VaSet 1141 1126 ) 1142 xt " 45000,26500,50300,27500"1127 xt "39000,26500,44300,27500" 1143 1128 st "config_wr_en" 1144 blo " 45000,27300"1129 blo "39000,27300" 1145 1130 tm "WireNameMgr" 1146 1131 ) … … 1160 1145 sl 0 1161 1146 ro 90 1162 xt " 42500,27625,44000,28375"1147 xt "36500,27625,38000,28375" 1163 1148 ) 1164 1149 (Line … … 1166 1151 sl 0 1167 1152 ro 90 1168 xt " 42000,28000,42500,28000"1153 xt "36000,28000,36500,28000" 1169 1154 pts [ 1170 " 42500,28000"1171 " 42000,28000"1155 "36500,28000" 1156 "36000,28000" 1172 1157 ] 1173 1158 ) … … 1184 1169 va (VaSet 1185 1170 ) 1186 xt " 45000,27500,50200,28500"1171 xt "39000,27500,44200,28500" 1187 1172 st "config_rd_en" 1188 blo " 45000,28300"1173 blo "39000,28300" 1189 1174 tm "WireNameMgr" 1190 1175 ) … … 1204 1189 sl 0 1205 1190 ro 270 1206 xt " 42500,33625,44000,34375"1191 xt "36500,33625,38000,34375" 1207 1192 ) 1208 1193 (Line … … 1210 1195 sl 0 1211 1196 ro 270 1212 xt " 42000,34000,42500,34000"1197 xt "36000,34000,36500,34000" 1213 1198 pts [ 1214 " 42000,34000"1215 " 42500,34000"1199 "36000,34000" 1200 "36500,34000" 1216 1201 ] 1217 1202 ) … … 1228 1213 va (VaSet 1229 1214 ) 1230 xt " 45000,33500,48700,34500"1215 xt "39000,33500,42700,34500" 1231 1216 st "dac_array" 1232 blo " 45000,34300"1217 blo "39000,34300" 1233 1218 tm "WireNameMgr" 1234 1219 ) … … 1248 1233 sl 0 1249 1234 ro 270 1250 xt " 42500,34625,44000,35375"1235 xt "36500,34625,38000,35375" 1251 1236 ) 1252 1237 (Line … … 1254 1239 sl 0 1255 1240 ro 270 1256 xt " 42000,35000,42500,35000"1241 xt "36000,35000,36500,35000" 1257 1242 pts [ 1258 " 42000,35000"1259 " 42500,35000"1243 "36000,35000" 1244 "36500,35000" 1260 1245 ] 1261 1246 ) … … 1272 1257 va (VaSet 1273 1258 ) 1274 xt " 45000,34500,48400,35500"1259 xt "39000,34500,42400,35500" 1275 1260 st "roi_array" 1276 blo " 45000,35300"1261 blo "39000,35300" 1277 1262 tm "WireNameMgr" 1278 1263 ) … … 1292 1277 sl 0 1293 1278 ro 270 1294 xt " 42500,31625,44000,32375"1279 xt "36500,31625,38000,32375" 1295 1280 ) 1296 1281 (Line … … 1298 1283 sl 0 1299 1284 ro 270 1300 xt " 42000,32000,42500,32000"1285 xt "36000,32000,36500,32000" 1301 1286 pts [ 1302 " 42000,32000"1303 " 42500,32000"1287 "36000,32000" 1288 "36500,32000" 1304 1289 ] 1305 1290 ) … … 1316 1301 va (VaSet 1317 1302 ) 1318 xt " 45000,31500,51600,32500"1303 xt "39000,31500,45600,32500" 1319 1304 st "config_data_valid" 1320 blo " 45000,32300"1305 blo "39000,32300" 1321 1306 tm "WireNameMgr" 1322 1307 ) … … 1336 1321 sl 0 1337 1322 ro 270 1338 xt " 42500,32625,44000,33375"1323 xt "36500,32625,38000,33375" 1339 1324 ) 1340 1325 (Line … … 1342 1327 sl 0 1343 1328 ro 270 1344 xt " 42000,33000,42500,33000"1329 xt "36000,33000,36500,33000" 1345 1330 pts [ 1346 " 42000,33000"1347 " 42500,33000"1331 "36000,33000" 1332 "36500,33000" 1348 1333 ] 1349 1334 ) … … 1360 1345 va (VaSet 1361 1346 ) 1362 xt " 45000,32500,49800,33500"1347 xt "39000,32500,43800,33500" 1363 1348 st "config_busy" 1364 blo " 45000,33300"1349 blo "39000,33300" 1365 1350 tm "WireNameMgr" 1366 1351 ) … … 1380 1365 fg "0,65535,0" 1381 1366 ) 1382 xt " 12250,23625,13000,24375"1367 xt "6250,23625,7000,24375" 1383 1368 ) 1384 1369 tg (CPTG … … 1390 1375 va (VaSet 1391 1376 ) 1392 xt " 14000,23500,15300,24500"1377 xt "8000,23500,9300,24500" 1393 1378 st "clk" 1394 blo " 14000,24300"1379 blo "8000,24300" 1395 1380 ) 1396 1381 ) … … 1416 1401 fg "0,65535,0" 1417 1402 ) 1418 xt "3 8000,28625,38750,29375"1403 xt "32000,28625,32750,29375" 1419 1404 ) 1420 1405 tg (CPTG … … 1426 1411 va (VaSet 1427 1412 ) 1428 xt " 31900,28500,37000,29500"1413 xt "25900,28500,31000,29500" 1429 1414 st "config_ready" 1430 1415 ju 2 1431 blo "3 7000,29300"1416 blo "31000,29300" 1432 1417 ) 1433 1418 ) … … 1455 1440 fg "0,65535,0" 1456 1441 ) 1457 xt "3 8000,29625,38750,30375"1442 xt "32000,29625,32750,30375" 1458 1443 ) 1459 1444 tg (CPTG … … 1465 1450 va (VaSet 1466 1451 ) 1467 xt " 32200,29500,37000,30500"1452 xt "26200,29500,31000,30500" 1468 1453 st "config_start" 1469 1454 ju 2 1470 blo "3 7000,30300"1455 blo "31000,30300" 1471 1456 ) 1472 1457 ) … … 1492 1477 fg "0,65535,0" 1493 1478 ) 1494 xt "3 8000,24625,38750,25375"1479 xt "32000,24625,32750,25375" 1495 1480 ) 1496 1481 tg (CPTG … … 1502 1487 va (VaSet 1503 1488 ) 1504 xt "2 9300,24500,37000,25500"1489 xt "23300,24500,31000,25500" 1505 1490 st "config_data : (15:0)" 1506 1491 ju 2 1507 blo "3 7000,25300"1492 blo "31000,25300" 1508 1493 ) 1509 1494 ) … … 1532 1517 fg "0,65535,0" 1533 1518 ) 1534 xt "3 8000,23625,38750,24375"1519 xt "32000,23625,32750,24375" 1535 1520 ) 1536 1521 tg (CPTG … … 1542 1527 va (VaSet 1543 1528 ) 1544 xt " 23600,23500,37000,24500"1529 xt "17600,23500,31000,24500" 1545 1530 st "config_addr : (ADDR_WIDTH - 1:0)" 1546 1531 ju 2 1547 blo "3 7000,24300"1532 blo "31000,24300" 1548 1533 ) 1549 1534 ) … … 1570 1555 fg "0,65535,0" 1571 1556 ) 1572 xt "3 8000,26625,38750,27375"1557 xt "32000,26625,32750,27375" 1573 1558 ) 1574 1559 tg (CPTG … … 1580 1565 va (VaSet 1581 1566 ) 1582 xt " 31700,26500,37000,27500"1567 xt "25700,26500,31000,27500" 1583 1568 st "config_wr_en" 1584 1569 ju 2 1585 blo "3 7000,27300"1570 blo "31000,27300" 1586 1571 ) 1587 1572 ) … … 1607 1592 fg "0,65535,0" 1608 1593 ) 1609 xt "3 8000,27625,38750,28375"1594 xt "32000,27625,32750,28375" 1610 1595 ) 1611 1596 tg (CPTG … … 1617 1602 va (VaSet 1618 1603 ) 1619 xt " 31800,27500,37000,28500"1604 xt "25800,27500,31000,28500" 1620 1605 st "config_rd_en" 1621 1606 ju 2 1622 blo "3 7000,28300"1607 blo "31000,28300" 1623 1608 ) 1624 1609 ) … … 1644 1629 fg "0,65535,0" 1645 1630 ) 1646 xt "3 8000,31625,38750,32375"1631 xt "32000,31625,32750,32375" 1647 1632 ) 1648 1633 tg (CPTG … … 1654 1639 va (VaSet 1655 1640 ) 1656 xt " 30400,31500,37000,32500"1641 xt "24400,31500,31000,32500" 1657 1642 st "config_data_valid" 1658 1643 ju 2 1659 blo "3 7000,32300"1644 blo "31000,32300" 1660 1645 ) 1661 1646 ) … … 1683 1668 fg "0,65535,0" 1684 1669 ) 1685 xt "3 8000,32625,38750,33375"1670 xt "32000,32625,32750,33375" 1686 1671 ) 1687 1672 tg (CPTG … … 1693 1678 va (VaSet 1694 1679 ) 1695 xt " 32200,32500,37000,33500"1680 xt "26200,32500,31000,33500" 1696 1681 st "config_busy" 1697 1682 ju 2 1698 blo "3 7000,33300"1683 blo "31000,33300" 1699 1684 ) 1700 1685 ) … … 1722 1707 fg "0,65535,0" 1723 1708 ) 1724 xt "3 8000,33625,38750,34375"1709 xt "32000,33625,32750,34375" 1725 1710 ) 1726 1711 tg (CPTG … … 1732 1717 va (VaSet 1733 1718 ) 1734 xt " 33300,33500,37000,34500"1719 xt "27300,33500,31000,34500" 1735 1720 st "dac_array" 1736 1721 ju 2 1737 blo "3 7000,34300"1722 blo "31000,34300" 1738 1723 ) 1739 1724 ) … … 1760 1745 fg "0,65535,0" 1761 1746 ) 1762 xt "3 8000,34625,38750,35375"1747 xt "32000,34625,32750,35375" 1763 1748 ) 1764 1749 tg (CPTG … … 1770 1755 va (VaSet 1771 1756 ) 1772 xt " 33600,34500,37000,35500"1757 xt "27600,34500,31000,35500" 1773 1758 st "roi_array" 1774 1759 ju 2 1775 blo "3 7000,35300"1760 blo "31000,35300" 1776 1761 ) 1777 1762 ) … … 1798 1783 fg "0,65535,0" 1799 1784 ) 1800 xt "3 8000,37625,38750,38375"1785 xt "32000,37625,32750,38375" 1801 1786 ) 1802 1787 tg (CPTG … … 1808 1793 va (VaSet 1809 1794 ) 1810 xt "2 9100,37500,37000,38500"1795 xt "23100,37500,31000,38500" 1811 1796 st "ram_data_in : (15:0)" 1812 1797 ju 2 1813 blo "3 7000,38300"1798 blo "31000,38300" 1814 1799 ) 1815 1800 ) … … 1835 1820 fg "0,65535,0" 1836 1821 ) 1837 xt "3 8000,38625,38750,39375"1822 xt "32000,38625,32750,39375" 1838 1823 ) 1839 1824 tg (CPTG … … 1845 1830 va (VaSet 1846 1831 ) 1847 xt "2 9100,38500,37000,39500"1832 xt "23100,38500,31000,39500" 1848 1833 st "ram_write_en : (0:0)" 1849 1834 ju 2 1850 blo "3 7000,39300"1835 blo "31000,39300" 1851 1836 ) 1852 1837 ) … … 1872 1857 fg "0,65535,0" 1873 1858 ) 1874 xt " 12250,24625,13000,25375"1859 xt "6250,38625,7000,39375" 1875 1860 ) 1876 1861 tg (CPTG … … 1882 1867 va (VaSet 1883 1868 ) 1884 xt " 14000,24500,22300,25500"1869 xt "8000,38500,16300,39500" 1885 1870 st "ram_data_out : (15:0)" 1886 blo " 14000,25300"1871 blo "8000,39300" 1887 1872 ) 1888 1873 ) … … 1907 1892 fg "0,65535,0" 1908 1893 ) 1909 xt "3 8000,39625,38750,40375"1894 xt "32000,39625,32750,40375" 1910 1895 ) 1911 1896 tg (CPTG … … 1917 1902 va (VaSet 1918 1903 ) 1919 xt " 24400,39500,37000,40500"1904 xt "18400,39500,31000,40500" 1920 1905 st "ram_addr : (ADDR_WIDTH - 1:0)" 1921 1906 ju 2 1922 blo "3 7000,40300"1907 blo "31000,40300" 1923 1908 ) 1924 1909 ) … … 1944 1929 fg "0,65535,0" 1945 1930 ) 1946 xt "3 8000,30625,38750,31375"1931 xt "32000,30625,32750,31375" 1947 1932 ) 1948 1933 tg (CPTG … … 1954 1939 va (VaSet 1955 1940 ) 1956 xt " 31400,30500,37000,31500"1941 xt "25400,30500,31000,31500" 1957 1942 st "config_started" 1958 1943 ju 2 1959 blo "3 7000,31300"1944 blo "31000,31300" 1960 1945 ) 1961 1946 ) … … 1980 1965 lineWidth 2 1981 1966 ) 1982 xt " 13000,23000,38000,42000"1967 xt "7000,23000,32000,42000" 1983 1968 ) 1984 1969 oxt "42000,14000,67000,32000" … … 1993 1978 font "Arial,8,1" 1994 1979 ) 1995 xt " 12950,42000,19150,43000"1980 xt "6950,42000,13150,43000" 1996 1981 st "FACT_FAD_lib" 1997 blo " 12950,42800"1982 blo "6950,42800" 1998 1983 tm "BdLibraryNameMgr" 1999 1984 ) … … 2003 1988 font "Arial,8,1" 2004 1989 ) 2005 xt " 12950,43000,20050,44000"1990 xt "6950,43000,14050,44000" 2006 1991 st "control_manager" 2007 blo " 12950,43800"1992 blo "6950,43800" 2008 1993 tm "CptNameMgr" 2009 1994 ) … … 2013 1998 font "Arial,8,1" 2014 1999 ) 2015 xt " 12950,44000,20650,45000"2000 xt "6950,44000,14650,45000" 2016 2001 st "I_control_manager" 2017 blo " 12950,44800"2002 blo "6950,44800" 2018 2003 tm "InstanceNameMgr" 2019 2004 ) … … 2030 2015 font "Courier New,8,0" 2031 2016 ) 2032 xt "1 2500,10600,30000,13000"2017 xt "10000,20600,27500,23000" 2033 2018 st "NO_OF_ROI = 36 ( integer ) 2034 2019 NO_OF_DAC = 8 ( integer ) … … 2062 2047 fg "49152,49152,49152" 2063 2048 ) 2064 xt " 13250,40250,14750,41750"2049 xt "7250,40250,8750,41750" 2065 2050 iconName "VhdlFileViewIcon.png" 2066 2051 iconMaskName "VhdlFileViewIcon.msk" … … 2081 2066 shape (Triangle 2082 2067 uid 971,0 2083 ro 902068 ro 180 2084 2069 va (VaSet 2085 2070 vasetType 1 2086 2071 fg "0,65535,0" 2087 2072 ) 2088 xt " 19250,50625,20000,51375"2073 xt "42625,41250,43375,42000" 2089 2074 ) 2090 2075 tg (CPTG 2091 2076 uid 972,0 2092 2077 ps "CptPortTextPlaceStrategy" 2093 stg " VerticalLayoutStrategy"2078 stg "RightVerticalLayoutStrategy" 2094 2079 f (Text 2095 2080 uid 973,0 2096 va (VaSet 2097 ) 2098 xt "21000,50500,22700,51500" 2081 ro 270 2082 va (VaSet 2083 ) 2084 xt "42500,43000,43500,44700" 2099 2085 st "clka" 2100 blo "21000,51300" 2086 ju 2 2087 blo "43300,43000" 2101 2088 ) 2102 2089 ) … … 2122 2109 fg "0,65535,0" 2123 2110 ) 2124 xt " 19250,52625,20000,53375"2111 xt "39250,45625,40000,46375" 2125 2112 ) 2126 2113 tg (CPTG … … 2132 2119 va (VaSet 2133 2120 ) 2134 xt " 21000,52500,25800,53500"2121 xt "41000,45500,45800,46500" 2135 2122 st "dina : (15:0)" 2136 blo " 21000,53300"2123 blo "41000,46300" 2137 2124 ) 2138 2125 ) … … 2159 2146 fg "0,65535,0" 2160 2147 ) 2161 xt " 19250,54625,20000,55375"2148 xt "39250,47625,40000,48375" 2162 2149 ) 2163 2150 tg (CPTG … … 2169 2156 va (VaSet 2170 2157 ) 2171 xt " 21000,54500,25900,55500"2158 xt "41000,47500,45900,48500" 2172 2159 st "addra : (7:0)" 2173 blo " 21000,55300"2160 blo "41000,48300" 2174 2161 ) 2175 2162 ) … … 2196 2183 fg "0,65535,0" 2197 2184 ) 2198 xt " 19250,53625,20000,54375"2185 xt "39250,46625,40000,47375" 2199 2186 ) 2200 2187 tg (CPTG … … 2206 2193 va (VaSet 2207 2194 ) 2208 xt " 21000,53500,25300,54500"2195 xt "41000,46500,45300,47500" 2209 2196 st "wea : (0:0)" 2210 blo " 21000,54300"2197 blo "41000,47300" 2211 2198 ) 2212 2199 ) … … 2233 2220 fg "0,65535,0" 2234 2221 ) 2235 xt " 30000,50625,30750,51375"2222 xt "50000,43625,50750,44375" 2236 2223 ) 2237 2224 tg (CPTG … … 2243 2230 va (VaSet 2244 2231 ) 2245 xt " 23800,50500,29000,51500"2232 xt "43800,43500,49000,44500" 2246 2233 st "douta : (15:0)" 2247 2234 ju 2 2248 blo " 29000,51300"2235 blo "49000,44300" 2249 2236 ) 2250 2237 ) … … 2271 2258 lineWidth 2 2272 2259 ) 2273 xt " 20000,49000,30000,59000"2260 xt "40000,42000,50000,52000" 2274 2261 ) 2275 2262 oxt "30000,7000,40000,17000" … … 2284 2271 font "Arial,8,1" 2285 2272 ) 2286 xt " 20200,59000,26400,60000"2273 xt "40200,52000,46400,53000" 2287 2274 st "FACT_FAD_lib" 2288 blo " 20200,59800"2275 blo "40200,52800" 2289 2276 tm "BdLibraryNameMgr" 2290 2277 ) … … 2294 2281 font "Arial,8,1" 2295 2282 ) 2296 xt " 20200,60000,30100,61000"2283 xt "40200,53000,50100,54000" 2297 2284 st "controlRAM_16bit_x256" 2298 blo " 20200,60800"2285 blo "40200,53800" 2299 2286 tm "CptNameMgr" 2300 2287 ) … … 2304 2291 font "Arial,8,1" 2305 2292 ) 2306 xt " 20200,61000,26100,62000"2293 xt "40200,54000,46100,55000" 2307 2294 st "I_control_ram" 2308 blo " 20200,61800"2295 blo "40200,54800" 2309 2296 tm "InstanceNameMgr" 2310 2297 ) … … 2321 2308 font "Courier New,8,0" 2322 2309 ) 2323 xt " 19500,48000,19500,48000"2310 xt "39500,41000,39500,41000" 2324 2311 ) 2325 2312 header "" … … 2335 2322 fg "49152,49152,49152" 2336 2323 ) 2337 xt "20250,57250,21750,58750" 2338 iconName "UnknownFile.png" 2339 iconMaskName "UnknownFile.msk" 2324 xt "40250,50250,41750,51750" 2325 iconName "VhdlFileViewIcon.png" 2326 iconMaskName "VhdlFileViewIcon.msk" 2327 ftype 10 2340 2328 ) 2341 2329 ordering 1 … … 2360 2348 font "Courier New,8,0" 2361 2349 ) 2362 xt "22000,8400,41500,9200" 2363 st "config_started : std_logic := '0' 2364 " 2350 xt "29000,8600,48500,9400" 2351 st "config_started : std_logic := '0'" 2365 2352 ) 2366 2353 ) … … 2378 2365 sl 0 2379 2366 ro 270 2380 xt " 42500,30625,44000,31375"2367 xt "36500,30625,38000,31375" 2381 2368 ) 2382 2369 (Line … … 2384 2371 sl 0 2385 2372 ro 270 2386 xt " 42000,31000,42500,31000"2373 xt "36000,31000,36500,31000" 2387 2374 pts [ 2388 " 42000,31000"2389 " 42500,31000"2375 "36000,31000" 2376 "36500,31000" 2390 2377 ] 2391 2378 ) … … 2402 2389 va (VaSet 2403 2390 ) 2404 xt " 45000,30500,50600,31500"2391 xt "39000,30500,44600,31500" 2405 2392 st "config_started" 2406 blo " 45000,31300"2393 blo "39000,31300" 2407 2394 tm "WireNameMgr" 2408 2395 ) … … 2417 2404 lineWidth 2 2418 2405 ) 2419 xt "3 8750,24000,42000,24000"2406 xt "32750,24000,36000,24000" 2420 2407 pts [ 2421 "42000,24000" 2422 "40000,24000" 2423 "38750,24000" 2408 "36000,24000" 2409 "32750,24000" 2424 2410 ] 2425 2411 ) … … 2442 2428 isHidden 1 2443 2429 ) 2444 xt " 45000,23000,49800,24000"2430 xt "39000,23000,43800,24000" 2445 2431 st "config_addr" 2446 blo " 45000,23800"2432 blo "39000,23800" 2447 2433 tm "WireNameMgr" 2448 2434 ) … … 2458 2444 lineWidth 2 2459 2445 ) 2460 xt " 13000,39000,43000,54000"2446 xt "32750,39000,39250,47000" 2461 2447 pts [ 2462 "19250,54000" 2463 "13000,54000" 2464 "13000,47000" 2465 "43000,47000" 2466 "43000,39000" 2467 "38750,39000" 2448 "39250,47000" 2449 "34000,47000" 2450 "34000,39000" 2451 "32750,39000" 2468 2452 ] 2469 2453 ) … … 2484 2468 va (VaSet 2485 2469 ) 2486 xt " 23000,46000,29300,47000"2470 xt "34000,46000,40300,47000" 2487 2471 st "ram_wren : (0:0)" 2488 blo " 23000,46800"2472 blo "34000,46800" 2489 2473 tm "WireNameMgr" 2490 2474 ) … … 2500 2484 lineWidth 2 2501 2485 ) 2502 xt " 14000,38000,44000,53000"2486 xt "32750,38000,39250,46000" 2503 2487 pts [ 2504 "19250,53000" 2505 "14000,53000" 2506 "14000,48000" 2507 "44000,48000" 2508 "44000,38000" 2509 "38750,38000" 2488 "39250,46000" 2489 "35000,46000" 2490 "35000,38000" 2491 "32750,38000" 2510 2492 ] 2511 2493 ) … … 2526 2508 va (VaSet 2527 2509 ) 2528 xt " 23000,47000,30900,48000"2510 xt "33000,37000,40900,38000" 2529 2511 st "ram_data_in : (15:0)" 2530 blo " 23000,47800"2512 blo "33000,37800" 2531 2513 tm "WireNameMgr" 2532 2514 ) … … 2541 2523 vasetType 3 2542 2524 ) 2543 xt " 5000,24000,12250,24000"2525 xt "4000,20000,6250,24000" 2544 2526 pts [ 2527 "4000,20000" 2528 "5000,20000" 2545 2529 "5000,24000" 2546 " 12250,24000"2530 "6250,24000" 2547 2531 ] 2548 2532 ) … … 2564 2548 isHidden 1 2565 2549 ) 2566 xt " 7000,23000,8300,24000"2550 xt "6000,19000,7300,20000" 2567 2551 st "clk" 2568 blo " 7000,23800"2552 blo "6000,19800" 2569 2553 tm "WireNameMgr" 2570 2554 ) … … 2579 2563 vasetType 3 2580 2564 ) 2581 xt "3 8750,32000,42000,32000"2565 xt "32750,32000,36000,32000" 2582 2566 pts [ 2583 "3 8750,32000"2584 " 42000,32000"2567 "32750,32000" 2568 "36000,32000" 2585 2569 ] 2586 2570 ) … … 2602 2586 isHidden 1 2603 2587 ) 2604 xt " 45000,30000,51600,31000"2588 xt "39000,30000,45600,31000" 2605 2589 st "config_data_valid" 2606 blo " 45000,30800"2590 blo "39000,30800" 2607 2591 tm "WireNameMgr" 2608 2592 ) … … 2617 2601 vasetType 3 2618 2602 ) 2619 xt "3 8750,33000,42000,33000"2603 xt "32750,33000,36000,33000" 2620 2604 pts [ 2621 "3 8750,33000"2622 " 42000,33000"2605 "32750,33000" 2606 "36000,33000" 2623 2607 ] 2624 2608 ) … … 2640 2624 isHidden 1 2641 2625 ) 2642 xt " 45000,31000,49800,32000"2626 xt "39000,31000,43800,32000" 2643 2627 st "config_busy" 2644 blo " 45000,31800"2628 blo "39000,31800" 2645 2629 tm "WireNameMgr" 2646 2630 ) … … 2656 2640 lineWidth 2 2657 2641 ) 2658 xt "3 8750,25000,42000,25000"2642 xt "32750,25000,36000,25000" 2659 2643 pts [ 2660 "42000,25000" 2661 "40000,25000" 2662 "38750,25000" 2644 "36000,25000" 2645 "32750,25000" 2663 2646 ] 2664 2647 ) … … 2681 2664 isHidden 1 2682 2665 ) 2683 xt " 45000,24000,49700,25000"2666 xt "39000,24000,43700,25000" 2684 2667 st "config_data" 2685 blo " 45000,24800"2668 blo "39000,24800" 2686 2669 tm "WireNameMgr" 2687 2670 ) … … 2696 2679 vasetType 3 2697 2680 ) 2698 xt "3 8750,35000,42000,35000"2681 xt "32750,35000,36000,35000" 2699 2682 pts [ 2700 "38750,35000" 2701 "40000,35000" 2702 "42000,35000" 2683 "32750,35000" 2684 "36000,35000" 2703 2685 ] 2704 2686 ) … … 2720 2702 isHidden 1 2721 2703 ) 2722 xt " 45000,34000,48400,35000"2704 xt "39000,34000,42400,35000" 2723 2705 st "roi_array" 2724 blo " 45000,34800"2706 blo "39000,34800" 2725 2707 tm "WireNameMgr" 2726 2708 ) … … 2735 2717 vasetType 3 2736 2718 ) 2737 xt " 17000,51000,19250,51000"2719 xt "43000,38000,43000,41250" 2738 2720 pts [ 2739 " 17000,51000"2740 " 19250,51000"2721 "43000,38000" 2722 "43000,41250" 2741 2723 ] 2742 2724 ) … … 2755 2737 va (VaSet 2756 2738 ) 2757 xt " 18000,50000,19300,51000"2739 xt "44000,37000,45300,38000" 2758 2740 st "clk" 2759 blo " 18000,50800"2741 blo "44000,37800" 2760 2742 tm "WireNameMgr" 2761 2743 ) … … 2771 2753 lineWidth 2 2772 2754 ) 2773 xt " 12000,40000,42000,55000"2755 xt "32750,40000,39250,48000" 2774 2756 pts [ 2775 "38750,40000" 2776 "42000,40000" 2777 "42000,46000" 2778 "12000,46000" 2779 "12000,55000" 2780 "19250,55000" 2757 "32750,40000" 2758 "33000,40000" 2759 "33000,48000" 2760 "39250,48000" 2781 2761 ] 2782 2762 ) … … 2797 2777 va (VaSet 2798 2778 ) 2799 xt " 23000,45000,29200,46000"2779 xt "33000,47000,39200,48000" 2800 2780 st "ram_addr : (7:0)" 2801 blo " 23000,45800"2781 blo "33000,47800" 2802 2782 tm "WireNameMgr" 2803 2783 ) … … 2812 2792 vasetType 3 2813 2793 ) 2814 xt "3 8750,30000,42000,30000"2794 xt "32750,30000,36000,30000" 2815 2795 pts [ 2816 "42000,30000" 2817 "40000,30000" 2818 "38750,30000" 2796 "36000,30000" 2797 "32750,30000" 2819 2798 ] 2820 2799 ) … … 2836 2815 isHidden 1 2837 2816 ) 2838 xt " 45000,29000,49800,30000"2817 xt "39000,29000,43800,30000" 2839 2818 st "config_start" 2840 blo " 45000,29800"2819 blo "39000,29800" 2841 2820 tm "WireNameMgr" 2842 2821 ) … … 2851 2830 vasetType 3 2852 2831 ) 2853 xt "3 8750,27000,42000,27000"2832 xt "32750,27000,36000,27000" 2854 2833 pts [ 2855 "42000,27000" 2856 "40000,27000" 2857 "38750,27000" 2834 "36000,27000" 2835 "32750,27000" 2858 2836 ] 2859 2837 ) … … 2875 2853 isHidden 1 2876 2854 ) 2877 xt " 45000,26000,50300,27000"2855 xt "39000,26000,44300,27000" 2878 2856 st "config_wr_en" 2879 blo " 45000,26800"2857 blo "39000,26800" 2880 2858 tm "WireNameMgr" 2881 2859 ) … … 2891 2869 lineWidth 2 2892 2870 ) 2893 xt " 9000,25000,34000,64000"2871 xt "3000,39000,52000,56000" 2894 2872 pts [ 2895 " 12250,25000"2896 " 9000,25000"2897 " 9000,64000"2898 " 34000,64000"2899 " 34000,51000"2900 " 30750,51000"2873 "6250,39000" 2874 "3000,39000" 2875 "3000,56000" 2876 "52000,56000" 2877 "52000,44000" 2878 "50750,44000" 2901 2879 ] 2902 2880 ) … … 2917 2895 va (VaSet 2918 2896 ) 2919 xt " 20000,63000,28300,64000"2897 xt "33000,55000,41300,56000" 2920 2898 st "ram_data_out : (15:0)" 2921 blo " 20000,63800"2899 blo "33000,55800" 2922 2900 tm "WireNameMgr" 2923 2901 ) … … 2932 2910 vasetType 3 2933 2911 ) 2934 xt "3 8750,34000,42000,34000"2912 xt "32750,34000,36000,34000" 2935 2913 pts [ 2936 "38750,34000" 2937 "40000,34000" 2938 "42000,34000" 2914 "32750,34000" 2915 "36000,34000" 2939 2916 ] 2940 2917 ) … … 2956 2933 isHidden 1 2957 2934 ) 2958 xt " 45000,33000,48700,34000"2935 xt "39000,33000,42700,34000" 2959 2936 st "dac_array" 2960 blo " 45000,33800"2937 blo "39000,33800" 2961 2938 tm "WireNameMgr" 2962 2939 ) … … 2971 2948 vasetType 3 2972 2949 ) 2973 xt "3 8750,28000,42000,28000"2950 xt "32750,28000,36000,28000" 2974 2951 pts [ 2975 "42000,28000" 2976 "40000,28000" 2977 "38750,28000" 2952 "36000,28000" 2953 "32750,28000" 2978 2954 ] 2979 2955 ) … … 2995 2971 isHidden 1 2996 2972 ) 2997 xt " 45000,27000,50200,28000"2973 xt "39000,27000,44200,28000" 2998 2974 st "config_rd_en" 2999 blo " 45000,27800"2975 blo "39000,27800" 3000 2976 tm "WireNameMgr" 3001 2977 ) … … 3010 2986 vasetType 3 3011 2987 ) 3012 xt "3 8750,29000,42000,29000"2988 xt "32750,29000,36000,29000" 3013 2989 pts [ 3014 "38750,29000" 3015 "40000,29000" 3016 "42000,29000" 2990 "32750,29000" 2991 "36000,29000" 3017 2992 ] 3018 2993 ) … … 3034 3009 isHidden 1 3035 3010 ) 3036 xt " 45000,28000,50100,29000"3011 xt "39000,28000,44100,29000" 3037 3012 st "config_ready" 3038 blo " 45000,28800"3013 blo "39000,28800" 3039 3014 tm "WireNameMgr" 3040 3015 ) … … 3049 3024 vasetType 3 3050 3025 ) 3051 xt "3 8750,31000,42000,31000"3026 xt "32750,31000,36000,31000" 3052 3027 pts [ 3053 "3 8750,31000"3054 " 42000,31000"3028 "32750,31000" 3029 "36000,31000" 3055 3030 ] 3056 3031 ) … … 3072 3047 isHidden 1 3073 3048 ) 3074 xt " 40000,30000,45600,31000"3049 xt "34000,30000,39600,31000" 3075 3050 st "config_started" 3076 blo " 40000,30800"3051 blo "34000,30800" 3077 3052 tm "WireNameMgr" 3078 3053 ) … … 3101 3076 font "arial,8,1" 3102 3077 ) 3103 xt " 0,0,5400,1000"3078 xt "1000,1000,6400,2000" 3104 3079 st "Package List" 3105 blo " 0,800"3080 blo "1000,1800" 3106 3081 ) 3107 3082 *88 (MLText … … 3109 3084 va (VaSet 3110 3085 ) 3111 xt " 0,1000,15300,6000"3086 xt "1000,2000,16300,7000" 3112 3087 st "LIBRARY ieee; 3113 3088 USE ieee.std_logic_1164.ALL; … … 3192 3167 associable 1 3193 3168 ) 3194 windowSize "0, 22,1286,1024"3195 viewArea " 834,16774,54098,59806"3196 cachedDiagramExtent " 0,0,53000,77000"3169 windowSize "0,0,1281,1002" 3170 viewArea "-6400,12035,60443,65774" 3171 cachedDiagramExtent "700,0,59000,77000" 3197 3172 pageSetupInfo (PageSetupInfo 3198 3173 ptrCmd "Brother HL-5270DN series,winspool," … … 3220 3195 hasePageBreakOrigin 1 3221 3196 pageBreakOrigin "0,0" 3222 lastUid 11 22,03197 lastUid 1172,0 3223 3198 defaultCommentText (CommentText 3224 3199 shape (Rectangle … … 4167 4142 font "Arial,8,1" 4168 4143 ) 4169 xt "2 0000,0,25400,1000"4144 xt "27000,200,32400,1200" 4170 4145 st "Declarations" 4171 blo "2 0000,800"4146 blo "27000,1000" 4172 4147 ) 4173 4148 portLabel (Text … … 4176 4151 font "Arial,8,1" 4177 4152 ) 4178 xt "2 0000,1000,22700,2000"4153 xt "27000,1200,29700,2200" 4179 4154 st "Ports:" 4180 blo "2 0000,1800"4155 blo "27000,2000" 4181 4156 ) 4182 4157 preUserLabel (Text … … 4186 4161 font "Arial,8,1" 4187 4162 ) 4188 xt "2 0000,0,23800,1000"4163 xt "27000,200,30800,1200" 4189 4164 st "Pre User:" 4190 blo "2 0000,800"4165 blo "27000,1000" 4191 4166 ) 4192 4167 preUserText (MLText … … 4196 4171 font "Courier New,8,0" 4197 4172 ) 4198 xt "2 0000,0,20000,0"4173 xt "27000,200,27000,200" 4199 4174 tm "BdDeclarativeTextMgr" 4200 4175 ) … … 4204 4179 font "Arial,8,1" 4205 4180 ) 4206 xt "2 0000,11600,27100,12600"4181 xt "27000,11800,34100,12800" 4207 4182 st "Diagram Signals:" 4208 blo "2 0000,12400"4183 blo "27000,12600" 4209 4184 ) 4210 4185 postUserLabel (Text … … 4214 4189 font "Arial,8,1" 4215 4190 ) 4216 xt "2 0000,0,24700,1000"4191 xt "27000,200,31700,1200" 4217 4192 st "Post User:" 4218 blo "2 0000,800"4193 blo "27000,1000" 4219 4194 ) 4220 4195 postUserText (MLText … … 4224 4199 font "Courier New,8,0" 4225 4200 ) 4226 xt "2 0000,0,20000,0"4201 xt "27000,200,27000,200" 4227 4202 tm "BdDeclarativeTextMgr" 4228 4203 ) -
FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/control_unit/symbol.sb
r246 r252 25 25 ) 26 26 version "24.1" 27 appVersion "2009. 1 (Build 12)"27 appVersion "2009.2 (Build 10)" 28 28 model (Symbol 29 29 commonDM (CommonDM 30 30 ldm (LogicalDM 31 suid 1 2,031 suid 14,0 32 32 usingSuid 1 33 33 emptyRow *1 (LEmptyRow … … 122 122 t "std_logic_vector" 123 123 b "(15 DOWNTO 0)" 124 o 1 2124 o 14 125 125 suid 5,0 126 126 ) … … 134 134 n "roi_array" 135 135 t "roi_array_type" 136 o 1 1136 o 13 137 137 suid 6,0 138 138 ) … … 210 210 uid 349,0 211 211 ) 212 *26 (LogPort 213 port (LogicalPort 214 m 1 215 decl (Decl 216 n "drs_address" 217 t "std_logic_vector" 218 b "(3 DOWNTO 0)" 219 o 11 220 suid 13,0 221 ) 222 ) 223 uid 518,0 224 ) 225 *27 (LogPort 226 port (LogicalPort 227 m 1 228 decl (Decl 229 n "drs_address_mode" 230 t "std_logic" 231 o 12 232 suid 14,0 233 ) 234 ) 235 uid 520,0 236 ) 212 237 ] 213 238 ) … … 217 242 uid 66,0 218 243 optionalChildren [ 219 *2 6(Sheet244 *28 (Sheet 220 245 sheetRow (SheetRow 221 246 headerVa (MVa … … 234 259 font "Tahoma,10,0" 235 260 ) 236 emptyMRCItem *2 7(MRCItem261 emptyMRCItem *29 (MRCItem 237 262 litem &1 238 263 pos 11 … … 241 266 uid 68,0 242 267 optionalChildren [ 243 * 28(MRCItem268 *30 (MRCItem 244 269 litem &2 245 270 pos 0 … … 247 272 uid 69,0 248 273 ) 249 * 29(MRCItem274 *31 (MRCItem 250 275 litem &3 251 276 pos 1 … … 253 278 uid 70,0 254 279 ) 255 *3 0(MRCItem280 *32 (MRCItem 256 281 litem &4 257 282 pos 2 … … 260 285 uid 71,0 261 286 ) 262 *3 1(MRCItem287 *33 (MRCItem 263 288 litem &14 264 289 pos 0 … … 266 291 uid 108,0 267 292 ) 268 *3 2(MRCItem293 *34 (MRCItem 269 294 litem &15 270 295 pos 1 … … 272 297 uid 110,0 273 298 ) 274 *3 3(MRCItem299 *35 (MRCItem 275 300 litem &16 276 301 pos 2 … … 278 303 uid 112,0 279 304 ) 280 *3 4(MRCItem305 *36 (MRCItem 281 306 litem &17 282 307 pos 3 … … 284 309 uid 114,0 285 310 ) 286 *3 5(MRCItem311 *37 (MRCItem 287 312 litem &18 288 313 pos 4 … … 290 315 uid 116,0 291 316 ) 292 *3 6(MRCItem317 *38 (MRCItem 293 318 litem &19 294 319 pos 5 … … 296 321 uid 118,0 297 322 ) 298 *3 7(MRCItem323 *39 (MRCItem 299 324 litem &20 300 325 pos 6 … … 302 327 uid 120,0 303 328 ) 304 * 38(MRCItem329 *40 (MRCItem 305 330 litem &21 306 331 pos 7 … … 308 333 uid 122,0 309 334 ) 310 * 39(MRCItem335 *41 (MRCItem 311 336 litem &22 312 337 pos 8 … … 314 339 uid 124,0 315 340 ) 316 *4 0(MRCItem341 *42 (MRCItem 317 342 litem &23 318 343 pos 9 … … 320 345 uid 126,0 321 346 ) 322 *4 1(MRCItem347 *43 (MRCItem 323 348 litem &24 324 349 pos 10 … … 326 351 uid 128,0 327 352 ) 328 *4 2(MRCItem353 *44 (MRCItem 329 354 litem &25 330 355 pos 11 331 356 dimension 20 332 357 uid 348,0 358 ) 359 *45 (MRCItem 360 litem &26 361 pos 12 362 dimension 20 363 uid 517,0 364 ) 365 *46 (MRCItem 366 litem &27 367 pos 13 368 dimension 20 369 uid 519,0 333 370 ) 334 371 ] … … 343 380 uid 72,0 344 381 optionalChildren [ 345 *4 3(MRCItem382 *47 (MRCItem 346 383 litem &5 347 384 pos 0 … … 349 386 uid 73,0 350 387 ) 351 *4 4(MRCItem388 *48 (MRCItem 352 389 litem &7 353 390 pos 1 … … 355 392 uid 74,0 356 393 ) 357 *4 5(MRCItem394 *49 (MRCItem 358 395 litem &8 359 396 pos 2 … … 361 398 uid 75,0 362 399 ) 363 * 46(MRCItem400 *50 (MRCItem 364 401 litem &9 365 402 pos 3 … … 367 404 uid 76,0 368 405 ) 369 * 47(MRCItem406 *51 (MRCItem 370 407 litem &10 371 408 pos 4 … … 373 410 uid 77,0 374 411 ) 375 * 48(MRCItem412 *52 (MRCItem 376 413 litem &11 377 414 pos 5 … … 379 416 uid 78,0 380 417 ) 381 * 49(MRCItem418 *53 (MRCItem 382 419 litem &12 383 420 pos 6 … … 385 422 uid 79,0 386 423 ) 387 *5 0(MRCItem424 *54 (MRCItem 388 425 litem &13 389 426 pos 7 … … 406 443 genericsCommonDM (CommonDM 407 444 ldm (LogicalDM 408 emptyRow *5 1(LEmptyRow445 emptyRow *55 (LEmptyRow 409 446 ) 410 447 uid 82,0 411 448 optionalChildren [ 412 *5 2(RefLabelRowHdr413 ) 414 *5 3(TitleRowHdr415 ) 416 *5 4(FilterRowHdr417 ) 418 *5 5(RefLabelColHdr449 *56 (RefLabelRowHdr 450 ) 451 *57 (TitleRowHdr 452 ) 453 *58 (FilterRowHdr 454 ) 455 *59 (RefLabelColHdr 419 456 tm "RefLabelColHdrMgr" 420 457 ) 421 * 56(RowExpandColHdr458 *60 (RowExpandColHdr 422 459 tm "RowExpandColHdrMgr" 423 460 ) 424 * 57(GroupColHdr461 *61 (GroupColHdr 425 462 tm "GroupColHdrMgr" 426 463 ) 427 * 58(NameColHdr464 *62 (NameColHdr 428 465 tm "GenericNameColHdrMgr" 429 466 ) 430 * 59(TypeColHdr467 *63 (TypeColHdr 431 468 tm "GenericTypeColHdrMgr" 432 469 ) 433 *6 0(InitColHdr470 *64 (InitColHdr 434 471 tm "GenericValueColHdrMgr" 435 472 ) 436 *6 1(PragmaColHdr473 *65 (PragmaColHdr 437 474 tm "GenericPragmaColHdrMgr" 438 475 ) 439 *6 2(EolColHdr476 *66 (EolColHdr 440 477 tm "GenericEolColHdrMgr" 441 478 ) … … 447 484 uid 94,0 448 485 optionalChildren [ 449 *6 3(Sheet486 *67 (Sheet 450 487 sheetRow (SheetRow 451 488 headerVa (MVa … … 464 501 font "Tahoma,10,0" 465 502 ) 466 emptyMRCItem *6 4(MRCItem467 litem &5 1503 emptyMRCItem *68 (MRCItem 504 litem &55 468 505 pos 0 469 506 dimension 20 … … 471 508 uid 96,0 472 509 optionalChildren [ 473 *6 5(MRCItem474 litem &5 2510 *69 (MRCItem 511 litem &56 475 512 pos 0 476 513 dimension 20 477 514 uid 97,0 478 515 ) 479 * 66(MRCItem480 litem &5 3516 *70 (MRCItem 517 litem &57 481 518 pos 1 482 519 dimension 23 483 520 uid 98,0 484 521 ) 485 * 67(MRCItem486 litem &5 4522 *71 (MRCItem 523 litem &58 487 524 pos 2 488 525 hidden 1 … … 501 538 uid 100,0 502 539 optionalChildren [ 503 * 68(MRCItem504 litem &5 5540 *72 (MRCItem 541 litem &59 505 542 pos 0 506 543 dimension 20 507 544 uid 101,0 508 545 ) 509 * 69(MRCItem510 litem & 57546 *73 (MRCItem 547 litem &61 511 548 pos 1 512 549 dimension 50 513 550 uid 102,0 514 551 ) 515 *7 0(MRCItem516 litem & 58552 *74 (MRCItem 553 litem &62 517 554 pos 2 518 555 dimension 100 519 556 uid 103,0 520 557 ) 521 *7 1(MRCItem522 litem & 59558 *75 (MRCItem 559 litem &63 523 560 pos 3 524 561 dimension 100 525 562 uid 104,0 526 563 ) 527 *7 2(MRCItem528 litem &6 0564 *76 (MRCItem 565 litem &64 529 566 pos 4 530 567 dimension 50 531 568 uid 105,0 532 569 ) 533 *7 3(MRCItem534 litem &6 1570 *77 (MRCItem 571 litem &65 535 572 pos 5 536 573 dimension 50 537 574 uid 106,0 538 575 ) 539 *7 4(MRCItem540 litem &6 2576 *78 (MRCItem 577 litem &66 541 578 pos 6 542 579 dimension 80 … … 561 598 (vvPair 562 599 variable "HDLDir" 563 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hdl"600 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hdl" 564 601 ) 565 602 (vvPair 566 603 variable "HDSDir" 567 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"604 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 568 605 ) 569 606 (vvPair 570 607 variable "SideDataDesignDir" 571 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info"608 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.info" 572 609 ) 573 610 (vvPair 574 611 variable "SideDataUserDir" 575 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user"612 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb.user" 576 613 ) 577 614 (vvPair 578 615 variable "SourceDir" 579 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds"616 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds" 580 617 ) 581 618 (vvPair … … 593 630 (vvPair 594 631 variable "d" 595 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"632 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 596 633 ) 597 634 (vvPair 598 635 variable "d_logical" 599 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit"636 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit" 600 637 ) 601 638 (vvPair 602 639 variable "date" 603 value " 27.05.2010"640 value "12.07.2010" 604 641 ) 605 642 (vvPair 606 643 variable "day" 607 value " Do"644 value "Mo" 608 645 ) 609 646 (vvPair 610 647 variable "day_long" 611 value " Donnerstag"648 value "Montag" 612 649 ) 613 650 (vvPair 614 651 variable "dd" 615 value " 27"652 value "12" 616 653 ) 617 654 (vvPair … … 641 678 (vvPair 642 679 variable "host" 643 value " IHP110"680 value "TU-CC4900F8C7D2" 644 681 ) 645 682 (vvPair … … 669 706 (vvPair 670 707 variable "mm" 671 value "0 5"708 value "07" 672 709 ) 673 710 (vvPair … … 677 714 (vvPair 678 715 variable "month" 679 value " Mai"716 value "Jul" 680 717 ) 681 718 (vvPair 682 719 variable "month_long" 683 value " Mai"720 value "Juli" 684 721 ) 685 722 (vvPair 686 723 variable "p" 687 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"724 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" 688 725 ) 689 726 (vvPair 690 727 variable "p_logical" 691 value " D:\\FAD_Firmware\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb"728 value "C:\\FPGA_projects\\fact_repos\\FPGA\\FAD\\stable\\FACT_FAD\\FACT_FAD_lib\\hds\\control_unit\\symbol.sb" 692 729 ) 693 730 (vvPair … … 713 750 (vvPair 714 751 variable "task_ModelSimPath" 715 value " D:\\modeltech_6.5e\\win32"752 value "<TBD>" 716 753 ) 717 754 (vvPair … … 745 782 (vvPair 746 783 variable "time" 747 value "1 0:24:05"784 value "14:13:34" 748 785 ) 749 786 (vvPair … … 753 790 (vvPair 754 791 variable "user" 755 value "d aqct3"792 value "dneise" 756 793 ) 757 794 (vvPair 758 795 variable "version" 759 value "2009. 1 (Build 12)"796 value "2009.2 (Build 10)" 760 797 ) 761 798 (vvPair … … 776 813 uid 51,0 777 814 optionalChildren [ 778 *7 5(SymbolBody815 *79 (SymbolBody 779 816 uid 8,0 780 817 optionalChildren [ 781 * 76(CptPort818 *80 (CptPort 782 819 uid 130,0 783 820 ps "OnEdgeStrategy" … … 811 848 ) 812 849 xt "44000,2000,65000,2800" 813 st "clk : IN STD_LOGIC ;" 850 st "clk : IN STD_LOGIC ; 851 " 814 852 ) 815 853 thePort (LogicalPort … … 822 860 ) 823 861 ) 824 * 77(CptPort862 *81 (CptPort 825 863 uid 135,0 826 864 ps "OnEdgeStrategy" … … 855 893 ) 856 894 xt "44000,2800,75000,3600" 857 st "config_addr : IN std_logic_vector (7 DOWNTO 0) ;" 895 st "config_addr : IN std_logic_vector (7 DOWNTO 0) ; 896 " 858 897 ) 859 898 thePort (LogicalPort … … 867 906 ) 868 907 ) 869 * 78(CptPort908 *82 (CptPort 870 909 uid 140,0 871 910 ps "OnEdgeStrategy" … … 900 939 ) 901 940 xt "44000,6800,65000,7600" 902 st "config_data_valid : OUT std_logic ;" 941 st "config_data_valid : OUT std_logic ; 942 " 903 943 ) 904 944 thePort (LogicalPort … … 912 952 ) 913 953 ) 914 * 79(CptPort954 *83 (CptPort 915 955 uid 145,0 916 956 ps "OnEdgeStrategy" … … 945 985 ) 946 986 xt "44000,6000,65000,6800" 947 st "config_busy : OUT std_logic ;" 987 st "config_busy : OUT std_logic ; 988 " 948 989 ) 949 990 thePort (LogicalPort … … 957 998 ) 958 999 ) 959 *8 0(CptPort1000 *84 (CptPort 960 1001 uid 150,0 961 1002 ps "OnEdgeStrategy" … … 989 1030 font "Courier New,8,0" 990 1031 ) 991 xt "44000,10800,74500,11600" 992 st "config_data : INOUT std_logic_vector (15 DOWNTO 0)" 1032 xt "44000,12400,74500,13200" 1033 st "config_data : INOUT std_logic_vector (15 DOWNTO 0) 1034 " 993 1035 ) 994 1036 thePort (LogicalPort … … 998 1040 t "std_logic_vector" 999 1041 b "(15 DOWNTO 0)" 1000 o 1 21042 o 14 1001 1043 suid 5,0 1002 1044 ) 1003 1045 ) 1004 1046 ) 1005 *8 1(CptPort1047 *85 (CptPort 1006 1048 uid 155,0 1007 1049 ps "OnEdgeStrategy" … … 1035 1077 font "Courier New,8,0" 1036 1078 ) 1037 xt "44000,10000,68000,10800" 1038 st "roi_array : OUT roi_array_type ;" 1079 xt "44000,11600,68000,12400" 1080 st "roi_array : OUT roi_array_type ; 1081 " 1039 1082 ) 1040 1083 thePort (LogicalPort … … 1043 1086 n "roi_array" 1044 1087 t "roi_array_type" 1045 o 1 11088 o 13 1046 1089 suid 6,0 1047 1090 ) 1048 1091 ) 1049 1092 ) 1050 *8 2(CptPort1093 *86 (CptPort 1051 1094 uid 160,0 1052 1095 ps "OnEdgeStrategy" … … 1081 1124 ) 1082 1125 xt "44000,5200,65000,6000" 1083 st "config_wr_en : IN std_logic ;" 1126 st "config_wr_en : IN std_logic ; 1127 " 1084 1128 ) 1085 1129 thePort (LogicalPort … … 1092 1136 ) 1093 1137 ) 1094 *8 3(CptPort1138 *87 (CptPort 1095 1139 uid 165,0 1096 1140 ps "OnEdgeStrategy" … … 1125 1169 ) 1126 1170 xt "44000,9200,68000,10000" 1127 st "dac_array : OUT dac_array_type ;" 1171 st "dac_array : OUT dac_array_type ; 1172 " 1128 1173 ) 1129 1174 thePort (LogicalPort … … 1137 1182 ) 1138 1183 ) 1139 *8 4(CptPort1184 *88 (CptPort 1140 1185 uid 170,0 1141 1186 ps "OnEdgeStrategy" … … 1170 1215 ) 1171 1216 xt "44000,3600,65000,4400" 1172 st "config_rd_en : IN std_logic ;" 1217 st "config_rd_en : IN std_logic ; 1218 " 1173 1219 ) 1174 1220 thePort (LogicalPort … … 1181 1227 ) 1182 1228 ) 1183 *8 5(CptPort1229 *89 (CptPort 1184 1230 uid 175,0 1185 1231 ps "OnEdgeStrategy" … … 1214 1260 ) 1215 1261 xt "44000,4400,65000,5200" 1216 st "config_start : IN std_logic ;" 1262 st "config_start : IN std_logic ; 1263 " 1217 1264 ) 1218 1265 thePort (LogicalPort … … 1225 1272 ) 1226 1273 ) 1227 * 86(CptPort1274 *90 (CptPort 1228 1275 uid 180,0 1229 1276 ps "OnEdgeStrategy" … … 1258 1305 ) 1259 1306 xt "44000,7600,65000,8400" 1260 st "config_ready : OUT std_logic ;" 1307 st "config_ready : OUT std_logic ; 1308 " 1261 1309 ) 1262 1310 thePort (LogicalPort … … 1270 1318 ) 1271 1319 ) 1272 * 87(CptPort1320 *91 (CptPort 1273 1321 uid 350,0 1274 1322 ps "OnEdgeStrategy" … … 1313 1361 ) 1314 1362 xt "44000,8400,69000,9200" 1315 st "config_started : OUT std_logic := '0' ;" 1363 st "config_started : OUT std_logic := '0' ; 1364 " 1316 1365 ) 1317 1366 thePort (LogicalPort … … 1326 1375 ) 1327 1376 ) 1377 *92 (CptPort 1378 uid 521,0 1379 ps "OnEdgeStrategy" 1380 shape (Triangle 1381 uid 522,0 1382 ro 90 1383 va (VaSet 1384 vasetType 1 1385 fg "0,65535,0" 1386 ) 1387 xt "33000,28625,33750,29375" 1388 ) 1389 tg (CPTG 1390 uid 523,0 1391 ps "CptPortTextPlaceStrategy" 1392 stg "RightVerticalLayoutStrategy" 1393 f (Text 1394 uid 524,0 1395 va (VaSet 1396 ) 1397 xt "24800,28500,32000,29500" 1398 st "drs_address : (3:0)" 1399 ju 2 1400 blo "32000,29300" 1401 tm "CptPortNameMgr" 1402 ) 1403 ) 1404 dt (MLText 1405 uid 525,0 1406 va (VaSet 1407 font "Courier New,8,0" 1408 ) 1409 xt "44000,10000,75000,10800" 1410 st "drs_address : OUT std_logic_vector (3 DOWNTO 0) ; 1411 " 1412 ) 1413 thePort (LogicalPort 1414 m 1 1415 decl (Decl 1416 n "drs_address" 1417 t "std_logic_vector" 1418 b "(3 DOWNTO 0)" 1419 o 11 1420 suid 13,0 1421 ) 1422 ) 1423 ) 1424 *93 (CptPort 1425 uid 526,0 1426 ps "OnEdgeStrategy" 1427 shape (Triangle 1428 uid 527,0 1429 ro 90 1430 va (VaSet 1431 vasetType 1 1432 fg "0,65535,0" 1433 ) 1434 xt "33000,30625,33750,31375" 1435 ) 1436 tg (CPTG 1437 uid 528,0 1438 ps "CptPortTextPlaceStrategy" 1439 stg "RightVerticalLayoutStrategy" 1440 f (Text 1441 uid 529,0 1442 va (VaSet 1443 ) 1444 xt "24800,30500,32000,31500" 1445 st "drs_address_mode" 1446 ju 2 1447 blo "32000,31300" 1448 tm "CptPortNameMgr" 1449 ) 1450 ) 1451 dt (MLText 1452 uid 530,0 1453 va (VaSet 1454 font "Courier New,8,0" 1455 ) 1456 xt "44000,10800,65000,11600" 1457 st "drs_address_mode : OUT std_logic ; 1458 " 1459 ) 1460 thePort (LogicalPort 1461 m 1 1462 decl (Decl 1463 n "drs_address_mode" 1464 t "std_logic" 1465 o 12 1466 suid 14,0 1467 ) 1468 ) 1469 ) 1328 1470 ] 1329 1471 shape (Rectangle … … 1335 1477 lineWidth 2 1336 1478 ) 1337 xt "15000,13000,33000, 28000"1479 xt "15000,13000,33000,32000" 1338 1480 ) 1339 1481 oxt "15000,13000,33000,26000" … … 1361 1503 ) 1362 1504 ) 1363 gi * 88(GenericInterface1505 gi *94 (GenericInterface 1364 1506 uid 13,0 1365 1507 ps "CenterOffsetStrategy" … … 1388 1530 ) 1389 1531 ) 1390 * 89(Grouping1532 *95 (Grouping 1391 1533 uid 16,0 1392 1534 optionalChildren [ 1393 *9 0(CommentText1535 *96 (CommentText 1394 1536 uid 18,0 1395 1537 shape (Rectangle … … 1409 1551 bg "0,0,32768" 1410 1552 ) 1411 xt "36200,48000,45 900,49000"1553 xt "36200,48000,45500,49000" 1412 1554 st " 1413 1555 by %user on %dd %month %year … … 1422 1564 titleBlock 1 1423 1565 ) 1424 *9 1(CommentText1566 *97 (CommentText 1425 1567 uid 21,0 1426 1568 shape (Rectangle … … 1453 1595 titleBlock 1 1454 1596 ) 1455 *9 2(CommentText1597 *98 (CommentText 1456 1598 uid 24,0 1457 1599 shape (Rectangle … … 1484 1626 titleBlock 1 1485 1627 ) 1486 *9 3(CommentText1628 *99 (CommentText 1487 1629 uid 27,0 1488 1630 shape (Rectangle … … 1515 1657 titleBlock 1 1516 1658 ) 1517 * 94(CommentText1659 *100 (CommentText 1518 1660 uid 30,0 1519 1661 shape (Rectangle … … 1545 1687 titleBlock 1 1546 1688 ) 1547 * 95(CommentText1689 *101 (CommentText 1548 1690 uid 33,0 1549 1691 shape (Rectangle … … 1576 1718 titleBlock 1 1577 1719 ) 1578 * 96(CommentText1720 *102 (CommentText 1579 1721 uid 36,0 1580 1722 shape (Rectangle … … 1608 1750 titleBlock 1 1609 1751 ) 1610 * 97(CommentText1752 *103 (CommentText 1611 1753 uid 39,0 1612 1754 shape (Rectangle … … 1639 1781 titleBlock 1 1640 1782 ) 1641 * 98(CommentText1783 *104 (CommentText 1642 1784 uid 42,0 1643 1785 shape (Rectangle … … 1670 1812 titleBlock 1 1671 1813 ) 1672 * 99(CommentText1814 *105 (CommentText 1673 1815 uid 45,0 1674 1816 shape (Rectangle … … 1726 1868 color "26368,26368,26368" 1727 1869 ) 1728 packageList *10 0(PackageList1870 packageList *106 (PackageList 1729 1871 uid 48,0 1730 1872 stg "VerticalLayoutStrategy" 1731 1873 textVec [ 1732 *10 1(Text1874 *107 (Text 1733 1875 uid 49,0 1734 1876 va (VaSet … … 1739 1881 blo "0,800" 1740 1882 ) 1741 *10 2(MLText1883 *108 (MLText 1742 1884 uid 50,0 1743 1885 va (VaSet … … 1840 1982 ) 1841 1983 ) 1842 gi *10 3(GenericInterface1984 gi *109 (GenericInterface 1843 1985 ps "CenterOffsetStrategy" 1844 1986 matrix (Matrix … … 1937 2079 ) 1938 2080 ) 1939 DeclarativeBlock *1 04(SymDeclBlock2081 DeclarativeBlock *110 (SymDeclBlock 1940 2082 uid 1,0 1941 2083 stg "SymDeclLayoutStrategy" … … 1963 2105 font "Arial,8,1" 1964 2106 ) 1965 xt "42000,1 1600,44400,12600"2107 xt "42000,13200,44400,14200" 1966 2108 st "User:" 1967 blo "42000,1 2400"2109 blo "42000,14000" 1968 2110 ) 1969 2111 internalLabel (Text … … 1982 2124 font "Courier New,8,0" 1983 2125 ) 1984 xt "44000,1 2600,44000,12600"2126 xt "44000,14200,44000,14200" 1985 2127 tm "SyDeclarativeTextMgr" 1986 2128 ) … … 1995 2137 ) 1996 2138 ) 1997 lastUid 401,02139 lastUid 530,0 1998 2140 okToSyncOnLoad 1 1999 2141 OkToSyncGenericsOnLoad 1
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