Changeset 9911

Timestamp:

08/30/10 16:01:15 (14 years ago)

Author:

weitzel

Message:

FTU rate counting modified; now synthesis works

Location:

firmware/FTU

Files:

• FTU_control.vhd (modified) (2 diffs)
• FTU_top.vhd (modified) (2 diffs)
• counter/FTU_rate_counter.vhd (modified) (4 diffs)

firmware/FTU/FTU_control.vhd

@@ -147 +147 @@
             FTU_control_State <= INIT;
           elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then  -- default DACs
-            if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO) then
+            if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then
               if (ram_ada_cntr mod 2 = 0) then
                 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
@@ -322 +322 @@
   detect_new_rates: process(new_rates, new_rates_busy)
   begin
-    if (new_rates_busy = '0' and rising_edge(new_rates)) then
+    if(new_rates_busy = '1') then
+      new_rates_sig <= '0';
+    elsif rising_edge(new_rates) then
       new_rates_sig <= '1';
-    else
-      new_rates_sig <= '0';
     end if;
   end process detect_new_rates;

firmware/FTU/FTU_top.vhd

@@ -205 +205 @@
   attribute syn_black_box : boolean;
   attribute syn_black_box of FTU_dual_port_ram: component is true;
+  -- avoid "black box" warning during synthesis
+  attribute box_type : string;
+  attribute box_type of FTU_dual_port_ram: component is "black_box";
   
 begin
@@ -215 +218 @@
   enables_D <= enable_array_sig(3)(8 downto 0);
 
-  new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig; 
+  new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
   
   --differential input buffer for patch A

firmware/FTU/counter/FTU_rate_counter.vhd

@@ -75 +75 @@
   begin
 
-    if rising_edge(cntr_reset) then
-      
-      --formula to calculate counting period from prescaling value
-      if (prescaling = "00000000") then
-        counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
-      else
-        counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
-      end if;
-      
+    if cntr_reset = '1' then
+          
       clk_cntr := 0;      
       period_finished <= '1';
@@ -91 +84 @@
       
     elsif rising_edge(clk_1M_sig) then
+      
       if (clk_cntr < counting_period - 1) then
         clk_cntr := clk_cntr + 1;
@@ -107 +101 @@
   process(trigger, period_finished)
   begin
-    if rising_edge(period_finished) then
+    if period_finished = '1' then
       trigger_counts <= 0;
       overflow_sig <= '0';
@@ -118 +112 @@
           overflow_sig <= '1';
         end if;
+      end if;
+    end if;
+  end process;
+
+  process(cntr_reset, prescaling)
+  begin
+    if rising_edge(cntr_reset) then
+      --formula to calculate counting period from prescaling value
+      if (prescaling = "00000000") then
+        counting_period <= COUNTER_FREQUENCY / (2 * CNTR_FREQ_DIVIDER);
+      else
+        counting_period <= ((conv_integer(unsigned(prescaling)) + 1) / 2) * (COUNTER_FREQUENCY / CNTR_FREQ_DIVIDER);
       end if;
     end if;