Changeset 10009
- Timestamp:
- 10/18/10 12:37:44 (14 years ago)
- Location:
- firmware/FTU
- Files:
-
- 2 added
- 7 edited
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FTU_control.vhd (modified) (10 diffs)
-
FTU_top.vhd (modified) (16 diffs)
-
FTU_top_tb.vhd (modified) (5 diffs)
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dna (added)
-
dna/FTU_dna_gen.vhd (added)
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ftu_board.ucf (modified) (1 diff)
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ftu_definitions.vhd (modified) (1 diff)
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rs485/FTU_rs485_control.vhd (modified) (17 diffs)
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rs485/FTU_rs485_interpreter.vhd (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTU/FTU_control.vhd
r9939 r10009 51 51 read_enables : IN std_logic; -- from RS485 module 52 52 read_prescaling : IN std_logic; -- from RS485 module 53 ping_pong : IN std_logic; -- from RS485 module 53 54 dac_array_rs485_out : IN dac_array_type; -- from RS485 module 54 55 enable_array_rs485_out : IN enable_array_type; -- from RS485 module 55 56 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module 57 dna_ready : IN std_logic; -- from FTU_dna_gen 56 58 reset : OUT std_logic; 57 59 config_start : OUT std_logic; … … 70 72 enables_ready : OUT std_logic := '0'; -- to RS485 module 71 73 prescaling_ready : OUT std_logic := '0'; -- to RS485 module 74 ping_pong_ready : OUT std_logic := '0'; -- to RS485 module 72 75 dac_array : OUT dac_array_type; 73 76 enable_array : OUT enable_array_type; 74 77 cntr_reset : OUT STD_LOGIC; 75 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 78 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0); 79 dna_start : OUT std_logic := '0' -- to FTU_dna_gen 76 80 ); 77 81 end FTU_control; … … 113 117 114 118 signal new_rates_sig : STD_LOGIC := '0'; 115 signal new_rates_busy : STD_LOGIC := ' 0';119 signal new_rates_busy : STD_LOGIC := '1'; -- veto the writing of new rates until in RUNNING 116 120 117 121 signal new_DACs_in_RAM : STD_LOGIC := '0'; … … 119 123 signal new_prescaling_in_RAM : STD_LOGIC := '0'; 120 124 121 type FTU_control_StateType is (IDLE, INIT , RUNNING,122 CONFIG_ENABLE, CONFIG_DAC, CONFIG_ COUNTER,125 type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING, 126 CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER, 123 127 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING, 124 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING); 128 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING, 129 DO_PING_PONG); 125 130 signal FTU_control_State : FTU_control_StateType; 126 131 … … 140 145 141 146 when IDLE => -- wait for DCMs to lock 142 config_start_sig <= '0';143 ram_ena_sig <= '0';144 ram_wea_sig <= "0";145 147 if (clk_ready = '1') then 146 FTU_control_State <= INIT ;148 FTU_control_State <= INIT_DNA; 147 149 else 148 150 FTU_control_State <= IDLE; 149 151 end if; 150 151 when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info 152 new_rates_busy <= '1'; 153 config_start_sig <= '0'; 152 153 when INIT_DNA => -- determine FPGA DNA 154 if (dna_ready = '1') then 155 FTU_control_State <= INIT_RAM; 156 dna_start <= '0'; 157 else 158 dna_start <= '1'; 159 FTU_control_State <= INIT_DNA; 160 end if; 161 162 when INIT_RAM => -- load default config data to RAM, see also ftu_definitions.vhd for more info 154 163 ram_ena_sig <= '1'; 155 164 ram_wea_sig <= "1"; … … 162 171 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8); 163 172 end if; 164 FTU_control_State <= INIT ;173 FTU_control_State <= INIT_RAM; 165 174 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values 166 175 ram_dia_sig <= (others => '0'); 167 FTU_control_State <= INIT ;176 FTU_control_State <= INIT_RAM; 168 177 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs 169 178 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then … … 180 189 end if; 181 190 end if; 182 FTU_control_State <= INIT ;191 FTU_control_State <= INIT_RAM; 183 192 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling 184 193 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8); 185 FTU_control_State <= INIT ;194 FTU_control_State <= INIT_RAM; 186 195 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register 187 196 ram_dia_sig <= (others => '0'); 188 FTU_control_State <= INIT ;197 FTU_control_State <= INIT_RAM; 189 198 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum 190 199 ram_dia_sig <= (others => '0'); 191 FTU_control_State <= INIT ;200 FTU_control_State <= INIT_RAM; 192 201 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell 193 202 ram_dia_sig <= (others => '0'); 194 FTU_control_State <= INIT ;203 FTU_control_State <= INIT_RAM; 195 204 else 196 205 ram_dia_sig <= (others => '0'); … … 252 261 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A); 253 262 FTU_control_State <= READOUT_PRESCALING; 263 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and 264 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '0' and 265 ping_pong = '1') then 266 FTU_control_State <= DO_PING_PONG; 254 267 else 255 268 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running … … 302 315 when CONFIG_DAC => 303 316 new_rates_busy <= '1'; 304 if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then 305 ram_dac_cntr <= ram_dac_cntr + 1; 306 if (ram_dac_cntr = 0) then 307 FTU_control_State <= CONFIG_DAC; 308 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 309 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 310 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 311 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 312 FTU_control_State <= CONFIG_DAC; 313 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then 314 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); 315 ram_adb_sig <= (others => '0'); 316 FTU_control_State <= CONFIG_DAC; 317 DACs_ready <= '1'; 318 else 319 ram_adb_sig <= (others => '0'); 320 config_start_sig <= '1'; 321 DACs_ready <= '0'; 322 FTU_control_State <= CONFIG_DAC; 323 end if; 324 else 325 if (config_ready = '1') then 326 ram_dac_cntr <= 0; 327 new_DACs_in_RAM <= '0'; 328 cntr_reset_sig <= '1'; 329 new_rates_busy <= '0'; 330 FTU_control_State <= RUNNING; 331 elsif (config_ready = '0' and config_started = '1') then 332 ram_enb_sig <= '0'; 333 config_start_sig <= '0'; 334 FTU_control_State <= CONFIG_DAC; 335 else 336 FTU_control_State <= CONFIG_DAC; 337 end if; 338 end if; 339 317 ram_dac_cntr <= ram_dac_cntr + 1; 318 if (ram_dac_cntr = 0) then 319 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 320 FTU_control_State <= CONFIG_DAC; 321 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then 322 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0))); 323 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B); 324 FTU_control_State <= CONFIG_DAC; 325 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then 326 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0))); 327 ram_adb_sig <= (others => '0'); 328 FTU_control_State <= CONFIG_DAC; 329 DACs_ready <= '1'; 330 else 331 ram_adb_sig <= (others => '0'); 332 ram_enb_sig <= '0'; 333 config_start_sig <= '1'; 334 ram_dac_cntr <= 0; 335 DACs_ready <= '0'; 336 FTU_control_State <= CONFIG_DAC_WAIT; 337 end if; 338 339 when CONFIG_DAC_WAIT => 340 if (config_ready = '1') then 341 new_DACs_in_RAM <= '0'; 342 cntr_reset_sig <= '1'; 343 new_rates_busy <= '0'; 344 config_start_sig <= '0'; 345 FTU_control_State <= RUNNING; 346 elsif (config_ready = '0' and config_started = '1') then 347 new_rates_busy <= '1'; 348 config_start_sig <= '0'; 349 FTU_control_State <= CONFIG_DAC_WAIT; 350 else 351 new_rates_busy <= '1'; 352 config_start_sig <= '1'; 353 FTU_control_State <= CONFIG_DAC_WAIT; 354 end if; 355 340 356 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A 341 357 new_rates_busy <= '1'; … … 535 551 FTU_control_State <= RUNNING; 536 552 end if; 537 553 554 when DO_PING_PONG => -- just answer to FTM 555 wait_cntr <= wait_cntr + 1; 556 if (wait_cntr = 0) then 557 ping_pong_ready <= '1'; 558 FTU_control_State <= DO_PING_PONG; 559 else 560 ping_pong_ready <= '0'; 561 wait_cntr <= 0; 562 FTU_control_State <= RUNNING; 563 end if; 564 538 565 end case; 539 566 end if; -
firmware/FTU/FTU_top.vhd
r9939 r10009 39 39 ext_clk : IN STD_LOGIC; -- external clock from FTU board 40 40 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address 41 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID41 --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID 42 42 43 43 -- rate counters LVDS inputs … … 73 73 74 74 -- testpoints 75 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints 75 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints 76 76 ); 77 77 end FTU_top; … … 131 131 signal read_enables_sig : std_logic; 132 132 signal read_prescaling_sig : std_logic; 133 signal ping_pong_sig : std_logic; 133 134 signal dac_array_rs485_out_sig : dac_array_type; 134 135 signal enable_array_rs485_out_sig : enable_array_type; … … 136 137 137 138 --signals to RS485 module, all initialized in FTU_control 138 signal rates_ready_sig : std_logic; 139 signal DACs_ready_sig : std_logic; 140 signal enables_ready_sig : std_logic; 141 signal prescaling_ready_sig : std_logic; 139 signal rates_ready_sig : std_logic; 140 signal DACs_ready_sig : std_logic; 141 signal enables_ready_sig : std_logic; 142 signal prescaling_ready_sig : std_logic; 143 signal ping_pong_ready_sig : std_logic; 142 144 signal rate_array_rs485_sig : rate_array_type; 143 145 signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0); 146 147 --signals for FPGA DNA identifier 148 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTU_dna_gen 149 signal dna_start_sig : STD_LOGIC; -- initialized in FTU_control 150 signal dna_ready_sig : STD_LOGIC; -- initialized in FTU_dna_gen 144 151 145 152 component FTU_clk_gen … … 182 189 read_enables : IN std_logic; 183 190 read_prescaling : IN std_logic; 191 ping_pong : IN std_logic; 184 192 dac_array_rs485_out : IN dac_array_type; 185 193 enable_array_rs485_out : IN enable_array_type; 186 194 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); 195 dna_ready : IN std_logic; 187 196 reset : OUT std_logic; 188 197 config_start : OUT std_logic; … … 200 209 DACs_ready : OUT std_logic; 201 210 enables_ready : OUT std_logic; 202 prescaling_ready : OUT std_logic; 211 prescaling_ready : OUT std_logic; 212 ping_pong_ready : OUT std_logic; 203 213 dac_array : OUT dac_array_type; 204 214 enable_array : OUT enable_array_type; 205 215 cntr_reset : OUT STD_LOGIC; 206 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0) 216 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0); 217 dna_start : OUT std_logic 207 218 ); 208 219 end component; … … 229 240 DACs_ready : IN std_logic; 230 241 enables_ready : IN std_logic; 231 prescaling_ready : IN std_logic; 242 prescaling_ready : IN std_logic; 243 ping_pong_ready : IN std_logic; 232 244 rate_array_rs485 : IN rate_array_type; 233 245 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); … … 235 247 enable_array_rs485_in : IN enable_array_type; 236 248 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); 249 dna : IN STD_LOGIC_VECTOR(63 downto 0); 237 250 rx_en : OUT std_logic; 238 251 tx_d : OUT std_logic; … … 245 258 read_enables : OUT std_logic; 246 259 read_prescaling : OUT std_logic; 260 ping_pong : OUT std_logic; 247 261 dac_array_rs485_out : OUT dac_array_type; 248 262 enable_array_rs485_out : OUT enable_array_type; … … 250 264 ); 251 265 end component; 252 266 267 component FTU_dna_gen 268 port( 269 clk : IN STD_LOGIC; 270 start : IN STD_LOGIC; 271 dna : OUT STD_LOGIC_VECTOR(63 downto 0); 272 ready : OUT STD_LOGIC 273 ); 274 end component; 275 253 276 component FTU_dual_port_ram 254 277 port( … … 413 436 read_enables => read_enables_sig, 414 437 read_prescaling => read_prescaling_sig, 438 ping_pong => ping_pong_sig, 415 439 dac_array_rs485_out => dac_array_rs485_out_sig, 416 440 enable_array_rs485_out => enable_array_rs485_out_sig, 417 prescaling_rs485_out => prescaling_rs485_out_sig, 441 prescaling_rs485_out => prescaling_rs485_out_sig, 442 dna_ready => dna_ready_sig, 418 443 reset => reset_sig, 419 444 config_start => config_start_sig, … … 432 457 enables_ready => enables_ready_sig, 433 458 prescaling_ready => prescaling_ready_sig, 459 ping_pong_ready => ping_pong_ready_sig, 434 460 dac_array => dac_array_sig, 435 461 enable_array => enable_array_sig, 436 462 cntr_reset => cntr_reset_sig, 437 prescaling => prescaling_sig 463 prescaling => prescaling_sig, 464 dna_start => dna_start_sig 438 465 ); 439 466 … … 459 486 enables_ready => enables_ready_sig, 460 487 prescaling_ready => prescaling_ready_sig, 488 ping_pong_ready => ping_pong_ready_sig, 461 489 rate_array_rs485 => rate_array_rs485_sig, 462 490 overflow_array_rs485_in => overflow_array_rs485_in_sig, … … 464 492 enable_array_rs485_in => enable_array_sig, 465 493 prescaling_rs485_in => prescaling_sig, 494 dna => dna_sig, 466 495 rx_en => rx_en, 467 496 tx_d => tx, … … 474 503 read_enables => read_enables_sig, 475 504 read_prescaling => read_prescaling_sig, 505 ping_pong => ping_pong_sig, 476 506 dac_array_rs485_out => dac_array_rs485_out_sig, 477 507 enable_array_rs485_out => enable_array_rs485_out_sig, 478 508 prescaling_rs485_out => prescaling_rs485_out_sig 509 ); 510 511 Inst_FTU_dna_gen : FTU_dna_gen 512 port map( 513 clk => clk_50M_sig, 514 start => dna_start_sig, 515 dna => dna_sig, 516 ready => dna_ready_sig 479 517 ); 480 518 … … 493 531 dinb => ram_dib_sig, 494 532 doutb => ram_dob_sig 495 ); 533 ); 496 534 497 535 end Behavioral; -
firmware/FTU/FTU_top_tb.vhd
r9939 r10009 46 46 ext_clk : IN STD_LOGIC; -- external clock from FTU board 47 47 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address 48 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID48 --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID 49 49 50 50 -- rate counters LVDS inputs … … 87 87 signal ext_clk : STD_LOGIC := '0'; 88 88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); 89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');89 --signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); 90 90 signal patch_A_p : STD_LOGIC := '0'; 91 91 signal patch_A_n : STD_LOGIC := '0'; … … 123 123 -- Clock period definitions 124 124 constant ext_clk_period : TIME := 20 ns; 125 constant baud_rate_period : TIME := 10us;125 constant baud_rate_period : TIME := 4 us; 126 126 127 127 begin … … 132 132 ext_clk => ext_clk, 133 133 brd_add => brd_add, 134 brd_id => brd_id,134 --brd_id => brd_id, 135 135 patch_A_p => patch_A_p, 136 136 patch_A_n => patch_A_n, … … 285 285 --------------------------------------------------------------------------- 286 286 assign_rs485("01000000"); --start delimiter 287 wait for 1us;287 wait for 0us; 288 288 assign_rs485("00000000"); --FTU address 289 wait for 10ns;289 wait for 0ns; 290 290 assign_rs485("11000000"); --FTM address 291 wait for 100ns;292 assign_rs485("00000 000"); --instruction293 wait for 200us;294 assign_rs485("000 10000"); --data byte 01295 wait for 100ns;291 wait for 0ns; 292 assign_rs485("00000101"); --instruction 293 wait for 0us; 294 assign_rs485("00000001"); --data byte 01 295 wait for 0ns; 296 296 assign_rs485("00000000"); --data byte 02 297 wait for 100ns;298 assign_rs485(" 10111100"); --data byte 03299 wait for 100ns;300 assign_rs485("0000000 1"); --data byte 04301 wait for 100ns;302 assign_rs485("00000 000"); --data byte 05303 wait for 100ns;297 wait for 0ns; 298 assign_rs485("00000010"); --data byte 03 299 wait for 0ns; 300 assign_rs485("00000000"); --data byte 04 301 wait for 0ns; 302 assign_rs485("00000100"); --data byte 05 303 wait for 0ns; 304 304 assign_rs485("00000000"); --data byte 06 305 wait for 100ns;306 assign_rs485("0000 0000"); --data byte 07307 wait for 100ns;305 wait for 0ns; 306 assign_rs485("00001000"); --data byte 07 307 wait for 0ns; 308 308 assign_rs485("00000000"); --data byte 08 309 wait for 100ns;310 assign_rs485("000 00000"); --data byte 09311 wait for 100ns;309 wait for 0ns; 310 assign_rs485("00010000"); --data byte 09 311 wait for 0ns; 312 312 assign_rs485("00000000"); --data byte 10 313 wait for 100ns;313 wait for 0ns; 314 314 assign_rs485("00000000"); --data byte 11 315 wait for 100ns;315 wait for 0ns; 316 316 assign_rs485("00000000"); --check sum 317 wait for 100ns; 318 --------------------------------------------------------------------------- 319 -- keep rx line high 320 --------------------------------------------------------------------------- 321 rx <= '1'; 317 --------------------------------------------------------------------------- 318 -- wait enough time and send another command 319 --------------------------------------------------------------------------- 320 wait for 1ms; 321 assign_rs485("01000000"); --start delimiter 322 wait for 0us; 323 assign_rs485("00000000"); --FTU address 324 wait for 0ns; 325 assign_rs485("11000000"); --FTM address 326 wait for 0ns; 327 assign_rs485("00000101"); --instruction 328 wait for 0us; 329 assign_rs485("00000001"); --data byte 01 330 wait for 0ns; 331 assign_rs485("00000000"); --data byte 02 332 wait for 0ns; 333 assign_rs485("00000010"); --data byte 03 334 wait for 0ns; 335 assign_rs485("00000000"); --data byte 04 336 wait for 0ns; 337 assign_rs485("00000100"); --data byte 05 338 wait for 0ns; 339 assign_rs485("00000000"); --data byte 06 340 wait for 0ns; 341 assign_rs485("00001000"); --data byte 07 342 wait for 0ns; 343 assign_rs485("00000000"); --data byte 08 344 wait for 0ns; 345 assign_rs485("00010000"); --data byte 09 346 wait for 0ns; 347 assign_rs485("00000000"); --data byte 10 348 wait for 0ns; 349 assign_rs485("00000000"); --data byte 11 350 wait for 0ns; 351 assign_rs485("00000000"); --check sum 352 --------------------------------------------------------------------------- 353 -- don't forget final wait! 354 --------------------------------------------------------------------------- 322 355 wait; 323 356 -
firmware/FTU/ftu_board.ucf
r9843 r10009 26 26 # local board-ID "solder programmable" 27 27 ####################################################### 28 NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P029 NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P130 NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P231 NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P332 NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P433 NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P534 NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P635 NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P728 #NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0 29 #NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1 30 #NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2 31 #NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3 32 #NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4 33 #NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5 34 #NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6 35 #NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7 36 36 37 37 -
firmware/FTU/ftu_definitions.vhd
r9939 r10009 74 74 75 75 --communication with FTM 76 constant RS485_BAUD_RATE : integer := 100000; -- bits / sec in our case76 constant RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case 77 77 constant RS485_BLOCK_WIDTH : integer := 128; -- 16 byte protocol 78 78 constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter 79 79 constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192 80 81 --DNA identifier for simulation 82 constant DNA_FOR_SIM : bit_vector := X"01710000E0000500"; 80 83 81 84 end ftu_constants; -
firmware/FTU/rs485/FTU_rs485_control.vhd
r9939 r10009 42 42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending 43 43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending 44 ping_pong_ready : IN std_logic; -- ping pong successful 44 45 rate_array_rs485 : IN rate_array_type; 45 46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); … … 47 48 enable_array_rs485_in : IN enable_array_type; 48 49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); 50 dna : IN STD_LOGIC_VECTOR(63 downto 0); 49 51 rx_en : OUT std_logic; 50 52 tx_d : OUT std_logic; … … 57 59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern 58 60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value 61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM 59 62 dac_array_rs485_out : OUT dac_array_type; 60 63 enable_array_rs485_out : OUT enable_array_type; … … 83 86 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter 84 87 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter 88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter 85 89 86 90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames … … 110 114 int_read_enables : OUT std_logic; 111 115 int_read_prescaling : OUT std_logic; 116 int_ping_pong : OUT std_logic; 112 117 dac_array_rs485_out : OUT dac_array_type; 113 118 enable_array_rs485_out : OUT enable_array_type; … … 136 141 type FTU_rs485_control_StateType is (RECEIVE, 137 142 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT, 138 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, 143 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT, 139 144 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT, 140 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT );145 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT); 141 146 signal FTU_rs485_control_State : FTU_rs485_control_StateType; 142 147 … … 166 171 int_read_enables => int_read_enables_sig, 167 172 int_read_prescaling => int_read_prescaling_sig, 173 int_ping_pong => int_ping_pong_sig, 168 174 dac_array_rs485_out => dac_array_rs485_out, 169 175 enable_array_rs485_out => enable_array_rs485_out, … … 205 211 read_enables <= '0'; 206 212 read_prescaling <= '0'; 213 ping_pong <= '0'; 207 214 FTU_rs485_control_State <= SET_DAC_WAIT; 208 215 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then … … 214 221 read_enables <= '0'; 215 222 read_prescaling <= '0'; 223 ping_pong <= '0'; 216 224 FTU_rs485_control_State <= SET_ENABLE_WAIT; 217 225 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then … … 223 231 read_enables <= '0'; 224 232 read_prescaling <= '0'; 233 ping_pong <= '0'; 225 234 FTU_rs485_control_State <= SET_PRESCALING_WAIT; 226 235 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 233 242 read_enables <= '0'; 234 243 read_prescaling <= '0'; 244 ping_pong <= '0'; 235 245 FTU_rs485_control_State <= READ_RATES_WAIT; 236 246 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 243 253 read_enables <= '0'; 244 254 read_prescaling <= '0'; 255 ping_pong <= '0'; 245 256 FTU_rs485_control_State <= READ_DAC_WAIT; 246 257 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 253 264 read_enables <= '1'; 254 265 read_prescaling <= '0'; 266 ping_pong <= '0'; 255 267 FTU_rs485_control_State <= READ_ENABLE_WAIT; 256 268 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 263 275 read_enables <= '0'; 264 276 read_prescaling <= '1'; 277 ping_pong <= '0'; 265 278 FTU_rs485_control_State <= READ_PRESCALING_WAIT; 266 else 279 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and 280 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and 281 int_ping_pong_sig = '1') then 267 282 new_DACs <= '0'; 268 283 new_enables <= '0'; … … 272 287 read_enables <= '0'; 273 288 read_prescaling <= '0'; 289 ping_pong <= '1'; 290 FTU_rs485_control_State <= PING_PONG_WAIT; 291 else 292 new_DACs <= '0'; 293 new_enables <= '0'; 294 new_prescaling <= '0'; 295 read_rates <= '0'; 296 read_DACs <= '0'; 297 read_enables <= '0'; 298 read_prescaling <= '0'; 299 ping_pong <= '0'; 274 300 FTU_rs485_control_State <= RECEIVE; 275 301 end if; … … 338 364 end if; 339 365 366 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM 367 if (ping_pong_ready = '1') then 368 ping_pong <= '0'; 369 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 370 else 371 ping_pong <= '1'; 372 FTU_rs485_control_State <= PING_PONG_WAIT; 373 end if; 374 340 375 when SET_DAC_TRANSMIT => 341 376 if tx_busy_sig = '0' then … … 869 904 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 870 905 end if; 906 907 when PING_PONG_TRANSMIT => 908 if tx_busy_sig = '0' then 909 if txcnt = 0 then -- start delimiter 910 txcnt <= txcnt + 1; 911 tx_data_sig <= RS485_START_DELIM; 912 tx_start_sig <= '1'; 913 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 914 elsif txcnt = 1 then -- FTM address 915 txcnt <= txcnt + 1; 916 tx_data_sig <= FTM_ADDRESS; 917 tx_start_sig <= '1'; 918 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 919 elsif txcnt = 2 then -- board address 920 txcnt <= txcnt + 1; 921 tx_data_sig <= "00" & brd_add; 922 tx_start_sig <= '1'; 923 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 924 elsif txcnt = 3 then -- mirrored command 925 txcnt <= txcnt + 1; 926 tx_data_sig <= "00000101"; 927 tx_start_sig <= '1'; 928 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 929 elsif txcnt = 4 then -- data: device DNA 930 txcnt <= txcnt + 1; 931 tx_data_sig <= dna(7 downto 0); 932 tx_start_sig <= '1'; 933 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 934 elsif txcnt = 5 then -- data: device DNA 935 txcnt <= txcnt + 1; 936 tx_data_sig <= dna(15 downto 8); 937 tx_start_sig <= '1'; 938 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 939 elsif txcnt = 6 then -- data: device DNA 940 txcnt <= txcnt + 1; 941 tx_data_sig <= dna(23 downto 16); 942 tx_start_sig <= '1'; 943 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 944 elsif txcnt = 7 then -- data: device DNA 945 txcnt <= txcnt + 1; 946 tx_data_sig <= dna(31 downto 24); 947 tx_start_sig <= '1'; 948 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 949 elsif txcnt = 8 then -- data: device DNA 950 txcnt <= txcnt + 1; 951 tx_data_sig <= dna(39 downto 32); 952 tx_start_sig <= '1'; 953 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 954 elsif txcnt = 9 then -- data: device DNA 955 txcnt <= txcnt + 1; 956 tx_data_sig <= dna(47 downto 40); 957 tx_start_sig <= '1'; 958 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 959 elsif txcnt = 10 then -- data: device DNA 960 txcnt <= txcnt + 1; 961 tx_data_sig <= dna(55 downto 48); 962 tx_start_sig <= '1'; 963 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 964 elsif txcnt = 11 then -- data: device DNA 965 txcnt <= txcnt + 1; 966 tx_data_sig <= dna(63 downto 56); 967 tx_start_sig <= '1'; 968 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 969 elsif txcnt < 15 then -- data: not used 970 txcnt <= txcnt + 1; 971 tx_data_sig <= "00000000"; 972 tx_start_sig <= '1'; 973 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 974 elsif txcnt = 15 then -- check sum 975 txcnt <= txcnt + 1; 976 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 977 tx_start_sig <= '1'; 978 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 979 else -- transmission finished 980 txcnt <= 0; 981 FTU_rs485_control_State <= RECEIVE; 982 end if; 983 else 984 tx_start_sig <= '0'; 985 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 986 end if; 871 987 872 988 end case; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r9939 r10009 46 46 int_read_enables : OUT std_logic := '0'; 47 47 int_read_prescaling : OUT std_logic := '0'; 48 int_ping_pong : OUT std_logic := '0'; 48 49 dac_array_rs485_out : OUT dac_array_type; 49 50 enable_array_rs485_out : OUT enable_array_type; … … 79 80 int_read_enables <= '0'; 80 81 int_read_prescaling <= '0'; 82 int_ping_pong <= '0'; 81 83 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal 82 84 FTU_rs485_interpreter_State <= CHECK_HEADER; … … 93 95 int_read_enables <= '0'; 94 96 int_read_prescaling <= '0'; 97 int_ping_pong <= '0'; 95 98 if (data_block(7 downto 0) = RS485_START_DELIM) and 96 99 (data_block(15 downto 8) = ("00" & brd_add)) and … … 102 105 103 106 when DECODE => -- decode instruction 104 if(data_block(31 downto 24) = "00000000") then 107 if(data_block(31 downto 24) = "00000000") then -- set DACs 105 108 int_new_DACs <= '1'; 106 109 int_new_enables <= '0'; … … 110 113 int_read_enables <= '0'; 111 114 int_read_prescaling <= '0'; 115 int_ping_pong <= '0'; 112 116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))), 113 117 conv_integer(unsigned(data_block(59 downto 48))), … … 120 124 ); 121 125 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 122 elsif (data_block(31 downto 24) = "00000001") then 126 elsif (data_block(31 downto 24) = "00000001") then -- read DACs 123 127 int_new_DACs <= '0'; 124 128 int_new_enables <= '0'; … … 128 132 int_read_enables <= '0'; 129 133 int_read_prescaling <= '0'; 130 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 131 elsif (data_block(31 downto 24) = "00000010") then 134 int_ping_pong <= '0'; 135 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 136 elsif (data_block(31 downto 24) = "00000010") then -- read rates 132 137 int_new_DACs <= '0'; 133 138 int_new_enables <= '0'; … … 137 142 int_read_enables <= '0'; 138 143 int_read_prescaling <= '0'; 139 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 140 elsif (data_block(31 downto 24) = "00000011") then 144 int_ping_pong <= '0'; 145 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 146 elsif (data_block(31 downto 24) = "00000011") then -- set enables 141 147 int_new_DACs <= '0'; 142 148 int_new_enables <= '1'; … … 146 152 int_read_enables <= '0'; 147 153 int_read_prescaling <= '0'; 154 int_ping_pong <= '0'; 148 155 enable_array_rs485_out_sig <= (data_block(47 downto 32), 149 156 data_block(63 downto 48), … … 152 159 ); 153 160 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 154 elsif (data_block(31 downto 24) = "00000100") then 161 elsif (data_block(31 downto 24) = "00000100") then -- read enables 155 162 int_new_DACs <= '0'; 156 163 int_new_enables <= '0'; … … 160 167 int_read_enables <= '1'; 161 168 int_read_prescaling <= '0'; 162 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 163 elsif (data_block(31 downto 24) = "00000110") then 169 int_ping_pong <= '0'; 170 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 171 elsif (data_block(31 downto 24) = "00000110") then -- set counter mode 164 172 int_new_DACs <= '0'; 165 173 int_new_enables <= '0'; … … 169 177 int_read_enables <= '0'; 170 178 int_read_prescaling <= '0'; 179 int_ping_pong <= '0'; 171 180 prescaling_rs485_out_sig <= data_block(39 downto 32); 172 181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 173 elsif (data_block(31 downto 24) = "00000111") then 182 elsif (data_block(31 downto 24) = "00000111") then -- read counter mode 174 183 int_new_DACs <= '0'; 175 184 int_new_enables <= '0'; … … 179 188 int_read_enables <= '0'; 180 189 int_read_prescaling <= '1'; 190 int_ping_pong <= '0'; 191 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 192 elsif (data_block(31 downto 24) = "00000101") then -- ping pong 193 int_new_DACs <= '0'; 194 int_new_enables <= '0'; 195 int_new_prescaling <= '0'; 196 int_read_rates <= '0'; 197 int_read_DACs <= '0'; 198 int_read_enables <= '0'; 199 int_read_prescaling <= '0'; 200 int_ping_pong <= '1'; 181 201 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 202 else … … 188 208 int_read_enables <= '0'; 189 209 int_read_prescaling <= '0'; 210 int_ping_pong <= '0'; 190 211 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 191 212 end if;
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