Changeset 10037 for firmware/FTU/rs485
- Timestamp:
- 10/25/10 15:29:13 (14 years ago)
- Location:
- firmware/FTU/rs485
- Files:
-
- 3 edited
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FTU_rs485_control.vhd (modified) (12 diffs)
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FTU_rs485_interface.vhd (modified) (2 diffs)
-
FTU_rs485_interpreter.vhd (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FTU/rs485/FTU_rs485_control.vhd
r10009 r10037 74 74 signal rx_valid_sig : std_logic; -- initialized in FTU_rs485_interface 75 75 signal rx_data_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTU_rs485_interface 76 signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface76 --signal rx_busy_sig : std_logic; -- initialized in FTU_rs485_interface 77 77 78 78 signal block_valid_sig : std_logic; -- initialized in FTU_rs485_receiver … … 88 88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter 89 89 90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 161-byte frames90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 28 1-byte frames 91 91 92 92 component FTU_rs485_receiver … … 131 131 -- FPGA 132 132 rx_data : OUT std_logic_vector (7 DOWNTO 0); 133 rx_busy : OUT std_logic := '0';133 --rx_busy : OUT std_logic := '0'; 134 134 rx_valid : OUT std_logic := '0'; 135 135 tx_data : IN std_logic_vector (7 DOWNTO 0); … … 187 187 -- FPGA 188 188 rx_data => rx_data_sig, 189 rx_busy => rx_busy_sig,189 --rx_busy => rx_busy_sig, 190 190 rx_valid => rx_valid_sig, 191 191 tx_data => tx_data_sig, … … 390 390 tx_start_sig <= '1'; 391 391 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 392 elsif txcnt = 3 then -- mirrored command 392 elsif txcnt = 3 then -- firmware ID 393 txcnt <= txcnt + 1; 394 tx_data_sig <= FIRMWARE_ID; 395 tx_start_sig <= '1'; 396 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 397 elsif txcnt = 4 then -- mirrored command 393 398 txcnt <= txcnt + 1; 394 399 tx_data_sig <= "00000000"; 395 400 tx_start_sig <= '1'; 396 401 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 397 elsif txcnt = 4then -- data: DAC A low402 elsif txcnt = 5 then -- data: DAC A low 398 403 txcnt <= txcnt + 1; 399 404 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); 400 405 tx_start_sig <= '1'; 401 406 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 402 elsif txcnt = 5then -- data: DAC A high407 elsif txcnt = 6 then -- data: DAC A high 403 408 txcnt <= txcnt + 1; 404 409 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); 405 410 tx_start_sig <= '1'; 406 411 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 407 elsif txcnt = 6then -- data: DAC B low412 elsif txcnt = 7 then -- data: DAC B low 408 413 txcnt <= txcnt + 1; 409 414 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); 410 415 tx_start_sig <= '1'; 411 416 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 412 elsif txcnt = 7then -- data: DAC B high417 elsif txcnt = 8 then -- data: DAC B high 413 418 txcnt <= txcnt + 1; 414 419 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); 415 420 tx_start_sig <= '1'; 416 421 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 417 elsif txcnt = 8then -- data: DAC C low422 elsif txcnt = 9 then -- data: DAC C low 418 423 txcnt <= txcnt + 1; 419 424 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); 420 425 tx_start_sig <= '1'; 421 426 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 422 elsif txcnt = 9then -- data: DAC C high427 elsif txcnt = 10 then -- data: DAC C high 423 428 txcnt <= txcnt + 1; 424 429 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); 425 430 tx_start_sig <= '1'; 426 431 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 427 elsif txcnt = 1 0then -- data: DAC D low432 elsif txcnt = 11 then -- data: DAC D low 428 433 txcnt <= txcnt + 1; 429 434 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); 430 435 tx_start_sig <= '1'; 431 436 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 432 elsif txcnt = 1 1then -- data: DAC D high437 elsif txcnt = 12 then -- data: DAC D high 433 438 txcnt <= txcnt + 1; 434 439 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); 435 440 tx_start_sig <= '1'; 436 441 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 437 elsif txcnt = 1 2then -- data: DAC E low442 elsif txcnt = 13 then -- data: DAC E low 438 443 txcnt <= txcnt + 1; 439 444 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); 440 445 tx_start_sig <= '1'; 441 446 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 442 elsif txcnt = 1 3then -- data: DAC E high447 elsif txcnt = 14 then -- data: DAC E high 443 448 txcnt <= txcnt + 1; 444 449 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); 445 450 tx_start_sig <= '1'; 446 451 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 447 elsif txcnt < 15then -- data: not used452 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 448 453 txcnt <= txcnt + 1; 449 454 tx_data_sig <= "00000000"; 450 455 tx_start_sig <= '1'; 451 456 FTU_rs485_control_State <= SET_DAC_TRANSMIT; 452 elsif txcnt = 15 then -- check sum 457 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 458 txcnt <= txcnt + 1; 459 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 460 tx_start_sig <= '1'; 461 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 462 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 453 463 txcnt <= txcnt + 1; 454 464 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 481 491 tx_start_sig <= '1'; 482 492 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 483 elsif txcnt = 3 then -- mirrored command 493 elsif txcnt = 3 then -- firmware ID 494 txcnt <= txcnt + 1; 495 tx_data_sig <= FIRMWARE_ID; 496 tx_start_sig <= '1'; 497 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 498 elsif txcnt = 4 then -- mirrored command 484 499 txcnt <= txcnt + 1; 485 500 tx_data_sig <= "00000011"; 486 501 tx_start_sig <= '1'; 487 502 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 488 elsif txcnt = 4then -- data: enable pattern A7-0503 elsif txcnt = 5 then -- data: enable pattern A7-0 489 504 txcnt <= txcnt + 1; 490 505 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); 491 506 tx_start_sig <= '1'; 492 507 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 493 elsif txcnt = 5then -- data: enable pattern A8508 elsif txcnt = 6 then -- data: enable pattern A8 494 509 txcnt <= txcnt + 1; 495 510 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); 496 511 tx_start_sig <= '1'; 497 512 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 498 elsif txcnt = 6then -- data: enable pattern B7-0513 elsif txcnt = 7 then -- data: enable pattern B7-0 499 514 txcnt <= txcnt + 1; 500 515 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); 501 516 tx_start_sig <= '1'; 502 517 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 503 elsif txcnt = 7then -- data: enable pattern B8518 elsif txcnt = 8 then -- data: enable pattern B8 504 519 txcnt <= txcnt + 1; 505 520 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); 506 521 tx_start_sig <= '1'; 507 522 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 508 elsif txcnt = 8then -- data: enable pattern C7-0523 elsif txcnt = 9 then -- data: enable pattern C7-0 509 524 txcnt <= txcnt + 1; 510 525 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); 511 526 tx_start_sig <= '1'; 512 527 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 513 elsif txcnt = 9then -- data: enable pattern C8528 elsif txcnt = 10 then -- data: enable pattern C8 514 529 txcnt <= txcnt + 1; 515 530 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); 516 531 tx_start_sig <= '1'; 517 532 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 518 elsif txcnt = 1 0then -- data: enable pattern D7-0533 elsif txcnt = 11 then -- data: enable pattern D7-0 519 534 txcnt <= txcnt + 1; 520 535 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); 521 536 tx_start_sig <= '1'; 522 537 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 523 elsif txcnt = 1 1then -- data: enable pattern D8538 elsif txcnt = 12 then -- data: enable pattern D8 524 539 txcnt <= txcnt + 1; 525 540 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); 526 541 tx_start_sig <= '1'; 527 542 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 528 elsif txcnt < 15then -- data: not used543 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 529 544 txcnt <= txcnt + 1; 530 545 tx_data_sig <= "00000000"; 531 546 tx_start_sig <= '1'; 532 547 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 533 elsif txcnt = 15 then -- check sum 548 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 549 txcnt <= txcnt + 1; 550 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 551 tx_start_sig <= '1'; 552 FTU_rs485_control_State <= SET_ENABLE_TRANSMIT; 553 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 534 554 txcnt <= txcnt + 1; 535 555 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 562 582 tx_start_sig <= '1'; 563 583 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 564 elsif txcnt = 3 then -- mirrored command 584 elsif txcnt = 3 then -- firmware ID 585 txcnt <= txcnt + 1; 586 tx_data_sig <= FIRMWARE_ID; 587 tx_start_sig <= '1'; 588 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 589 elsif txcnt = 4 then -- mirrored command 565 590 txcnt <= txcnt + 1; 566 591 tx_data_sig <= "00000110"; 567 592 tx_start_sig <= '1'; 568 593 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 569 elsif txcnt = 4then -- data: prescaling594 elsif txcnt = 5 then -- data: prescaling 570 595 txcnt <= txcnt + 1; 571 596 tx_data_sig <= prescaling_rs485_in; 572 597 tx_start_sig <= '1'; 573 598 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 574 elsif txcnt < 15then -- data: not used599 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 575 600 txcnt <= txcnt + 1; 576 601 tx_data_sig <= "00000000"; 577 602 tx_start_sig <= '1'; 578 603 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 579 elsif txcnt = 15 then -- check sum 604 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 605 txcnt <= txcnt + 1; 606 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 607 tx_start_sig <= '1'; 608 FTU_rs485_control_State <= SET_PRESCALING_TRANSMIT; 609 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 580 610 txcnt <= txcnt + 1; 581 611 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 608 638 tx_start_sig <= '1'; 609 639 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 610 elsif txcnt = 3 then -- mirrored command 640 elsif txcnt = 3 then -- firmware ID 641 txcnt <= txcnt + 1; 642 tx_data_sig <= FIRMWARE_ID; 643 tx_start_sig <= '1'; 644 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 645 elsif txcnt = 4 then -- mirrored command 611 646 txcnt <= txcnt + 1; 612 647 tx_data_sig <= "00000010"; 613 648 tx_start_sig <= '1'; 614 649 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 615 elsif txcnt = 4 then -- data: counter A low 616 txcnt <= txcnt + 1; 617 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(7 downto 0); 618 tx_start_sig <= '1'; 619 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 620 elsif txcnt = 5 then -- data: counter A high 621 txcnt <= txcnt + 1; 622 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),16)(15 downto 8); 623 tx_start_sig <= '1'; 624 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 625 elsif txcnt = 6 then -- data: counter B low 626 txcnt <= txcnt + 1; 627 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(7 downto 0); 628 tx_start_sig <= '1'; 629 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 630 elsif txcnt = 7 then -- data: counter B high 631 txcnt <= txcnt + 1; 632 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),16)(15 downto 8); 633 tx_start_sig <= '1'; 634 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 635 elsif txcnt = 8 then -- data: counter C low 636 txcnt <= txcnt + 1; 637 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(7 downto 0); 638 tx_start_sig <= '1'; 639 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 640 elsif txcnt = 9 then -- data: counter C high 641 txcnt <= txcnt + 1; 642 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),16)(15 downto 8); 643 tx_start_sig <= '1'; 644 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 645 elsif txcnt = 10 then -- data: counter D low 646 txcnt <= txcnt + 1; 647 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(7 downto 0); 648 tx_start_sig <= '1'; 649 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 650 elsif txcnt = 11 then -- data: counter D high 651 txcnt <= txcnt + 1; 652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),16)(15 downto 8); 653 tx_start_sig <= '1'; 654 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 655 elsif txcnt = 12 then -- data: trigger counter low 656 txcnt <= txcnt + 1; 657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(7 downto 0); 658 tx_start_sig <= '1'; 659 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 660 elsif txcnt = 13 then -- data: trigger counter high 661 txcnt <= txcnt + 1; 662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),16)(15 downto 8); 663 tx_start_sig <= '1'; 664 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 665 elsif txcnt = 14 then -- data: overflow register 650 elsif txcnt = 5 then -- data: counter A 7...0 651 txcnt <= txcnt + 1; 652 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(7 downto 0); 653 tx_start_sig <= '1'; 654 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 655 elsif txcnt = 6 then -- data: counter A 15...8 656 txcnt <= txcnt + 1; 657 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(15 downto 8); 658 tx_start_sig <= '1'; 659 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 660 elsif txcnt = 7 then -- data: counter A 23...16 661 txcnt <= txcnt + 1; 662 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(23 downto 16); 663 tx_start_sig <= '1'; 664 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 665 elsif txcnt = 8 then -- data: counter A 31...24 666 txcnt <= txcnt + 1; 667 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(0),32)(31 downto 24); 668 tx_start_sig <= '1'; 669 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 670 elsif txcnt = 9 then -- data: counter B 7...0 671 txcnt <= txcnt + 1; 672 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(7 downto 0); 673 tx_start_sig <= '1'; 674 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 675 elsif txcnt = 10 then -- data: counter B 15...8 676 txcnt <= txcnt + 1; 677 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(15 downto 8); 678 tx_start_sig <= '1'; 679 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 680 elsif txcnt = 11 then -- data: counter B 23...16 681 txcnt <= txcnt + 1; 682 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(23 downto 16); 683 tx_start_sig <= '1'; 684 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 685 elsif txcnt = 12 then -- data: counter B 31...24 686 txcnt <= txcnt + 1; 687 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(1),32)(31 downto 24); 688 tx_start_sig <= '1'; 689 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 690 elsif txcnt = 13 then -- data: counter C 7...0 691 txcnt <= txcnt + 1; 692 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(7 downto 0); 693 tx_start_sig <= '1'; 694 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 695 elsif txcnt = 14 then -- data: counter C 15...8 696 txcnt <= txcnt + 1; 697 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(15 downto 8); 698 tx_start_sig <= '1'; 699 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 700 elsif txcnt = 15 then -- data: counter C 23...16 701 txcnt <= txcnt + 1; 702 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(23 downto 16); 703 tx_start_sig <= '1'; 704 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 705 elsif txcnt = 16 then -- data: counter C 31...24 706 txcnt <= txcnt + 1; 707 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(2),32)(31 downto 24); 708 tx_start_sig <= '1'; 709 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 710 elsif txcnt = 17 then -- data: counter D 7...0 711 txcnt <= txcnt + 1; 712 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(7 downto 0); 713 tx_start_sig <= '1'; 714 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 715 elsif txcnt = 18 then -- data: counter D 15...8 716 txcnt <= txcnt + 1; 717 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(15 downto 8); 718 tx_start_sig <= '1'; 719 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 720 elsif txcnt = 19 then -- data: counter D 23...16 721 txcnt <= txcnt + 1; 722 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(23 downto 16); 723 tx_start_sig <= '1'; 724 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 725 elsif txcnt = 20 then -- data: counter D 31...24 726 txcnt <= txcnt + 1; 727 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(3),32)(31 downto 24); 728 tx_start_sig <= '1'; 729 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 730 elsif txcnt = 21 then -- data: trigger counter 7...0 731 txcnt <= txcnt + 1; 732 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(7 downto 0); 733 tx_start_sig <= '1'; 734 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 735 elsif txcnt = 22 then -- data: trigger counter 15...8 736 txcnt <= txcnt + 1; 737 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(15 downto 8); 738 tx_start_sig <= '1'; 739 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 740 elsif txcnt = 23 then -- data: trigger counter 23...16 741 txcnt <= txcnt + 1; 742 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(23 downto 16); 743 tx_start_sig <= '1'; 744 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 745 elsif txcnt = 24 then -- data: trigger counter 31...24 746 txcnt <= txcnt + 1; 747 tx_data_sig <= conv_std_logic_vector(rate_array_rs485(4),32)(31 downto 24); 748 tx_start_sig <= '1'; 749 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 750 elsif txcnt = 25 then -- data: overflow register 666 751 txcnt <= txcnt + 1; 667 752 tx_data_sig <= overflow_array_rs485_in; 668 753 tx_start_sig <= '1'; 669 754 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 670 elsif txcnt = 15 then -- check sum 755 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 756 txcnt <= txcnt + 1; 757 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 758 tx_start_sig <= '1'; 759 FTU_rs485_control_State <= READ_RATES_TRANSMIT; 760 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 671 761 txcnt <= txcnt + 1; 672 762 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 699 789 tx_start_sig <= '1'; 700 790 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 701 elsif txcnt = 3 then -- mirrored command 791 elsif txcnt = 3 then -- firmware ID 792 txcnt <= txcnt + 1; 793 tx_data_sig <= FIRMWARE_ID; 794 tx_start_sig <= '1'; 795 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 796 elsif txcnt = 4 then -- mirrored command 702 797 txcnt <= txcnt + 1; 703 798 tx_data_sig <= "00000001"; 704 799 tx_start_sig <= '1'; 705 800 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 706 elsif txcnt = 4then -- data: DAC A low801 elsif txcnt = 5 then -- data: DAC A low 707 802 txcnt <= txcnt + 1; 708 803 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(7 downto 0); 709 804 tx_start_sig <= '1'; 710 805 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 711 elsif txcnt = 5then -- data: DAC A high806 elsif txcnt = 6 then -- data: DAC A high 712 807 txcnt <= txcnt + 1; 713 808 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(0),16)(15 downto 8); 714 809 tx_start_sig <= '1'; 715 810 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 716 elsif txcnt = 6then -- data: DAC B low811 elsif txcnt = 7 then -- data: DAC B low 717 812 txcnt <= txcnt + 1; 718 813 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(7 downto 0); 719 814 tx_start_sig <= '1'; 720 815 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 721 elsif txcnt = 7then -- data: DAC B high816 elsif txcnt = 8 then -- data: DAC B high 722 817 txcnt <= txcnt + 1; 723 818 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(1),16)(15 downto 8); 724 819 tx_start_sig <= '1'; 725 820 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 726 elsif txcnt = 8then -- data: DAC C low821 elsif txcnt = 9 then -- data: DAC C low 727 822 txcnt <= txcnt + 1; 728 823 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(7 downto 0); 729 824 tx_start_sig <= '1'; 730 825 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 731 elsif txcnt = 9then -- data: DAC C high826 elsif txcnt = 10 then -- data: DAC C high 732 827 txcnt <= txcnt + 1; 733 828 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(2),16)(15 downto 8); 734 829 tx_start_sig <= '1'; 735 830 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 736 elsif txcnt = 1 0then -- data: DAC D low831 elsif txcnt = 11 then -- data: DAC D low 737 832 txcnt <= txcnt + 1; 738 833 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(7 downto 0); 739 834 tx_start_sig <= '1'; 740 835 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 741 elsif txcnt = 1 1then -- data: DAC D high836 elsif txcnt = 12 then -- data: DAC D high 742 837 txcnt <= txcnt + 1; 743 838 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(3),16)(15 downto 8); 744 839 tx_start_sig <= '1'; 745 840 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 746 elsif txcnt = 1 2then -- data: DAC E low841 elsif txcnt = 13 then -- data: DAC E low 747 842 txcnt <= txcnt + 1; 748 843 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(7 downto 0); 749 844 tx_start_sig <= '1'; 750 845 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 751 elsif txcnt = 1 3then -- data: DAC E high846 elsif txcnt = 14 then -- data: DAC E high 752 847 txcnt <= txcnt + 1; 753 848 tx_data_sig <= conv_std_logic_vector(dac_array_rs485_in(7),16)(15 downto 8); 754 849 tx_start_sig <= '1'; 755 850 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 756 elsif txcnt < 15then -- data: not used851 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 757 852 txcnt <= txcnt + 1; 758 853 tx_data_sig <= "00000000"; 759 854 tx_start_sig <= '1'; 760 855 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 761 elsif txcnt = 15 then -- check sum 856 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 857 txcnt <= txcnt + 1; 858 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 859 tx_start_sig <= '1'; 860 FTU_rs485_control_State <= READ_DAC_TRANSMIT; 861 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 762 862 txcnt <= txcnt + 1; 763 863 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 790 890 tx_start_sig <= '1'; 791 891 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 792 elsif txcnt = 3 then -- mirrored command 892 elsif txcnt = 3 then -- firmware ID 893 txcnt <= txcnt + 1; 894 tx_data_sig <= FIRMWARE_ID; 895 tx_start_sig <= '1'; 896 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 897 elsif txcnt = 4 then -- mirrored command 793 898 txcnt <= txcnt + 1; 794 899 tx_data_sig <= "00000100"; 795 900 tx_start_sig <= '1'; 796 901 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 797 elsif txcnt = 4then -- data: enable pattern A7-0902 elsif txcnt = 5 then -- data: enable pattern A7-0 798 903 txcnt <= txcnt + 1; 799 904 tx_data_sig <= enable_array_rs485_in(0)(7 downto 0); 800 905 tx_start_sig <= '1'; 801 906 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 802 elsif txcnt = 5then -- data: enable pattern A8907 elsif txcnt = 6 then -- data: enable pattern A8 803 908 txcnt <= txcnt + 1; 804 909 tx_data_sig <= enable_array_rs485_in(0)(15 downto 8); 805 910 tx_start_sig <= '1'; 806 911 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 807 elsif txcnt = 6then -- data: enable pattern B7-0912 elsif txcnt = 7 then -- data: enable pattern B7-0 808 913 txcnt <= txcnt + 1; 809 914 tx_data_sig <= enable_array_rs485_in(1)(7 downto 0); 810 915 tx_start_sig <= '1'; 811 916 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 812 elsif txcnt = 7then -- data: enable pattern B8917 elsif txcnt = 8 then -- data: enable pattern B8 813 918 txcnt <= txcnt + 1; 814 919 tx_data_sig <= enable_array_rs485_in(1)(15 downto 8); 815 920 tx_start_sig <= '1'; 816 921 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 817 elsif txcnt = 8then -- data: enable pattern C7-0922 elsif txcnt = 9 then -- data: enable pattern C7-0 818 923 txcnt <= txcnt + 1; 819 924 tx_data_sig <= enable_array_rs485_in(2)(7 downto 0); 820 925 tx_start_sig <= '1'; 821 926 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 822 elsif txcnt = 9then -- data: enable pattern C8927 elsif txcnt = 10 then -- data: enable pattern C8 823 928 txcnt <= txcnt + 1; 824 929 tx_data_sig <= enable_array_rs485_in(2)(15 downto 8); 825 930 tx_start_sig <= '1'; 826 931 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 827 elsif txcnt = 1 0then -- data: enable pattern D7-0932 elsif txcnt = 11 then -- data: enable pattern D7-0 828 933 txcnt <= txcnt + 1; 829 934 tx_data_sig <= enable_array_rs485_in(3)(7 downto 0); 830 935 tx_start_sig <= '1'; 831 936 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 832 elsif txcnt = 1 1then -- data: enable pattern D8937 elsif txcnt = 12 then -- data: enable pattern D8 833 938 txcnt <= txcnt + 1; 834 939 tx_data_sig <= enable_array_rs485_in(3)(15 downto 8); 835 940 tx_start_sig <= '1'; 836 941 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 837 elsif txcnt < 15then -- data: not used942 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 838 943 txcnt <= txcnt + 1; 839 944 tx_data_sig <= "00000000"; 840 945 tx_start_sig <= '1'; 841 946 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 842 elsif txcnt = 15 then -- check sum 947 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 948 txcnt <= txcnt + 1; 949 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 950 tx_start_sig <= '1'; 951 FTU_rs485_control_State <= READ_ENABLE_TRANSMIT; 952 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 843 953 txcnt <= txcnt + 1; 844 954 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 871 981 tx_start_sig <= '1'; 872 982 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 873 elsif txcnt = 3 then -- mirrored command 983 elsif txcnt = 3 then -- firmware ID 984 txcnt <= txcnt + 1; 985 tx_data_sig <= FIRMWARE_ID; 986 tx_start_sig <= '1'; 987 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 988 elsif txcnt = 4 then -- mirrored command 874 989 txcnt <= txcnt + 1; 875 990 tx_data_sig <= "00000111"; 876 991 tx_start_sig <= '1'; 877 992 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 878 elsif txcnt = 4then -- data: prescaling993 elsif txcnt = 5 then -- data: prescaling 879 994 txcnt <= txcnt + 1; 880 995 tx_data_sig <= prescaling_rs485_in; 881 996 tx_start_sig <= '1'; 882 997 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 883 elsif txcnt = 5then -- data: overflow register998 elsif txcnt = 6 then -- data: overflow register 884 999 txcnt <= txcnt + 1; 885 1000 tx_data_sig <= overflow_array_rs485_in; 886 1001 tx_start_sig <= '1'; 887 1002 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 888 elsif txcnt < 15then -- data: not used1003 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 889 1004 txcnt <= txcnt + 1; 890 1005 tx_data_sig <= "00000000"; 891 1006 tx_start_sig <= '1'; 892 1007 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 893 elsif txcnt = 15 then -- check sum 1008 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1009 txcnt <= txcnt + 1; 1010 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 1011 tx_start_sig <= '1'; 1012 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 1013 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 894 1014 txcnt <= txcnt + 1; 895 1015 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! … … 922 1042 tx_start_sig <= '1'; 923 1043 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 924 elsif txcnt = 3 then -- mirrored command 1044 elsif txcnt = 3 then -- firmware ID 1045 txcnt <= txcnt + 1; 1046 tx_data_sig <= FIRMWARE_ID; 1047 tx_start_sig <= '1'; 1048 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1049 elsif txcnt = 4 then -- mirrored command 925 1050 txcnt <= txcnt + 1; 926 1051 tx_data_sig <= "00000101"; 927 1052 tx_start_sig <= '1'; 928 1053 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 929 elsif txcnt = 4then -- data: device DNA1054 elsif txcnt = 5 then -- data: device DNA 930 1055 txcnt <= txcnt + 1; 931 1056 tx_data_sig <= dna(7 downto 0); 932 1057 tx_start_sig <= '1'; 933 1058 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 934 elsif txcnt = 5then -- data: device DNA1059 elsif txcnt = 6 then -- data: device DNA 935 1060 txcnt <= txcnt + 1; 936 1061 tx_data_sig <= dna(15 downto 8); 937 1062 tx_start_sig <= '1'; 938 1063 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 939 elsif txcnt = 6then -- data: device DNA1064 elsif txcnt = 7 then -- data: device DNA 940 1065 txcnt <= txcnt + 1; 941 1066 tx_data_sig <= dna(23 downto 16); 942 1067 tx_start_sig <= '1'; 943 1068 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 944 elsif txcnt = 7then -- data: device DNA1069 elsif txcnt = 8 then -- data: device DNA 945 1070 txcnt <= txcnt + 1; 946 1071 tx_data_sig <= dna(31 downto 24); 947 1072 tx_start_sig <= '1'; 948 1073 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 949 elsif txcnt = 8then -- data: device DNA1074 elsif txcnt = 9 then -- data: device DNA 950 1075 txcnt <= txcnt + 1; 951 1076 tx_data_sig <= dna(39 downto 32); 952 1077 tx_start_sig <= '1'; 953 1078 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 954 elsif txcnt = 9then -- data: device DNA1079 elsif txcnt = 10 then -- data: device DNA 955 1080 txcnt <= txcnt + 1; 956 1081 tx_data_sig <= dna(47 downto 40); 957 1082 tx_start_sig <= '1'; 958 1083 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 959 elsif txcnt = 1 0then -- data: device DNA1084 elsif txcnt = 11 then -- data: device DNA 960 1085 txcnt <= txcnt + 1; 961 1086 tx_data_sig <= dna(55 downto 48); 962 1087 tx_start_sig <= '1'; 963 1088 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 964 elsif txcnt = 1 1then -- data: device DNA1089 elsif txcnt = 12 then -- data: device DNA 965 1090 txcnt <= txcnt + 1; 966 1091 tx_data_sig <= dna(63 downto 56); 967 1092 tx_start_sig <= '1'; 968 1093 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 969 elsif txcnt < 15then -- data: not used1094 elsif txcnt < ((RS485_BLOCK_WIDTH / 8) - 2) then -- data: not used 970 1095 txcnt <= txcnt + 1; 971 1096 tx_data_sig <= "00000000"; 972 1097 tx_start_sig <= '1'; 973 1098 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 974 elsif txcnt = 15 then -- check sum 1099 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 2) then -- CRC error counter 1100 txcnt <= txcnt + 1; 1101 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 1102 tx_start_sig <= '1'; 1103 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 1104 elsif txcnt = ((RS485_BLOCK_WIDTH / 8) - 1) then -- check sum 975 1105 txcnt <= txcnt + 1; 976 1106 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! -
firmware/FTU/rs485/FTU_rs485_interface.vhd
r9928 r10037 34 34 -- FPGA 35 35 rx_data : OUT std_logic_vector (7 DOWNTO 0); 36 rx_busy : OUT std_logic := '0';36 --rx_busy : OUT std_logic := '0'; 37 37 rx_valid : OUT std_logic := '0'; 38 38 tx_data : IN std_logic_vector (7 DOWNTO 0); … … 122 122 rx_en <= flow_ctrl; 123 123 rx_data <= rx_sr; 124 rx_busy <= '1' when (rx_bitcnt < 11) else '0';124 --rx_busy <= '1' when (rx_bitcnt < 11) else '0'; 125 125 126 126 END ARCHITECTURE beha; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r10009 r10037 105 105 106 106 when DECODE => -- decode instruction 107 if(data_block(3 1 downto 24) = "00000000") then -- set DACs107 if(data_block(39 downto 32) = "00000000") then -- set DACs 108 108 int_new_DACs <= '1'; 109 109 int_new_enables <= '0'; … … 114 114 int_read_prescaling <= '0'; 115 115 int_ping_pong <= '0'; 116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block( 43 downto 32))),117 conv_integer(unsigned(data_block( 59 downto 48))),118 conv_integer(unsigned(data_block( 75 downto 64))),119 conv_integer(unsigned(data_block(9 1 downto 80))),116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(51 downto 40))), 117 conv_integer(unsigned(data_block(67 downto 56))), 118 conv_integer(unsigned(data_block(83 downto 72))), 119 conv_integer(unsigned(data_block(99 downto 88))), 120 120 DEFAULT_DAC(4), 121 121 DEFAULT_DAC(5), 122 122 DEFAULT_DAC(6), 123 conv_integer(unsigned(data_block(1 07 downto 96)))123 conv_integer(unsigned(data_block(115 downto 104))) 124 124 ); 125 125 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 126 elsif (data_block(3 1 downto 24) = "00000001") then -- read DACs126 elsif (data_block(39 downto 32) = "00000001") then -- read DACs 127 127 int_new_DACs <= '0'; 128 128 int_new_enables <= '0'; … … 134 134 int_ping_pong <= '0'; 135 135 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 136 elsif (data_block(3 1 downto 24) = "00000010") then -- read rates136 elsif (data_block(39 downto 32) = "00000010") then -- read rates 137 137 int_new_DACs <= '0'; 138 138 int_new_enables <= '0'; … … 144 144 int_ping_pong <= '0'; 145 145 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 146 elsif (data_block(3 1 downto 24) = "00000011") then -- set enables146 elsif (data_block(39 downto 32) = "00000011") then -- set enables 147 147 int_new_DACs <= '0'; 148 148 int_new_enables <= '1'; … … 153 153 int_read_prescaling <= '0'; 154 154 int_ping_pong <= '0'; 155 enable_array_rs485_out_sig <= (data_block( 47 downto 32),156 data_block( 63 downto 48),157 data_block( 79 downto 64),158 data_block( 95 downto 80)155 enable_array_rs485_out_sig <= (data_block(55 downto 40), 156 data_block(71 downto 56), 157 data_block(87 downto 72), 158 data_block(103 downto 88) 159 159 ); 160 160 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 161 elsif (data_block(3 1 downto 24) = "00000100") then -- read enables161 elsif (data_block(39 downto 32) = "00000100") then -- read enables 162 162 int_new_DACs <= '0'; 163 163 int_new_enables <= '0'; … … 169 169 int_ping_pong <= '0'; 170 170 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 171 elsif (data_block(3 1 downto 24) = "00000110") then -- set counter mode171 elsif (data_block(39 downto 32) = "00000110") then -- set counter mode 172 172 int_new_DACs <= '0'; 173 173 int_new_enables <= '0'; … … 178 178 int_read_prescaling <= '0'; 179 179 int_ping_pong <= '0'; 180 prescaling_rs485_out_sig <= data_block( 39 downto 32);181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 elsif (data_block(3 1 downto 24) = "00000111") then -- read counter mode180 prescaling_rs485_out_sig <= data_block(47 downto 40); 181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 elsif (data_block(39 downto 32) = "00000111") then -- read counter mode 183 183 int_new_DACs <= '0'; 184 184 int_new_enables <= '0'; … … 190 190 int_ping_pong <= '0'; 191 191 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 192 elsif (data_block(3 1 downto 24) = "00000101") then -- ping pong192 elsif (data_block(39 downto 32) = "00000101") then -- ping pong 193 193 int_new_DACs <= '0'; 194 194 int_new_enables <= '0';
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