Changeset 10009 for firmware/FTU/rs485
- Timestamp:
- 10/18/10 12:37:44 (14 years ago)
- Location:
- firmware/FTU/rs485
- Files:
-
- 2 edited
-
FTU_rs485_control.vhd (modified) (17 diffs)
-
FTU_rs485_interpreter.vhd (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTU/rs485/FTU_rs485_control.vhd
r9939 r10009 42 42 enables_ready : IN std_logic; -- enable_array_rs485_in is ok for sending 43 43 prescaling_ready : IN std_logic; -- prescaling byte is ok for sending 44 ping_pong_ready : IN std_logic; -- ping pong successful 44 45 rate_array_rs485 : IN rate_array_type; 45 46 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); … … 47 48 enable_array_rs485_in : IN enable_array_type; 48 49 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0); 50 dna : IN STD_LOGIC_VECTOR(63 downto 0); 49 51 rx_en : OUT std_logic; 50 52 tx_d : OUT std_logic; … … 57 59 read_enables : OUT std_logic := '0'; -- FTM wants to read enable pattern 58 60 read_prescaling : OUT std_logic := '0'; -- FTM wants to read prescaling value 61 ping_pong : OUT std_logic := '0'; -- ping pong command from FTM 59 62 dac_array_rs485_out : OUT dac_array_type; 60 63 enable_array_rs485_out : OUT enable_array_type; … … 83 86 signal int_read_enables_sig : std_logic; -- initialized in FTU_rs485_interpreter 84 87 signal int_read_prescaling_sig : std_logic; -- initialized in FTU_rs485_interpreter 88 signal int_ping_pong_sig : std_logic; -- initialized in FTU_rs485_interpreter 85 89 86 90 signal txcnt : integer range 0 to (RS485_BLOCK_WIDTH / 8) := 0; -- count 16 1-byte frames … … 110 114 int_read_enables : OUT std_logic; 111 115 int_read_prescaling : OUT std_logic; 116 int_ping_pong : OUT std_logic; 112 117 dac_array_rs485_out : OUT dac_array_type; 113 118 enable_array_rs485_out : OUT enable_array_type; … … 136 141 type FTU_rs485_control_StateType is (RECEIVE, 137 142 READ_RATES_WAIT, READ_DAC_WAIT, READ_ENABLE_WAIT, READ_PRESCALING_WAIT, 138 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, 143 SET_DAC_WAIT, SET_ENABLE_WAIT, SET_PRESCALING_WAIT, PING_PONG_WAIT, 139 144 READ_RATES_TRANSMIT, READ_DAC_TRANSMIT, READ_ENABLE_TRANSMIT, READ_PRESCALING_TRANSMIT, 140 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT );145 SET_DAC_TRANSMIT, SET_ENABLE_TRANSMIT, SET_PRESCALING_TRANSMIT, PING_PONG_TRANSMIT); 141 146 signal FTU_rs485_control_State : FTU_rs485_control_StateType; 142 147 … … 166 171 int_read_enables => int_read_enables_sig, 167 172 int_read_prescaling => int_read_prescaling_sig, 173 int_ping_pong => int_ping_pong_sig, 168 174 dac_array_rs485_out => dac_array_rs485_out, 169 175 enable_array_rs485_out => enable_array_rs485_out, … … 205 211 read_enables <= '0'; 206 212 read_prescaling <= '0'; 213 ping_pong <= '0'; 207 214 FTU_rs485_control_State <= SET_DAC_WAIT; 208 215 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '1') then … … 214 221 read_enables <= '0'; 215 222 read_prescaling <= '0'; 223 ping_pong <= '0'; 216 224 FTU_rs485_control_State <= SET_ENABLE_WAIT; 217 225 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '1') then … … 223 231 read_enables <= '0'; 224 232 read_prescaling <= '0'; 233 ping_pong <= '0'; 225 234 FTU_rs485_control_State <= SET_PRESCALING_WAIT; 226 235 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 233 242 read_enables <= '0'; 234 243 read_prescaling <= '0'; 244 ping_pong <= '0'; 235 245 FTU_rs485_control_State <= READ_RATES_WAIT; 236 246 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 243 253 read_enables <= '0'; 244 254 read_prescaling <= '0'; 255 ping_pong <= '0'; 245 256 FTU_rs485_control_State <= READ_DAC_WAIT; 246 257 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 253 264 read_enables <= '1'; 254 265 read_prescaling <= '0'; 266 ping_pong <= '0'; 255 267 FTU_rs485_control_State <= READ_ENABLE_WAIT; 256 268 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and … … 263 275 read_enables <= '0'; 264 276 read_prescaling <= '1'; 277 ping_pong <= '0'; 265 278 FTU_rs485_control_State <= READ_PRESCALING_WAIT; 266 else 279 elsif (int_new_DACs_sig = '0' and int_new_enables_sig = '0' and int_new_prescaling_sig = '0' and 280 int_read_rates_sig = '0' and int_read_DACs_sig = '0' and int_read_enables_sig = '0' and int_read_prescaling_sig = '0' and 281 int_ping_pong_sig = '1') then 267 282 new_DACs <= '0'; 268 283 new_enables <= '0'; … … 272 287 read_enables <= '0'; 273 288 read_prescaling <= '0'; 289 ping_pong <= '1'; 290 FTU_rs485_control_State <= PING_PONG_WAIT; 291 else 292 new_DACs <= '0'; 293 new_enables <= '0'; 294 new_prescaling <= '0'; 295 read_rates <= '0'; 296 read_DACs <= '0'; 297 read_enables <= '0'; 298 read_prescaling <= '0'; 299 ping_pong <= '0'; 274 300 FTU_rs485_control_State <= RECEIVE; 275 301 end if; … … 338 364 end if; 339 365 366 when PING_PONG_WAIT => -- wait until FTU control says "done" and then answer to FTM 367 if (ping_pong_ready = '1') then 368 ping_pong <= '0'; 369 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 370 else 371 ping_pong <= '1'; 372 FTU_rs485_control_State <= PING_PONG_WAIT; 373 end if; 374 340 375 when SET_DAC_TRANSMIT => 341 376 if tx_busy_sig = '0' then … … 869 904 FTU_rs485_control_State <= READ_PRESCALING_TRANSMIT; 870 905 end if; 906 907 when PING_PONG_TRANSMIT => 908 if tx_busy_sig = '0' then 909 if txcnt = 0 then -- start delimiter 910 txcnt <= txcnt + 1; 911 tx_data_sig <= RS485_START_DELIM; 912 tx_start_sig <= '1'; 913 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 914 elsif txcnt = 1 then -- FTM address 915 txcnt <= txcnt + 1; 916 tx_data_sig <= FTM_ADDRESS; 917 tx_start_sig <= '1'; 918 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 919 elsif txcnt = 2 then -- board address 920 txcnt <= txcnt + 1; 921 tx_data_sig <= "00" & brd_add; 922 tx_start_sig <= '1'; 923 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 924 elsif txcnt = 3 then -- mirrored command 925 txcnt <= txcnt + 1; 926 tx_data_sig <= "00000101"; 927 tx_start_sig <= '1'; 928 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 929 elsif txcnt = 4 then -- data: device DNA 930 txcnt <= txcnt + 1; 931 tx_data_sig <= dna(7 downto 0); 932 tx_start_sig <= '1'; 933 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 934 elsif txcnt = 5 then -- data: device DNA 935 txcnt <= txcnt + 1; 936 tx_data_sig <= dna(15 downto 8); 937 tx_start_sig <= '1'; 938 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 939 elsif txcnt = 6 then -- data: device DNA 940 txcnt <= txcnt + 1; 941 tx_data_sig <= dna(23 downto 16); 942 tx_start_sig <= '1'; 943 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 944 elsif txcnt = 7 then -- data: device DNA 945 txcnt <= txcnt + 1; 946 tx_data_sig <= dna(31 downto 24); 947 tx_start_sig <= '1'; 948 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 949 elsif txcnt = 8 then -- data: device DNA 950 txcnt <= txcnt + 1; 951 tx_data_sig <= dna(39 downto 32); 952 tx_start_sig <= '1'; 953 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 954 elsif txcnt = 9 then -- data: device DNA 955 txcnt <= txcnt + 1; 956 tx_data_sig <= dna(47 downto 40); 957 tx_start_sig <= '1'; 958 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 959 elsif txcnt = 10 then -- data: device DNA 960 txcnt <= txcnt + 1; 961 tx_data_sig <= dna(55 downto 48); 962 tx_start_sig <= '1'; 963 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 964 elsif txcnt = 11 then -- data: device DNA 965 txcnt <= txcnt + 1; 966 tx_data_sig <= dna(63 downto 56); 967 tx_start_sig <= '1'; 968 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 969 elsif txcnt < 15 then -- data: not used 970 txcnt <= txcnt + 1; 971 tx_data_sig <= "00000000"; 972 tx_start_sig <= '1'; 973 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 974 elsif txcnt = 15 then -- check sum 975 txcnt <= txcnt + 1; 976 tx_data_sig <= "00000000"; -- NOT YET IMPLEMENTED!!! 977 tx_start_sig <= '1'; 978 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 979 else -- transmission finished 980 txcnt <= 0; 981 FTU_rs485_control_State <= RECEIVE; 982 end if; 983 else 984 tx_start_sig <= '0'; 985 FTU_rs485_control_State <= PING_PONG_TRANSMIT; 986 end if; 871 987 872 988 end case; -
firmware/FTU/rs485/FTU_rs485_interpreter.vhd
r9939 r10009 46 46 int_read_enables : OUT std_logic := '0'; 47 47 int_read_prescaling : OUT std_logic := '0'; 48 int_ping_pong : OUT std_logic := '0'; 48 49 dac_array_rs485_out : OUT dac_array_type; 49 50 enable_array_rs485_out : OUT enable_array_type; … … 79 80 int_read_enables <= '0'; 80 81 int_read_prescaling <= '0'; 82 int_ping_pong <= '0'; 81 83 if (block_valid_sr(3 downto 2) = "01") then -- rising edge of valid signal 82 84 FTU_rs485_interpreter_State <= CHECK_HEADER; … … 93 95 int_read_enables <= '0'; 94 96 int_read_prescaling <= '0'; 97 int_ping_pong <= '0'; 95 98 if (data_block(7 downto 0) = RS485_START_DELIM) and 96 99 (data_block(15 downto 8) = ("00" & brd_add)) and … … 102 105 103 106 when DECODE => -- decode instruction 104 if(data_block(31 downto 24) = "00000000") then 107 if(data_block(31 downto 24) = "00000000") then -- set DACs 105 108 int_new_DACs <= '1'; 106 109 int_new_enables <= '0'; … … 110 113 int_read_enables <= '0'; 111 114 int_read_prescaling <= '0'; 115 int_ping_pong <= '0'; 112 116 dac_array_rs485_out_sig <= (conv_integer(unsigned(data_block(43 downto 32))), 113 117 conv_integer(unsigned(data_block(59 downto 48))), … … 120 124 ); 121 125 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 122 elsif (data_block(31 downto 24) = "00000001") then 126 elsif (data_block(31 downto 24) = "00000001") then -- read DACs 123 127 int_new_DACs <= '0'; 124 128 int_new_enables <= '0'; … … 128 132 int_read_enables <= '0'; 129 133 int_read_prescaling <= '0'; 130 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 131 elsif (data_block(31 downto 24) = "00000010") then 134 int_ping_pong <= '0'; 135 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 136 elsif (data_block(31 downto 24) = "00000010") then -- read rates 132 137 int_new_DACs <= '0'; 133 138 int_new_enables <= '0'; … … 137 142 int_read_enables <= '0'; 138 143 int_read_prescaling <= '0'; 139 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 140 elsif (data_block(31 downto 24) = "00000011") then 144 int_ping_pong <= '0'; 145 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 146 elsif (data_block(31 downto 24) = "00000011") then -- set enables 141 147 int_new_DACs <= '0'; 142 148 int_new_enables <= '1'; … … 146 152 int_read_enables <= '0'; 147 153 int_read_prescaling <= '0'; 154 int_ping_pong <= '0'; 148 155 enable_array_rs485_out_sig <= (data_block(47 downto 32), 149 156 data_block(63 downto 48), … … 152 159 ); 153 160 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 154 elsif (data_block(31 downto 24) = "00000100") then 161 elsif (data_block(31 downto 24) = "00000100") then -- read enables 155 162 int_new_DACs <= '0'; 156 163 int_new_enables <= '0'; … … 160 167 int_read_enables <= '1'; 161 168 int_read_prescaling <= '0'; 162 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 163 elsif (data_block(31 downto 24) = "00000110") then 169 int_ping_pong <= '0'; 170 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 171 elsif (data_block(31 downto 24) = "00000110") then -- set counter mode 164 172 int_new_DACs <= '0'; 165 173 int_new_enables <= '0'; … … 169 177 int_read_enables <= '0'; 170 178 int_read_prescaling <= '0'; 179 int_ping_pong <= '0'; 171 180 prescaling_rs485_out_sig <= data_block(39 downto 32); 172 181 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 173 elsif (data_block(31 downto 24) = "00000111") then 182 elsif (data_block(31 downto 24) = "00000111") then -- read counter mode 174 183 int_new_DACs <= '0'; 175 184 int_new_enables <= '0'; … … 179 188 int_read_enables <= '0'; 180 189 int_read_prescaling <= '1'; 190 int_ping_pong <= '0'; 191 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 192 elsif (data_block(31 downto 24) = "00000101") then -- ping pong 193 int_new_DACs <= '0'; 194 int_new_enables <= '0'; 195 int_new_prescaling <= '0'; 196 int_read_rates <= '0'; 197 int_read_DACs <= '0'; 198 int_read_enables <= '0'; 199 int_read_prescaling <= '0'; 200 int_ping_pong <= '1'; 181 201 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 182 202 else … … 188 208 int_read_enables <= '0'; 189 209 int_read_prescaling <= '0'; 210 int_ping_pong <= '0'; 190 211 FTU_rs485_interpreter_State <= WAIT_FOR_DATA; 191 212 end if;
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